FEATURES
TYPICAL APPLICATIONS CIRCUIT
VIN = 2.95V TO 20V
The ADP1874/ADP1875 are versatile current mode, synchronous
step-down controllers. They provide superior transient response,
optimal stability, and current-limit protection by using a constant
on-time, pseudo fixed frequency with a programmable current
limit, current control scheme. In addition, these devices offer
optimum performance at low duty cycles by using a valley, current
mode control architecture. This allows the ADP1874/ADP1875
to drive all N-channel power stages to regulate output voltages
to as low as 0.6 V.
The ADP1875 is the power saving mode (PSM) version of
the device and is capable of pulse skipping to maintain output
regulation while achieving improved system efficiency at light
loads (see the ADP1875 Power Saving Mode (PSM) section for
more information).
Available in three frequency options (300 kHz, 600 kHz, and
1.0 MHz, plus the PSM option), the ADP1874/ADP1875 are well
suited for a wide range of applications that require a single-input
power supply range from 2.95 V to 20 V. Low voltage biasing is
supplied via a 5 V internal low dropout regulator (LDO).
ADP1874/
ADP1875
COMP
VREG
VOUT
10kΩ
RTOP
CIN
BST
CBST
EN
DRVH
FB
SW
RBOT
GND
L
VOUT
COUT
Q2
RPGD
VREG PGOOD
SS
VREG_IN
CVREG
Q1
LOAD
DRVL
CVREG2
VEXT
CSS
RTRK2
RES
RRES
TRACK
VMASTER
RTRK1
PGND
Figure 1. Typical Applications Circuit
100
95
VIN = 5V (PSM)
90
85
80
EFFICIENCY (%)
GENERAL DESCRIPTION
CC2
RC
APPLICATIONS
Telecom and networking systems
Mid- to high-end servers
Set-top boxes
DSP core power supplies
VIN
CC
09347-001
Power input voltage range: 2.95 V to 20 V
On-board bias regulator
Minimum output voltage: 0.6 V
0.6 V reference voltage with ±1.0% accuracy
Supports all N-channel MOSFET power stages
Available in 300 kHz, 600 kHz, and 1.0 MHz options
No current-sense resistor required
Power saving mode (PSM) for light loads (ADP1875 only)
Resistor programmable current limit
Power good with internal pull-up resistor
Externally programmable soft start
Thermal overload protection
Short-circuit protection
Standalone precision enable input
Integrated bootstrap diode for high-side drive
Starts into a precharged output
Available in a 16-lead QSOP package
75
VIN = 16.5V
70
65
VIN = 13V
60
55
VIN = 13V (PSM)
50
45
40 VIN = 16.5V (PSM)
35
30
25
10
100
TA = 25°C
VOUT = 1.8V
fSW = 300kHz
WÜRTH INDUCTOR:
744325120, L = 1.2µH, DCR = 1.8mΩ
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
1k
LOAD CURRENT (mA)
10k
100k
09347-102
Data Sheet
Synchronous Buck Controller with Constant
On-Time and Valley Current Mode
ADP1874/ADP1875
Figure 2. ADP1874/ADP1875 Efficiency vs. Load Current (VOUT = 1.8 V, 300 kHz)
In addition, soft start programmability is included to limit input
in-rush current from the input supply during startup and to
provide reverse current protection during precharged output
conditions. The low-side current sense, current gain scheme, and
integration of a boost diode, along with the PSM/forced pulsewidth modulation (PWM) option, reduce the external part count
and improve efficiency.
The ADP1874/ADP1875 operate over the −40°C to +125°C
junction temperature range and are available in a 16-lead QSOP
package.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
ADP1874/ADP1875
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Timer Operation ........................................................................ 23
Applications ....................................................................................... 1
Pseudo-Fixed Frequency ........................................................... 24
General Description ......................................................................... 1
Power Good Monitoring ........................................................... 24
Typical Applications Circuit............................................................ 1
Voltage Tracking ......................................................................... 25
Revision History ............................................................................... 2
Applications Information .............................................................. 27
Specifications..................................................................................... 3
Feedback Resistor Divider ........................................................ 27
Absolute Maximum Ratings ............................................................ 6
Inductor Selection ...................................................................... 27
Thermal Resistance ...................................................................... 6
Output Ripple Voltage (ΔVRR) .................................................. 27
Boundary Condition .................................................................... 6
Output Capacitor Selection....................................................... 27
ESD Caution .................................................................................. 6
Compensation Network ............................................................ 28
Pin Configuration and Function Descriptions ............................. 7
Efficiency Consideration ........................................................... 29
Typical Performance Characteristics ............................................. 8
Input Capacitor Selection .......................................................... 30
ADP1874/ADP1875 Block Digram ............................................... 18
Thermal Considerations............................................................ 31
Theory of Operation ...................................................................... 19
Design Example .......................................................................... 32
Startup .......................................................................................... 19
External Component Recommendations .................................... 34
Soft Start ...................................................................................... 19
Layout Considerations ................................................................... 36
Precision Enable Circuitry ........................................................ 19
IC Section (Left Side of Evaluation Board) ............................. 38
Undervoltage Lockout ............................................................... 19
Power Section ............................................................................. 38
On-Board Low Dropout Regulator .......................................... 20
Differential Sensing .................................................................... 39
Thermal Shutdown ..................................................................... 20
Typical Application Circuits ......................................................... 40
Programming Resistor (RES) Detect Circuit.......................... 20
12 A, 300 kHz High Current Application Circuit .................. 40
Valley Current-Limit Setting .................................................... 20
5.5 V Input, 600 kHz Application Circuit ............................... 40
Hiccup Mode During Short Circuit ......................................... 22
300 kHz High Current Application Circuit ............................ 41
Synchronous Rectifier ................................................................ 22
Outline Dimensions ....................................................................... 42
ADP1875 Power Saving Mode (PSM) ...................................... 22
Ordering Guide .......................................................................... 42
REVISION HISTORY
7/12—Rev. 0 to Rev. A
Changes to Table 7 .......................................................................... 21
3/11—Revision 0: Initial Version
Rev. A | Page 2 of 44
Data Sheet
ADP1874/ADP1875
SPECIFICATIONS
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VREG = 5 V,
BST − SW = VREG − VRECT_DROP (see Figure 40 to Figure 42). VIN = 12 V. The specifications are valid for TJ = −40°C to +125°C,
unless otherwise specified.
Table 1.
Parameter
POWER SUPPLY CHARACTERISTICS
High Input Voltage Range
Quiescent Current
Shutdown Current
Undervoltage Lockout
UVLO Hysteresis
INTERNAL REGULATOR
CHARACTERISTICS
VREG Operational Output Voltage
Symbol
Test Conditions/Comments
VIN
CVIN = 22 µF(25 V rating) to PGND (at Pin 1)
ADP1874ARQZ-0.3/ADP1875ARQZ-0.3 (300 kHz)
ADP1874ARQZ-0.6/ADP1875ARQZ-0.6 (600 kHz)
ADP1874ARQZ-1.0/ADP1875ARQZ-1.0 (1.0 MHz)
FB = 1.5 V, no switching
EN < 600 mV
Rising VIN (see Figure 35 for temperature variation)
Falling VIN from operational state
VREG and VREG_IN tied together and should not be
loaded externally because they are intended to only
bias internal circuitry
CVREG = 4.7 µF to PGND, 0.22 µF to GND, VIN = 2.95 V to 20 V
ADP1874ARQZ-0.3/ADP1875ARQZ-0.3 (300 kHz)
ADP1874ARQZ-0.6/ADP1875ARQZ-0.6 (600 kHz)
ADP1874ARQZ-1.0/ADP1875ARQZ-1.0 (1.0 MHz)
VIN = 7 V, 100 mA
VIN = 12 V, 100 mA
0 mA to 100 mA, VIN = 7 V
0 mA to 100 mA, VIN = 20 V
VIN = 7 V to 20 V, 20 mA
VIN = 7 V to 20 V, 100 mA
100 mA out of VREG, VIN ≤ 5 V
VIN = 20 V
IQ_REG + IQ_BST
IREG,SD + IBST,SD
UVLO
VREG
VREG Output in Regulation
Load Regulation
Line Regulation
VIN to VREG Dropout Voltage
Short VREG to PGND
SOFT START
Soft Start Period Calculation
ERROR AMPLIFER
FB Regulation Voltage
Transconductance
FB Input Leakage Current
CURRENT-SENSE AMPLIFIER GAIN
Programming Resistor (RES)
Value from RES to PGND
SWITCHING FREQUENCY
ADP1874ARQZ-0.3/
ADP1875ARQZ-0.3 (300 kHz)
On-Time
Minimum On-Time
Minimum Off-Time
Min
Typ
Max
Unit
2.95
2.95
3.25
12
12
12
1.1
140
2.65
190
20
20
20
V
V
V
mA
µA
V
mV
2.75
2.75
3.05
4.82
4.83
Connect external capacitor from SS pin to GND,
CSS = 10 nF/ms
VFB
Gm
IFB, LEAK
TJ = 25°C
TJ = −40°C to +85°C
TJ = −40°C to +125°C
5
5
5
4.981
4.982
32
34
2.5
2
300
229
225
5.5
5.5
5.5
5.16
5.16
415
320
10
V
V
V
V
V
mV
mV
mV
mV
mV
mA
nF/ms
596
594.2
320
600
600
600
496
1
604
605.8
670
50
mV
mV
mV
µS
nA
RES = 47 kΩ ± 1%
2.7
3
3.3
V/V
RES = 22 kΩ ± 1%
RES = none
RES = 100 kΩ ± 1%
Typical values measured at 50% time points with
0 nF at DRVH and DRVL; maximum values are
guaranteed by bench evaluation 1
5.5
11
22
6
12
24
6.5
13
26
V/V
V/V
V/V
FB = 0.6 V, EN = VREG
300
VIN = 5 V, VOUT = 2 V, TJ = 25°C
VIN = 20 V
84% duty cycle (maximum)
Rev. A | Page 3 of 44
1120
1200
145
340
kHz
1280
190
400
ns
ns
ns
ADP1874/ADP1875
Parameter
ADP1874ARQZ-0.6/
ADP1875ARQZ-0.6 (600 kHz)
On-Time
Minimum On-Time
Minimum Off-Time
ADP1874ARQZ-1.0/
ADP1875ARQZ-1.0 (1.0 MHz)
On-Time
Minimum On-Time
Minimum Off-Time
OUTPUT DRIVER CHARACTERISTICS
High-Side Driver
Output Source Resistance 2
Output Sink Resistance2
Rise Time 3
Fall Time3
Low-Side Driver
Output Source Resistance2
Output Sink Resistance2
Rise Time3
Fall Time3
Propagation Delays
DRVL Fall to DRVH Rise3
DRVH Fall to DRVL Rise3
SW Leakage Current
Integrated Rectifier
Channel Impedance
PRECISION ENABLE THRESHOLD
Logic High Level
Enable Hysteresis
COMP VOLTAGE
COMP Clamp Low Voltage
COMP Clamp High Voltage
COMP Zero Current Threshold
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
CURRENT LIMIT
Hiccup Current Limit Timing
OVERVOLTAGE AND POWER GOOD
THRESHOLDS
FB Power Good Threshold
FB Power Good Hysteresis
FB Overvoltage Threshold
FB Overvoltage Hysteresis
PGOOD Low Voltage During Sink
PGOOD Leakage Current
Data Sheet
Symbol
Test Conditions/Comments
Min
Typ
600
Max
Unit
kHz
VIN = 5 V, VOUT = 2 V, TJ = 25°C
VIN = 20 V, VOUT = 0.8 V
65% duty cycle (maximum)
500
540
82
340
1.0
580
110
400
ns
ns
ns
MHz
VIN = 5 V, VOUT = 2 V, TJ = 25°C
VIN = 20 V
45% duty cycle (maximum)
285
312
52
340
340
85
400
ns
ns
ns
2.25
0.70
25
11
3.5
1
tr, DRVH
tf, DRVH
ISOURCE = 1.5 A, 100 ns, positive pulse (0 V to 5 V)
ISINK = 1.5 A, 100 ns, negative pulse (5 V to 0 V)
BST − SW = 4.4 V, CIN = 4.3 nF (see Figure 59)
BST − SW = 4.4 V, CIN = 4.3 nF (see Figure 60)
Ω
Ω
ns
ns
1.6
0.7
18
16
2.4
1
tr,DRVL
tf,DRVL
ISOURCE = 1.5 A, 100 ns, positive pulse (0 V to 5 V)
ISINK = 1.5 A, 100 ns, negative pulse (5 V to 0 V)
VREG = 5.0 V, CIN = 4.3 nF (see Figure 60)
VREG = 5.0 V, CIN = 4.3 nF (see Figure 59)
Ω
Ω
ns
ns
ttpdhDRVH
ttpdhDRVL
ISWLEAK
BST − SW = 4.4 V (see Figure 59)
BST − SW = 4.4 V (see Figure 60)
BST = 25 V, SW = 20 V, VREG = 5 V
15.4
18
ISINK = 10 mA
22
VCOMP(LOW)
VCOMP(HIGH)
VCOMP_ZCT
TTMSD
110
VIN = 2.9 V to 20 V, VREG = 2.75 V to 5.5 V
VIN = 2.9 V to 20 V, VREG = 2.75 V to 5.5 V
570
Tie EN pin to VREG to enable device
(2.75 V ≤ VREG ≤ 5.5 V)
(2.75 V ≤ VREG ≤ 5.5 V)
(2.75 V ≤ VREG ≤ 5.5 V)
0.47
630
31
ns
ns
µA
Ω
680
mV
mV
V
1.15
2.55
V
V
Rising temperature
155
15
°C
°C
COMP = 2.4 V
6
ms
FBPGD
VFB rising during system power-up
FBOV
VFB rising during overvoltage event, IPGOOD = 1 mA
VPGOOD
IPGOOD = 1 mA
PGOOD = 5 V
542
30
691
30
143
1
PGOOD
Rev. A | Page 4 of 44
568
710
200
400
mV
mV
mV
mV
mV
nA
Data Sheet
Parameter
TRACKING
Track Input Voltage Range
FB-to-Tracking Offset Voltage
Leakage Current
ADP1874/ADP1875
Symbol
Test Conditions/Comments
Min
Typ
0
0.5 V < TRACK < 0.6 V, offset = VFB − VTRACK
VTRACK = 5 V
1
63
1
Max
Unit
5
V
mV
nA
50
The maximum specified values are with the closed loop measured at 10% to 90% time points (see Figure 59 and Figure 60), CGATE = 4.3 nF, and the upper side and lower
side MOSFETs being Infineon BSC042N03MS G.
Guaranteed by design.
3
Not automatic test equipment (ATE) tested.
2
Rev. A | Page 5 of 44
ADP1874/ADP1875
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
VREG, VREG_IN, TRACK to PGND, GND
VIN, EN, PGOOD to PGND
FB, COMP, RES, SS to GND
DRVL to PGND
SW to PGND
BST to SW
BST to PGND
DRVH to SW
PGND to GND
PGOOD Input Current
θJA (16-Lead QSOP)
4-Layer Board
Operating Junction Temperature Range
Storage Temperature Range
Soldering Conditions
Maximum Soldering Lead Temperature
(10 sec)
Rating
−0.3 V to +6 V
−0.3 V to +28 V
−0.3 V to (VREG + 0.3 V)
−0.3 V to (VREG + 0.3 V)
−2.0 V to +28 V
−0.6 V to (VREG + 0.3 V)
−0.3 V to +28 V
−0.3 V to VREG
±0.3 V
20 mA
104°C/W
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
300°C
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
θJA (16-Lead QSOP)
4-Layer Board
θJA
Unit
104°
°C/W
BOUNDARY CONDITION
In determining the values given in Table 2 and Table 3, natural
convection is used to transfer heat to a 4-layer evaluation board.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages
are referenced to PGND.
Rev. A | Page 6 of 44
Data Sheet
ADP1874/ADP1875
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
16 BST
VIN 1
15 SW
COMP 2
FB 4
GND 5
RES 6
VREG 7
VREG_IN 8
ADP1874/
ADP1875
14 DRVH
13 PGND
TOP VIEW
12 DRVL
(Not to Scale)
11 PGOOD
10 SS
9
TRACK
09347-003
EN 3
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin
No.
1
2
Mnemonic
VIN
COMP
3
4
5
EN
FB
GND
6
7
RES
VREG
8
9
VREG_IN
TRACK
10
SS
11
PGOOD
12
DRVL
13
14
15
16
PGND
DRVH
SW
BST
Description
High-Side Input Voltage. Connect VIN to the drain of the upper side MOSFET.
Output of the Error Amplifier. Connect the compensation network between this pin and AGND to achieve stability (see the
Compensation Network section).
Connect to VREG to Enable IC. When pulled down to AGND externally, disables the IC.
Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected.
Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground plane
(see the Layout Considerations section).
Current Sense Gain Resistor (External). Connect a resistor between the RES pin and GND (Pin 5).
Internal Regulator Supply Bias Voltage for the ADP1874/ADP1875 Controller (Includes the Output Gate Drivers). A
bypass capacitor of 1 µF directly from this pin to PGND and a 0.1 µF across VREG and GND are recommended.
Input to the Internal LDO. Tie this pin directly to Pin 7 (VREG).
Tracking Input. If the tracking function is not used, it is recommended to connect TRACK to VREG through a resistor
higher than 1 MΩ or simply connect TRACK between 0.7 V and 2 V to reduce the bias current going into the pin.
Soft Start Input. Connect an external capacitor to GND to program the soft start period. Capacitance value of 10 nF for
every 1 ms of soft start delay.
Open-Drain Power Good Output. Sinks current when FB is out of regulation or during thermal shutdown. Connect a
3 kΩ resistor between PGOOD and VREG. Leave unconnected if not used.
Drive Output for the External Lower Side, N-Channel MOSFET. This pin also serves as the current-sense gain setting pin (see
Figure 69).
Power GND. Ground for the lower side gate driver and lower side, N-channel MOSFET.
Drive Output for the External Upper Side, N-Channel MOSFET.
Switch Node Connection.
Bootstrap for the Upper Side MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected between VREG and
BST. A capacitor from BST to SW is required. An external Schottky diode can also be connected between VREG and BST for
increased gate drive capability.
Rev. A | Page 7 of 44
ADP1874/ADP1875
Data Sheet
VIN = 16.5V
VIN = 13V
TA = 25°C
VOUT = 0.8V
fSW = 300kHz
WÜRTH INDUCTOR:
744325072, L = 0.72µH, DCR = 1.3mΩ
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
100k
EFFICIENCY (%)
09347-105
EFFICIENCY (%)
LOAD CURRENT (mA)
EFFICIENCY (%)
VIN = 16.5V
TA = 25°C
VOUT = 7V
fSW = 300kHz
WÜRTH INDUCTOR:
7443551200, L = 2.0µH, DCR = 2.6mΩ
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
100k
09347-106
EFFICIENCY (%)
100
1k
10k
100k
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
10
VIN = 13V
VIN = 13V (PSM)
VIN = 16.5V
VIN = 16.5V (PSM)
TA = 25°C
VOUT = 1.8V
fSW = 600kHz
WÜRTH INDUCTOR:
744325072, L = 0.72µH, DCR = 1.3mΩ
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
100
1k
10k
100k
Figure 8. Efficiency—600 kHz, VOUT = 1.8 V
VIN = 13V
10k
WÜRTH INDUCTOR:
744355147, L = 0.47µH, DCR = 0.67mΩ
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
LOAD CURRENT (mA)
Figure 5. Efficiency—300 kHz, VOUT = 1.8 V
1k
TA = 25°C
VOUT = 0.8V
fSW = 600kHz
VIN = 16.5V
(PSM)
Figure 7. Efficiency—600 kHz, VOUT = 0.8 V
100
95
VIN = 5V (PSM)
90
85
80
75
70
VIN = 16.5V
65
VIN = 13V (PSM)
60
55
VIN = 13V
50
45
40 VIN = 16.5V (PSM)
35
TA = 25°C
30
VOUT = 1.8V
25
fSW = 300kHz
20
WÜRTH INDUCTOR:
15
744325120, L = 1.2µH, DCR = 1.8mΩ
10
INFINEON FETs:
5
BSC042N03MS G (UPPER/LOWER)
0
10
100
1k
10k
100k
LOAD CURRENT (mA)
VIN = 16.5V
LOAD CURRENT (mA)
Figure 4. Efficiency—300 kHz, VOUT = 0.8 V
100
95 VIN = 16.5V (PSM)
90
85
80
75 V = 13V (PSM)
IN
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
10
100
VIN = 13V (PSM)
09347-108
10k
VIN = 13V
Figure 6. Efficiency—300 kHz, VOUT = 7 V
100
VIN = 13V (PSM)
95
90 V = 16.5V (PSM)
IN
85
80
75
70
65
VIN = 16.5V
60
55
50
VIN = 20V (PSM)
VIN = 20V
45
40
35
TA = 25°C
30
VOUT = 5V
25
fSW = 600kHz
20
WÜRTH INDUCTOR:
15
744318180, L = 1.4µH, DCR = 3.2mΩ
10
INFINEON FETs:
5
BSC042N03MS G (UPPER/LOWER)
0
10
100
1k
10k
100k
LOAD CURRENT (mA)
Figure 9. Efficiency—600 kHz, VOUT = 5 V
Rev. A | Page 8 of 44
09347-109
1k
LOAD CURRENT (mA)
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
10
09347-107
EFFICIENCY (%)
100
95
90
VIN = 13V (PSM)
85
80
75
70
65
60
55
50
45
40
35 V = 16.5V (PSM)
IN
30
25
20
15
10
5
0
10
100
09347-104
EFFICIENCY (%)
TYPICAL PERFORMANCE CHARACTERISTICS
ADP1874/ADP1875
100
95
90
85
80
75
70
65 VIN = 13V (PSM)
60
55
50
45
40
35
30
VIN = 16.5V (PSM)
25
20
15
10
5
0
10
100
0.807
0.806
VIN = 13V
0.805
VIN = 16.5V
TA = 25°C
VOUT = 0.8V
fSW = 1.0MHz
10k
100k
LOAD CURRENT (mA)
0.798
0.797
0.796
VIN = 16.5V
+125°C
+25°C
–40°C
VIN = 13V
+125°C
+25°C
–40°C
0.792
0
2000
4000
6000
8000
10,000
LOAD CURRENT (mA)
1.821
VIN = 13V
VIN = 16.5V
TA = 25°C
VOUT = 1.8V
fSW = 1.0MHz
WÜRTH INDUCTOR:
744303022, L = 0.22µH, DCR = 0.33mΩ
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
10k
100k
TA = 25°C
VOUT = 5V
fSW = 1.0MHz
0
VIN = 13V
+125°C
+25°C
–40°C
VIN = 16.5V
+125°C
+25°C
–40°C
1500
3000
4500
6000
7500
9000 10,500 12,000 13,500 15,000
LOAD CURRENT (mA)
100k
09347-112
WÜRTH INDUCTOR:
744355090, L = 0.9µH, DCR = 1.6mΩ
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
10k
VIN = 5.5V
+125°C
+25°C
–40°C
1.786
OUTPUT VOLTAGE (V)
VIN = 13V
1k
1.796
Figure 14. Output Voltage Accuracy—300 kHz, VOUT = 1.8 V
VIN = 16.5V
LOAD CURRENT (mA)
1.801
1.791
VIN = 13V (PSM)
VIN = 16.5V (PSM)
1.806
Figure 12. Efficiency—1.0 MHz, VOUT = 5 V
7.100
7.095
7.090
7.085
7.080
7.075
7.070
7.065
7.060
7.055
7.050
7.045
7.040
7.035
7.030
7.025
7.020
7.015
7.010
7.005
7.000
+125°C
+25°C
–40°C
0
1000
2000
VIN = 13V
VIN = 16.5V
3000
4000
5000
6000
7000
8000
9000
LOAD CURRENT (mA)
Figure 15. Output Voltage Accuracy—300 kHz, VOUT = 7 V
Rev. A | Page 9 of 44
09347-015
1k
1.811
09347-014
OUTPUT VOLTAGE (V)
1.816
09347-111
EFFICIENCY (%)
EFFICIENCY (%)
0.799
0.793
Figure 11. Efficiency—1.0 MHz, VOUT = 1.8 V
100
0.800
Figure 13. Output Voltage Accuracy—300 kHz, VOUT = 0.8 V
LOAD CURRENT (mA)
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
10
0.801
0.794
Figure 10. Efficiency—1.0 MHz, VOUT = 0.8 V
100
95
90
85
80
VIN = 13V (PSM)
75
70
65
60
55
50
45
40 V = 16.5V (PSM)
IN
35
30
25
20
15
10
5
0
10
100
0.802
0.795
WÜRTH INDUCTOR:
744303012, L = 0.12µH, DCR = 0.33mΩ
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
1k
0.803
09347-013
OUTPUT VOLTAGE (V)
0.804
09347-110
EFFICIENCY (%)
Data Sheet
ADP1874/ADP1875
Data Sheet
0.808
0.807
0.805
0.806
0.803
OUTPUT VOLTAGE (V)
FREQUENCY (kHz)
0.804
0.802
0.800
0.798
0.801
0.799
0.797
0.795
0.793
0.796
0.791
0.792
0
1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000
LOAD CURRENT (mA)
0.787
0
4000
6000
8000
10,000
Figure 19. Output Voltage Accuracy—1.0 MHz, VOUT = 0.8 V
1.820
1.818
1.816
1.814
1.812
1.810
1.808
1.806
1.804
1.802
1.800
1.798
1.796
1.794
1.792
1.790
1.788
1.786
1.784
1.782
1.780
1.778
1.776
1.774
1.772
1.770
OUTPUT VOLTAGE (V)
1.815
0
1500
3000
4500
VIN = 16.5V
+125°C
+25°C
–40°C
6000
7500
9000
1.810
1.805
1.800
VIN = 13V
+125°C
+25°C
–40°C
1.795
10,500 12,000
LOAD CURRENT (mA)
VIN = 16.5V
+125°C
+25°C
–40°C
1.790
0
09347-019
VIN = 13V
+125°C
+25°C
–40°C
09347-016
1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000
LOAD CURRENT (mA)
Figure 17. Output Voltage Accuracy—600 kHz, VOUT = 1.8 V
Figure 20. Output Voltage Accuracy—1.0 MHz, VOUT = 1.8 V
5.030
5.04
5.025
5.03
5.02
5.020
5.01
OUTPUT VOLTAGE (V)
5.015
5.010
5.005
5.000
4.995
4.990
4.985
5.00
4.99
4.98
4.97
4.96
4.95
4.94
4.93
4.980
4.975
4.970
0
1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000
LOAD CURRENT (mA)
VIN = 13V
+125°C
+25°C
–40°C
4.92
VIN = 13V
VIN = 16.5V
VIN = 20V
4.91
09347-017
+125°C
+25°C
–40°C
Figure 18. Output Voltage Accuracy—600 kHz, VOUT = 5 V
VIN = 16.5V
+125°C
+25°C
–40°C
4.90
0
800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 9600
LOAD CURRENT (mA)
Figure 21. Output Voltage Accuracy—1.0 MHz, VOUT =5 V
Rev. A | Page 10 of 44
09347-020
OUTPUT VOLTAGE (V)
2000
VIN = 16.5V
+125°C
+25°C
–40°C
LOAD CURRENT (mA)
Figure 16. Output Voltage Accuracy—600 kHz, VOUT = 0.8 V
OUTPUT VOLTAGE (V)
VIN = 13V
+125°C
+25°C
–40°C
0.789
VIN = 13V
VIN = 16.5V
09347-118
+125°C
+25°C
–40°C
09347-115
0.794
Data Sheet
ADP1874/ADP1875
601.0
900
SWITCHING FREQUENCY (kHz)
599.5
VREG = 5V, VIN = 13V
599.0
598.5
598.0
840
820
800
780
760
740
25.0
57.5
90.0
700
13.0
09347-121
–7.5
122.5
TEMPERATURE (°C)
+125°C
+25°C
–40°C
315
14.0
14.5
15.0
15.5
16.0
16.5
VIN (V)
Figure 22. Feedback Voltage vs. Temperature
325
13.5
09347-124
720
597.0
–40.0
Figure 25. Switching Frequency vs. High Input Voltage, 1.0 MHz,
VIN Range = 13 V to 16.5 V
280
NO LOAD
VIN = 13V
VIN = 20V
VIN = 16.5V
265
+125°C
+25°C
–40°C
305
FREQUENCY (kHz)
SWITCHING FREQUENCY (kHz)
860
295
285
250
235
220
275
205
265
VIN (V)
190
09347-022
255
10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2
0
6000
8000
10,000
Figure 26. Frequency vs. Load Current, 300 kHz, VOUT = 0.8 V
330
NO LOAD
+125°C
+25°C
–40°C
4000
LOAD CURRENT (mA)
Figure 23. Switching Frequency vs. High Input Voltage, 300 kHz, ±10% of 12 V
650
2000
09347-025
FEEDBACK VOLTAGE (V)
VREG = 5V, VIN = 20V
600.0
597.5
600
+125°C
+25°C
–40°C
VIN = 20V
VIN = 13V
VIN = 16.5V
320
310
FREQUENCY (kHz)
SWITCHING FREQUENCY (kHz)
+125°C
+25°C
–40°C
880
600.5
550
500
300
290
280
270
260
450
13.4
13.8
14.2
14.6
15.0
VIN (V)
15.4
15.8
16.2 16.5
Figure 24. Switching Frequency vs. High Input Voltage, 600 kHz, VOUT = 1.8 V,
VIN Range = 13 V to 16.5 V
Rev. A | Page 11 of 44
240
0
1500
3000
4500
6000
7500
9000 10,500 12,000 13,500 15,000
LOAD CURRENT (mA)
Figure 27. Frequency vs. Load Current, 300 kHz, VOUT = 1.8 V
09347-026
400
13.0
09347-123
250
ADP1874/ADP1875
VIN = 13V
VIN = 16.5V
334
+125°C
+25°C
–40°C
326
FREQUENCY (kHz)
FREQUENCY (kHz)
330
322
318
314
310
306
298
0
800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800
LOAD CURRENT (mA)
09347-027
302
740
733
726
719
712
705
698
691
684
677
670
663
656
649
642
635
628
621
0
Figure 31. Frequency vs. Load Current, 600 kHz, VOUT = 5 V
850
+125°C
+25°C
–40°C
VIN = 13V
VIN = 16.5V
510
800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 9600
LOAD CURRENT (mA)
Figure 28. Frequency vs. Load Current, 300 kHz, VOUT = 7 V
540
+125°C
+25°C
–40°C
VIN = 13V
VIN = 16.5V
09347-030
338
Data Sheet
VIN = 13V
VIN = 16.5V
+125°C
+25°C
–40°C
775
FREQUENCY (kHz)
FREQUENCY (kHz)
480
450
420
390
700
625
550
360
0
1200
2400
3600
4800
6000
7200
8400
9600 10,800 12,000
LOAD CURRENT (mA)
400
09347-028
300
0
6000
8000
10,000
12,000
Figure 32. Frequency vs. Load Current, VOUT = 1.0 MHz, 0.8 V
675
1225
VIN = 13V
VIN = 16.5V
655
4000
LOAD CURRENT (mA)
Figure 29. Frequency vs. Load Current, 600 kHz, VOUT = 0.8 V
VIN = 13V
VIN = 16.5V
1150
635
+125°C
+25°C
–40°C
FREQUENCY (kHz)
1075
615
595
575
555
535
1000
925
850
775
700
+125°C
+25°C
–40°C
495
0
1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000
LOAD CURRENT (mA)
625
Figure 30. Frequency vs. Load Current, 600 kHz, VOUT = 1.8 V
550
0
1200
2400
3600
4800
6000
7200
8400
9600 10,800 12,000
LOAD CURRENT (mA)
Figure 33. Frequency vs. Load Current, 1.0 MHz, VOUT = 1.8 V
Rev. A | Page 12 of 44
09347-032
515
09347-029
FREQUENCY (kHz)
2000
09347-031
475
330
Data Sheet
ADP1874/ADP1875
1450
82
VIN = 13V
VIN = 16.5V
1400
+125°C
+25°C
–40°C
MAXIMUM DUTY CYCLE (%)
1300
1250
1200
1150
1100
78
76
74
72
70
68
66
1050
0
800
1600 2400 3200 4000 4800 5600 6400 7200 8000
LOAD CURRENT (mA)
62
5.5
09347-033
1000
7.9
9.1
10.3
11.5
12.7
13.9
15.1
16.3
VIN (V)
Figure 34. Frequency vs. Load Current, 1.0 MHz, VOUT = 5 V
Figure 37. Maximum Duty Cycle vs. High Voltage Input (VIN)
680
2.657
630
2.656
580
MINUMUM OFF-TIME (ns)
2.658
2.655
2.654
2.653
2.652
2.651
VREG = 2.7V
VREG = 3.6V
VREG = 5.5V
530
480
430
380
330
280
2.650
230
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
180
–40
09347-034
2.649
–40
6.7
09347-036
64
20
40
60
80
100
120
Figure 38. Minimum Off-Time vs. Temperature
680
+125°C
+25°C
–40°C
90
0
TEMPERATURE (°C)
Figure 35. UVLO vs. Temperature
95
–20
09347-037
FREQUENCY (kHz)
1350
UVLO (V)
+125°C
+25°C
–40°C
80
+125°C
+25°C
–40°C
630
MINUMUM OFF-TIME (ns)
80
75
70
65
530
480
430
380
330
280
60
230
400
500
600
700
800
900
FREQUENCY (kHz)
1000
180
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VREG (V)
Figure 39. Minimum Off-Time vs. VREG (Low Input Voltage)
Figure 36. Maximum Duty Cycle vs. Frequency
Rev. A | Page 13 of 44
09347-038
55
300
09347-035
MAXIMUM DUTY CYCLE (%)
580
85
ADP1874/ADP1875
80
+125°C
+25°C
–40°C
RECTIFIER DROP (mV)
640
560
480
400
320
240
80
300
400
500
600
700
800
900
1000
FREQUENCY (kHz)
1200
1120
VIN = 5.5V
VIN = 13V
VIN = 16.5V
1MHz
300kHz
48
40
32
24
16
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VREG (V)
Figure 43. Lower Side MOSFET Body Diode Conduction Time vs. VREG
TA = 25°C
OUTPUT VOLTAGE
1
1040
RECTIFIER DROP (mV)
56
8
2.7
Figure 40. Internal Rectifier Drop vs. Frequency
1280
+125°C
+25°C
–40°C
64
09347-039
160
300kHz
1MHz
72
09347-042
720
VREG = 2.7V
VREG = 3.6V
VREG = 5.5V
BODY DIODE CONDUCTION TIME (ns)
800
Data Sheet
960
880
800
INDUCTOR CURRENT
720
2
640
560
SW NODE
480
400
3
320
240
LOW SIDE
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VREG (V)
Figure 41. Internal Boost Rectifier Drop vs. VREG (Low Input Voltage)
Over VIN Variation
720
640
300kHz
1MHz
CH1 50mV BW
CH3 10V BW
09347-040
80
2.7
CH2 5A Ω
CH4 5V
M400ns
T 35.8%
A CH2
3.90A
09347-043
4
160
Figure 44. Power Saving Mode (PSM) Operational Waveform, 100 mA
+125°C
+25°C
–40°C
OUTPUT VOLTAGE
INDUCTOR CURRENT
480
2
400
320
SW NODE
240
3
160
LOW SIDE
80
2.7
3.1
3.5
3.9
4.3
4.7
5.1
VREG (V)
5.5
Figure 42. Internal Boost Rectifier Drop vs. VREG
CH1 50mV BW
CH3 10V BW
CH2 5A Ω
CH4 5V
M4.0µs
T 35.8%
A CH2
3.90A
Figure 45. PSM Waveform at Light Load, 500 mA
Rev. A | Page 14 of 44
09347-044
4
09347-041
RECTIFIER DROP (mV)
1
560
Data Sheet
ADP1874/ADP1875
OUTPUT VOLTAGE
2
4
OUTPUT VOLTAGE
INDUCTOR CURRENT
12A NEGATIVE STEP
1
SW NODE
1
3
SW NODE
LOW SIDE
3
CH4 100mV
B
W
M400ns
T 30.6%
A CH3
2.20V
CH1 10A Ω
CH3 20V
CH2 200mV
CH4 5V
B
W
M20µs
T 48.2%
A CH1
3.40A
09347-048
CH1 5A Ω
CH3 10V
09347-045
4
Figure 49. Negative Step During Heavy Load Transient Behavior—PSM Enabled,
12 A (See Figure 99 Application Circuit)
Figure 46. CCM Operation at Heavy Load, 12 A
(See Figure 99 for Application Circuit)
OUTPUT VOLTAGE
2
4
OUTPUT VOLTAGE
12A STEP
12A STEP
LOW SIDE
1
1
SW NODE
3
2
SW NODE
LOW SIDE
4
B
W
M2ms
T 75.6%
A CH1
3.40A
3
CH1 10A Ω
CH3 20V
Figure 47. Load Transient Step—PSM Enabled, 12 A
(See Figure 99 Application Circuit)
CH2 5V
CH4 200mV
B
W
M2ms
T 15.6%
A CH1
6.20A
09347-049
CH2 200mV
CH4 5V
09347-046
CH1 10A Ω
CH3 20V
Figure 50. Load Transient Step—Forced PWM at Light Load, 12 A
(See Figure 99 Application Circuit)
OUTPUT VOLTAGE
OUTPUT VOLTAGE
2
4
12A POSITIVE STEP
12A POSITIVE STEP
SW NODE
1
LOW SIDE
1
3
2
SW NODE
LOW SIDE
4
B
W
M20µs
T 30.6%
A CH1
3.40A
3
CH1 10A Ω
CH3 20V
Figure 48. Positive Step During Heavy Load Transient Behavior—PSM Enabled,
12 A, VOUT = 1.8 V (See Figure 99 Application Circuit)
CH2 5V
CH4 200mV
B
W
M20µs
T 43.8%
A CH1
6.20A
09347-050
CH2 200mV
CH4 5V
09347-047
CH1 10A Ω
CH3 20V
Figure 51. Positive Step During Heavy Load Transient Behavior—Forced PWM
at Light Load, 12 A, VOUT = 1.8 V (See Figure 99 Application Circuit)
Rev. A | Page 15 of 44
ADP1874/ADP1875
Data Sheet
OUTPUT VOLTAGE
2
OUTPUT VOLTAGE
1
INDUCTOR CURRENT
12A NEGATIVE STEP
2
1
SW NODE
LOW SIDE
4
3
SW NODE
LOW
SIDE
CH2 200mV
CH4 5V
B
W
M10µs
T 23.8%
A CH1
5.60A
CH1 2V BW CH2 5A Ω
CH3 10V
CH4 5V
Figure 52. Negative Step During Heavy Load Transient Behavior—Forced PWM
at Light Load, 12 A (See Figure 99 Application Circuit)
M2ms
T 32.8%
A CH1
720mV
09347-054
CH1 10A Ω
CH3 20V
3
09347-051
4
Figure 55. Start-Up Behavior at Heavy Load, 12 A, 300 kHz
(See Figure 99 Application Circuit)
OUTPUT VOLTAGE
OUTPUT VOLTAGE
1
1
INDUCTOR CURRENT
2
INDUCTOR CURRENT
LOW SIDE
2
LOW SIDE
4
4
SW NODE
SW NODE
3
M4ms
T 49.4%
A CH1
920mV
CH1 2V BW CH2 5A Ω
CH3 10V
CH4 5V
Figure 53. Output Short-Circuit Behavior Leading to Hiccup Mode
1
M4ms
T 41.6%
A CH1
720mV
09347-055
CH1 2V BW CH2 5A Ω
CH3 10V
CH4 5V
09347-052
3
Figure 56. Power-Down Waveform During Heavy Load
OUTPUT VOLTAGE
OUTPUT VOLTAGE
1
INDUCTOR CURRENT
INDUCTOR CURRENT
2
2
SW NODE
SW NODE
3
3
LOW SIDE
LOW SIDE
4
A CH2
8.20A
CH1 50mV BW
CH3 10V BW
CH2 5A Ω
CH4 5V
M2µs
T 35.8%
A CH2
3.90A
09347-056
M10µs
T 36.2%
09347-053
4
CH1 5V BW CH2 10A Ω
CH3 10V
CH4 5V
Figure 57. Output Voltage Ripple Waveform During PSM Operation
at Light Load, 2 A
Figure 54. Magnified Waveform During Hiccup Mode
Rev. A | Page 16 of 44
Data Sheet
ADP1874/ADP1875
TA = 25°C
VREG = 5.5V
VREG = 3.6V
VREG = 2.7V
570
TRANSCONDUCTANCE (µS)
LOW SIDE
4
HIGH SIDE
SW NODE
3
2
550
530
510
490
470
450
M
M40ns
T 29.0%
A CH2
4.20V
430
–40
09347-058
CH3 5V
MATH 2V 40ns
CH2 5V
CH4 2V
20
40
60
80
100
680
+125°C
+25°C
–40°C
TRANSCONDUCTANCE (µs)
630
4
120
Figure 61. Transconductance (Gm) vs. Temperature
TA = 25°C
16ns (tf,DRVL )
0
TEMPERATURE (°C)
Figure 58. Output Drivers and SW Node Waveforms
LOW SIDE
–20
09347-061
HS MINUS
SW
22ns (tpdhDRVH )
HIGH SIDE
25ns (tr,DRVH )
SW NODE
580
530
480
430
3
2
CH2 5V
CH3 5V
CH4 2V
MATH 2V 40ns
M40ns
T 29.0%
A CH2
4.20V
330
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
VREG (V)
09347-062
380
HS MINUS
SW
09347-059
M
Figure 62. Transconductance (Gm) vs. VREG
Figure 59. Upper Side Driver Rising and Lower Side Falling Edge Waveforms
(CIN = 4.3 nF (Upper Side/Lower Side MOSFET),
QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3))
1.30
18ns (tr,DRVL )
LOW SIDE
1.25
QUIESCENT CURRENT (mA)
1.20
4
HIGH SIDE
HS MINUS
SW
24ns (tpdh,DRVL )
11ns (tf,DRVH )
SW NODE
3
2
1.15
+125°C
1.10
1.05
+25°C
1.00
0.95
–40°C
0.90
0.85
0.80
M
M20ns
T 39.2%
A CH2
4.20V
0.70
2.7
09347-060
CH2 5V
CH3 5V
CH4 2V
MATH 2V 20ns
3.1
3.5
3.9
4.3
4.7
VREG (V)
Figure 60. Upper Side Driver Falling and Lower Side Rising Edge Waveforms
(CIN = 4.3 nF (Upper Side/Lower Side MOSFET),
QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3))
Rev. A | Page 17 of 44
Figure 63. Quiescent Current vs. VREG
5.1
5.5
09347-163
0.75
TA = 25°C
ADP1874/ADP1875
Data Sheet
ADP1874/ADP1875 BLOCK DIGRAM
PGOOD
690mV
FB
600mV
ADP1874/ADP1875
530mV
VREG
tON TIMER
PRECISION
ENABLE
VIN
C
EN
TO ENABLE
ALL BLOCKS
EN_REF
I
SW
INFORMATION
LDO
VREG
R (TRIMMED)
tON = 2RC(VOUT/VIN)
VREG_IN
REF
SW FILTER
VREG
BST
BIAS BLOCK
AND REFERENCE
STATE
MACHINE
REF_ZERO
TON
BG_REF
ISS
SS
COMP
SS
PSM
DRVH
300kΩ
IN_PSM HS_O
IN_SS
HS
SS_REF
IN_HICC
COMP
LEVEL
SHIFT
HS
SW
SW
8kΩ
FB
PWM
IREV
TRACK
LS
LS_O
VREG
LS
DRVL
800kΩ
ERROR
AMP
PGND
PWM
0.6V
IREV
COMP
CS
AMP
REF_ZERO
ADC
RES DETECT AND
GAIN SET
CS GAIN SET
0.4V
GND
RES
Figure 64. ADP1874/ADP1875 Block Diagram
Rev. A | Page 18 of 44
09347-063
LOWER
COMP
CLAMP
Data Sheet
ADP1874/ADP1875
THEORY OF OPERATION
PRECISION ENABLE CIRCUITRY
The ADP1874/ADP1875 have precision enable circuitry. The
precision enable threshold is 630 mV with 30 mV of hysteresis
(see Figure 65). Connecting the EN pin to GND disables the
ADP1874/ADP1875, reducing the supply current of the device
to approximately 140 µA.
VREG
10kΩ
EN
PRECISION
ENABLE COMP.
STARTUP
TO ENABLE
ALL BLOCKS
630mV
Figure 65. Connecting EN Pin to VREG via a Pull-Up Resistor to Enable the
ADP1874/ADP1875
COMP
The current-sense blocks provide valley current information
(see the Programming Resistor (RES) Detect Circuit section)
and are a variable of the compensation equation for loop stability
(see the Compensation Network section). The valley current
information is extracted by forcing a voltage across the RES and
PGND pins, which generates a current depending on the resistor
value across RES and PGND. The current through the resistor is
used to set the current-sense amplifier gain. This process takes
approximately 800 µs, after which the drive signal pulses appear
at the DRVL and DRVH pins synchronously, and the output
voltage begins to rise in a controlled manner through the soft
start sequence.
The rise time of the output voltage is determined by the soft
start and error amplifier blocks (see the Soft Start section). At
the beginning of a soft start, the error amplifier charges the
external compensation capacitor, causing the COMP pin to
begin to rise (see Figure 66). Tying the VREG pin to the EN pin
via a pull-up resistor causes the voltage at this pin to rise above the
enable threshold of 630 mV to enable the ADP1874/ADP1875.
SOFT START
The ADP1874 employs externally programmable, soft start
circuitry that charges up a capacitor tied to the SS pin to GND.
This prevents input in-rush current through the external MOSFET
from the input supply (VIN). The output tracks the ramping voltage
by producing PWM output pulses to the upper side MOSFET.
The purpose is to limit the in-rush current from the high
voltage input supply (VIN) to the output (VOUT).
2.4V
1.0V
MAXIMUM CURRENT (UPPER CLAMP)
ZERO CURRENT
USABLE RANGE ONLY AFTER SOFT START
PERIOD IF CONTUNUOUS CONDUCTION
MODE OF OPERATION IS SELECTED.
500mV
LOWER CLAMP
09347-065
The ADP1874/ADP1875 have an internal regulator (VREG) for
biasing and supplying power for the integrated MOSFET drivers.
A bypass capacitor should be located directly across the VREG
(Pin 7) and PGND (Pin 13) pins. Included in the power-up
sequence is the biasing of the current-sense amplifier, the currentsense gain circuit (see the Programming Resistor (RES) Detect
Circuit section), the soft start circuit, and the error amplifier.
09347-064
The ADP1874/ADP1875 are versatile current mode, synchronous
step-down controllers that provide superior transient response,
optimal stability, and current limit protection by using a constant
on-time, pseudo-fixed frequency with a programmable currentsense gain, current-control scheme. In addition, these devices offer
optimum performance at low duty cycles by using a valley, current
mode control architecture. This allows the ADP1874/ADP1875
to drive all N-channel power stages to regulate output voltages
to as low as 0.6 V.
0V
Figure 66. COMP Voltage Range
UNDERVOLTAGE LOCKOUT
The undervoltage lockout (UVLO) feature prevents the part
from operating both the upper side and lower side MOSFETs at
extremely low or undefined input voltage (VIN) ranges. Operation
at an undefined bias voltage may result in the incorrect propagation
of signals to the high-side power switches. This, in turn, results
in invalid output behavior that can cause damage to the output
devices, ultimately destroying the device tied at the output. The
UVLO level is set at 2.65 V (nominal).
Rev. A | Page 19 of 44
ADP1874/ADP1875
Data Sheet
ON-BOARD LOW DROPOUT REGULATOR
The ADP1874/ADP1875 use an on-board LDO to bias the
internal digital and analog circuitry. Connect the VREG and
VREG_IN pins together for normal LDO operation for low
voltage internal block biasing (see Figure 67).
ON-BOARD REGULATOR
VIN
VREG_IN
09347-168
REF
Q1
DRVH
Figure 67. Connecting VREG and VREG_IN Together
SW
With proper bypass capacitors connected to the VREG pin (output
of the internal LDO), this pin also provides power for the internal
MOSFET drivers. It is recommended to float VREG/VREG_IN
if VIN is used for greater than 5.5 V operation. The minimum
voltage where bias is guaranteed to operate is 2.75 V at VREG.
Q2
DRVL
RES
09347-066
VREG
The RES detect circuit digitizes the value of the resistor at the
RES pin (Pin 6). An internal ADC outputs a 2-bit digital code
that is used to program four separate gain configurations in the
current-sense amplifier (see Figure 69). Each configuration corresponds to a current-sense gain (ACS) of 3 V/V, 6 V/V, 12 V/V, or
24 V/V, respectively (see Table 6 and Table 7). This variable is used
for the valley current-limit setting, which sets up the appropriate
current-sense gain for a given application and sets the compensation
necessary to achieve loop stability (see the Valley Current-Limit
Setting section and the Compensation Network section).
CS GAIN
PROGRAMMING
Figure 68. Programming Resistor Location
SW
CS
AMP
For applications where VIN is decoupled from VREG, the
minimum voltage at VIN must be 2.9 V. It is recommended to tie
VIN and VREG together if the VIN pin is subjected to a 2.75 V rail.
PGND
CS GAIN
SET
ADC
0.4V
VREG/VREG_IN
Float
Connect to VIN
5.5 V
fSW
09347-076
PWM OUTPUT
VALLEY
TRIP POINTS
Figure 78. Load Transient Response Operation
POWER GOOD MONITORING
The ADP1874/ADP1875 power good circuitry monitors the
output voltage via the FB pin. The PGOOD pin is an open-drain
output that can be pulled up by an external resistor to a voltage
rail that does not necessarily have to be VREG. When the internal
NMOS switch is in high impedance (off state), this means that
the PGOOD pin is logic high, and the output voltage via the FB
pin is within the specified regulation window. When the internal
switch is turned on, PGOOD is internally pulled low when the
output voltage via the FB pin is outside this regulation window.
The power good window is defined with a typical upper
specification of +90 mV and a lower specification of −70 mV
below the FB voltage of 600 mV. When an overvoltage event occurs
at the output, there is a typical propagation delay of 12 µs prior
to the PGOOD pin deassertion (logic low). When the output
voltage re-enters the regulation window, there is a propagation
delay of 12 µs prior to PGOOD reasserting back to a logic high
state. When the output is outside the regulation window, the
PGOOD open drain switch is capable of sinking 1mA of current
and provides 140 mV of drop across this switch. The user is free
to tie the external pull-up resistor (RRES) to any voltage rail up to
20 V. The following equation provides the proper external pull-up
resistor value:
V − 140 mV
RPGD = EXT
1 mA
where:
RPGD is the PGOOD external resistor.
VEXT is a user-chosen voltage rail.
Because the ADP1874/ADP1875 have the ability to respond rapidly
to sudden changes in load demand, the recovery period in which
the output voltage settles back to its original steady state operating
point is much quicker than it would be for a fixed-frequency
equivalent. Therefore, using a pseudo-fixed frequency results in
significantly better load-transient performance compared to
using a fixed frequency.
VEXT
1mA
690mV
+
140mV
–
RPGD
PGOOD
FB
600mV
530mV
09347-180
To illustrate this feature more clearly, this section describes
one such load transient event—a positive load step—in detail.
During load transient events, the high-side driver output pulsewidth stays relatively consistent from cycle to cycle; however,
the off-time (DRVL on-time) dynamically adjusts according to
the instantaneous changes in the external conditions mentioned.
LOAD CURRENT
DEMAND
Figure 79. Power Good, Output Voltage Monitoring Circuit
Rev. A | Page 24 of 44
Data Sheet
ADP1874/ADP1875
OUTPUT OVERVOLTAGE
PGOOD DEASSERT
690mV
PGOOD
REASSERT
HYSTERESIS (50mV)
640mV
FB
600mV
530mV
0V
PGOOD
ASSERTION
AT POWER-UP
PGOOD
DEASSERTION
AT POWER DOWN
SOFT-START
VEXT
tPGD
tPGD
09347-181
tPGD
PGOOD
tPGD
0V
Figure 80. Power Good Timing Diagram, tPGD = 12 µs (Diagram May Look Disproportionate for Illustration Purposes.)
SLAVE
VREG 10kΩ
EN
MASTER
PGOOD
VREG 10kΩ
EN
1.8V VOUT1 (MASTER)
1.2V VOUT2 (SLAVE)
SS
FB
RBOT2
1kΩ
GND TRACK
PGND
CSS
FB
RTOP1
RTRK2
0.9V 1kΩ
RBOT1
RTRK1
1kΩ
GND
PGND
09347-182
RTOP2
1kΩ
VEXT
RPGD
Figure 81. Coincident Tracking Circuit Implementation
SLAVE
VREG 10kΩ
EN
MASTER
PGOOD
VREG 10kΩ
EN
2.5V VOUT1 (MASTER)
FB
RBOT2
1kΩ
SS
GND TRACK
PGND
CSS
FB
RTOP1
RTRK2
1.7V 500Ω
RBOT1
RTRK1
1kΩ
GND
PGND
09347-184
1.2V VOUT2 (SLAVE)
RTOP2
1kΩ
VEXT
RPGD
Figure 82. Ratiometric Tracking Circuit Implementation
Tracking is made possible by four inputs to the error amplifier,
three of which are input pins to the IC. The TRACK and SS pins
are positive inputs, and the FB pin provides the negative feedback
from the output voltage via the divider network. The fourth input
to the amplifier is the reference voltage of 0.6 V. The negative
feedback pin (FB pin) regulates the output voltage to the lowest
of the three positive inputs (TRACK, SS, and 0.6 V reference).
In all tracking configurations, the slave output can be set to as
low as 0.6 V for a given operating condition. The master voltage
must have a longer rise time than the slaves programmed soft start
period; otherwise, the tracking relationship will not be observed
at the slave output.
MASTER VOLTAGE
SLAVE VOLTAGE
TIME (ms)
09347-083
The ADP1874/ADP1875 feature a voltage-tracking function that
facilitates proper power-up sequencing in applications that require
tracking a master voltage. In this manner, the user is free to
impose a master voltage that typically comes with a selectable
or programmable ramp rate on slave or secondary power rails.
To impose any voltage tracking relationship, the master voltage
rise time must be longer than the slave voltage soft start period.
This is particularly important in applications such as I/O voltage
sequencing and core voltage applications where specific power
sequencing is required.
Coincident and ratiometric tracking are two possible tracking
configuration options offered by the ADP1874/ADP1875.
Coincident tracking is the most commonly used tracking
technique. It is primarily used in core and I/O sequencing
applications. The ramp rate of the master voltage is fully
imposed onto the ramp rate of the slave output voltage until it
has reached its regulation setpoint. Connecting the TRACK pin,
by differentially tapping onto the master voltage via a resistive
divider of similar ratio to the slave feedback divider network,
is depicted in Figure 83.
OUTPUT VOLTAGE (V)
VOLTAGE TRACKING
Figure 83. Coincident Tracking: Master Voltage—Slave Voltage Tracking
Relationship
Rev. A | Page 25 of 44
ADP1874/ADP1875
Data Sheet
not recommended to force any voltage on the slave TRACK pin
lower than 0.6 V. Figure 84 illustrates a circuit with a ratiometric
tracking configuration. Setting RTRK1 > RTRK2 ensures that the
slave TRACK voltage will rise up more quickly (to the regulation
point) than the master voltage.
MASTER VOLTAGE
SLAVE VOLTAGE
TIME (ms)
09347-085
OUTPUT VOLTAGE (V)
The slave output tracks the master output dv/dt until the slave
output regulation point is reached. Any influence by the master
voltage thereafter will no longer be in effect. Ensure that the voltage
forced on the slave TRACK pin is above 0.7 V at the end of TRACK
phase. Voltages imposed on the TRACK pin below 0.7 V, once
that tracking period has expired (steady state), may result in
regulation inaccuracies due to the internal offsets of the error
amplifier between TRACK and FB. Ratiometric tracking can be
achieved by assigning the slave output to rise more quickly than
the master voltage. The simplest way to perform ratiometric
tracking is to differentially connect the slave TRACK pin to the
FB pin of the master voltage IC. The slave output, however, must
be limited to a fraction of the master voltage. In this tracking
configuration, it is not recommended for the slave TRACK pin
to terminate at a voltage lower than 0.6 V due to inaccuracies
between the TRACK and FB inputs previously mentioned. It is
Figure 84. Ratiometric Tracking: Master Voltage—Slave Voltage Tracking
Relationship
Rev. A | Page 26 of 44
Data Sheet
ADP1874/ADP1875
APPLICATIONS INFORMATION
Table 8. Recommended Inductors
FEEDBACK RESISTOR DIVIDER
INDUCTOR SELECTION
L
(µH)
0.12
0.22
0.47
0.72
0.9
1.2
1.0
1.4
2.0
0.8
The inductor value is inversely proportional to the inductor
ripple current. The peak-to-peak ripple current is given by
OUTPUT RIPPLE VOLTAGE (ΔVRR)
The required resistor divider network can be determined for a
given VOUT value because the internal band gap reference (VREF)
is fixed at 0.6 V. Selecting values for RT and RB determines the
minimum output load current of the converter. Therefore, for
a given value of RB, the RT value can be determined through the
following expression:
RT = RB ×
(VOUT − 0.6 V)
0. 6 V
∆I L = K I × I LOAD ≈
I LOAD
The equation for the inductor value is given by
(V IN − VOUT ) VOUT
×
∆I L × f SW
V IN
Dimensions
(mm)
10.2 × 7
10.2 × 7
14.2 × 12.8
10.5 × 10.2
14 × 12.8
10.5 × 10.2
10.2 × 10.2
14 × 12.8
10.2 × 10.2
Manufacturer
Würth Elek.
Würth Elek.
Würth Elek.
Würth Elek.
Würth Elek.
Würth Elek.
Würth Elek.
Würth Elek.
Würth Elek.
Sumida
Model
Number
744303012
744303022
744355147
744325072
744318120
744325120
7443552100
744318180
7443551200
CEP125U-0R8
ΔVRR = (0.01) × VOUT
where:
VIN is the high voltage input.
VOUT is the desired output voltage.
fSW is the controller switching frequency (300 kHz, 600 kHz,
or 1.0 MHz).
OUTPUT CAPACITOR SELECTION
When selecting the inductor, choose an inductor saturation
rating that is above the peak current level, and then calculate
the inductor current ripple (see the Valley Current-Limit
Setting section and Figure 85).
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
ΔI = 50%
ΔI = 40%
The primary objective of the output capacitor is to facilitate the
reduction of the output voltage ripple; however, the output capacitor
also assists in the output voltage recovery during load transient
events. For a given load current step, the output voltage ripple
generated during this step event is inversely proportional to the
value chosen for the output capacitor. The speed at which the
output voltage settles during this recovery period depends on
where the crossover frequency (loop bandwidth) is set. This
crossover frequency is determined by the output capacitor, the
equivalent series resistance (ESR) of the capacitor, and the
compensation network.
To calculate the small signal voltage ripple (output ripple voltage) at
the steady state operating point, use the following equation:
1
C OUT = ∆I L ×
8 × f SW × [∆V RIPPLE − (∆I L × ESR)]
ΔI = 33%
where ESR is the equivalent series resistance of the output
capacitors.
To calculate the output load step, use the following equation:
6
8
10
12
14
16
18
20
22
VALLEY CURRENT LIMIT (A)
24
26
28
30
09347-077
PEAK INDUCTOR CURRENT (A)
ISAT
(A)
55
30
50
35
32
25
16
24
23
27.5
The output ripple voltage is the ac component of the dc output
voltage during steady state. For a ripple error of 1.0%, the output
capacitor value needed to achieve this tolerance can be determined
using the following equation. (Note that an accuracy of 1.0% is
only possible during steady state conditions, not during load
transients.)
3
where KI is typically 0.33.
L=
DCR
(mΩ)
0.33
0.33
0.8
1.65
1.6
1.8
3.8
3.2
2.0
Figure 85. Peak Inductor Current vs. Valley Current Limit for 33%, 40%, and
50% of Inductor Ripple Current
C OUT = 2 ×
∆I LOAD
f SW × (∆V DROOP − (∆I LOAD × ESR))
where ΔVDROOP is the amount that VOUT is allowed to deviate for
a given positive load current step (ΔILOAD).
Rev. A | Page 27 of 44
ADP1874/ADP1875
Data Sheet
Ceramic capacitors are known to have low ESR. However, there
is a trade-off in using the popular X5R capacitor technology
because up to 80% of its capacitance may be lost due to derating
as the voltage applied across the capacitor is increased (see
Figure 86). Although X7R series capacitors can also be used, the
available selection is limited to 22 µF maximum.
Error Amplifier Output Impedance (ZCOMP)
Assuming that CC2 is significantly smaller than CCOMP, CC2 can
be omitted from the output impedance equation of the error
amplifier. The transfer function simplifies to
ZCOMP =
RCOMP
× fCROSS 2 + f ZERO 2
fCROSS
fCROSS =
1
× f SW
12
20
and
10
X7R (50V)
–10
–20
where fZERO, the zero frequency, is set to be 1/4 the crossover
frequency for the ADP1874.
–30
–40
–50
Error Amplifier Gain (Gm)
X5R (25V)
–60
The error amplifier gain (transconductance) is
–70
X5R (16V)
–80
Gm = 500 µA/V (µs)
10µF TDK 25V, X7R, 1210 C3225X7R1E106M
22µF MURATA 25V, X7R, 1210 GRM32ER71E226KE15L
47µF MURATA 16V, X5R, 1210 GRM32ER61C476KE15L
–90
–100
0
5
10
15
20
25
Current-Sense Loop Gain (GCS)
30
DC VOLTAGE (VDC)
09347-078
CAPACITANCE CHARGE (%)
0
The current-sense loop-gain is
Figure 86. Capacitance vs. DC Voltage Characteristics for Ceramic Capacitors
Electrolytic capacitors satisfy the bulk capacitance requirements
for most high current applications. However, because the ESR
of electrolytic capacitors is much higher than that of ceramic
capacitors, several MLCCs should be mounted in parallel with
the electrolytic capacitors to reduce the overall series resistance.
COMPENSATION NETWORK
Due to its current-mode architecture, the ADP1874/ADP1875
require Type II compensation. To determine the component
values needed for compensation (resistance and capacitance
values), it is necessary to examine the converter’s overall loop
gain (H) at the unity gain frequency (fSW/10) when H = 1 V/V.
H = 1 V/V = GM × GCS ×
VREF
× ZCOMP × Z FILT
VOUT
G CS =
where:
ACS (V/V) is programmable for 3 V/V, 6 V/V, 12 V/V, and 24 V/V
(see the Programming Resistor (RES) Detect Circuit and Valley
Current-Limit Setting sections).
RON is the channel impedance of the lower side MOSFET.
Crossover Frequency
The crossover frequency is the frequency at which the overall
loop (system) gain is 0 dB (H = 1 V/V). It is recommended for
current-mode converters, such as the ADP1874, that the user
set the crossover frequency between 1/10 and 1/15 the
switching frequency.
fCROSS =
Examining each variable at high frequency enables the unitygain transfer function to be simplified to provide expressions
for the RCOMP and CCOMP component values.
f ZERO =
Examining the filter’s transfer function at high frequencies
simplifies to
1
f SW
12
The relationship between CCOMP and fZERO (zero frequency) is as
follows:
Output Filter Impedance (ZFILT)
Z FILTER = RL ×
1
(A/V)
ACS × RON
1
2π × RCOMP × CCOMP
The zero frequency is set to 1/4 the crossover frequency.
1 + s × ESR × COUT
1 + s(RL + ESR)COUT
Combining all of the above parameters results in
RCOMP =
at the crossover frequency (s = 2πfCROSS). ESR is the equivalent
series resistance of the output capacitors.
fCROSS
fCROSS + f ZERO
2
2
×
12 + (s(RL + ESR)COUT )2
12 + (s × ESR × COUT )2
×
1 VOUT
1
×
×
RL VREF GM GCS
where ESR is the equivalent series resistance of the output
capacitors.
C COMP =
Rev. A | Page 28 of 44
1
2 × π × R COMP × f ZERO
Data Sheet
ADP1874/ADP1875
EFFICIENCY CONSIDERATION
MOSFET Driver Loss
One of the important criteria to consider in constructing a dc-to-dc
converter is efficiency. By definition, efficiency is the ratio of the
output power to the input power. For high power applications at
load currents up to 20 A, the following are important MOSFET
parameters that aid in the selection process:
Other dissipative elements are the MOSFET drivers. The contributing factors are the dc current flowing through a driver
during operation and the QGATE parameter of the external MOSFETs.
•
•
•
The following are the losses experienced through the external
component during normal switching operation:
•
•
•
•
•
[VREG × ( f SW C lowerFET VREG + I BIAS )]
where:
CupperFET is the input gate capacitance of the upper side MOSFET.
ClowerFET is the input gate capacitance of the lower side MOSFET.
IBIAS is the dc current flowing into the upper side and lower side
drivers.
VDR is the driver bias voltage (that is, the low input voltage
(VREG) minus the rectifier drop (see Figure 87)).
VREG is the bias voltage.
800
Channel conduction loss (both the MOSFETs)
MOSFET driver loss
MOSFET switching loss
Body diode conduction loss (lower side MOSFET)
Inductor loss (copper and core loss)
640
During normal operation, the bulk of the loss in efficiency is due
to the power dissipated through MOSFET channel conduction.
Power loss through the upper side MOSFET is directly proportional to the duty-cycle (D) for each switching period, and
the power loss through the lower side MOSFET is directly
proportional to 1 − D for each switching period. The selection
of MOSFETs is governed by the maximum dc load current that
the converter is expected to deliver. In particular, the selection
of the lower side MOSFET is dictated by the maximum load
current because a typical high current application employs duty
cycles of less than 50%. Therefore, the lower side MOSFET is
in the on state for most of the switching period.
[
]
VREG = 2.7V
VREG = 3.6V
VREG = 5.5V
720
Channel Conduction Loss
2
PN1,N2(CL) = D × RN1(ON) + (1 − D ) × RN2(ON) × I LOAD
)]
(
560
480
400
320
240
+125°C
+25°C
–40°C
160
80
300
400
500
600
700
800
900
1000
SWITCHING FREQUENCY (kHz)
09347-079
•
VGS (TH) is the MOSFET voltage applied between the gate
and the source that starts channel conduction.
RDS (ON) is the MOSFET on resistance during channel
conduction.
QG is the total gate charge.
CN1 is the input capacitance of the upper side switch.
CN2 is the input capacitance of the lower side switch.
RECTIFIER DROP (mV)
•
[
PDR( LOSS ) = V DR × f SW C upperFET V DR + I BIAS +
Figure 87. Internal Rectifier Voltage Drop vs. Switching Frequency
Switching Loss
The SW node transitions due to the switching activities of the
upper side and lower side MOSFETs. This causes removal and
replenishing of charge to and from the gate oxide layer of the
MOSFET, as well as to and from the parasitic capacitance
associated with the gate oxide edge overlap and the drain and
source terminals. The current that enters and exits these charge
paths presents additional loss during these transition times.
This can be approximately quantified by using the following
equation, which represents the time in which charge enters and
exits these capacitive regions:
tSW-TRANS = RGATE × CTOTAL
where:
CTOTAL is the CGD + CGS of the external MOSFET.
RGATE is the gate input resistance of the external MOSFET.
The ratio of this time constant to the period of one switching cycle
is the multiplying factor to be used in the following expression:
PSW ( LOSS ) =
t SW -TRANS
× I LOAD × VIN × 2
t SW
or
PSW(LOSS) = fSW × RGATE × CTOTAL × ILOAD × VIN × 2
Rev. A | Page 29 of 44
ADP1874/ADP1875
Data Sheet
Diode Conduction Loss
INPUT CAPACITOR SELECTION
The ADP1874/ADP1875 employ anti cross-conduction circuitry
that prevents the upper side and lower side MOSFETs from
conducting current simultaneously. This overlap control is
beneficial, avoiding large current flow that may lead to irreparable
damage to the external components of the power stage. However,
this blanking period comes with the trade-off of a diode
conduction loss occurring immediately after the MOSFET
change states and continuing well into idle mode. The amount of
loss through the body diode of the lower side MOSFET during
the anti-overlap state is given by the following expression:
The goal in selecting an input capacitor is to reduce or minimize
input voltage ripple and to reduce the high frequency source
impedance, which is essential for achieving predictable loop
stability and transient performance.
PBODY ( LOSS) =
t BODY ( LOSS)
t SW
× I LOAD × V F × 2
where:
tBODY(LOSS) is the body conduction time (see Figure 88 for dead
time periods).
tSW is the period per switching cycle.
VF is the forward drop of the body diode during conduction.
(See the selected external MOSFET data sheet for more
information about the VF parameter.)
If bulk electrolytic capacitors are used, it is recommended to use
multilayered ceramic capacitors (MLCC) in parallel due to their
low ESR values. This dramatically reduces the input voltage ripple
amplitude as long as the MLCCs are mounted directly across the
drain of the upper side MOSFET and the source terminal of the
lower side MOSFET (see the Layout Considerations section).
Improper placement and mounting of these MLCCs may cancel
their effectiveness due to stray inductance and an increase in
trace impedance.
+125°C
+25°C
–40°C
1MHz
300kHz
72
64
VOUT
The maximum input voltage ripple and maximum input capacitor
rms current occur at the end of the duration of 1 − D while the
upper side MOSFET is in the off state. The input capacitor rms
current reaches its maximum at Time D. When calculating the
maximum input voltage ripple, account for the ESR of the input
capacitor as follows:
56
48
40
32
VMAX,RIPPLE = VRIPP + (ILOAD,MAX × ESR)
24
16
8
2.7
VOUT × (V IN − VOUT )
I CIN , RMS = I LOAD , MAX ×
3.4
4.1
VREG (V)
4.8
5.5
09347-080
BODY DIODE CONDUCTION TIME (ns)
80
The problem with using bulk capacitors, other than their physical
geometries, is their large equivalent series resistance (ESR) and
large equivalent series inductance (ESL). Aluminum electrolytic
capacitors have such high ESR that they cause undesired input
voltage ripple magnitudes and are generally not effective at high
switching frequencies.
Figure 88. Body Diode Conduction Time vs. Low Voltage Input (VREG)
Inductor Loss
During normal conduction mode, further power loss is caused
by the conduction of current through the inductor windings,
which have dc resistance (DCR). Typically, larger sized inductors
have smaller DCR values.
The inductor core loss is a result of the eddy currents generated
within the core material. These eddy currents are induced by the
changing flux, which is produced by the current flowing through
the windings. The amount of inductor core loss depends on the
core material, the flux swing, the frequency, and the core volume.
Ferrite inductors have the lowest core losses, whereas powdered iron
inductors have higher core losses. It is recommended to use shielded
ferrite core material type inductors with the ADP1874/ADP1875
for a high current, dc-to-dc switching application to achieve
minimal loss and negligible electromagnetic interference (EMI).
where:
VRIPP is usually 1% of the minimum voltage input.
ILOAD,MAX is the maximum load current.
ESR is the equivalent series resistance rating of the input capacitor.
Inserting VMAX,RIPPLE into the charge balance equation to
calculate the minimum input capacitor requirement gives
C IN,min =
I LOAD , MAX
V MAX , RIPPLE
×
D(1 − D)
f SW
or
C IN,min =
I LOAD , MAX
4 f SW V MAX , RIPPLE
where D = 50%.
2
+ Core Loss
PDCR( LOSS ) = DCR × I LOAD
Rev. A | Page 30 of 44
Data Sheet
ADP1874/ADP1875
THERMAL CONSIDERATIONS
The ADP1874/ADP1875 are used for dc-to-dc, step down, high
current applications that have an on-board controller, an on-board
LDO, and on-board MOSFET drivers. Because applications may
require up to 20 A of load current and be subjected to high ambient
temperature, the selection of external upper side and lower side
MOSFETs must be associated with careful thermal consideration
to not exceed the maximum allowable junction temperature of
125°C. To avoid permanent or irreparable damage, if the junction
temperature reaches or exceeds 155°C, the part enters thermal
shutdown, turning off both external MOSFETs and is not reenabled until the junction temperature cools to 140°C (see the
On-Board Low Dropout Regulator section).
In addition, it is important to consider the thermal impedance
of the package. Because the ADP1874/ADP1875 employ an
on-board LDO, the ac current (fxCxV) consumed by the internal
drivers to drive the external MOSFETs, adds another element of
power dissipation across the internal LDO. Equation 3 shows the
power dissipation calculations for the integrated drivers and for
the internal LDO.
Table 9 lists the thermal impedance for the ADP1874/ADP1875,
which are available in a 16-lead QSOP.
Table 9. Thermal Impedance for 16-lead QSOP
Parameter
16-Lead QSOP θJA
4-Layer Board
Thermal Impedance
104°C/W
Figure 89 specifies the maximum allowable ambient temperature
that can surround the ADP1874/ADP1875 IC for a specified
high input voltage (VIN). Figure 89 illustrates the temperature
derating conditions for each available switching frequency for
low, typical, and high output setpoints for the 16-lead QSOP
package. All temperature derating criteria are based on a
maximum IC junction temperature of 125°C.
150
600kHz
300kHz
1MHz
VOUT = 0.8V
VOUT = 1.8V
VOUT = HIGH SETPOINT
130
TJ = TR × TA
(1)
where:
TJ is the maximum junction temperature.
TR is the rise in package temperature due to the power
dissipated from within.
TA is the ambient temperature.
The rise in package temperature is directly proportional to its
thermal impedance characteristics. The following equation
represents this proportionality relationship:
TR = θJA × PDR(LOSS)
(2)
where:
θJA is the thermal resistance of the package from the junction to
the outside surface of the die, where it meets the surrounding air.
PDR(LOSS) is the overall power dissipated by the IC.
The bulk of the power dissipated is due to the gate capacitance of
the external MOSFETs and current running through the on-board
LDO. The power loss equations for the MOSFET drivers and
internal low dropout regulator (see the MOSFET Driver Loss
section and the Efficiency Consideration section) are
PDR(LOSS) = [VDR × (fSWCupperFETVDR + IBIAS)] +
[VREG × (fSWClowerFET VREG + IBIAS)]
(3)
where:
CupperFET is the input gate capacitance of the upper side MOSFET.
ClowerFET is the input gate capacitance of the lower side MOSFET.
IBIAS is the dc current (2 mA) flowing into the upper side and
lower side drivers.
VDR is the driver bias voltage (the low input voltage (VREG) minus
the rectifier drop (see Figure 87)).
VREG is the LDO output/bias voltage.
120
PDISS( LDO ) =
110
PDR( LOSS ) + (V IN − VREG) × ( f SW × C TOTAL × VREG + I BIAS )
100
90
80
70
60
50
40
30
5.5
7.0
8.5
10.0
11.5
13.0
14.5
16.0
17.5
19.0
VIN (V)
09347-183
MAXIMUM ALLOWABLE AMBIENT
TEMPERATURE (°C)
140
The maximum junction temperature allowed for the ADP1874/
ADP1875 ICs is 125°C. This means that the sum of the ambient
temperature (TA) and the rise in package temperature (TR), which is
caused by the thermal impedance of the package and the internal
power dissipation, should not exceed 125°C, as dictated by the
following expression:
where:
PDISS(LDO) is the power dissipated through the pass device in the
LDO block across VIN and VREG.
PDR(LOSS) is the MOSFET driver loss.
VIN is the high voltage input.
VREG is the LDO output voltage and bias voltage.
CTOTAL is the CGD + CGS of the external MOSFET.
IBIAS is the dc input bias current.
Figure 89. Ambient Temperature vs. VIN,
4-Layer EVB, CIN = 4.3 nF (Upper Side/Lower Side MOSFET)
Rev. A | Page 31 of 44
(4)
ADP1874/ADP1875
Data Sheet
For example, if the external MOSFET characteristics are θJA
(16-lead QSOP) = 104°C/W, fSW = 300 kHz, IBIAS = 2 mA, CupperFET =
3.3 nF, ClowerFET = 3.3 nF, VDR = 4.62 V, and VREG = 5.0 V, then the
power loss is
[
(
)]
PDR( LOSS ) = V DR × f SW C upperFET V DR + I BIAS +
[VREG × ( f SW C lowerFET VREG + I BIAS )]
Inductor
Determine inductor ripple current amplitude as follows:
∆I L ≈
Therefore, calculating for the inductor value
= (4.62 × (300 × 10 3 × 3.3 × 10 −9 × 4.62 + 0.002)) +
L=
(5.0 × (300 × 10 3 × 3.3 × 10 −9 × 5.0 + 0.002))
= 57.12 mW
=
= (13 V − 5 V) × (300 × 10 3 × 3.3 × 10 −9 × 5 + 0.002)
3
×
VOUT
V IN,MAX
1. 8 V
13.2 V
Therefore, an appropriate inductor selection is 1.0 µH with
DCR = 3.3 mΩ (Würth Elektronik 7443552100) from Table 10
with peak current handling of 20 A.
= 77.13 mW + 55.6 mW
= 132.73 mW
The rise in package temperature (for 16-lead QSOP) is
PDCR( LOSS ) = DCR × I L2
TR = θ JA × PDR( LOSS )
= 0.003 × (15 A)2 = 675 mW
= 104°C × 132.05 mW
Current Limit Programming
= 13.7°C
Assuming a maximum ambient temperature environment of 85°C,
TJ = TR × TA = 13.7°C + 85°C = 98.7°C
which is below the maximum junction temperature of 125°C.
DESIGN EXAMPLE
The ADP1874/ADP1875 are easy to use, requiring only a few
design criteria. For example, the example outlined in this section
uses only four design criteria: VOUT = 1.8 V, ILOAD = 15 A (pulsing),
VIN = 12 V (typical), and fSW = 300 kHz.
Input Capacitor
VRIPP = 120 mV
VMAX,RIPPLE = VRIPP − (ILOAD,MAX × ESR)
= 120 mV − (15 A × 0.001) = 45 mV
=
The valley current is approximately
15 A − (5 A × 0.5) = 12.5 A
Assuming a lower side MOSFET RON of 4.5 mΩ and 13 A as
the valley current limit from Table 7 and Figure 71 indicates, a
programming resistor (RES) of 100 kΩ corresponds to an ACS
of 24 V/V.
Choose a programmable resistor of RRES = 100 kΩ for a currentsense gain of 24 V/V.
Output Capacitor
Assume that a load step of 15 A occurs at the output and no more
than 5% output deviation is allowed from the steady state
operating point. In this case, the ADP1874 advantage is that,
because the frequency is pseudo-fixed, the converter is able to
respond quickly because of the immediate, though temporary,
increase in switching frequency.
The maximum input voltage ripple is usually 1% of the
minimum input voltage (11.8 V × 0.01 = 120 mV).
ΔVDROOP = 0.05 × 1.8 V = 90 mV
15 A
Assuming that the overall ESR of the output capacitor ranges
from 5 mΩ to 10 mΩ,
4 × 300 × 103 × 105 mV
= 120 µF
C OUT = 2 ×
Choose five 22 µF ceramic capacitors. The overall ESR of five
22 µF ceramic capacitors is less than 1 mΩ.
= 2×
IRMS = ILOAD/2 = 7.5 A
2
(13.2 V − 1.8 V)
×
15 A + (5 A × 0.5) = 17.5 A
PDISS(TOTAL ) = PDISS( LDO ) + PDR( LOSS )
4 f SWVMAX , RIPPLE
∆I L × f SW
The inductor peak current is approximately
= 55.6 mW
CIN,min =
(V IN,MAX − VOUT )
5 V × 300 × 10
= 1.03 µH
PDISS( LDO ) = (V IN − VREG) × ( f SW × C total × VREG + I BIAS )
I LOAD , MAX
I LOAD
=5A
3
∆I LOAD
f SW × (∆VDROOP )
15 A
300 × 10 3 × (90 mV)
= 1.11 mF
2
PCIN = (IRMS) × ESR = (7.5 A) × 1 mΩ = 56.25 mW
Therefore, an appropriate inductor selection is five 270 µF
polymer capacitors with a combined ESR of 3.5 mΩ.
Rev. A | Page 32 of 44
Data Sheet
ADP1874/ADP1875
Assuming an overshoot of 45 mV, determine if the output
capacitor that was calculated previously is adequate.
C OUT =
=
(L × I
2
CCOMP =
LOAD )
((VOUT − ∆VOVSHT )2 − (VOUT )2 )
=
1
2πRCOMP f ZERO
1
2 × 3.14 × 60.25 × 103 × 6.25 × 103
1× 10 −6 × (15 A) 2
= 423 pF
(1.8 − 45 mV) 2 − (1.8) 2
Loss Calculations
= 1.4 mF
Duty cycle = 1.8/12 V = 0.15
Choose five 270 µF polymer capacitors.
RON (N2) = 5.4 mΩ
The rms current through the output capacitor is
tBODY(LOSS) = 20 ns (body conduction time)
I RMS
1 1 (V IN , MAX − VOUT ) VOUT
= ×
×
L × f SW
V IN , MAX
2
3
VF = 0.84 V (MOSFET forward voltage)
CIN = 3.3 nF (MOSFET gate input capacitance)
1 1 (13.2 V − 1.8 V) 1.8 V
= ×
×
= 1.49 A
2
3 1 μF × 300 × 10 3 13.2 V
QN1,N2 = 17 nC (total MOSFET gate charge)
RGATE = 1.5 Ω (MOSFET gate input resistance)
[
The power loss dissipated through the ESR of the output
capacitor is
= (0.15 × 0.0054 + 0.85 × 0.0054) × (15 A)2
= 1.215 W
PCOUT = (IRMS)2 × ESR = (1.5 A)2 × 1.4 mΩ = 3.15 mW
Feedback Resistor Network Setup
PBODY ( LOSS ) =
(1.8 V − 0.6 V)
0. 6 V
= 2 kΩ
PSW(LOSS) = fSW × RGATE × CTOTAL × ILOAD × VIN × 2
= 300 × 103 × 1.5 Ω × 3.3 × 10−9 × 15 A × 12 × 2
= 534.6 mW
Compensation Network
To calculate RCOMP, CCOMP, and CPAR, the transconductance
parameter and the current-sense gain variable are required. The
transconductance parameter (Gm) is 500 µA/V, and the currentsense loop gain is
G CS
[
[VREG × ( f SW C lowerFET VREG + I BIAS )]
(5.0 × (300 × 10 3 × 3.3 × 10 −9 × 5.0 + 0.002))
= 57.12 mW
PDISS( LDO ) = (V IN − VREG) × ( f SW × C total × VREG + I BIAS )
= (13 V − 5 V) × (300 × 10 3 × 3.3 × 10 −9 × 5 + 0.002)
The crossover frequency is 1/12 the switching frequency.
= 55.6 mW
300 kHz/12 = 25 kHz
PCOUT = (IRMS)2 × ESR = (1.5 A)2 × 1.4 mΩ = 3.15 mW
The zero frequency is 1/4 the crossover frequency.
2
= 0.003 × (15 A)2 = 675 mW
PDCR( LOSS) = DCR × I LOAD
25 kHz/4 = 6.25 kHz
RCOMP =
f CROSS 2 + f ZERO 2
RCOMP =
25K
12 + (s(R L + ESR)C OUT )2
1 + (s × ESR × COUT )
2
×
25k 2 + 6.25k 2
1. 8
1
15
×
×
0.6 500 × 10 −6 × 8.3 1.8
)]
= (4.62 × (300 × 10 3 × 3.3 × 10 −9 × 4.62 + 0.002)) +
where ACS and RON are taken from setting up the current limit
(see the Programming Resistor (RES) Detect Circuit section
and the Valley Current-Limit Setting section).
×
(
PDR( LOSS ) = V DR × f SW C upperFET V DR + I BIAS +
1
1
=
=
= 8.33 A/V
ACS × RON 24 × 0.005
f CROSS
t BODY ( LOSS )
× I LOAD × VF × 2
t SW
= 20 ns × 300 × 103 × 15 A × 0.84 × 2
= 151.2 mW
Choosing RB = 1 kΩ as an example, calculate RT as follows:
RT = 1 kΩ ×
]
2
PN1,N2(CL) = D × RN1(ON) + (1 − D ) × RN2(ON) × I LOAD
2
PCIN = (IRMS)2 × ESR = (7.5 A)2 × 1 mΩ = 56.25 mW
×
1 VOUT
1
×
×
R L VREF G M GCS
12 + (2 π × 25k × ((1.8 15) + 0.0035) × 0.0011)2
12 + (2 π × 25k × 0.0035 × 0.0011)2
×
= 60.25 kΩ
Rev. A | Page 33 of 44
PLOSS = PN1,N2 + PBODY(LOSS) + PSW + PDCR + PDR + PDISS(LDO) +
PCOUT + PCIN
= 1.215 W + 151.2 mW + 534.6 mW + 57.12 mW + 55.6 +
3.15 mW + 675 mW + 56.25 mW
= 2.655 W
ADP1874/ADP1875
Data Sheet
EXTERNAL COMPONENT RECOMMENDATIONS
The configurations listed in Table 10 are with fCROSS = 1/12 × fSW, fZERO = ¼ × fCROSS, RRES = 100 kΩ, RBOT = 1 kΩ, RON = 5.4 mΩ (BSC042N03MS G),
VREG = 5 V (float), and a maximum load current of 14 A.
The ADP1875 models listed in Table 10 are the PSM versions of the device.
Table 10. External Component Values
Marking Code
(First Line/Second Line)
SAP Model
ADP1874ARQZ-0.3-R7/
ADP1875ARQZ-0.3-R7
ADP1874ARQZ-0.6-R7/
ADP1875ARQZ-0.6-R7
ADP1874
1874/0.3
1874/0.3
1874/0.3
1874/0.3
1874/0.3
1874/0.3
1874/0.3
1874/0.3
1874/0.3
1874/0.3
1874/0.3
1874/0.3
1874/0.3
1874/0.6
1874/0.6
1874/0.6
1874/0.6
1874/0.6
1874/0.6
1874/0.6
1874/0.6
1874/0.6
1874/0.6
1874/0.6
1874/0.6
1874/0.6
1874/0.6
1874/0.6
ADP1875
1875/0.3
1875/0.3
1875/0.3
1875/0.3
1875/0.3
1875/0.3
1875/0.3
1875/0.3
1875/0.3
1875/0.3
1875/0.3
1875/0.3
1875/0.3
1875/0.6
1875/0.6
1875/0.6
1875/0.6
1875/0.6
1875/0.6
1875/0.6
1875/0.6
1875/0.6
1875/0.6
1875/0.6
1875/0.6
1875/0.6
1875/0.6
1875/0.6
VOUT
(V)
0.8
1.2
1.8
2.5
3.3
5
7
1.2
1.8
2.5
3.3
5
7
0.8
1.2
1.8
2.5
1.2
1.8
2.5
3.3
5
1.2
1.8
2.5
3.3
5
7
VIN
(V)
13
13
13
13
13
13
13
16.5
16.5
16.5
16.5
16.5
16.5
5.5
5.5
5.5
5.5
13
13
13
13
13
16.5
16.5
16.5
16.5
16.5
16.5
CIN
(µF)
5 × 22 2
5 × 222
4 × 222
4 × 222
5 × 222
4 × 222
4 × 222
4 × 222
3 × 222
3 × 222
3 × 222
3 × 222
3 × 222
5 × 222
5 × 222
5 × 222
5 × 222
3 × 222
5 × 10 9
5 × 109
5 × 109
5 × 109
3 × 109
4 × 109
4 × 109
4 × 109
4 × 109
4 × 109
Rev. A | Page 34 of 44
COUT (µF)
5 × 560 3
4 × 5603
4 × 270 4
3 × 2704
2 × 330 5
3305
222 + ( 4 × 47 6)
4 × 5603
4 × 2704
4 × 2704
2 × 3305
2 × 150 7
222 + 4 × 476
4 × 5603
4 × 2704
3 × 2704
3 × 180 8
5 × 2704
3 × 3305
3 × 2704
2 × 2704
1507
4 × 2704
2 × 3305
3 × 2704
3305
4 × 476
3 × 476
L1
(µH)
0.72
1.0
1.2
1.53
2.0
3.27
3.44
1.0
1.0
1.67
2.00
3.84
4.44
0.22
0.47
0.47
0.47
0.47
0.47
0.90
1.00
1.76
0.47
0.72
0.90
1.0
2.0
2.0
RC
(kΩ)
56.9
56.9
56.9
57.6
56.9
40.7
40.7
56.9
56.9
57.6
56.9
41.2
40.7
56.2
56.9
56.9
56.9
56.9
56.2
57.6
57.6
40.7
56.9
53.6
57.6
53.0
41.2
40.7
CCOMP
(pF)
620
620
470
470
470
680
680
620
470
470
510
680
680
300
270
220
220
360
270
240
240
360
300
270
270
270
360
300
CPAR
(pF)
62
62
47
47
47
68
68
62
47
47
51
68
68
300
27
22
22
36
27
24
24
36
30
27
27
27
36
30
RTOP
(kΩ)
0.3
1.0
2.0
3.2
4.5
7.3
10.7
1.0
2.0
3.2
4.5
7.3
10.7
0.3
1.0
2.0
3.2
1.0
2.0
3.2
4.5
7.3
1.0
2.0
3.2
4.5
7.3
10.7
Data Sheet
ADP1874/ADP1875
Marking Code
(First Line/Second Line)
SAP Model
ADP1874ARQZ-1.0-R7/
ADP1875ARQZ-1.0-R7
ADP1874
1874/1.0
1874/1.0
1874/1.0
1874/1.0
1874/1.0
1874/1.0
1874/1.0
1874/1.0
1874/1.0
1874/1.0
1874/1.0
1874/1.0
1874/1.0
1874/1.0
1874/1.0
ADP1875
1875/1.0
1875/1.0
1875/1.0
1875/1.0
1875/1.0
1875/1.0
1875/1.0
1875/1.0
1875/1.0
1875/1.0
1875/1.0
1875/1.0
1875/1.0
1875/1.0
1875/1.0
VOUT
(V)
0.8
1.2
1.8
2.5
1.2
1.8
2.5
3.3
5
1.2
1.8
2.5
3.3
5
7
VIN
(V)
5.5
5.5
5.5
5.5
13
13
13
13
13
16.5
16.5
16.5
16.5
16.5
16.5
CIN
(µF)
5 × 222
5 × 222
3 × 222
3 × 222
3 × 109
4 × 109
4 × 109
5 × 109
4 × 109
3 × 109
3 × 109
4 × 109
4 × 109
3 × 109
3 × 109
L1
(µH)
0.22
0.22
0.22
0.22
0.22
0.47
0.47
0.72
1.0
0.47
0.47
0.72
0.72
1.2
1.2
COUT (µF)
4 × 2704
2 × 3305
3 × 1808
2704
3 × 3305
3 × 2704
2704
2704
3 × 476
4 × 2704
3 × 2704
3 × 1808
2704
3 × 476
222 + 476
RC
(kΩ)
54.9
49.3
56.9
54.9
53.6
56.9
54.9
56.2
40.7
56.9
56.9
56.9
56.2
40.7
40.7
CCOMP
(pF)
200
220
130
130
200
180
180
180
220
270
220
200
180
220
180
CPAR
(pF)
20
22
13
13
20
18
18
18
22
27
22
20
18
22
18
RTOP
(kΩ)
0.3
1.0
2.0
3.2
1.0
2.0
3.2
4.5
7.3
1.0
2.0
3.2
4.5
7.3
10.7
1
See the Inductor Selection section and Table 11.
22 µF Murata 25 V, X7R, 1210 GRM32ER71E226KE15L (3.2 mm × 2.5 mm × 2.5 mm).
3
560 µF Panasonic (SP-series) 2 V, 7 mΩ, 3.7 A EEFUE0D561LR (4.3 mm × 7.3 mm × 4.2 mm).
4
270 µF Panasonic (SP-series) 4 V, 7 mΩ, 3.7 A EEFUE0G271LR (4.3 mm × 7.3 mm × 4.2 mm).
5
330 µF Panasonic (SP-series) 4 V, 12 mΩ, 3.3 A EEFUE0G331R (4.3 mm × 7.3 mm × 4.2 mm).
6
47 µF Murata 16 V, X5R, 1210 GRM32ER61C476KE15L (3.2 mm × 2.5 mm × 2.5 mm).
7
150 µF Panasonic (SP-series) 6.3 V, 10 mΩ, 3.5 A EEFUE0J151XR (4.3 mm × 7.3 mm × 4.2 mm).
8
180 µF Panasonic (SP-series) 4 V, 10 mΩ, 3.5 A EEFUE0G181XR (4.3 mm × 7.3 mm × 4.2 mm).
9
10 µF TDK 25 V, X7R, 1210 C3225X7R1E106M.
2
Table 11. Recommended Inductors
L (µH)
0.12
0.22
0.47
0.72
0.9
1.2
1.0
1.4
2.0
0.8
DCR (mΩ)
0.33
0.33
0.8
1.65
1.6
1.8
3.8
3.2
2.6
ISAT (A)
55
30
50
35
32
25
16
24
23
27.5
Dimension (mm)
10.2 × 7
10.2 × 7
14.2 × 12.8
10.5 × 10.2
14 × 12.8
10.5 × 10.2
10.2 × 10.2
14 × 12.8
10.2 × 10.2
Manufacturer
Würth Elektronik
Würth Elektronik
Würth Elektronik
Würth Elektronik
Würth Elektronik
Würth Elektronik
Würth Elektronik
Würth Elektronik
Würth Elektronik
Sumida
Model Number
744303012
744303022
744355147
744325072
744318120
744325120
7443552100
744318180
7443551200
CEP125U-0R8
Table 12. Recommended MOSFETs
VGS = 4.5 V
Upper Side MOSFET
(Q1/Q2)
Lower Side MOSFET
(Q3/Q4)
RON (mΩ)
5.4
ID (A)
47
VDS (V)
30
CIN (nF)
3.2
QTOTAL (nC)
20
Package
PG-TDSON8
Manufacturer
Infineon
Model Number
BSC042N03MS G
10.2
6.0
9
5.4
53
19
14
47
30
30
30
30
1.6
10
35
25
20
PG-TDSON8
SO-8
SO-8
PG-TDSON8
Infineon
Vishay
International Rectifier
Infineon
BSC080N03MS G
Si4842DY
IRF7811
BSC042N03MS G
10.2
6.0
82
19
30
30
1.6
10
35
PG-TDSON8
SO-8
Infineon
Vishay
BSC080N03MS G
Si4842DY
2.4
3.2
Rev. A | Page 35 of 44
ADP1874/ADP1875
Data Sheet
LAYOUT CONSIDERATIONS
Figure 90 shows the schematic of a typical ADP1874/ADP1875
used for a high current application. Blue traces denote high current
pathways. VIN, PGND, and VOUT traces should be wide and
possibly replicated, descending down into the multiple layers.
Vias should populate, mainly around the positive and negative
terminals of the input and output capacitors, alongside the source
of Q1/Q2, the drain of Q3/Q4, and the inductor.
The performance of a dc-to-dc converter depends highly on how
the voltage and current paths are configured on the printed circuit
board (PCB). Optimizing the placement of sensitive analog and
power components is essential to minimize output ripple, maintain
tight regulation specifications, and reduce PWM jitter and
electromagnetic interference.
HIGH VOLTAGE INPUT
VIN = 12V
JP3
CVIN
22µF
CPAR
53pF
VOUT
R7 10kΩ
1
VIN
2
COMP
3
EN
DRVH 14
4
FB
PGND 13
RTOP 2kΩ
RBOT
1kΩ
RRES
100kΩ
C2
0.1µF
BST 16
5
GND
DRVL 12
RES
PGOOD 11
7
VREG
VREG_IN
C3
22µF
Q1
C1
1µF
C5
22µF
C6
22µF
1.0µH
Q3
5kΩ
Q4
RSNB
2Ω
CSNB
1.5nF
10kΩ
VREG
C7
22µF
C9
N/A
C8
N/A
VOUT = 1.8V, 15A
C20
270µF
C24
N/A
VREG
SS 10
TRACK 9
C4
22µF
Q2
SW 15
6
8
CBST
100nF
CSS
34nF
+
+
C21
270µF
C25
N/A
+
+
+
C22
270µF
C26
N/A
+
C23
270µF
C27
N/A
+
+ C14 TO C19
N/A
MURATA: (HIGH VOLTAGE INPUT CAPACITORS)
22µF, 25V, X7R, 1210 GRM32ER71E226KE15L
PANASONIC: (OUTPUT CAPACITORS)
270µF, SP-SERIES, 4V, 7mΩ EEFUE0G271LR
INFINEON MOSFETs:
BSC042N03MS G (LOWER SIDE)
BSC080N03MS G (UPPER SIDE)
WÜRTH INDUCTORS:
1µH, 3.8mΩ, 16A 7443552100
Figure 90. ADP1874/ADP1875 High Current Evaluation Board Schematic (Blue Traces Indicate High Current Paths)
SENSITIVE ANALOG
COMPONENTS
LOCATED FAR
FROM NOISY
POWER SECTION
SEPARATE ANALOG
GROUND PLANE FOR
COMPENSATION AND
FEEDBACK RESISTORS
OUTPUT
CAPACITORS
ARE MOUNTED
AT RIGHTMOST
AREA OF
EVALUATION
BOARD
INPUT CAPACITORS
ARE MOUNTED CLOSE
TO DRAIN OF Q1/Q2
AND SOURCE OF Q3/Q4
09347-092
VREG
ADP1874/
ADP1875
Figure 91. Overall Layout of the ADP1874/ADP1875 High Current Evaluation Board
Rev. A | Page 36 of 44
09347-081
CC
430pF
RC
57kΩ
ADP1874/ADP1875
09347-093
Data Sheet
Figure 92. Layer 2 of ADP1874/ADP1875 Evaluation Board
TOP RESISTOR
FEEDBACK TAP
09347-094
VOUT SENSE TAP LINE
EXTENDING BACK TO THE
TOP RESISTOR IN THE
FEEDBACK DIVIDER
NETWORK. THIS OVERLAPS
WITH PGND SENSE TAP
LINE EXTENDING TO THE
ANALOG GROUND PLANE
Figure 93. Layer 3 of ADP1874/ADP1875 Evaluation Board
Rev. A | Page 37 of 44
ADP1874/ADP1875
Data Sheet
BOTTOM
RESISTOR TAP
TO ANALOG
GROUND PLANE
09347-095
PGND SENSE TAP FROM
NEGATIVE TERMINALS OF
THE OUTPUT BULK
CAPACITORS. THIS
TRACK PLACEMENT
SHOULD BE DIRECTLY
BELOW THE VOUT SENSE
LINE OF LAYER 3.
Figure 94. Layer 4 (Bottom Layer) of ADP1874/ADP1875 Evaluation Board
A dedicated plane for the analog ground plane (GND) should
be separate from the main power ground plane (PGND). With
the shortest path possible, connect the analog ground plane to
the GND pin (Pin 5). This plane should be on only the top layer
of the evaluation board. To avoid crosstalk interference, there
should not be any other voltage or current pathway directly below
this plane on Layer 2, Layer 3, or Layer 4. Connect the negative
terminals of all sensitive analog components to the analog ground
plane. Examples of such sensitive analog components include
the resistor divider’s bottom resistor, the high frequency bypass
capacitor for biasing (0.1 µF), and the compensation network.
Mount a 1 µF bypass capacitor directly across the VREG pin
(Pin 7) and the PGND pin (Pin 13). In addition, a 0.1 µF should
be tied across the VREG pin (Pin 7) and the GND pin (Pin 5).
POWER SECTION
As shown in Figure 91, an appropriate configuration to localize
large current transfer from the high voltage input (VIN) to the
output (VOUT) and then back to the power ground is to put the
VIN plane on the left, the output plane on the right, and the main
power ground plane in between the two. Current transfers from
the input capacitors to the output capacitors, through Q1/Q2,
during the on state (see Figure 95). The direction of this current
(yellow arrow) is maintained as Q1/Q2 turns off and Q3/Q4 turns
on. When Q3/Q4 turns on, the current direction continues to be
maintained (yellow arrow) as it circles from the bulk capacitor
power ground terminal to the output capacitors, through
Q3/Q4. Arranging the power planes in this manner minimizes
the area in which changes in flux occur if the current through
Q1/Q2 stops abruptly. Sudden changes in flux, usually at the
source terminals of Q1/Q2 and the drain terminal of Q3/Q4,
cause large dv/dt at the SW node.
The SW node is near the top of the evaluation board. The SW
node should use the least amount of area possible and be away
from any sensitive analog circuitry and components. This is
because the SW node is where most sudden changes in flux
density occur. When possible, replicate this pad onto Layer 2
and Layer 3 for thermal relief and eliminate any other voltage and
current pathways directly beneath the SW node plane. Populate
the SW node plane with vias, mainly around the exposed pad of
the inductor terminal and around the perimeter of the source of
Q1/Q2 and the drain of Q3/Q4. The output voltage power plane
(VOUT) is at the rightmost end of the evaluation board. This plane
should be replicated, descending down to multiple layers with
vias surrounding the inductor terminal and the positive terminals
of the output bulk capacitors. Ensure that the negative terminals of
the output capacitors are placed close to the main power ground
(PGND), as previously mentioned. All of these points form a
tight circle (component geometry permitting) that minimizes
the area of flux change as the event switches between D and 1 − D.
09347-086
IC SECTION (LEFT SIDE OF EVALUATION BOARD)
Figure 95. Primary Current Pathways During the On State of the Upper Side
MOSFET (Left Arrow) and the On State of the Lower Side MOSFET (Right Arrow)
Rev. A | Page 38 of 44
Data Sheet
ADP1874/ADP1875
DIFFERENTIAL SENSING
Because the ADP1874/ADP1875 operate in valley current-mode
control, a differential voltage reading is taken across the drain
and source of the lower side MOSFET. The drain of the lower
side MOSFET should be connected as close as possible to the SW
pin (Pin 15) of the IC. Likewise, the source should be connected
as close as possible to the PGND pin (Pin 13) of the IC. When
possible, both of these track lines should be narrow and away
from any other active device or voltage/current path.
Differential sensing should also be employed between the
outermost output capacitor and the feedback resistor divider
(see Figure 93 and Figure 94). Connect the positive terminal of
the output capacitor to the top resistor (RT). Connect the negative
terminal of the output capacitor to the negative terminal of the
bottom resistor, which connects to the analog ground plane as
well. Both of these track lines, as previously mentioned, should
be narrow and away from any other active device or voltage/
current path.
SW
LAYER 1: SENSE LINE FOR SW
(DRAIN OF LOWER MOSFET)
LAYER 1: SENSE LINE FOR PGND
(SOURCE OF LOWER MOSFET)
09347-087
PGND
Figure 96. Drain/Source Tracking Tapping of the Lower Side MOSFET for CS
Amp Differential Sensing (Yellow Sense Line on Layer 2).
Rev. A | Page 39 of 44
ADP1874/ADP1875
Data Sheet
TYPICAL APPLICATION CIRCUITS
12 A, 300 kHz HIGH CURRENT APPLICATION CIRCUIT
HIGH VOLTAGE INPUT
VIN = 12V
JP3
CVIN
22µF
CPAR
56pF
R7 10kΩ
VREG
ADP1874/
ADP1875
1
VIN
2
COMP
3
EN
DRVH 14
4
FB
PGND 13
5
GND
DRVL 12
6
RES
PGOOD 11
7
VREG
RTOP 2kΩ
VOUT
RBOT
1kΩ
RRES
100kΩ
VREG_IN
8
C2
0.1µF
BST 16
C3
22µF
CBST
100nF
Q1
C5
22µF
C6
22µF
1.2µH
Q3
5kΩ
10kΩ
Q4
+
C24
N/A
VREG
C1
1µF
C8
N/A
C9
N/A
VOUT = 1.8V, 12A
+
C20
270µF
RSNB
2Ω
CSNB
1.5nF
VREG
SS 10
C7
22µF
Q2
SW 15
TRACK 9
C4
22µF
+
C21
270µF
+
C25
N/A
+
C22
270µF
+
C26
N/A
C23
270µF
+
+ C14 TO C19
N/A
C27
N/A
MURATA: (HIGH VOLTAGE INPUT CAPACITORS)
22µF, 25V, X7R, 1210 GRM32ER71E226KE15L
PANASONIC: (OUTPUT CAPACITORS)
270µF, SP-SERIES, 4V, 7mΩ EEFUE0G271LR
INFINEON MOSFETs:
BSC042N03MS G (LOWER SIDE)
BSC080N03MS G (UPPER SIDE)
WÜRTH INDUCTORS:
1.2µH, 2.00mΩ, 20A 744325120
CSS
34nF
09347-088
CC
560pF
RC
49.3kΩ
Figure 97. Application Circuit for 12 V Input, 1.8 V Output, 12 A, 300 kHz (Q2/Q4 No Connect)
5.5 V INPUT, 600 kHz APPLICATION CIRCUIT
HIGH VOLTAGE INPUT
VIN = 5.5V
JP3
CVIN
22µF
CF
22pF
VREG
VOUT
R7 10kΩ
RTOP 3.2kΩ
RBOT
1kΩ
RRES
100kΩ
ADP1874/
ADP1875
1
VIN
2
COMP
3
EN
DRVH 14
4
FB
PGND 13
5
GND
DRVL 12
6
RES
PGOOD 11
7
VREG
8
C2
0.1µF
C1
1µF
VREG_IN
BST 16
CBST
100nF
C3
22µF
Q1
C5
22µF
C6
22µF
1.2µH
Q3
5kΩ
Q4
RSNB
2Ω
CSNB
1.5nF
10kΩ
VREG
C8
N/A
C9
N/A
VOUT = 2.5V, 12A
C20
180µF
C24
N/A
VREG
SS 10
C7
22µF
Q2
SW 15
TRACK 9
C4
22µF
CSS
34nF
+
+
C21
180µF
C25
N/A
+
+
C22
180µF
C26
N/A
+
+
C27
N/A
C23
N/A
+
+ C14 TO C19
N/A
MURATA: (HIGH VOLTAGE INPUT CAPACITORS)
22µF, 25V, X7R, 1210 GRM32ER71E226KE15L
PANASONIC: (OUTPUT CAPACITORS)
180µF, SP-SERIES, 4V, 10mΩ EEFUE0G181XR
INFINEON MOSFETs:
BSC042N03MS G (LOWER SIDE)
BSC080N03MS G (UPPER SIDE)
WÜRTH INDUCTORS:
0.47µH, 0.8mΩ, 30A 744355147
Figure 98. Application Circuit for 5.5 V Input, 2.5 V Output, 12 A, 600 kHz (Q2/Q4 No Connect)
Rev. A | Page 40 of 44
09347-089
CC
220pF
RC
56.9kΩ
Data Sheet
ADP1874/ADP1875
300 kHz HIGH CURRENT APPLICATION CIRCUIT
HIGH VOLTAGE INPUT
VIN = 13V
JP3
CVIN
22µF
CPAR
56pF
VREG
VOUT
R7 10kΩ
ADP1874/
ADP1875
1
VIN
2
COMP
3
EN
RTOP 2kΩ
RBOT
1kΩ
RRES
100kΩ
C1
1µF
Q1
FB
PGND 13
GND
DRVL 12
6
RES
PGOOD 11
7
VREG
C5
22µF
C6
22µF
1.2µH
Q3
5kΩ
Q4
RSNB
2Ω
CSNB
1.5nF
10kΩ
VREG
C7
22µF
C8
N/A
C9
N/A
VOUT = 1.8V, 12A
C20
270µF
C24
N/A
VREG
SS 10
TRACK 9
C4
22µF
Q2
SW 15
5
VREG_IN
C3
22µF
DRVH 14
4
8
C2
0.1µF
BST 16
CBST
100nF
CSS
34nF
+
+
C21
270µF
C25
N/A
+
+
C22
270µF
C26
N/A
+
+
C23
270µF
C27
N/A
+
+ C14 TO C19
N/A
MURATA: (HIGH VOLTAGE INPUT CAPACITORS)
22µF, 25V, X7R, 1210 GRM32ER71E226KE15L
PANASONIC: (OUTPUT CAPACITORS)
270µF, SP-SERIES, 4V, 7mΩ EEFUE0G271LR
INFINEON MOSFETs:
BSC042N03MS G (LOWER SIDE)
BSC080N03MS G (UPPER SIDE)
WÜRTH INDUCTORS:
1.2µH, 2.00mΩ, 20A 744325120
Figure 99. Application Circuit for 13 V Input, 1.8 V Output, 12 A, 300 kHz (Q2/Q4 No Connect)
Rev. A | Page 41 of 44
09347-090
CC
560pF
RC
49.3kΩ
ADP1874/ADP1875
Data Sheet
OUTLINE DIMENSIONS
0.197 (5.00)
0.193 (4.90)
0.189 (4.80)
16
9
1
8
0.244 (6.20)
0.236 (5.99)
0.228 (5.79)
0.010 (0.25)
0.006 (0.15)
0.069 (1.75)
0.053 (1.35)
0.065 (1.65)
0.049 (1.25)
0.010 (0.25)
0.004 (0.10)
COPLANARITY
0.004 (0.10)
0.158 (4.01)
0.154 (3.91)
0.150 (3.81)
0.025 (0.64)
BSC
SEATING
PLANE
0.012 (0.30)
0.008 (0.20)
8°
0°
0.050 (1.27)
0.016 (0.41)
0.020 (0.51)
0.010 (0.25)
0.041 (1.04)
REF
01-28-2008-A
COMPLIANT TO JEDEC STANDARDS MO-137-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 100. 16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model 1
ADP1874ARQZ-0.3-R7
ADP1874ARQZ-0.6-R7
ADP1874ARQZ-1.0-R7
ADP1874-0.3-EVALZ
ADP1874-0.6-EVALZ
ADP1874-1.0-EVALZ
ADP1875ARQZ-0.3-R7
ADP1875ARQZ-0.6-R7
ADP1875ARQZ-1.0-R7
ADP1875-0.3-EVALZ
ADP1875-0.6-EVALZ
ADP1875-1.0-EVALZ
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead Shrink Small Outline Package [QSOP]
16-Lead Shrink Small Outline Package [QSOP]
16-Lead Shrink Small Outline Package [QSOP]
Evaluation Board
Evaluation Board
Evaluation Board
16-Lead Shrink Small Outline Package [QSOP]
16-Lead Shrink Small Outline Package [QSOP]
16-Lead Shrink Small Outline Package [QSOP]
Evaluation Board
Evaluation Board
Evaluation Board
Z = RoHS Compliant Part.
Rev. A | Page 42 of 44
Package Option
RQ-16
RQ-16
RQ-16
Branding (First Line/
Second Line)
1874/0.3
1874/0.6
1874/1.0
RQ-16
RQ-16
RQ-16
1875/0.3
1875/0.6
1875/1.0
Data Sheet
ADP1874/ADP1875
NOTES
Rev. A | Page 43 of 44
ADP1874/ADP1875
Data Sheet
NOTES
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09347-0-7/12(A)
Rev. A | Page 44 of 44
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