ADP1878-0.6-EVALZ

FEATURES TYPICAL APPLICATIONS CIRCUIT Power input voltage range: 2.95 V to 20 V On-board bias regulator Minimum output voltage: 0.6 V 0.6 V reference voltage with ±1.0% accuracy Supports all N-channel MOSFET power stages Available in 300 kHz, 600 kHz, and 1.0 MHz options No current sense resistor required Power saving mode (PSM) for light loads (ADP1879 only) Resistor programmable current limit Power good with internal pull-up resistor Externally programmable soft start Thermal overload protection Short-circuit protection Standalone precision enable input Integrated bootstrap diode for high-side drive Starts into a precharged output Available in a 14-lead LFCSP_WD package VIN = 2.95V TO 20V VIN CC RC VREG VOUT CC2 10kΩ RTOP RBOT CVREG2 CVREG RRES ADP1878/ ADP1879 COMP CIN BST EN CBST DRVH FB L VOUT COUT Q2 SW GND Q1 LOAD DRVL VREG RPGD PGOOD RES SS VEXT CSS PGND 09441-001 Data Sheet Synchronous Buck Controller with Constant On Time and Valley Current Mode ADP1878/ADP1879 Figure 1. APPLICATIONS Telecommunications and networking systems Mid-to-high end servers Set-top boxes DSP core power supplies The ADP1879 is the power saving mode (PSM) version of the device and is capable of pulse skipping to maintain output regulation while achieving improved system efficiency at light loads (see the ADP1879 Power Saving Mode (PSM) section for more information). Available in three frequency options (300 kHz, 600 kHz, and 1.0 MHz) plus the PSM option, the ADP1878/ADP1879 are well suited for a wide range of applications that require a single input power supply range from 2.95 V to 20 V. Low voltage biasing is supplied via a 5 V internal low dropout regulator (LDO). In addition, soft start programmability is included to limit input inrush current from the input supply during startup and to provide reverse current protection during precharged output Rev. B The ADP1878/ADP1879 operate over the −40°C to +125°C junction temperature range and are available in a 14-lead LFCSP_WD package. 100 95 VIN = 5V (PSM) 90 85 80 75 VIN = 16.5V 70 65 VIN = 13V 60 55 VIN = 13V (PSM) 50 45 40 VIN = 16.5V (PSM) 35 30 25 10 100 TA = 25°C VOUT = 1.8V fSW = 300kHz WÜRTH INDUCTOR: 744325120, L = 1.2µH, DCR = 1.8mΩ INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 1k LOAD CURRENT (mA) 10k 100k 09441-102 The ADP1878/ADP1879 are versatile current-mode, synchronous step-down controllers. They provide superior transient response, optimal stability, and current-limit protection by using a constant on time, pseudo fixed frequency with a programmable current-limit, current control scheme. These devices offer optimum performance at low duty cycles by using a valley, current-mode control architecture allowing the ADP1878/ADP1879 to drive all N-channel power stages to regulate output voltages to as low as 0.6 V. conditions. The low-side current sense, current gain scheme and integration of a boost diode, together with the PSM/forced pulse-width modulation (PWM) option, reduce the external device count and improve efficiency. EFFICIENCY (%) GENERAL DESCRIPTION Figure 2. ADP1878/ADP1879 Efficiency vs. Load Current (VOUT = 1.8 V, 300 kHz) Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011–2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADP1878/ADP1879 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pseudo Fixed Frequency............................................................ 22 Applications ....................................................................................... 1 Power-Good Monitoring ........................................................... 23 Typical Applications Circuit............................................................ 1 Applications Information .............................................................. 24 General Description ......................................................................... 1 Feedback Resistor Divider ........................................................ 24 Revision History ............................................................................... 2 Inductor Selection ...................................................................... 24 Specifications..................................................................................... 3 Output Ripple Voltage (ΔVRR) .................................................. 24 Absolute Maximum Ratings ....................................................... 5 Output Capacitor Selection....................................................... 24 Thermal Resistance ...................................................................... 5 Compensation Network ............................................................ 25 ESD Caution .................................................................................. 5 Efficiency Consideration ........................................................... 26 Pin Configuration and Function Descriptions ............................. 6 Input Capacitor Selection .......................................................... 27 Typical Performance Characteristics ............................................. 7 Thermal Considerations............................................................ 27 Theory of Operation ...................................................................... 17 Design Example .......................................................................... 29 Block Diagram ............................................................................ 17 External Component Recommendations .................................... 31 Startup .......................................................................................... 18 Layout Considerations ................................................................... 33 Soft Start ...................................................................................... 18 IC Section (Left Side of Evaluation Board) ............................. 35 Precision Enable Circuitry ........................................................ 18 Power Section ............................................................................. 35 Undervoltage Lockout ............................................................... 18 Differential Sensing .................................................................... 36 On-Board Low Dropout (LDO) Regulator ............................. 18 Typical Application Circuits ......................................................... 37 Thermal Shutdown ..................................................................... 19 12 A, 300 kHz High Current Application Circuit .................. 37 Programming Resistor (RES) Detect Circuit.......................... 19 5.5 V Input, 600 kHz Current Application Circuit ................ 37 Valley Current-Limit Setting .................................................... 19 300 kHz High Current Application Circuit ............................ 38 Hiccup Mode During Short Circuit ......................................... 21 Packaging and Ordering Information ......................................... 39 Synchronous Rectifier ................................................................ 21 Outline Dimensions ................................................................... 39 ADP1879 Power Saving Mode (PSM) ...................................... 21 Ordering Guide .......................................................................... 40 Timer Operation ......................................................................... 22 REVISION HISTORY 9/12—Rev. A to Rev. B Changes to Table 7 ...........................................................................20 6/12—Rev. 0 to Rev. A Changes to Table 1 ............................................................................. 3 7/11—Revision 0: Initial Version Rev. B | Page 2 of 40 Data Sheet ADP1878/ADP1879 SPECIFICATIONS All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VREG = 5 V, BST − SW = VREG − VRECT_DROP (see Figure 40 to Figure 42). VIN = 12 V. The specifications are valid for TJ = −40°C to +125°C, unless otherwise specified. Table 1. Parameter POWER SUPPLY CHARACTERISTICS High Input Voltage Range Quiescent Current Shutdown Current Undervoltage Lockout UVLO Hysteresis INTERNAL REGULATOR CHARACTERISTICS VREG Operational Output Voltage Symbol Test Conditions/Comments Min Typ Max Unit VIN CVIN = 22 µF(25 V rating) right at Pin 1 to PGND (Pin 11) ADP1878ACPZ-0.3-R7/ADP1879ACPZ-0.3-R7 (300 kHz) ADP1878ACPZ-0.6-R7/ADP1879ACPZ-0.6-R7 (600 kHz) ADP1878ACPZ-1.0-R7/ADP1879ACPZ-1.0-R7 (1.0 MHz) FB = 1.5 V, no switching 2.95 2.95 3.25 12 12 12 1.1 20 20 20 V V V mA EN < 600 mV 140 225 µA Rising VIN (see Figure 35 for temperature variation) Falling VIN from operational state Do not load VREG externally because it is intended to bias internal circuitry only CVREG = 4.7 µF to PGND, 0.22 µF to GND, VIN = 2.95 V to 20 V ADP1878ACPZ-0.3-R7/ADP1879ACPZ-0.3-R7 (300 kHz) ADP1878ACPZ-0.6-R7/ADP1879ACPZ-0.6-R7 (600 kHz) ADP1878ACPZ-1.0-R7/ADP1879ACPZ-1.0-R7 (1.0 MHz) VIN = 7 V, 100 mA VIN = 12 V, 100 mA 0 mA to 100 mA, VIN = 7 V 0 mA to 100 mA, VIN = 20 V VIN = 7 V to 20 V, 20 mA VIN = 7 V to 20 V, 100 mA 100 mA out of VREG, VIN ≤ 5 V VIN = 20 V Connect external capacitor from SS pin to GND, CSS = 10 nF/ms 2.65 178 IQ_REG + IQ_BST IREG,SD + IBST,SD UVLO VREG VREG Output in Regulation Load Regulation Line Regulation VIN to VREG Dropout Voltage Short VREG to PGND SOFT START Soft Start Period Calculation ERROR AMPLIFER FB Regulation Voltage Transconductance FB Input Leakage Current CURRENT SENSE AMPLIFIER GAIN Programming Resistor (RES) Value from RES to PGND SWITCHING FREQUENCY ADP1878ACPZ-0.3-R7/ ADP1879ACPZ-0.3-R7 On Time Minimum On Time Minimum Off Time VFB Gm IFB, LEAK TJ = 25°C TJ = −40°C to +85°C TJ = −40°C to +125°C 2.75 2.75 3.05 4.82 4.83 5 5 5 4.981 4.982 32 34 1.8 2.0 306 229 V mV 5.5 5.5 5.5 5.16 5.16 415 320 10 V V V V V mV mV mV mV mV mA nF/ms 596 594.2 320 600 600 600 496 1 604 605.8 670 50 mV mV mV µS nA RES = 47 kΩ ± 1% 2.7 3 3.3 V/V RES = 22 kΩ ± 1% RES = none RES = 100 kΩ ± 1% Typical values measured at 50% time points with 0 nF at DRVH and DRVL; maximum values are guaranteed by bench evaluation 1 5.5 11 22 6 12 24 6.5 13 26 V/V V/V V/V FB = 0.6 V, EN = VREG 300 VIN = 5 V, VOUT = 2 V, TJ = 25°C VIN = 20 V 84% duty cycle (maximum) Rev. B | Page 3 of 40 1120 1200 145 340 kHz 1345 190 400 ns ns ns ADP1878/ADP1879 Data Sheet Parameter ADP1878ACPZ-0.6-R7/ ADP1879ACPZ-0.6-R7 On Time Minimum On Time Minimum Off Time ADP1878ACPZ-1.0-R7/ ADP1879ACPZ-1.0-R7 On Time Minimum On Time Minimum Off Time OUTPUT DRIVER CHARACTERISTICS High-Side Driver Output Source Resistance Output Sink Resistance Rise Time 2 Fall Time2 Low-Side Driver Output Source Resistance Output Sink Resistance Rise Time2 Fall Time2 Propagation Delays DRVL Fall to DRVH Rise2 DRVH Fall to DRVL Rise2 SW Leakage Current Integrated Rectifier Channel Impedance PRECISION ENABLE THRESHOLD Logic High Level Enable Hysteresis COMP VOLTAGE COMP Clamp Low Voltage Symbol Test Conditions/Comments Min Typ 600 Max Unit kHz VIN = 5 V, VOUT = 2 V, TJ = 25°C VIN = 20 V, VOUT = 0.8 V 65% duty cycle (maximum) 500 540 82 340 1.0 605 110 400 ns ns ns MHz VIN = 5 V, VOUT = 2 V, TJ = 25°C VIN = 20 V 45% duty cycle (maximum) 285 312 52 340 360 85 400 ns ns ns 2.20 0.72 25 11 3 1 tr, DRVH tf, DRVH ISOURCE = 1.5 A, 100 ns, positive pulse (0 V to 5 V) ISINK = 1.5 A, 100 ns, negative pulse (5 V to 0 V) BST − SW = 4.4 V, CIN = 4.3 nF (see Figure 59) BST − SW = 4.4 V, CIN = 4.3 nF (see Figure 60) Ω Ω ns ns 1.5 0.7 18 16 2.2 1 tr,DRVL tf,DRVL ISOURCE = 1.5 A, 100 ns, positive pulse (0 V to 5 V) ISINK = 1.5 A, 100 ns, negative pulse (5 V to 0 V) VREG = 5.0 V, CIN = 4.3 nF (see Figure 60) VREG = 5.0 V, CIN = 4.3 nF (see Figure 59) Ω Ω ns ns ttpdhDRVH ttpdhDRVL ISWLEAK BST − SW = 4.4 V (see Figure 59) BST − SW = 4.4 V (see Figure 60) BST = 25 V, SW = 20 V, VREG = 5 V 15.7 16 ISINK = 10 mA 22.3 COMP Clamp High Voltage COMP Zero Current Threshold THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis CURRENT LIMIT Hiccup Current-Limit Timing OVERVOLTAGE AND POWERGOOD THRESHOLDS FB Power-Good Threshold FB Power-Good Hysteresis FB Overvoltage Threshold FB Overvoltage Hysteresis PGOOD Low Voltage During Sink PGOOD Leakage Current VCOMP(HIGH) VCOMP_ZCT TTMSD VCOMP(LOW) 110 VIN = 2.9 V to 20 V, VREG = 2.75 V to 5.5 V VIN = 2.9 V to 20 V, VREG = 2.75 V to 5.5 V 605 Tie EN pin to VREG to enable device (2.75 V ≤ VREG ≤ 5.5 V) (2.75 V ≤ VREG ≤ 5.5 V) (2.75 V ≤ VREG ≤ 5.5 V) 0.47 634 31 ns ns µA Ω 663 mV mV V 1.10 2.55 V V Rising temperature 155 15 °C °C COMP = 2.4 V 6 ms FBPGD VFB rising during system power up FBOV VFB rising during overvoltage event, IPGOOD = 1 mA VPGOOD IPGOOD = 1 mA PGOOD = 5 V 542 34 691 35 143 1 PGOOD 1 566 55 710 55 200 100 mV mV mV mV mV nA The maximum specified values are with the closed loop measured at 10% to 90% time points (see Figure 59 and Figure 60), CGATE = 4.3 nF, and the high- and low-side MOSFETs being Infineon BSC042N03MS G. 2 Not automatic test equipment (ATE) tested. Rev. B | Page 4 of 40 Data Sheet ADP1878/ADP1879 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter VREG to PGND, GND VIN, EN, PGOOD to PGND FB, COMP, RES, SS to GND DRVL to PGND SW to PGND BST to SW BST to PGND DRVH to SW PGND to GND PGOOD Input Current θJA (14-Lead LFCSP_WD) 4-Layer Board Operating Junction Temperature Range Storage Temperature Range Soldering Conditions Maximum Soldering Lead Temperature (10 sec) Rating −0.3 V to +6 V −0.3 V to +28 V −0.3 V to (VREG + 0.3 V) −0.3 V to (VREG + 0.3 V) −2.0 V to +28 V −0.6 V to (VREG + 0.3 V) −0.3 V to +28 V −0.3 V to VREG ±0.3 V 35 mA θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Boundary Condition In determining the values given in Table 2 and Table 3, natural convection is used to transfer heat to a 4-layer evaluation board. Table 3. Thermal Resistance Package Type θJA (14-Lead LFCSP_WD) 4-Layer Board ESD CAUTION 30°C/W −40°C to +125°C −65°C to +150°C JEDEC J-STD-020 300°C Stresses a bove those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to PGND. Rev. B | Page 5 of 40 θJA Unit 30 °C/W ADP1878/ADP1879 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADP1878/ADP1879 VIN 1 14 BST COMP 2 13 SW EN 3 12 DRVH FB 11 PGND 4 GND 5 10 RES 6 9 DRVL PGOOD VREG 7 8 SS NOTES 1. CONNECT THE EXPOSED PAD TO THE ANALOG GROUND PIN (GND). 09441-003 TOP VIEW (Not to Scale) Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 Mnemonic VIN COMP 3 4 5 EN FB GND 6 7 RES VREG 8 SS 9 PGOOD 10 DRVL 11 12 13 14 PGND DRVH SW BST EP Description High-Side Input Voltage. Connect VIN to the drain of the high-side MOSFET. Output of the Error Amplifier. Connect compensation network between this pin and AGND to achieve stability (see the Compensation Network section). IC Enable. Connect EN to VREG to enable the IC. When pulled down to AGND externally, EN disables the IC. Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected. Analog Ground Reference Pin of the IC. Connect all sensitive analog components to this ground plane (see the Layout Considerations section). Current Sense Gain Resistor (External). Connect a resistor between the RES pin and GND (Pin 5). Internal Regulator Supply Bias Voltage for the ADP1878/ADP1879 Controller (Includes the Output Gate Drivers). Connecting a bypass capacitor of 1 μF directly from this pin to PGND and a 0.1 μF capacitor across VREG and GND are recommended. Soft Start Input. Connect an external capacitor to GND to program the soft start period. There is a capacitance value of 10 nF for every 1 ms of soft start delay. Open-Drain Power-Good Output. PGOOD sinks current when FB is out of regulation or during thermal shutdown. Connect a 3 kΩ resistor between PGOOD and VREG. Leave PGOOD unconnected if it is not used. Drive Output for the External Low-Side, N-Channel MOSFET. This pin also serves as the current sense gain setting pin (see Figure 69). Power Ground. Ground for the low-side gate driver and low-side N-channel MOSFET. Drive Output for the External High-Side N-Channel MOSFET. Switch Node Connection. Bootstrap for the High-Side N-Channel MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected between VREG and BST. A capacitor from BST to SW is required. An external Schottky diode can also be connected between VREG and BST for increased gate drive capability. Exposed Pad. Connect the exposed pad to the analog ground pin (GND). Rev. B | Page 6 of 40 Data Sheet ADP1878/ADP1879 VIN = 16.5V VIN = 13V TA = 25°C VOUT = 0.8V fSW = 300kHz WÜRTH INDUCTOR: 744325072, L = 0.72µH, DCR = 1.3mΩ INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 100k EFFICIENCY (%) 09441-005 EFFICIENCY (%) LOAD CURRENT (mA) EFFICIENCY (%) VIN = 16.5V TA = 25°C VOUT = 7V fSW = 300kHz WÜRTH INDUCTOR: 7443551200, L = 2.0µH, DCR = 2.6mΩ INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 100k 09441-006 EFFICIENCY (%) 100 1k 10k 100k 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 VIN = 13V VIN = 13V (PSM) VIN = 16.5V VIN = 16.5V (PSM) TA = 25°C VOUT = 1.8V fSW = 600kHz WÜRTH INDUCTOR: 744325072, L = 0.72µH, DCR = 1.3mΩ INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 100 1k 10k 100k Figure 8. Efficiency—600 kHz, VOUT = 1.8 V VIN = 13V 10k WÜRTH INDUCTOR: 744355147, L = 0.47µH, DCR = 0.67mΩ INFINEON FETs: BSC042N03MS G (UPPER/LOWER) LOAD CURRENT (mA) Figure 5. Efficiency—300 kHz, VOUT = 1.8 V 1k TA = 25°C VOUT = 0.8V fSW = 600kHz VIN = 16.5V (PSM) Figure 7. Efficiency—600 kHz, VOUT = 0.8 V 100 95 VIN = 5V (PSM) 90 85 80 75 70 VIN = 16.5V 65 VIN = 13V (PSM) 60 55 VIN = 13V 50 45 40 VIN = 16.5V (PSM) 35 TA = 25°C 30 VOUT = 1.8V 25 fSW = 300kHz 20 WÜRTH INDUCTOR: 15 744325120, L = 1.2µH, DCR = 1.8mΩ 10 INFINEON FETs: 5 BSC042N03MS G (UPPER/LOWER) 0 100k 100 1k 10k 10 LOAD CURRENT (mA) VIN = 16.5V LOAD CURRENT (mA) Figure 4. Efficiency—300 kHz, VOUT = 0.8 V 100 95 VIN = 16.5V (PSM) 90 85 80 75 V = 13V (PSM) IN 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 VIN = 13V (PSM) 09441-008 10k VIN = 13V Figure 6. Efficiency—300 kHz, VOUT = 7 V 100 VIN = 13V (PSM) 95 90 V = 16.5V (PSM) IN 85 80 75 70 65 VIN = 16.5V 60 55 50 VIN = 20V (PSM) VIN = 20V 45 40 35 TA = 25°C 30 VOUT = 5V 25 fSW = 600kHz 20 WÜRTH INDUCTOR: 15 744318180, L = 1.4µH, DCR = 3.2mΩ 10 INFINEON FETs: 5 BSC042N03MS G (UPPER/LOWER) 0 100k 10 100 1k 10k LOAD CURRENT (mA) Figure 9. Efficiency—600 kHz, VOUT = 5 V Rev. B | Page 7 of 40 09441-009 1k LOAD CURRENT (mA) 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 09441-007 EFFICIENCY (%) 100 95 90 VIN = 13V (PSM) 85 80 75 70 65 60 55 50 45 40 35 V = 16.5V (PSM) IN 30 25 20 15 10 5 0 100 10 09441-004 EFFICIENCY (%) TYPICAL PERFORMANCE CHARACTERISTICS 100 95 90 85 80 75 70 65 VIN = 13V (PSM) 60 55 50 45 40 35 30 VIN = 16.5V (PSM) 25 20 15 10 5 0 10 100 Data Sheet 0.807 0.806 VIN = 13V 0.805 VIN = 16.5V TA = 25°C VOUT = 0.8V fSW = 1.0MHz 10k 100k LOAD CURRENT (mA) 0.798 0.797 0.796 0.792 VIN = 13V +125°C +25°C –40°C 0 2000 VIN = 16.5V +125°C +25°C –40°C 4000 6000 8000 10,000 LOAD CURRENT (mA) 1.821 VIN = 13V VIN = 16.5V TA = 25°C VOUT = 1.8V fSW = 1.0MHz WÜRTH INDUCTOR: 744303022, L = 0.22µH, DCR = 0.33mΩ INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 10k 100k 1.786 TA = 25°C VOUT = 5V fSW = 1.0MHz 100k 09441-012 WÜRTH INDUCTOR: 744355090, L = 0.9µH, DCR = 1.6mΩ INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 10k VIN = 5.5V +125°C +25°C –40°C 0 1500 3000 4500 VIN = 13V +125°C +25°C –40°C 6000 7500 VIN = 16.5V +125°C +25°C –40°C 9000 10,500 12,000 13,500 15,000 LOAD CURRENT (mA) OUTPUT VOLTAGE (V) VIN = 16.5V 1k 1.796 Figure 14. Output Voltage Accuracy—300 kHz, VOUT = 1.8 V VIN = 13V LOAD CURRENT (mA) 1.801 1.791 VIN = 13V (PSM) VIN = 16.5V (PSM) 1.806 7.100 7.095 7.090 7.085 7.080 7.075 7.070 7.065 7.060 7.055 7.050 7.045 7.040 7.035 7.030 7.025 7.020 7.015 7.010 7.005 7.000 +125°C +25°C –40°C 0 1000 2000 VIN = 13V VIN = 16.5V 3000 4000 5000 6000 7000 8000 LOAD CURRENT (mA) Figure 15. Output Voltage Accuracy—300 kHz, VOUT = 7 V Figure 12. Efficiency—1.0 MHz, VOUT = 5 V Rev. B | Page 8 of 40 9000 09441-015 1k 1.811 09441-014 OUTPUT VOLTAGE (V) 1.816 09441-011 EFFICIENCY (%) EFFICIENCY (%) 0.799 0.793 Figure 11. Efficiency—1.0 MHz, VOUT = 1.8 V 100 0.800 Figure 13. Output Voltage Accuracy—300 kHz, VOUT = 0.8 V LOAD CURRENT (mA) 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 0.801 0.794 Figure 10. Efficiency—1.0 MHz, VOUT = 0.8 V 100 95 90 85 80 VIN = 13V (PSM) 75 70 65 60 55 50 45 40 V = 16.5V (PSM) IN 35 30 25 20 15 10 5 0 10 100 0.802 0.795 WÜRTH INDUCTOR: 744303012, L = 0.12µH, DCR = 0.33mΩ INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 1k 0.803 09441-013 OUTPUT VOLTAGE (V) 0.804 09441-010 EFFICIENCY (%) ADP1878/ADP1879 Data Sheet ADP1878/ADP1879 0.808 0.807 0.805 0.806 0.803 OUTPUT VOLTAGE (V) FREQUENCY (kHz) 0.804 0.802 0.800 0.798 0.801 0.799 0.797 0.795 0.793 0.796 0.791 0.792 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 LOAD CURRENT (mA) 0.787 0 4000 6000 8000 10,000 Figure 19. Output Voltage Accuracy—1.0 MHz, VOUT = 0.8 V 1.820 1.818 1.816 1.814 1.812 1.810 1.808 1.806 1.804 1.802 1.800 1.798 1.796 1.794 1.792 1.790 1.788 1.786 1.784 1.782 1.780 1.778 1.776 1.774 1.772 1.770 VIN = 13V +125°C +25°C –40°C 0 1500 3000 4500 VIN = 16.5V +125°C +25°C –40°C 6000 7500 9000 1.810 1.805 1.800 VIN = 13V +125°C +25°C –40°C 1.795 10,500 12,000 LOAD CURRENT (mA) VIN = 16.5V +125°C +25°C –40°C 1.790 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 LOAD CURRENT (mA) Figure 17. Output Voltage Accuracy—600 kHz, VOUT = 1.8 V Figure 20. Output Voltage Accuracy—1.0 MHz, VOUT = 1.8 V 5.030 5.04 5.025 5.03 5.020 5.02 5.01 5.010 5.005 5.000 4.995 4.990 4.985 5.00 4.99 4.98 4.97 4.96 4.95 4.94 4.93 4.980 4.975 4.970 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 LOAD CURRENT (mA) VIN = 13V +125°C +25°C –40°C 4.92 VIN = 13V VIN = 16.5V VIN = 20V 4.91 09441-018 +125°C +25°C –40°C Figure 18. Output Voltage Accuracy—600 kHz, VOUT = 5 V VIN = 16.5V +125°C +25°C –40°C 4.90 0 800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 9600 LOAD CURRENT (mA) Figure 21. Output Voltage Accuracy—1.0 MHz, VOUT = 5 V Rev. B | Page 9 of 40 09441-021 OUTPUT VOLTAGE (V) 5.015 09441-020 OUTPUT VOLTAGE (V) 1.815 09441-017 OUTPUT VOLTAGE (V) 2000 VIN = 16.5V +125°C +25°C –40°C LOAD CURRENT (mA) Figure 16. Output Voltage Accuracy—600 kHz, VOUT = 0.8 V OUTPUT VOLTAGE (V) VIN = 13V +125°C +25°C –40°C 0.789 VIN = 13V VIN = 16.5V 09441-019 +125°C +25°C –40°C 09441-016 0.794 ADP1878/ADP1879 Data Sheet 900 601.0 599.5 VREG = 5V, VIN = 13V 599.0 598.5 598.0 840 820 800 780 760 740 597.5 25.0 57.5 90.0 700 13.0 09441-022 –7.5 122.5 TEMPERATURE (°C) +125°C +25°C –40°C 14.5 15.0 15.5 16.0 16.5 Figure 25. Switching Frequency vs. High Input Voltage, 1.0 MHz, VIN Range = 13 V to 16.5 V 280 NO LOAD VIN = 13V VIN = 20V VIN = 16.5V 265 +125°C +25°C –40°C 305 FREQUENCY (kHz) SWITCHING FREQUENCY (kHz) 315 14.0 VIN (V) Figure 22. Feedback Voltage vs. Temperature 325 13.5 09441-025 720 597.0 –40.0 295 285 250 235 220 275 205 265 VIN (V) 190 09441-023 255 10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2 0 +125°C +25°C –40°C 4000 6000 8000 10,000 LOAD CURRENT (mA) Figure 26. Frequency vs. Load Current, 300 kHz, VOUT = 0.8 V Figure 23. Switching Frequency vs. High Input Voltage, 300 kHz, ±10% of 12 V 650 2000 09441-026 FEEDBACK VOLTAGE (V) 860 SWITCHING FREQUENCY (kHz) VREG = 5V, VIN = 20V 600.0 330 NO LOAD VIN = 20V VIN = 13V VIN = 16.5V 320 600 +125°C +25°C –40°C 310 FREQUENCY (kHz) SWITCHING FREQUENCY (kHz) +125°C +25°C –40°C 880 600.5 550 500 300 290 280 270 260 450 13.4 13.8 14.2 14.6 15.0 VIN (V) 15.4 15.8 16.2 Figure 24. Switching Frequency vs. High Input Voltage, 600 kHz, VOUT = 1.8 V, VIN Range = 13 V to 16.5 V Rev. B | Page 10 of 40 240 0 1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000 LOAD CURRENT (mA) Figure 27. Frequency vs. Load Current, 300 kHz, VOUT = 1.8 V 09441-027 400 13.0 09441-024 250 Data Sheet VIN = 13V VIN = 16.5V 334 +125°C +25°C –40°C 326 FREQUENCY (kHz) FREQUENCY (kHz) 330 322 318 314 310 306 302 0 09441-028 298 800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 LOAD CURRENT (mA) +125°C +25°C –40°C 800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 9600 LOAD CURRENT (mA) Figure 31. Frequency vs. Load Current, 600 kHz, VOUT = 5 V 850 +125°C +25°C –40°C VIN = 13V VIN = 16.5V VIN = 13V VIN = 16.5V 0 Figure 28. Frequency vs. Load Current, 300 kHz, VOUT = 7 V 540 740 733 726 719 712 705 698 691 684 677 670 663 656 649 642 635 628 621 09441-031 338 ADP1878/ADP1879 510 VIN = 13V VIN = 16.5V +125°C +25°C –40°C 775 FREQUENCY (kHz) FREQUENCY (kHz) 480 450 420 390 700 625 550 360 0 1200 2400 3600 4800 6000 7200 8400 9600 10,800 12,000 LOAD CURRENT (mA) 400 09441-029 300 0 6000 8000 10,000 12,000 Figure 32. Frequency vs. Load Current, VOUT = 1.0 MHz, 0.8 V 1225 675 VIN = 13V VIN = 16.5V 655 4000 LOAD CURRENT (mA) Figure 29. Frequency vs. Load Current, 600 kHz, VOUT = 0.8 V VIN = 13V VIN = 16.5V 1150 +125°C +25°C –40°C 1075 FREQUENCY (kHz) 635 615 595 575 555 1000 925 850 775 700 535 495 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 LOAD CURRENT (mA) Figure 30. Frequency vs. Load Current, 600 kHz, VOUT = 1.8 V 550 0 1200 2400 3600 4800 6000 7200 8400 9600 10,800 12,000 LOAD CURRENT (mA) Figure 33. Frequency vs. Load Current, 1.0 MHz, VOUT = 1.8 V Rev. B | Page 11 of 40 09441-033 625 +125°C +25°C –40°C 515 09441-030 FREQUENCY (kHz) 2000 09441-032 475 330 ADP1878/ADP1879 Data Sheet 1450 82 VIN = 13V VIN = 16.5V 1400 +125°C +25°C –40°C MAXIMUM DUTY CYCLE (%) 1300 1250 1200 1150 1100 76 74 72 70 68 66 1050 800 1600 2400 3200 4000 4800 5600 6400 7200 8000 LOAD CURRENT (mA) 62 5.5 09441-034 7.9 9.1 10.3 11.5 12.7 13.9 15.1 16.3 VIN (V) Figure 37. Maximum Duty Cycle vs. High Voltage Input (VIN) Figure 34. Frequency vs. Load Current, 1.0 MHz, VOUT = 5 V 2.658 680 2.657 630 VREG = 2.7V VREG = 3.6V VREG = 5.5V 580 MINiMUM OFF TIME (ns) 2.656 2.655 2.654 2.653 2.652 530 480 430 380 330 2.651 280 2.650 230 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 180 –40 09441-035 2.649 –40 6.7 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 35. UVLO vs. Temperature 09441-038 0 09441-037 64 1000 UVLO (V) 78 Figure 38. Minimum Off Time vs. Temperature 95 680 +125°C +25°C –40°C 90 +125°C +25°C –40°C 630 580 MINIMUM OFF TIME (ns) 85 80 75 70 65 530 480 430 380 330 280 60 230 400 500 600 700 800 900 FREQUENCY (kHz) 1000 09441-036 55 300 Figure 36. Maximum Duty Cycle vs. Frequency 180 2.7 3.1 3.5 3.9 4.3 4.7 5.1 VREG (V) Figure 39. Minimum Off Time vs. VREG (Low Input Voltage) Rev. B | Page 12 of 40 5.5 09441-039 FREQUENCY (kHz) 1350 MAXIMUM DUTY CYCLE (%) +125°C +25°C –40°C 80 Data Sheet 80 +125°C +25°C –40°C RECTIFIER DROP (mV) 640 560 480 400 320 240 160 400 500 600 700 800 900 1000 FREQUENCY (kHz) 1200 1120 VIN = 5.5V VIN = 13V VIN = 16.5V 1MHz 300kHz 48 40 32 24 16 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VREG (V) Figure 43. Low-Side MOSFET Body Diode Conduction Time vs. VREG TA = 25°C OUTPUT VOLTAGE 1 1040 RECTIFIER DROP (mV) 56 8 2.7 Figure 40. Internal Rectifier Drop vs. Frequency 1280 +125°C +25°C –40°C 64 09441-040 80 300 300kHz 1MHz 72 09441-043 720 VREG = 2.7V VREG = 3.6V VREG = 5.5V BODY DIODE CONDUCTION TIME (ns) 800 ADP1878/ADP1879 960 880 800 INDUCTOR CURRENT 720 2 640 560 SW NODE 480 400 3 320 240 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VREG (V) Figure 41. Internal Boost Rectifier Drop vs. VREG (Low Input Voltage) Over VIN Variation 720 640 300kHz 1MHz CH1 50mV BW CH3 10V BW 09441-041 80 2.7 LOW SIDE 4 CH2 5A Ω CH4 5V M400ns T 35.8% A CH2 3.90A 09441-044 160 Figure 44. Power Saving Mode (PSM) Operational Waveform, 100 mA +125°C +25°C –40°C OUTPUT VOLTAGE INDUCTOR CURRENT 480 2 400 320 SW NODE 240 3 160 LOW SIDE 80 2.7 3.1 3.5 3.9 4.3 4.7 5.1 VREG (V) 5.5 Figure 42. Internal Boost Rectifier Drop vs. VREG CH1 50mV BW CH3 10V BW CH2 5A Ω CH4 5V M4.0µs T 35.8% A CH2 Figure 45. PSM Waveform at Light Load, 500 mA Rev. B | Page 13 of 40 3.90A 09441-045 4 09441-042 RECTIFIER DROP (mV) 1 560 ADP1878/ADP1879 Data Sheet OUTPUT VOLTAGE 2 4 OUTPUT VOLTAGE INDUCTOR CURRENT 12A NEGATIVE STEP 1 SW NODE 1 3 SW NODE LOW SIDE 3 M400ns CH4 100mV A CH3 2.20V B W T 30.6% CH1 10A Ω CH3 20V Figure 46. CCM Operation at Heavy Load, 12 A (See Figure 95 for Application Circuit) CH2 200mV CH4 5V B W M20µs A CH1 3.40A T 48.2% 09441-049 CH1 5A Ω CH3 10V 09441-046 4 Figure 49. Negative Step During Heavy Load Transient Behavior—PSM Enabled, 12 A (See Figure 95 Application Circuit) OUTPUT VOLTAGE 2 4 OUTPUT VOLTAGE 12A STEP 12A STEP LOW SIDE 1 1 SW NODE 3 2 SW NODE LOW SIDE 4 B W M2ms T 75.6% A CH1 3.40A CH1 10A Ω CH3 20V Figure 47. Load Transient Step—PSM Enabled, 12 A (See Figure 95 Application Circuit) CH2 5V CH4 200mV B W M2ms T 15.6% A CH1 6.20A 09441-050 CH2 200mV CH4 5V 09441-047 3 CH1 10A Ω CH3 20V Figure 50. Load Transient Step—Forced PWM at Light Load, 12 A (See Figure 95 Application Circuit) OUTPUT VOLTAGE OUTPUT VOLTAGE 2 4 12A POSITIVE STEP 12A POSITIVE STEP SW NODE 1 LOW SIDE 1 3 2 SW NODE LOW SIDE 4 B W M20µs T 30.6% A CH1 3.40A CH1 10A Ω CH3 20V Figure 48. Positive Step During Heavy Load Transient Behavior—PSM Enabled, 12 A, VOUT = 1.8 V (See Figure 95 Application Circuit) CH2 5V CH4 200mV M20µs B W T 43.8% A CH1 6.20A 09441-051 CH2 200mV CH4 5V 09441-048 3 CH1 10A Ω CH3 20V Figure 51. Positive Step During Heavy Load Transient Behavior—Forced PWM at Light Load, 12 A, VOUT = 1.8 V (See Figure 95 Application Circuit) Rev. B | Page 14 of 40 Data Sheet ADP1878/ADP1879 OUTPUT VOLTAGE OUTPUT VOLTAGE 2 1 INDUCTOR CURRENT 12A NEGATIVE STEP 2 1 SW NODE LOW SIDE 4 3 SW NODE LOW SIDE CH2 200mV CH4 5V B W M10µs A CH1 5.60A T 23.8% CH1 2V BW CH2 5A Ω CH3 10V CH4 5V Figure 52. Negative Step During Heavy Load Transient Behavior—Forced PWM at Light Load, 12 A (See Figure 95 Application Circuit) M2ms T 32.8% A CH1 720mV 09441-055 CH1 10A Ω CH3 20V 3 09441-052 4 Figure 55. Start-Up Behavior at Heavy Load, 12 A, 300 kHz (See Figure 95 Application Circuit) OUTPUT VOLTAGE OUTPUT VOLTAGE 1 1 INDUCTOR CURRENT 2 INDUCTOR CURRENT LOW SIDE 2 LOW SIDE 4 4 SW NODE SW NODE 3 M4ms T 49.4% A CH1 920mV CH1 2V BW CH2 5A Ω CH3 10V CH4 5V Figure 53. Output Short-Circuit Behavior Leading to Hiccup Mode 1 M4ms T 41.6% A CH1 720mV 09441-056 CH1 2V BW CH2 5A Ω CH3 10V CH4 5V 09441-053 3 Figure 56. Power-Down Waveform During Heavy Load OUTPUT VOLTAGE OUTPUT VOLTAGE 1 INDUCTOR CURRENT INDUCTOR CURRENT 2 2 SW NODE SW NODE 3 3 LOW SIDE LOW SIDE 4 A CH2 8.20A CH1 50mV BW CH3 10V BW Figure 54. Magnified Waveform During Hiccup Mode CH2 5A Ω CH4 5V M2µs T 35.8% A CH2 3.90A 09441-057 M10µs T 36.2% 09441-054 4 CH1 5V BW CH2 10A Ω CH3 10V CH4 5V Figure 57. Output Voltage Ripple Waveform During PSM Operation at Light Load, 2 A Rev. B | Page 15 of 40 ADP1878/ADP1879 Data Sheet TA = 25°C VREG = 5.5V VREG = 3.6V VREG = 2.7V 570 TRANSCONDUCTANCE (µS) LOW SIDE 4 HIGH SIDE SW NODE 3 2 550 530 510 490 470 450 M M40ns T 29.0% A CH2 4.20V 430 –40 09441-058 CH3 5V MATH 2V 40ns CH2 5V CH4 2V 20 40 60 80 100 680 +125°C +25°C –40°C TRANSCONDUCTANCE (µS) 630 22ns (tpdhDRVH ) HIGH SIDE 25ns (tr,DRVH ) SW NODE 3 2 530 480 430 380 HS MINUS SW CH2 5V CH3 5V CH4 2V MATH 2V 40ns M40ns T 29.0% A CH2 4.20V 330 2.7 09441-059 M 580 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 VREG (V) 09441-062 4 120 Figure 61. Transconductance vs. Temperature TA = 25°C 16ns (tf,DRVL ) 0 TEMPERATURE (°C) Figure 58. Output Drivers and SW Node Waveforms LOW SIDE –20 09441-061 HS MINUS SW Figure 62. Transconductance vs. VREG Figure 59. High-Side Driver Rising and Low-Side Falling Edge Waveforms (CIN = 4.3 nF (High-/Low-Side MOSFET), QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3)) 1.30 18ns (tr,DRVL ) LOW SIDE 1.25 QUIESCENT CURRENT (mA) 1.20 4 24ns (tpdh,DRVL ) HIGH SIDE HS MINUS SW 11ns (tf,DRVH) SW NODE 3 2 1.15 +125°C 1.10 1.05 +25°C 1.00 0.95 –40°C 0.90 0.85 0.80 M M20ns T 39.2% A CH2 4.20V 0.70 2.7 09441-060 CH3 5V MATH 2V 20ns CH2 5V CH4 2V 3.1 3.5 3.9 4.3 4.7 VREG (V) Figure 60. High-Side Driver Falling and Low-Side Rising Edge Waveforms (CIN = 4.3 nF (High-/Low-Side MOSFET), QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3)) Rev. B | Page 16 of 40 Figure 63. Quiescent Current vs. VREG 5.1 5.5 09441-063 0.75 TA = 25°C Data Sheet ADP1878/ADP1879 THEORY OF OPERATION BLOCK DIAGRAM PGOOD 690mV FB 600mV ADP1878/ADP1879 530mV VREG tON TIMER PRECISION ENABLE EN C TO ENABLE ALL BLOCKS THRESHOLD/ HYSTERESIS 630mV VIN I SW INFORMATION LDO VREG R (TRIMMED) tON = 2RC(VOUT/VIN) REF SW FILTER VREG BST BIAS BLOCK AND REFERENCE STATE MACHINE REF_ZERO TON BG_REF ISS SS COMP SS PSM IN_PSM IN_SS DRVH 300kΩ HS_0 HS LEVEL SHIFT SS_REF COMP COMP PWM FB SW IREV SW 8kΩ LS LS_0 VREG LS ERROR AMP 0.6V HS IN_HICCUP DRVL 800kΩ PGND PWM IREV COMP LOWER COMP CLAMP CS AMP REF_ZERO ADC RES DETECT AND GAIN SET CS GAIN SET GND RES 09441-064 0.4V Figure 64. ADP1878/ADP1879 Block Diagram The ADP1878/ADP1879 are versatile current-mode, synchronous step-down controllers that provide superior transient response, optimal stability, and current-limit protection by using a constant on time, pseudo fixed frequency with a programmable current sense gain, current control scheme. In addition, these devices offer optimum performance at low duty cycles by using a valley, currentmode control architecture. This allows the ADP1878/ADP1879 to drive all N-channel power stages to regulate output voltages to as low as 0.6 V. Rev. B | Page 17 of 40 ADP1878/ADP1879 Data Sheet STARTUP PRECISION ENABLE CIRCUITRY Each ADP1878/ADP1879 has an internal regulator (VREG) for biasing and supplying power for the integrated N-channel MOSFET drivers. Place a bypass capacitor directly across the VREG (Pin 7) and PGND (Pin 13) pins. Included in the powerup sequence is the biasing of the current sense amplifier, the current sense gain circuit (see the Programming Resistor (RES) Detect Circuit section), the soft start circuit, and the error amplifier. The ADP1878/ADP1879 have precision enable circuitry. The precision enable threshold is 630 mV including 30 mV of hysteresis (see Figure 66). Connecting the EN pin to GND disables the ADP1878/ADP1879, reducing the supply current of the device to approximately 140 µA. The soft start and error amplifier blocks determine the rise time of the output voltage (see the Soft Start section). At the beginning of a soft start, the error amplifier charges the external compensation capacitor, causing the COMP pin to rise (see Figure 65). Tying the VREG pin to the EN pin via a pull-up resistor causes the voltage at the EN pin to rise above the enable threshold of 630 mV, thereby enabling the ADP1878/ADP1879. COMP >2.4V 2.4V HICCUP MODE INITIALIZED MAXIMUM CURRENT (UPPER CLAMP) 10kΩ PRECISION ENABLE COMP. EN TO ENABLE ALL BLOCKS 630mV 09441-065 The current sense blocks provide valley current information (see the Programming Resistor (RES) Detect Circuit section) and they are a variable of the compensation equation for loop stability (see the Compensation Network section). In a process performed by the RES detect circuit, the valley current information is extracted by forcing 0.4 V across the RES and PGND pins generating current. The current through the RES resistor is used to set the current sense amplifier gain (see the Programming Resistor (RES) Detect Circuit section). This process takes approximately 800 µs, after which time the drive signal pulses appear at the DRVL and DRVH pins synchronously, and the output voltage begins to rise in a controlled manner through the soft start sequence. VREG Figure 66. Connecting EN Pin to VREG via a Pull-Up Resistor to Enable the ADP1878/ADP1879 UNDERVOLTAGE LOCKOUT The undervoltage lockout (UVLO) feature prevents the device from operating both the high- and low-side N-channel MOSFETs at extremely low or undefined input voltage (VIN) ranges. Operation at an undefined bias voltage can result in the incorrect propagation of signals to the high-side power switches. This, in turn, results in invalid output behavior that can cause damage to the output devices, ultimately destroying the device tied at the output. The UVLO level is set at 2.65 V (nominal). ON-BOARD LOW DROPOUT (LDO) REGULATOR The ADP1878/ADP1879 use an on-board LDO to bias the internal digital and analog circuitry. With proper bypass capacitors connected to the VREG pin (output of the internal LDO), this pin also provides power for the internal MOSFET drivers. It is recommended to float VREG if VIN is used for greater than 5.5 V operation. The minimum voltage at which bias is guaranteed to operate is 2.75 V at VREG (see Figure 67). ON-BOARD REGULATOR VREG 1.0V ZERO CURRENT USABLE RANGE ONLY AFTER SOFT START PERIOD IF CONTINUOUS CONDUCTION MODE OF OPERATION IS SELECTED. REF 09441-067 500mV VIN LOWER CLAMP Figure 67. On-Board Regulator For applications where VIN is decoupled from VREG, the minimum voltage at VIN must be 2.9 V. It is recommended to tie VIN and VREG together if the VIN pin is subjected to a 2.75 V rail. 09441-066 0V Figure 65. COMP Voltage Range SOFT START The ADP1878 employs externally programmable, soft start circuitry that charges up a capacitor tied to the SS pin to GND. This prevents input inrush current through the external MOSFET from the input supply (VIN). The output tracks the ramping voltage by producing PWM output pulses to the high-side MOSFET. The purpose is to limit the inrush current from the high voltage input supply (VIN) to the output (VOUT). Rev. B | Page 18 of 40 Data Sheet ADP1878/ADP1879 Table 5. Power Input and LDO Output Configurations VREG Float Connect to VIN 5.5 V fSW 690mV 09441-078 PWM OUTPUT 09441-079 530mV HYSTERESIS (50mV) 640mV FB PGOOD REASSERT 600mV Figure 78. Load Transient Response Operation 530mV POWER-GOOD MONITORING 0V SOFT START PGOOD DEASSERTION AT POWER-DOWN VEXT tPGD PGOOD 0V tPGD tPGD tPGD 09441-080 The ADP1878/ADP1879 power-good circuitry monitors the output voltage via the FB pin. The PGOOD pin is an opendrain output that can be pulled up by an external resistor to a voltage rail that does not necessarily have to be VREG. When the internal NMOS switch is in high impedance (off state), this means that the PGOOD pin is logic high and the output voltage via the FB pin is within the specified regulation window. When PGOOD ASSERTION AT POWER-UP Figure 80. Power-Good Timing Diagram, tPGD = 12 μs (Diagram May Look Disproportionate For Illustration Purposes) Rev. B | Page 23 of 40 ADP1878/ADP1879 Data Sheet APPLICATIONS INFORMATION FEEDBACK RESISTOR DIVIDER Table 8. Recommended Inductors The required resistor divider network can be determined for a given VOUT value because the internal band gap reference (VREF) is fixed at 0.6 V. Selecting values for RT and RB determine the minimum output load current of the converter. Therefore, for a given value of RB, the RT value can be determined through the following expression: L (µH) 0.12 0.22 0.47 0.72 0.9 1.2 1.0 1.4 2.0 0.8 𝑅𝑇 = 𝑅𝐵 × (𝑉𝑂𝑈𝑇 − 0.6 V) 0.6 V INDUCTOR SELECTION The inductor value is inversely proportional to the inductor ripple current. The peak-to-peak ripple current is given by ∆𝐼𝐿 = 𝐾𝐼 × 𝐼𝐿𝑂𝐴𝐷 (𝑉𝐼𝑁 − 𝑉𝑂𝑈𝑇 ) 𝑉𝑂𝑈𝑇 × 𝑉𝐼𝑁 ∆𝐼𝐿 × 𝑓𝑆𝑊 where: VIN is the high voltage input. VOUT is the desired output voltage. fSW is the controller switching frequency (300 kHz, 600 kHz, and 1.0 MHz). When selecting the inductor, choose an inductor saturation rating that is above the peak current level, and then calculate the inductor current ripple (see the Valley Current-Limit Setting section and Figure 81). Manufacturer Würth Elek. Würth Elek. Würth Elek. Würth Elek. Würth Elek. Würth Elek. Würth Elek. Würth Elek. Würth Elek. Sumida Model Number 744303012 744303022 744355147 744325072 744318120 744325120 7443552100 744318180 7443551200 CEP125U-0R8 ΔI = 50% ΔI = 40% ΔVRR = (0.01) × VOUT OUTPUT CAPACITOR SELECTION The primary objective of the output capacitor is to facilitate the reduction of the output voltage ripple; however, the output capacitor also assists in the output voltage recovery during load transient events. For a given load current step, the output voltage ripple generated during this step event is inversely proportional to the value chosen for the output capacitor. The speed at which the output voltage settles during this recovery period depends on where the crossover frequency (loop bandwidth) is set. This crossover frequency is determined by the output capacitor, the equivalent series resistance (ESR) of the capacitor, and the compensation network. To calculate the small signal voltage ripple (output ripple voltage) at the steady state operating point, use the following equation: ΔI = 33% 1 𝐶𝑂𝑈𝑇 = ∆𝐼𝐿 × � � 8 × 𝑓𝑆𝑊 × [∆𝑉𝑅𝐼𝑃𝑃𝐿𝐸 − (∆𝐼𝐿 × 𝐸𝑆𝑅)] where ESR is the equivalent series resistance of the output capacitors. To calculate the output load step, use the following equation: 6 8 10 12 14 16 18 20 22 VALLEY CURRENT LIMIT (A) 24 26 28 30 09441-081 PEAK INDUCTOR CURRENT (A) Dimensions (mm) 10.2 × 7 10.2 × 7 14.2 × 12.8 10.5 × 10.2 14 × 12.8 10.5 × 10.2 10.2 × 10.2 14 × 12.8 10.2 × 10.2 The output ripple voltage is the ac component of the dc output voltage during steady state. For a ripple error of 1.0%, the output capacitor value needed to achieve this tolerance can be determined using the following equation. (Note that an accuracy of 1.0% is possible during steady state conditions only, not during load transients.) The equation for the inductor value is given by 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 ISAT (A) 55 30 50 35 32 25 16 24 23 27.5 OUTPUT RIPPLE VOLTAGE (ΔVRR) 𝐼𝐿𝑂𝐴𝐷 ≈ 3 where KI is typically 0.33. 𝐿= DCR (mΩ) 0.33 0.33 0.8 1.65 1.6 1.8 3.8 3.2 2.6 Figure 81. Peak Inductor Current vs. Valley Current Limit for 33%, 40%, and 50% of Inductor Ripple Current 𝐶𝑂𝑈𝑇 = 2 × ∆𝐼𝐿𝑂𝐴𝐷 𝑓𝑆𝑊 × �∆𝑉𝐷𝑅𝑂𝑂𝑃 − (∆𝐼𝐿𝑂𝐴𝐷 × 𝐸𝑆𝑅)� where ΔVDROOP is the amount that VOUT is allowed to deviate for a given positive load current step (ΔILOAD). Rev. B | Page 24 of 40 Data Sheet ADP1878/ADP1879 Ceramic capacitors are known to have low ESR. However, there is a trade-off in using the popular X5R capacitor technology because as much as 80% of its capacitance may be lost due to derating as the voltage applied across the capacitor is increased (see Figure 82). Although X7R series capacitors can also be used, the available selection is limited to 22 µF maximum. Error Amplifier Output Impedance (ZCOMP) Assuming CC2 is significantly smaller than CCOMP, CC2 can be omitted from the output impedance equation of the error amplifier. The transfer function simplifies to 20 and 10 X7R (50V) 𝑅𝐶𝑂𝑀𝑃 × �𝑓𝐶𝑅𝑂𝑆𝑆 2 + 𝑓𝑍𝐸𝑅𝑂2 𝑓𝐶𝑅𝑂𝑆𝑆 1 × 𝑓𝑆𝑊 12 where fZERO, the zero frequency, is set to be 1/4th of the crossover frequency for the ADP1878. 0 𝑓𝐶𝑅𝑂𝑆𝑆 = –10 –20 –30 –40 Error Amplifier Gain (Gm) –50 X5R (25V) The error amplifier gain (transconductance) is –60 Gm = 500 µA/V (µs) –70 X5R (16V) –80 Current-Sense Loop Gain (GCS) 10µF TDK 25V, X7R, 1210 C3225X7R1E106M 22µF MURATA 25V, X7R, 1210 GRM32ER71E226KE15L 47µF MURATA 16V, X5R, 1210 GRM32ER61C476KE15L –90 –100 0 5 10 15 20 25 DC VOLTAGE (VDC) 30 The current-sense loop gain is 09441-082 CAPACITANCE CHARGE (%) 𝑍𝐶𝑂𝑀𝑃 = 𝐺𝐶𝑆 = Figure 82. Capacitance vs. DC Voltage Characteristics for Ceramic Capacitors 1 (𝐴⁄𝑉 ) 𝐴𝐶𝑆 × 𝑅𝑂𝑁 Electrolytic capacitors satisfy the bulk capacitance requirements for most high current applications. However, because the ESR of electrolytic capacitors is much higher than that of ceramic capacitors, mount several MLCCs in parallel with the electrolytic capacitors to reduce the overall series resistance. where: ACS (V/V) is programmable for 3 V/V, 6 V/V, 12 V/V, and 24 V/V (see the Programming Resistor (RES) Detect Circuit and Valley Current-Limit Setting sections). RON is the channel impedance of the low-side MOSFET. COMPENSATION NETWORK Crossover Frequency Due to its current-mode architecture, the ADP1878/ADP1879 require Type II compensation. To determine the component values needed for compensation (resistance and capacitance values), it is necessary to examine the overall loop gain (H) of the converter at the unity-gain frequency (fSW/10) when H = 1 V/V: 𝐻 = 1 V⁄V = 𝐺𝑀 × 𝐺𝐶𝑆 × 𝑉𝑅𝐸𝐹 × 𝑍𝐶𝑂𝑀𝑃 × 𝑍𝐹𝐼𝐿𝑇 𝑉𝑂𝑈𝑇 Examining each variable at high frequency enables the unitygain transfer function to be simplified to provide expressions for the RCOMP and CCOMP component values. Output Filter Impedance (ZFILT) Examining the transfer function of the filter at high frequencies simplifies to 𝑍𝐹𝐼𝐿𝑇𝐸𝑅 = 𝑅𝐿 × The crossover frequency is the frequency at which the overall loop (system) gain is 0 dB (H = 1 V/V). It is recommended for current-mode converters, such as the ADP1878, that the user set the crossover frequency between 1/10th and 1/15th of the switching frequency. 𝑓𝐶𝑅𝑂𝑆𝑆 = 1 𝑓 12 𝑆𝑊 The relationship between CCOMP and fZERO (zero frequency) is as follows: 𝑓𝑍𝐸𝑅𝑂 = 1 2𝜋 × 𝑅𝐶𝑂𝑀𝑃 × 𝐶𝐶𝑂𝑀𝑃 The zero frequency is set to 1/4th of the crossover frequency. Combining all of the above parameters results in 𝑅𝐶𝑂𝑀𝑃 = 1 + 𝑠 × 𝐸𝑆𝑅 × 𝐶𝑂𝑈𝑇 1 + 𝑠(𝑅𝐿 + 𝐸𝑆𝑅)𝐶𝑂𝑈𝑇 𝑓𝐶𝑅𝑂𝑆𝑆 �𝑓𝐶𝑅𝑂𝑆𝑆 + 𝑓𝑍𝐸𝑅𝑂 at the crossover frequency (s = 2πfCROSS). ESR is the equivalent series resistance of the output capacitors. 2 𝑉𝑂𝑈𝑇 1 × 𝑉𝑅𝐸𝐹 𝐺𝑀 𝐺𝐶𝑆 2 × �12 + (𝑠(𝑅𝐿 + 𝐸𝑆𝑅)𝐶𝑂𝑈𝑇 )2 �12 + (𝑠 × 𝐸𝑆𝑅 × 𝐶𝑂𝑈𝑇 )2 × where ESR is the equivalent series resistance of the output capacitors. 𝐶𝐶𝑂𝑀𝑃 = Rev. B | Page 25 of 40 1 2 × 𝜋 × 𝑅𝐶𝑂𝑀𝑃 × 𝑓𝑍𝐸𝑅𝑂 1 × 𝑅𝐿 ADP1878/ADP1879 Data Sheet 800 An important criteria to consider in constructing a dc-to-dc converter is efficiency. By definition, efficiency is the ratio of the output power to the input power. For high power applications at load currents of up to 20 A, the following are important MOSFET parameters that aid in the selection process: 720     VGS (TH) is the MOSFET voltage applied between the gate and the source that starts channel conduction. RDS (ON) is the on resistance of the MOSFET during channel conduction. QG is the total gate charge. CN1 is the input capacitance of the high-side switch. CN2 is the input capacitance of the low-side switch. 640 560 480 400 320 240 80 300 Channel Conduction Loss During normal operation, the bulk of the loss in efficiency is due to the power dissipated through MOSFET channel conduction. Power loss through the high-side MOSFET is directly proportional to the duty cycle (D) for each switching period, and the power loss through the low-side MOSFET is directly proportional to 1 − D for each switching period. The selection of MOSFETs is governed by the maximum dc load current that the converter is expected to deliver. In particular, the selection of the low-side MOSFET is dictated by the maximum load current because a typical high current application employs duty cycles of less than 50%. Therefore, the low-side MOSFET is in the on state for most of the switching period. 1 1 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz) Figure 83. Internal Rectifier Voltage Drop vs. Switching Frequency MOSFET Switching Loss Channel conduction loss (both of the MOSFETs). MOSFET driver loss. MOSFET switching loss. Body diode conduction loss (low-side MOSFET). Inductor loss (copper and core loss). 1, 2 +125°C +25°C –40°C 160 The following are the losses experienced through the external component during normal switching operation:      VREG = 2.7V VREG = 3.6V VREG = 5.5V 09441-083  RECTIFIER VOLTAGE DROP (mV) EFFICIENCY CONSIDERATION The SW node transitions due to the switching activities of the high- and low-side MOSFETs. This causes removal and replenishing of charge to and from the gate oxide layer of the MOSFET, as well as to and from the parasitic capacitance associated with the gate oxide edge overlap and the drain and source terminals. The current that enters and exits these charge paths presents additional loss during these transition times. This can be approximately quantified by using the following equation, which represents the time in which charge enters and exits these capacitive regions: tSW-TRANS = RGATE × CTOTAL where: CTOTAL is the CGD + CGS of the external MOSFET. RGATE is the gate input resistance of the external MOSFET. The ratio of this time constant to the period of one switching cycle is the multiplying factor to be used in the following expression: -TRANS 2 or 2 MOSFET Driver Loss PSW(LOSS) = fSW × RGATE × CTOTAL × ILOAD × VIN × 2 Other dissipative elements are the MOSFET drivers. The contributing factors are the dc current flowing through the driver during operation and the QGATE parameter of the external MOSFETs. PDR(LOSS) = [VDR × (fSWCupperFETVDR + IBIAS)] + [VREG × (fSWClowerFETVREG + IBIAS)] where: CupperFET is the input gate capacitance of the high-side MOSFET. ClowerFET is the input gate capacitance of the low-side MOSFET. IBIAS is the dc current flowing into the high- and low-side drivers. VDR is the driver bias voltage (that is, the low input voltage (VREG) minus the rectifier drop (see Figure 83)). VREG is the bias voltage. Body Diode Conduction Loss The ADP1878/ADP1879 employ anti cross conduction circuitry that prevents the high- and low-side MOSFETs from conducting current simultaneously. This overlap control is beneficial, avoiding large current flow that may lead to irreparable damage to the external components of the power stage. However, this blanking period comes with the trade-off of a diode conduction loss occurring immediately after the MOSFETs change states and continuing well into idle mode. Rev. B | Page 26 of 40 Data Sheet ADP1878/ADP1879 The amount of loss through the body diode of the low-side MOSFET during the anti overlap state is given by the following expression: 2 where: tBODY(LOSS) is the body conduction time (refer to Figure 84 for dead time periods). tSW is the period per switching cycle. VF is the forward drop of the body diode during conduction. (Refer to the selected external MOSFET data sheet for more information about the VF parameter.) If bulk electrolytic capacitors are used, it is recommended to use multilayered ceramic capacitors (MLCC) in parallel due to their low ESR values. This dramatically reduces the input voltage ripple amplitude as long as the MLCCs are mounted directly across the drain of the high-side MOSFET and the source terminal of the low-side MOSFET (see the Layout Considerations section). Improper placement and mounting of these MLCCs may cancel their effectiveness due to stray inductance and an increase in trace impedance. +125°C +25°C –40°C 1MHz 300kHz 72 , 56 48 40 32 VMAX,RIPPLE = VRIPP + (ILOAD,MAX × ESR) 24 16 8 2.7 , The maximum input voltage ripple and maximum input capacitor rms current occur at the end of the duration of 1 − D while the high-side MOSFET is in the off state. The input capacitor rms current reaches its maximum at time D. When calculating the maximum input voltage ripple, account for the ESR of the input capacitor as follows: 64 3.4 4.1 4.8 VREG (V) 5.5 09441-084 BODY DIODE CONDUCTION TIME (ns) 80 capacitors have such high ESR that they cause undesired input voltage ripple magnitudes and are generally not effective at high switching frequencies. Figure 84. Body Diode Conduction Time vs. Low Voltage Input (VREG) where: VRIPP is usually 1% of the minimum voltage input. ILOAD,MAX is the maximum load current. ESR is the equivalent series resistance rating of the input capacitor. Inserting VMAX,RIPPLE into the charge balance equation to calculate the minimum input capacitor requirement gives Inductor Loss During normal conduction mode, further power loss is caused by the conduction of current through the inductor windings, which have dc resistance (DCR). Typically, larger sized inductors have smaller DCR values. The inductor core loss is a result of the eddy currents generated within the core material. These eddy currents are induced by the changing flux, which is produced by the current flowing through the windings. The amount of inductor core loss depends on the core material, the flux swing, the frequency, and the core volume. Ferrite inductors have the lowest core losses, whereas powdered iron inductors have higher core losses. It is recommended to use shielded ferrite core material type inductors with the ADP1878/ADP1879 for a high current, dc-to-dc switching application to achieve minimal loss and negligible electromagnetic interference (EMI). INPUT CAPACITOR SELECTION The goal in selecting an input capacitor is to reduce or minimize input voltage ripple and to reduce the high frequency source impedance, which is essential for achieving predictable loop stability and transient performance. The problem with using bulk capacitors, other than their physical geometries, is their large equivalent series resistance (ESR) and large equivalent series inductance (ESL). Aluminum electrolytic 1 , , , or , , 4 , where D = 50%. THERMAL CONSIDERATIONS The ADP1878/ADP1879 are used for dc-to-dc, step down, high current applications that have an on-board controller, an on-board LDO, and on-board MOSFET drivers. Because applications may require up to 20 A of load current and be subjected to high ambient temperature, the selection of external high- and low-side MOSFETs must be associated with careful thermal consideration to not exceed the maximum allowable junction temperature of 125°C. To avoid permanent or irreparable damage, if the junction temperature reaches or exceeds 155°C, the part enters thermal shutdown, turning off both external MOSFETs, and is not reenabled until the junction temperature cools to 140°C (see the On-Board Low Dropout (LDO) Regulator section). In addition, it is important to consider the thermal impedance of the package. Because the ADP1878/ADP1879 employ an on-board LDO, the ac current (fxCxV) consumed by the internal drivers to drive the external MOSFETs, adds another element of Rev. B | Page 27 of 40 ADP1878/ADP1879 Data Sheet power dissipation across the internal LDO. Equation 3 shows the power dissipation calculations for the integrated drivers and for the internal LDO. Table 9 lists the thermal impedance for the ADP1878/ADP1879, which are available in a 14-lead LFCSP_WD. The rise in package temperature is directly proportional to its thermal impedance characteristics. The following equation represents this proportionality relationship: Table 9. Thermal Impedance for 14-Lead LFCSP_WD where: θJA is the thermal resistance of the package from the junction to the outside surface of the die, where it meets the surrounding air. PDR(LOSS) is the overall power dissipated by the IC. Package 14-Lead LFCSP_WD θJA 4-Layer Board Thermal Impedance 30°C/W Figure 85 specifies the maximum allowable ambient temperature that can surround the ADP1878/ADP1879 IC for a specified high input voltage (VIN). Figure 85 illustrates the temperature derating conditions for each available switching frequency for low, typical, and high output setpoints for the 14-lead LFCSP_WD package. All temperature derating criteria are based on a maximum IC junction temperature of 125°C. 120 110 The bulk of the power dissipated is due to the gate capacitance of the external MOSFETs and current running through the on-board LDO. The power loss equations for the MOSFET drivers and internal low dropout regulator (see the MOSFET Driver Loss section and the Efficiency Consideration section) are: PDR(LOSS) = [VDR × (fSWCupperFETVDR + IBIAS)] + [VREG × (fSWClowerFET VREG + IBIAS)] PDISS(LDO) = PDR(LOSS) + (VIN – VREG) × (fSW × CTOTAL × VREG + IBIAS 100 300kHz 600kHz 1MHz 90 5.5 (2) (3) where: CupperFET is the input gate capacitance of the high-side MOSFET. ClowerFET is the input gate capacitance of the low-side MOSFET. IBIAS is the dc current (2 mA) flowing into the high- and lowside drivers. VDR is the driver bias voltage (the low input voltage (VREG) minus the rectifier drop (see Figure 83)). VREG is the LDO output/bias voltage. 7.0 8.5 VOUT = 0.8V VOUT = 1.8V VOUT = HIGH SETPOINT 10.0 11.5 13.0 14.5 16.0 17.5 19.0 VIN (V) Figure 85. Ambient Temperature vs. VIN, 4-Layer Evaluation Board, CIN = 4.3 nF (High-/Low-Side MOSFET) The maximum junction temperature allowed for the ADP1878/ ADP1879 IC is 125°C. This means that the sum of the ambient temperature (TA) and the rise in package temperature (TR), which is caused by the thermal impedance of the package and the internal power dissipation, should not exceed 125°C, as dictated by the following expression: TJ = TR × TA (4) where PDISS(LDO) is the power dissipated through the pass device in the LDO block across VIN and VREG. 09441-085 MAXIMUM ALLOWABLE AMBIENT TEMPERATURE (°C) 130 TR = θJA × PDR(LOSS) PDR(LOSS) is the MOSFET driver loss. VIN is the high voltage input. VREG is the LDO output voltage and bias voltage. CTOTAL is the CGD + CGS of the external MOSFET. IBIAS is the dc input bias current. For example, if the external MOSFET characteristics are θJA (14-lead LFCSP_WD) = 30°C/W, fSW = 300 kHz, IBIAS = 2 mA, CupperFET = 3.3 nF, ClowerFET = 3.3 nF, VDR = 4.62 V, and VREG = 5.0 V, then the power loss is (1) where: TJ is the maximum junction temperature. TR is the rise in package temperature due to the power dissipated from within. TA is the ambient temperature. PDR(LOSS) = [VDR × (fSWCupperFETVDR + IBIAS)] + [VREG × (fSWClowerFETVREG + IBIAS)] = (4.62 × (300 × 103 × 3.3 × 10−9 × 4.62 + 0.002)) + (5.0 × (300 × 103 × 3.3 × 10−9 × 5.0 + 0.002)) = 57.12 mW PDISS(LDO) = (VIN – VREG) × (fSW × CTOTAL × VREG + IBIAS) = (13 V – 5 V) × (300 × 103 × 3.3 × 10−9 × 5 + 0.002) = 55.6 mW PDISS(TOTAL) = PDISS(LDO) + PDR(LOSS) = 77.13 mW + 55.6 mW = 132.73 mW Rev. B | Page 28 of 40 Data Sheet ADP1878/ADP1879 The rise in package temperature (for a 14-lead LFCSP_WD) is Current-Limit Programming The valley current is approximately TR = θJA × PDR(LOSS) 15 A − (5 A × 0.5) = 12.5 A = 30°C × 132.05 mW = 4.0°C Assuming a maximum ambient temperature environment of 85°C, TJ = TR × TA = 4.0°C + 85°C = 89.0°C, which is below the maximum junction temperature of 125°C. DESIGN EXAMPLE The ADP1878/ADP1879 are easy to use, requiring only a few design criteria. For example, the example outlined in this section uses only four design criteria: VOUT = 1.8 V, ILOAD = 15 A (pulsing), VIN = 12 V (typical), and fSW = 300 kHz. Input Capacitor The maximum input voltage ripple is usually 1% of the minimum input voltage (11.8 V × 0.01 = 120 mV). Output Capacitor Assume that a load step of 15 A occurs at the output and no more than 5% output deviation is allowed from the steady state operating point. In this case, the advantage of the ADP1878 is that because the frequency is pseudo fixed, the converter is able to respond quickly because of the immediate, though temporary, increase in switching frequency. Assuming the overall ESR of the output capacitor ranges from 5 mΩ to 10 mΩ, VMAX,RIPPLE = VRIPP − (ILOAD,MAX × ESR) = 120 mV − (15 A × 0.001) = 45 mV = 120 µF Choose a programmable resistor of RRES = 100 kΩ for a current sense gain of 24 V/V. ΔVDROOP = 0.05 × 1.8 V = 90 mV VRIPP = 120 mV 𝐶𝐼𝑁,𝑀𝐼𝑁 = Assuming a low-side MOSFET RON of 4.5 mΩ and 13 A, as the valley current limit from Table 7 and Figure 71 indicate, a programming resistor (RES) of 100 kΩ corresponds to an ACS of 24 V/V. 𝐼𝐿𝑂𝐴𝐷,𝑀𝐴𝑋 15 A = 4𝑓𝑆𝑊 𝑉𝑀𝐴𝑋,𝑅𝐼𝑃𝑃𝐿𝐸 4 × 300 × 103 × 105 mV 𝐶𝑂𝑈𝑇 = 2 × Choose five 22 µF ceramic capacitors. The overall ESR of five 22 µF ceramic capacitors is less than 1 mΩ. IRMS = ILOAD/2 = 7.5 A PCIN = (IRMS)2 × ESR = (7.5 A)2 × 1 mΩ = 56.25 mW Inductor =2× Therefore, an appropriate inductor selection is five 270 µF polymer capacitors with a combined ESR of 3.5 mΩ. Assuming an overshoot of 45 mV, determine if the output capacitor that was calculated previously is adequate 𝐶𝑂𝑈𝑇 = 𝐼𝐿𝑂𝐴𝐷 =5A 3 = Then, calculating for the inductor value 𝐿= �𝑉𝐼𝑁,𝑀𝐴𝑋 − 𝑉𝑂𝑈𝑇 � 𝑉𝑂𝑈𝑇 × 𝑉𝐼𝑁,𝑀𝐴𝑋 ∆𝐼𝐿 1.8 V 13.2 V – 1.8 V × = 5 V × 300 × 103 13.2 V (𝐿 × 𝐼2𝐿𝑂𝐴𝐷 ) ((𝑉𝑂𝑈𝑇 − ∆𝑉𝑂𝑉𝑆𝐻𝑇 )2 − (𝑉𝑂𝑈𝑇 )2 ) 1 × 10−6 × (15 A)2 (1.8 − 45 mV)2 − (1.8)2 = 1.4 mF Choose five 270 µF polymer capacitors. The rms current through the output capacitor is = 1.03 µH 𝐼𝑅𝑀𝑆 = The inductor peak current is approximately = 15 A + (5 A × 0.5) = 17.5 A Therefore, an appropriate inductor selection is 1.0 µH with DCR = 3.3 mΩ (Würth Elektronik 7443552100) with a peak current handling of 20 A. 15 A 300 × 103 × (90 mV) = 1.11 mF Determining inductor ripple current amplitude: ∆𝐼𝐿 ≈ ∆𝐼𝐿𝑂𝐴𝐷 𝑓𝑆𝑊 × (∆𝑉𝐷𝑅𝑂𝑂𝑃 ) 1 1 �𝑉𝐼𝑁,𝑀𝐴𝑋 − 𝑉𝑂𝑈𝑇 � 𝑉𝑂𝑈𝑇 × × 𝐿 × 𝑓𝑆𝑊 𝑉𝐼𝑁,𝑀𝐴𝑋 2 √3 1 1 (13.2 V – 1.8 V) 1.8 V × × =1.49 A 2 √3 1 µF×300×103 13.2 V The power loss dissipated through the ESR of the output capacitor is PCOUT = (IRMS)2 × ESR = (1.5 A)2 × 1.4 mΩ = 3.15 mW 𝑃𝐷𝐶𝑅(𝐿𝑂𝑆𝑆) = 𝐷𝐶𝑅 × 𝐼𝐿2 = 0.003 × (15 A)2 = 675 mW Rev. B | Page 29 of 40 ADP1878/ADP1879 Data Sheet Feedback Resistor Network Setup Loss Calculations Choosing RB = 1 kΩ as an example. Calculate RT as follows: Duty cycle = 1.8/12 V = 0.15 𝑅𝑇 = 1 kΩ × (1.8 V − 0.6 V) = 2 kΩ 0.6 V RON(N2) = 5.4 mΩ tBODY(LOSS) = 20 ns (body conduction time) Compensation Network To calculate RCOMP, CCOMP, and CPAR, the transconductance parameter and the current sense gain variable are required. The transconductance parameter (Gm) is 500 µA/V, and the current sense loop gain is 𝐺𝐶𝑆 1 1 = = = 8.33 A/V 𝐴𝐶𝑆 𝑅𝑂𝑁 24 × 0.005 VF = 0.84 V (MOSFET forward voltage) CIN = 3.3 nF (MOSFET gate input capacitance) QN1,N2 = 17 nC (total MOSFET gate charge) RGATE = 1.5 Ω (MOSFET gate input resistance) 2 𝑃𝑁1,𝑁2(𝐶𝐿) = �𝐷 × 𝑅𝑁1(𝑂𝑁) + (1 − 𝐷) × 𝑅𝑁2(𝑂𝑁) � × 𝐼𝐿𝑂𝐴𝐷 = (0.15 × 0.0054 + 0.85 × 0.0054) × (15 A)2 = 1.215 W where ACS and RON are taken from setting up the current limit (see the Programming Resistor (RES) Detect Circuit section and the Valley Current-Limit Setting section). 𝑃𝐵𝑂𝐷𝑌(𝐿𝑂𝑆𝑆) = The crossover frequency is 1/12th of the switching frequency: = 20 ns × 300 × 103 × 15 A × 0.84 × 2 = 151.2 mW 300 kHz/12 = 25 kHz The zero frequency is 1/4th of the crossover frequency: PSW(LOSS) = fSW × RGATE × CTOTAL × ILOAD × VIN × 2 = 300 × 103 × 1.5 Ω × 3.3 × 10−9 × 15 A × 12 × 2 = 534.6 mW 25 kHz/4 = 6.25 kHz 𝑅𝐶𝑂𝑀𝑃 = 𝑓𝐶𝑅𝑂𝑆𝑆 �𝑓𝐶𝑅𝑂𝑆𝑆 + 𝑓𝑍𝐸𝑅𝑂 2 1 1 𝑉𝑂𝑈𝑇 × × 𝑅𝐿 𝑉𝑅𝐸𝐹 𝐺𝑀 𝐺𝐶𝑆 𝑅𝐶𝑂𝑀𝑃 = 2 × 25 kΩ �12 + (𝑠(𝑅𝐿 + 𝐸𝑆𝑅)𝐶𝑂𝑈𝑇 )2 √25 kΩ2 + 6.25 kΩ2 �12 + (𝑠 × 𝐸𝑆𝑅 × 𝐶𝑂𝑈𝑇 × )2 �12 + (2π × 25 kΩ × ((1.8/15) + 0.0035) × 0.0011)2 �12 + (2π × 25 kΩ × 0.0035 × 0.0011)2 1.8 1 15 × × 0.6 500 × 10−6 × 8.3 1.8 × PDR(LOSS) = [VDR × (fSWCupperFETVDR + IBIAS)] + [VREG × (fSWClowerFETVREG +IBIAS)] =(4.62 × (300 ×103 × 3.3 × 10−9 × 4.62 + 0.002)) + (5.0 × (300 × 103 × 3.3 × 10−9 × 5.0 + 0.002)) = 57.12 mW × PDISS(LDO) = (VIN – VREG) × (fSW × CTOTAL × VREG + IBIAS) = (13 V – 5 V) × (300 × 103 × 3.3 × 10−9 × 5 + 0.002) = 55.6 mW PCOUT = (IRMS)2 × ESR = (1.5 A)2 × 1.4 mΩ = 3.15 mW 2 = 0.003 × (15 A)2 = 675 mW PDCR( LOSS) = DCR × I LOAD = 60.25 kΩ 𝐶𝐶𝑂𝑀𝑃 = 𝑡𝐵𝑂𝐷𝑌(𝐿𝑂𝑆𝑆) × 𝐼𝐿𝑂𝐴𝐷 × 𝑉𝐹 × 2 𝑡𝑆𝑊 1 PCIN = (IRMS)2 × ESR = (7.5 A)2 × 1 mΩ = 56.25 mW 2𝜋𝑅𝐶𝑂𝑀𝑃 𝑓𝑍𝐸𝑅𝑂 1 = 2 × 3.14 × 60.25 × 103 × 6.25 × 103 PLOSS = PN1,N2 + PBODY(LOSS) + PSW + PDCR + PDR + PDISS(LDO) + PCOUT + PCIN = 1.215 W + 151.2 mW + 534.6 mW + 57.12 mW + 55.6 + 3.15 mW + 675 mW + 56.25 mW = 2.655 W = 423 pF Rev. B | Page 30 of 40 Data Sheet ADP1878/ADP1879 EXTERNAL COMPONENT RECOMMENDATIONS The configurations listed in Table 10 are with fCROSS = 1/12 × fSW, fZERO = ¼ × fCROSS, RRES = 100 kΩ, RBOT = 1kΩ, RON = 5.4 mΩ (BSC042N03MS G), VREG = 5 V (float), and a maximum load current of 14 A. The ADP1879 models listed in Table 10 are the PSM versions of the device. Table 10. External Component Values Model ADP1878ACPZ-0.3-R7/ ADP1879ACPZ-0.3-R7 ADP1878ACPZ-0.6-R7/ ADP1879ACPZ-0.6-R7 ADP1878ACPZ-1.0-R7/ ADP1879ACPZ-1.0-R7 VOUT (V) 0.8 1.2 1.8 2.5 3.3 5 7 1.2 1.8 2.5 3.3 5 7 0.8 1.2 1.8 2.5 1.2 1.8 2.5 3.3 5 1.2 1.8 2.5 3.3 5 7 0.8 1.2 1.8 2.5 1.2 1.8 2.5 3.3 5 1.2 1.8 2.5 3.3 5 7 VIN (V) 13 13 13 13 13 13 13 16.5 16.5 16.5 16.5 16.5 16.5 5.5 5.5 5.5 5.5 13 13 13 13 13 16.5 16.5 16.5 16.5 16.5 16.5 5.5 5.5 5.5 5.5 13 13 13 13 13 16.5 16.5 16.5 16.5 16.5 16.5 CIN (μF) 5 × 222 5 × 222 4 × 222 4 × 222 5 × 222 4 × 222 4 × 222 4 × 222 3 × 222 3 × 222 3 × 222 3 × 222 3 × 222 5 × 222 5 × 222 5 × 222 5 × 222 3 × 222 5 × 109 5 × 109 5 × 109 5 × 109 3 × 109 4 × 109 4 × 109 4 × 109 4 × 109 4 × 109 5 × 222 5 × 222 3 × 222 3 × 222 3 × 109 4 × 109 4 × 109 5 × 109 4 × 109 3 × 109 3 × 109 4 × 109 4 × 109 3 × 109 3 × 109 COUT (μF) 5 × 5603 4 × 5603 4 × 2704 3 × 2704 2 × 3305 3305 222 + ( 4 × 476) 4 × 5603 4 × 2704 4 × 2704 2 × 3305 2 × 1507 222 + 4 × 476 4 × 5603 4 × 2704 3 × 2704 3 × 1808 5 × 2704 3 × 3305 3 × 2704 2 × 2704 1507 4 × 2704 2 × 3305 3 × 2704 3305 4 × 476 3 × 476 4 × 2704 2 × 3305 3 × 1808 2704 3 × 3305 3 × 2704 2704 2704 3 × 476 4 × 2704 3 × 2704 3 × 1808 2704 3 × 476 222 + 476 1 See the Inductor Selection section and Table 11. 22 μF Murata 25 V, X7R, 1210 GRM32ER71E226KE15L (3.2 mm × 2.5 mm × 2.5 mm). 3 560 μF Panasonic (SP-series) 2 V, 7 mΩ, 3.7 A EEFUE0D561LR (4.3 mm × 7.3 mm × 4.2 mm). 4 270 μF Panasonic (SP-series) 4 V, 7 mΩ, 3.7 A EEFUE0G271LR (4.3 mm × 7.3 mm × 4.2 mm). 5 330 μF Panasonic (SP-series) 4 V, 12 mΩ, 3.3 A EEFUE0G331R (4.3 mm × 7.3 mm × 4.2 mm). 6 47 μF Murata 16 V, X5R, 1210 GRM32ER61C476KE15L (3.2 mm × 2.5 mm × 2.5 mm). 7 150 μF Panasonic (SP-series) 6.3 V, 10 mΩ, 3.5 A EEFUE0J151XR (4.3 mm × 7.3 mm × 4.2 mm). 8 180 μF Panasonic (SP-series) 4 V, 10 mΩ, 3.5 A EEFUE0G181XR (4.3 mm × 7.3 mm × 4.2 mm). 9 10 μF TDK 25 V, X7R, 1210 C3225X7R1E106M. 2 Rev. B | Page 31 of 40 L1 (μH) 0.72 1.0 1.2 1.53 2.0 3.27 3.44 1.0 1.0 1.67 2.00 3.84 4.44 0.22 0.47 0.47 0.47 0.47 0.47 0.90 1.00 1.76 0.47 0.72 0.90 1.0 2.0 2.0 0.22 0.22 0.22 0.22 0.22 0.47 0.47 0.72 1.0 0.47 0.47 0.72 0.72 1.2 1.2 RC (kΩ) 56.9 56.9 56.9 57.6 56.9 40.7 40.7 56.9 56.9 57.6 56.9 41.2 40.7 56.2 56.9 56.9 56.9 56.9 56.2 57.6 57.6 40.7 56.9 53.6 57.6 53.0 41.2 40.7 54.9 49.3 56.9 54.9 53.6 56.9 54.9 56.2 40.7 56.9 56.9 56.9 56.2 40.7 40.7 CCOMP (pF) 620 620 470 470 470 680 680 620 470 470 510 680 680 300 270 220 220 360 270 240 240 360 300 270 270 270 360 300 200 220 130 130 200 180 180 180 220 270 220 200 180 220 180 CPAR (pF) 62 62 47 47 47 68 68 62 47 47 51 68 68 300 27 22 22 36 27 24 24 36 30 27 27 27 36 30 20 22 13 13 20 18 18 18 22 27 22 20 18 22 18 RTOP (kΩ) 0.3 1.0 2.0 3.2 4.5 7.3 10.7 1.0 2.0 3.2 4.5 7.3 10.7 0.3 1.0 2.0 3.2 1.0 2.0 3.2 4.5 7.3 1.0 2.0 3.2 4.5 7.3 10.7 0.3 1.0 2.0 3.2 1.0 2.0 3.2 4.5 7.3 1.0 2.0 3.2 4.5 7.3 10.7 ADP1878/ADP1879 Data Sheet Table 11. Recommended Inductors L (μH) 0.12 0.22 0.47 0.72 0.9 1.2 1.0 1.4 2.0 0.8 DCR (mΩ) 0.33 0.33 0.8 1.65 1.6 1.8 3.8 3.2 2.6 ISAT (A) 55 30 50 35 32 25 16 24 23 27.5 Dimension (mm) 10.2 × 7 10.2 × 7 14.2 × 12.8 10.5 × 10.2 14 × 12.8 10.5 × 10.2 10.2 × 10.2 14 × 12.8 10.2 × 10.2 Manufacturer Würth Elektronik Würth Elektronik Würth Elektronik Würth Elektronik Würth Elektronik Würth Elektronik Würth Elektronik Würth Elektronik Würth Elektronik Sumida Model Number 744303012 744303022 744355147 744325072 744318120 744325120 7443552100 744318180 7443551200 CEP125U-0R8 Table 12. Recommended MOSFETs VGS = 4.5 V High-Side MOSFET (Q1/Q2) Low-Side MOSFET (Q3/Q4) RON (mΩ) 5.4 10.2 6.0 9 5.4 10.2 6.0 ID (A) 47 53 19 14 47 82 19 VDS (V) 30 30 30 30 30 30 30 CIN (nF) 3.2 1.6 2.4 3.2 1.6 QTOTAL (nC) 20 10 35 25 20 10 35 Rev. B | Page 32 of 40 Package PG-TDSON8 PG-TDSON8 SO-8 SO-8 PG-TDSON8 PG-TDSON8 SO-8 Manufacturer Infineon Infineon Vishay International Rectifier Infineon Infineon Vishay Model Number BSC042N03MS G BSC080N03MS G Si4842DY IRF7811 BSC042N03MS G BSC080N03MS G Si4842DY Data Sheet ADP1878/ADP1879 LAYOUT CONSIDERATIONS Figure 86 shows the schematic of a typical ADP1878/ADP1879 used for a high current application. Blue traces denote high current pathways. VIN, PGND, and VOUT traces should be wide and possibly replicated, descending down into the multiple layers. Vias should populate, mainly around the positive and negative terminals of the input and output capacitors, alongside the source of Q1/Q2, the drain of Q3/Q4, and the inductor. The performance of a dc-to-dc converter depends highly on how the voltage and current paths are configured on the printed circuit board (PCB). Optimizing the placement of sensitive analog and power components are essential to minimize output ripple, maintain tight regulation specifications, and reduce PWM jitter and electromagnetic interference. HIGH VOLTAGE INPUT VIN = 12V JP3 CC 430pF RC 57kΩ CPAR 53pF VOUT R7 10kΩ ADP1878/ ADP1879 1 VIN 2 COMP 3 EN DRVH 12 4 FB PGND 11 5 GND DRVL 10 6 RES PGOOD 9 7 VREG RTOP 2kΩ RBOT 1kΩ RRES 100kΩ C2 0.1µF BST 14 CBST 100nF Q1 SS 8 C5 22µF C6 22µF 1.0µH Q3 5kΩ Q4 RSNB 2Ω CSNB 1.5nF C8 N/A C9 N/A VOUT = 1.8V, 15A C20 270µF C24 N/A VREG CSS 34nF C7 22µF Q2 SW 13 C1 1µF C4 22µF + + C21 270µF C25 N/A + + + C22 270µF C26 N/A + C23 270µF C27 N/A + + C14 TO C19 N/A MURATA: (HIGH VOLTAGE INPUT CAPACITORS) 22µF, 25V, X7R, 1210 GRM32ER71E226KE15L PANASONIC: (OUTPUT CAPACITORS) 270µF, SP-SERIES, 4V, 7mΩ, EEFUE0G271LR INFINEON FETs: BSC042N03MS G (LOWER SIDE) BSC080N03MS G (UPPER SIDE) WÜRTH INDUCTORS: 1µH, 3.8mΩ, 16A, 7443552100 Figure 86. ADP1878 High Current Evaluation Board Schematic (Blue Traces Indicate High Current Paths) SENSITIVE ANALOG COMPONENTS LOCATED FAR FROM NOISY POWER SECTION SEPARATE ANALOG GROUND PLANE FOR COMPENSATION AND FEEDBACK RESISTORS OUTPUT CAPACITORS ARE MOUNTED AT RIGHTMOST AREA OF EVALUATION BOARD INPUT CAPACITORS ARE MOUNTED CLOSE TO DRAIN OF Q1/Q2 AND SOURCE OF Q3/Q4 09441-087 VREG C3 22µF Figure 87. Overall Layout of the ADP1878/ADP1879 High Current Evaluation Board Rev. B | Page 33 of 40 09441-086 CVIN 22µF Data Sheet 09441-088 ADP1878/ADP1879 Figure 88. Layer 2 of Evaluation Board TOP RESISTOR FEEDBACK TAP 09441-089 VOUT SENSE TAP LINE EXTENDING BACK TO THE TOP RESISTOR IN THE FEEDBACK DIVIDER NETWORK. THIS OVERLAPS WITH PGND SENSE TAP LINE EXTENDING TO THE ANALOG GROUND PLANE Figure 89. Layer 3 of Evaluation Board Rev. B | Page 34 of 40 Data Sheet ADP1878/ADP1879 BOTTOM RESISTOR TAP TO ANALOG GROUND PLANE 09441-090 PGND SENSE TAP FROM NEGATIVE TERMINALS OF THE OUTPUT BULK CAPACITORS. THIS TRACK PLACEMENT SHOULD BE DIRECTLY BELOW THE VOUT SENSE LINE OF LAYER 3. Figure 90. Layer 4 (Bottom Layer) of Evaluation Board IC SECTION (LEFT SIDE OF EVALUATION BOARD) A dedicated plane for the analog ground plane (GND) should be separate from the main power ground plane (PGND). With the shortest path possible, connect the analog ground plane to the GND pin (Pin 5). Place this plane on the top layer only of the evaluation board. To avoid crosstalk interference, do not allow any other voltage or current pathway directly below this plane on Layer 2, Layer 3, or Layer 4. Connect the negative terminals of all sensitive analog components to the analog ground plane. Examples of such sensitive analog components include the bottom resistor of the resistor divider, the high frequency bypass capacitor for biasing (0.1 µF), and the compensation network. Mount a 1 µF bypass capacitor directly across the VREG pin (Pin 7) and the PGND pin (Pin 11). In addition, tie a 0.1 µF across the VREG pin (Pin 7) and the GND pin (Pin 5). POWER SECTION As shown in Figure 87, an appropriate configuration to localize large current transfer from the high voltage input (VIN) to the output (VOUT) and then back to the power ground is to put the VIN plane on the left, the output plane on the right, and the main power ground plane in between the two. Current transfers from the input capacitors to the output capacitors, through Q1/Q2, during the on state (see Figure 91). The direction of this current (yellow arrow) is maintained as Q1/Q2 turns off and Q3/Q4 turns on. When Q3/Q4 turns on, the current direction continues to be maintained (red arrow) as it circles from the power ground terminal of the bulk capacitor to the output capacitors, through the Q3/Q4. Arranging the power planes in this manner minimizes the area in which changes in flux occur if the current through Q1/Q2 stops abruptly. Sudden changes in flux, usually at the source terminals of Q1/Q2 and the drain terminal of Q3/Q4, cause large dV/dt at the SW node. The SW node is near the top of the evaluation board. The SW node should use the least amount of area possible and be away from any sensitive analog circuitry and components. This is because the SW node is where most sudden changes in flux density occur. When possible, replicate this pad onto Layer 2 and Layer 3 for thermal relief and eliminate any other voltage and current pathways directly beneath the SW node plane. Populate the SW node plane with vias, mainly around the exposed pad of the inductor terminal and around the perimeter of the source of Q1/Q2 and the drain of Q3/Q4. The output voltage power plane (VOUT) is at the rightmost end of the evaluation board. This plane should be replicated, descending down to multiple layers with vias surrounding the inductor terminal and the positive terminals of the output bulk capacitors. Ensure that the negative terminals of the output capacitors are placed close to the main power ground (PGND), as previously mentioned. All of these points form a tight circle (component geometry permitting) that minimizes the area of flux change as the event switches between D and 1 − D. Rev. B | Page 35 of 40 ADP1878/ADP1879 Data Sheet SW Figure 91. Primary Current Pathways During the On State of the High-Side MOSFET (Left Arrow) and the On State of the Low-Side MOSFET (Right Arrow) DIFFERENTIAL SENSING Because the ADP1878/ADP1879 operate in valley current-mode control, a differential voltage reading is taken across the drain and source of the low-side MOSFET. Connect the drain of the low-side MOSFET s as close as possible to the SW pin (Pin 13) of the IC. Likewise, connect the source as close as possible to the PGND pin (Pin 11) of the IC. When possible, keep both of these track lines narrow and away from any other active device or voltage/current path. LAYER 1: SENSE LINE FOR SW (DRAIN OF LOWER MOSFET) LAYER 1: SENSE LINE FOR PGND (SOURCE OF LOWER MOSFET) 09441-092 09441-091 PGND Figure 92. Drain/Source Tracking Tapping of the Low-Side MOSFET for CS Amp Differential Sensing (Yellow Sense Line on Layer 2) In addition, employ differential sensing between the outermost output capacitor and the feedback resistor divider (see Figure 89 and Figure 90). Connect the positive terminal of the output capacitor to the top resistor (RT). Connect the negative terminal of the output capacitor to the negative terminal of the bottom resistor, which connects to the analog ground plane as well. Keep both of these track lines, as previously mentioned, narrow and away from any other active device or voltage/ current path. Rev. B | Page 36 of 40 Data Sheet ADP1878/ADP1879 TYPICAL APPLICATION CIRCUITS 12 A, 300 kHz HIGH CURRENT APPLICATION CIRCUIT HIGH VOLTAGE INPUT VIN = 12V JP3 CVIN 22µF CPAR 56pF R7 10kΩ VREG ADP1878/ ADP1879 1 RBOT 1kΩ RRES 100kΩ C2 0.1µF BST 14 2 COMP 3 EN DRVH 12 4 FB PGND 11 5 GND DRVL 10 RTOP 2kΩ VOUT VIN 6 RES 7 VREG CBST 100nF Q1 C4 22µF C6 22µF 1.2µH Q3 SS 8 Q4 C9 N/A C20 270µF + + C21 270µF C25 N/A + + C22 270µF C26 N/A + + C23 270µF C27 N/A + + C14 TO C19 N/A VREG MURATA: (HIGH VOLTAGE INPUT CAPACITORS) 22µF, 25V, X7R, 1210 GRM32ER71E226KE15L PANASONIC: (OUTPUT CAPACITORS) 270µF (SP-SERIES), 4V, 7mΩ, EEFUE0G271LR INFINEON MOSFETs: BSC042N03MS G (LOWER SIDE) BSC080N03MS G (UPPER SIDE) WÜRTH INDUCTORS: 1.2µH, 2mΩ, 20A, 744325120 CSS 34nF C1 1µF C8 N/A VOUT = 1.8V, 12A RSNB 2Ω CSNB 1.5nF C24 N/A 5kΩ C7 22µF Q2 SW 13 PGOOD 9 C5 22µF 09441-093 CC 560pF RC 49.3kΩ C3 22µF Figure 93. Application Circuit for 12 V Input, 1.8 V Output, 12 A, 300 kHz (Q2/Q4 No Connect) 5.5 V INPUT, 600 kHz CURRENT APPLICATION CIRCUIT HIGH VOLTAGE INPUT VIN = 5.5V JP3 CVIN 22µF CF 22pF VREG VOUT R7 10kΩ ADP1878/ ADP1879 1 VIN 2 COMP 3 EN DRVH 12 4 FB PGND 11 5 GND DRVL 10 RTOP 32kΩ RBOT 1kΩ RRES 100kΩ C2 0.1µF C1 1µF 6 RES 7 VREG BST 14 CBST 100nF Q1 SS 8 C5 22µF C6 22µF 0.47µH Q3 5kΩ C7 22µF C8 N/A C9 N/A Q2 SW 13 PGOOD 9 C4 22µF Q4 RSNB 2Ω CSNB 1.5nF VOUT = 2.5V, 12A C20 180µF C24 N/A + + C21 180µF C25 N/A + + C22 180µF C26 N/A + + C27 N/A C23 N/A + + C14 TO C19 N/A VREG CSS 34nF MURATA: (INPUT CAPACITORS) 22µF, 25V, X7R, 1210 GRM32ER71E226KE15L PANASONIC: (OUTPUT CAPACITORS) 180µF (SP-SERIES), 4V, 10mΩ, EEFUE0G181XR INFINEON MOSFETs: BSC042N03MS G (LOWER SIDE) BSC080N03MS G (UPPER SIDE) WÜRTH INDUCTORS: 0.47µH, 0.8mΩ, 30A, 744355147 Figure 94. Application Circuit for 5.5 V Input, 2.5 V Output, 12 A, 600 kHz (Q2/Q4 No Connect) Rev. B | Page 37 of 40 09441-094 CC 220pF RC 56.9kΩ C3 22µF ADP1878/ADP1879 Data Sheet 300 kHz HIGH CURRENT APPLICATION CIRCUIT HIGH VOLTAGE INPUT VIN = 13V JP3 CVIN 22µF CPAR 56pF VREG VOUT R7 10kΩ ADP1878/ ADP1879 1 2 COMP 3 EN RTOP 2kΩ RBOT 1kΩ RRES 100kΩ C2 0.1µF C1 1µF VIN BST 14 FB PGND 11 GND DRVL 10 7 VREG PGOOD 9 SS 8 C5 22µF C6 22µF 1.2µH Q3 5kΩ C7 22µF C8 N/A C9 N/A Q2 SW 13 5 RES Q1 DRVH 12 4 6 CBST 100nF C4 22µF Q4 RSNB 2Ω CSNB 1.5nF VOUT = 1.8V, 12A C20 270µF C24 N/A + + C21 270µF C25 N/A + + C22 270µF C26 N/A + + C23 270µF C27 N/A + + C14 TO C19 N/A VREG CSS 34nF MURATA: (HIGH VOLTAGE INPUT CAPACITORS) 22µF, 25V, X7R, 1210 GRM32ER71E226KE15L PANASONIC: (OUTPUT CAPACITORS) 270µF (SP-SERIES), 4V, 7mΩ, EEFUE0G271LR INFINEON MOSFETs: BSC042N03MS G (LOWER SIDE) BSC080N03MS G (UPPER SIDE) WÜRTH INDUCTORS: 1.2µH, 2mΩ, 20A, 744325120 Figure 95. Application Circuit for 13 V Input, 1.8 V Output, 12 A, 300 kHz (Q2/Q4 No Connect) Rev. B | Page 38 of 40 09441-095 CC 560pF RC 49.3kΩ C3 22µF Data Sheet ADP1878/ADP1879 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS 4.10 4.00 3.90 3.40 3.30 3.15 0.10 REF 0.20 MIN 8 0.30 REF TOP VIEW 0.80 0.75 0.70 SEATING PLANE END VIEW 7 0.50 0.40 0.30 SIDE VIEW 0.30 0.25 0.20 0.50 BSC 1.80 1.70 1.55 EXPOSED PAD 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.15 REF 1 BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-229-WEGD Figure 96. 14-Lead Lead Frame Chip Scale Package [LFCSP_WD] 4 mm × 3 mm Body, Very Very Thin Dual (CP-14-2) Dimensions shown in millimeters Rev. B | Page 39 of 40 101309-A 0.90 REF 3.10 3.00 2.90 PIN 1 INDICATOR (LASER MARKING) 14 ADP1878/ADP1879 Data Sheet ORDERING GUIDE Model 1 ADP1878ACPZ-0.3-R7 ADP1878ACPZ-0.6-R7 ADP1878ACPZ-1.0-R7 ADP1878-0.3-EVALZ ADP1878-0.6-EVALZ ADP1878-1.0-EVALZ ADP1879ACPZ-0.3-R7 ADP1879ACPZ-0.6-R7 ADP1879ACPZ-1.0-R7 ADP1879-0.3-EVALZ ADP1879-0.6-EVALZ ADP1879-1.0-EVALZ 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 14-Lead Frame Chip Scale Package [LFCSP_WD] 14-Lead Frame Chip Scale Package [LFCSP_WD] 14-Lead Frame Chip Scale Package [LFCSP_WD] Evaluation Board Evaluation Board Evaluation Board 14-Lead Frame Chip Scale Package [LFCSP_WD] 14-Lead Frame Chip Scale Package [LFCSP_WD] 14-Lead Frame Chip Scale Package [LFCSP_WD] Evaluation Board Evaluation Board Evaluation Board Package Option CP-14-2 CP-14-2 CP-14-2 CP-14-2 CP-14-2 CP-14-2 Z = RoHS Compliant Part. ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09441-0-9/12(B) www.analog.com/ADP1878/ADP1879 Rev. B | Page 40 of 40