Synchronous Current-Mode with Constant On-Time, PWM Buck Controller
ADP1882/ADP1883
FEATURES
Power input voltage as low as 2.75 V to 20 V Bias supply voltage range: 2.75 V to 5.5 V Minimum output voltage: 0.8 V 0.8 V reference voltage with ±1.0% accuracy Supports all N-channel MOSFET power stages Available in 300 kHz, 600 kHz, and 1.0 MHz options No current-sense resistor required Power saving mode (PSM) for light loads (ADP1883 only) Resistor-programmable current-sense gain Thermal overload protection Short-circuit protection Precision enable input Integrated bootstrap diode for high-side drive 140 μA shutdown supply current Starts into a precharged load Small, 10-lead MSOP package
TYPICAL APPLICATIONS CIRCUIT
VIN = 2.75V TO 20V
CC RTOP RC CC2
VIN
ADP1882/ ADP1883
COMP/EN BST CBST FB DRVH SW
CIN
VOUT
Q1
L
VOUT
RBOT GND CVDD2 VDD COUT Q2 RRES LOAD
DRVL PGND
Figure 1.
100 95 90 85 80
EFFICIENCY (%)
APPLICATIONS
Telecom and networking systems Mid to high end servers Set-top boxes DSP core power supplies
VDD = 5.5V, VIN = 13.0V VDD = 5.5V, VIN = 16.5V VDD = 5.5V, VDD = 5.5V, VDD = 3.6V, VIN = 5.5V (PSM) VIN = 5.5V VIN = 5.5V
75 70 65 60 55 50 45 40 35 30 25 100 1k TA = 25°C VOUT = 1.8V fSW = 300kHz WURTH INDUCTOR: 744325120, L = 1.2µH, DCR = 1.8mΩ INFINEON MOSFETs: BSC042N03MS G (UPPER/LOWER) 10k 100k
08901-002
LOAD CURRENT (mA)
Figure 2. ADP1882/ADP1883 Efficiency vs. Load Current (VOUT = 1.8 V, 300 kHz)
GENERAL DESCRIPTION
The ADP1882/ADP1883 are versatile current-mode, synchronous step-down controllers that provide superior transient response, optimal stability, and current-limit protection by using a constant on-time, pseudo-fixed frequency with a programmable currentlimit, current-control scheme. In addition, these devices offer optimum performance at low duty cycles by using valley currentmode control architecture. This allows the ADP1882/ADP1883 to drive all N-channel power stages to regulate output voltages as low as 0.8 V. The ADP1883 is the power saving mode (PSM) version of the device and is capable of pulse skipping to maintain output regulation while achieving improved system efficiency at light loads (see the Power Saving Mode (PSM) Version (ADP1883) section for more information).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
Available in three frequency options (300 kHz, 600 kHz, and 1.0 MHz, plus the PSM option), the ADP1882/ADP1883 are well suited for a wide range of applications. These ICs not only operate from a 2.75 V to 5.5 V bias supply, but they also can accept a power input as high as 20 V. In addition, an internally fixed soft start period is included to limit input in-rush current from the input supply during startup and to provide reverse current protection during soft start for a precharged output. The low-side current-sense, current-gain scheme and integration of a boost diode, along with the PSM/forced pulse-width modulation (PWM) option, reduce the external part count and improve efficiency. The ADP1882/ADP1883 operate over the −40°C to +125°C junction temperature range and are available in a 10-lead MSOP.
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08901-001
VDD = 2.75V TO 5.5V CVDD
ADP1882/ADP1883 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Typical Applications Circuit............................................................ 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 Boundary Condition .................................................................... 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 7 ADP1882/ADP1883 Block Diagram............................................ 18 Theory of Operation ...................................................................... 19 Startup .......................................................................................... 19 Soft Start ...................................................................................... 19 Precision Enable Circuitry ........................................................ 19 Undervoltage Lockout ............................................................... 19 Thermal Shutdown..................................................................... 19 Programming Resistor (RES) Detect Circuit .......................... 20 Valley Current-Limit Setting .................................................... 20 Hiccup Mode During Short Circuit ......................................... 21 Synchronous Rectifier ................................................................ 22 Power Saving Mode (PSM) Version (ADP1883) .................... 22 Timer Operation ........................................................................ 22 Pseudo-Fixed Frequency ........................................................... 23 Applications Information .............................................................. 24 Feedback Resistor Divider ........................................................ 24 Inductor Selection ...................................................................... 24 Output Ripple Voltage (ΔVRR) .................................................. 24 Output Capacitor Selection....................................................... 24 Compensation Network ............................................................ 25 Efficiency Considerations ......................................................... 26 Input Capacitor Selection .......................................................... 27 Thermal Considerations............................................................ 28 Design Example .......................................................................... 28 External Component Recommendations .................................... 31 Layout Considerations ................................................................... 33 IC Section (Left Side of Evaluation Board) ............................. 36 Power Section ............................................................................. 36 Differential Sensing .................................................................... 36 Typical Applications Circuits ........................................................ 37 Dual-Input, 300 kHz High Current Applications Circuit..... 37 Single-Input, 600 kHz Applications Circuit ........................... 37 Dual-Input, 300 kHz High Current Applications Circuit..... 38 Outline Dimensions ....................................................................... 39 Ordering Guide .......................................................................... 39
REVISION HISTORY
4/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 40
ADP1882/ADP1883 SPECIFICATIONS
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VDD = 5 V, BST − SW = 5 V, VIN = 13 V. The specifications are valid for TJ = −40°C to +125°C, unless otherwise specified. Table 1.
Parameter POWER SUPPLY CHARACTERISTICS High Input Voltage Range Symbol VIN Conditions ADP1882ARMZ-0.3/ADP1883ARMZ-0.3 (300 kHz) ADP1882ARMZ-0.6/ADP1883ARMZ-0.6 (600 kHz) ADP1882ARMZ-1.0/ADP1883ARMZ-1.0 (1.0 MHz) CIN = 1 μF to PGND, CIN = 0.22 μF to GND ADP1882ARMZ-0.3/ADP1883ARMZ-0.3 (300 kHz) ADP1882ARMZ-0.6/ADP1883ARMZ-0.6 (600 kHz) ADP1882ARMZ-1.0/ADP1883ARMZ-1.0 (1.0 MHz) FB = 1.5 V, no switching COMP/EN < 285 mV Rising VDD (see Figure 35 for temperature variation) Falling VDD from operational state See Figure 58 VFB TJ = 25°C TJ = −40°C to +85°C TJ = −40°C to +125°C FB = 0.8 V, COMP/EN = released RES = 47 kΩ ± 1% RES = 22 kΩ ± 1% RES = none RES = 100 kΩ ± 1% Typical values measured at 50% time points with 0 nF at DRVH and DRVL; maximum values are guaranteed by bench evaluation 1 2.98 6 24.1 12.1 Min 2.75 2.75 3.0 2.75 2.75 3.0 Typ 12 12 12 5 5 5 1.1 140 2.65 190 3.0 800 800 800 520 1 3.4 6.6 26.7 13.4 Max 20 20 20 5.5 5.5 5.5 215 Unit V V V V V V mA μA V mV ms mV mV mV μs nA V/V V/V V/V V/V
Low Input Voltage Range
VDD
Quiescent Current Shutdown Current Undervoltage Lockout UVLO Hysteresis SOFT START Soft Start Period ERROR AMPLIFIER FB Regulation Voltage
IQ_DD + IQ_BST IDD, SD + IBST, SD UVLO
Transconductance FB Input Leakage Current CURRENT-SENSE AMPLIFIER GAIN Programming Resistor (RES) Value from DRVL to PGND
GM IFB, LEAK
795.3 792.8 300
805.5 808.0 730 50 3.7 7.4 29.3 14.7
SWITCHING FREQUENCY
ADP1882ARMZ-0.3/ ADP1883ARMZ-0.3 (300 kHz) On Time Minimum On Time Minimum Off Time ADP1882ARMZ-0.6/ ADP1883ARMZ-0.6 (600 kHz) On Time Minimum On Time Minimum Off Time ADP1882ARMZ-1.0/ ADP1883ARMZ-1.0 (1.0 MHz) On Time Minimum On Time Minimum Off Time
300 VIN = 5 V, VOUT = 2 V, TJ = 25°C VIN = 20 V 84% duty cycle (maximum) 1115 1200 145 340 600 540 82 340 1.0 312 60 340 1285 190 400
kHz ns ns ns kHz ns ns ns MHz ns ns ns
VIN = 5 V, VOUT = 2 V, TJ = 25°C VIN = 20 V, VOUT = 0.8 V 65% duty cycle (maximum)
490
585 110 400
VIN = 5 V, VOUT = 2 V, TJ = 25°C VIN = 20 V 45% duty cycle (maximum)
280
340 85 400
Rev. 0 | Page 3 of 40
ADP1882/ADP1883
Parameter OUTPUT DRIVER CHARACTERISTICS High-Side Driver Output Source Resistance Output Sink Resistance Rise Time 2 Fall Time2 Low-Side Driver Output Source Resistance Output Sink Resistance Rise Time2 Fall Time2 Propagation Delays DRVL Fall to DRVH Rise2 DRVH Fall to DRVL Rise2 SW Leakage Current Integrated Rectifier Channel Impedance PRECISION ENABLE THRESHOLD Logic High Level Enable Hysteresis COMP VOLTAGE COMP Clamp Low Voltage COMP Clamp High Voltage COMP Zero Current Threshold THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis Hiccup Current Limit Timing
1
Symbol
Conditions
Min
Typ
Max
Unit
tR, DRVH tF, DRVH
ISOURCE = 1.5 A, 100 ns, positive pulse (0 V to 5 V) ISINK = 1.5 A, 100 ns, negative pulse (5 V to 0 V) BST − SW = 4.4 V, CIN = 4.3 nF (see Figure 60) BST − SW = 4.4 V, CIN = 4.3 nF (see Figure 61) ISOURCE = 1.5 A, 100 ns, positive pulse (0 V to 5 V) ISINK = 1.5 A, 100 ns, negative pulse (5 V to 0 V) VDD = 5.0 V, CIN = 4.3 nF (see Figure 61) VDD = 5.0 V, CIN = 4.3 nF (see Figure 60) BST − SW = 4.4 V (see Figure 60) BST − SW = 4.4 V (see Figure 61) BST = 25 V, SW = 20 V, VDD = 5.5 V ISINK = 10 mA VIN = 2.75 V to 20 V, VDD = 2.75 V to 5.5 V VIN = 2.75 V to 20 V, VDD = 2.75 V to 5.5 V 235
2 0.8 25 11 1.7 0.75 18 16 22 24
3.5 2
Ω Ω ns ns Ω Ω ns ns ns ns μA Ω
3 2
tR, DRVL tF, DRVL tTPDH, DRVH tTPDH, DRVL ISW, LEAK
110 22 285 35 330
mV mV V
VCOMP(LOW) VCOMP(HIGH) VCOMP_ZCT TTMSD
From disable state, release COMP/EN pin to enable device; 2.75 V ≤ VDD ≤ 5.5 V 2.75 V ≤ VDD ≤ 5.5 V 2.75 V ≤ VDD ≤ 5.5 V Rising temperature
0.47 2.55 0.95 155 15 6
V V °C °C ms
2
The maximum specified values are with the closed loop measured at 10% to 90% time points (see Figure 60 and Figure 61), CGATE = 4.3 nF, and the upper-side and lower-side MOSFETs specified as Infineon BSC042N030MSG. Not automatic test equipment (ATE) tested.
Rev. 0 | Page 4 of 40
ADP1882/ADP1883 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter VDD to GND VIN to PGND FB, COMP/EN to GND DRVL to PGND SW to PGND BST to SW BST to PGND DRVH to SW PGND to GND θJA (10-Lead MSOP) 2-Layer Board 4-Layer Board Operating Junction Temperature Range Storage Temperature Range Soldering Conditions Maximum Soldering Lead Temperature (10 sec) Rating −0.3 V to +6 V −0.3 V to +28 V −0.3 V to (VDD + 0.3 V) −0.3 V to (VDD + 0.3 V) −2.0 V to +28 V −0.8 V to (VDD + 0.3 V) −0.3 V to 28 V −0.3 V to VDD ±0.3 V 213.1°C/W 171.7°C/W −40°C to +125°C −65°C to +150°C JEDEC J-STD-020 300°C
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance
Package Type θJA (10-Lead MSOP) 2-Layer Board 4-Layer Board
1
θJA1 213.1 171.7
Unit °C/W °C/W
θJA is specified for the worst-case conditions; that is, θJA is specified for device soldered in a circuit board for surface-mount packages.
BOUNDARY CONDITION
In determining the values given in Table 2 and Table 3, natural convection was used to transfer heat to a 4-layer evaluation board.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to PGND.
Rev. 0 | Page 5 of 40
ADP1882/ADP1883 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VIN 1 COMP/EN 2 FB 3 GND 4 VDD 5
10
BST SW DRVH
08901-003
ADP1882/ ADP1883
TOP VIEW (Not to Scale)
9 8 7 6
PGND DRVL
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic VIN COMP/EN FB GND VDD DRVL PGND DRVH SW BST Description High Input Voltage. Connect VIN to the drain of the upper-side MOSFET. Output of the Internal Error Amplifier/IC Enable. When this pin functions as EN, applying 0 V to this pin disables the IC. Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected. Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground plane (see the Layout Considerations section). Bias Voltage Supply for the ADP1882/ADP1883 Controller, Including the Output Gate Drivers. A bypass capacitor of 1 μF directly from this pin to PGND and a 0.1 μF across VDD and GND are recommended. Drive Output for the External Lower-Side N-Channel MOSFET. This pin also serves as the current-sense gain setting pin (see Figure 69). Power GND. Ground for the lower-side gate driver and lower-side N-channel MOSFET. Drive Output for the External Upper-Side, N-Channel MOSFET. Switch Node Connection. Bootstrap for the Upper-Side MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected between VDD and BST. A capacitor from BST to SW is required. An external Schottky diode can also be connected between VDD and BST for increased gate drive capability.
Rev. 0 | Page 6 of 40
ADP1882/ADP1883 TYPICAL PERFORMANCE CHARACTERISTICS
100 95 90 85 80
VDD = 5.5V, VIN = 5.5V (PSM) VDD = 5.5V, VIN = 13V (PSM) VDD = 5.5V, VIN = 5.5V
75 70 65 60 55 50 45 40 35 30 100
VDD = 5.5V, VIN = 13V (PSM) VDD = 5.5V, VIN = 16.5V (PSM) VDD = 3.6V, VIN = 16.5V (PSM) VDD = 3.6V, VIN = 5.5V (PSM)
VDD = 3.6V, VIN = 13V (PSM)
WURTH IND: 744355147, L = 0.47 µH, DCR: 0.80MΩ INFENION FETs: BSC042N03MS G (UPPER/LOWER) TA = 25°C
1k
10k
100k
08901-004
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 4. Efficiency—300 kHz, VOUT = 0.8 V
100 95 90 85 80
VDD = 5.5V, VIN = 13V VDD = 5.5V, VIN = 16.5V VDD = 5.5V, VIN = 13V (PSM) VDD = 5.5V, VIN = 5.5V
Figure 7. Efficiency—600 kHz, VOUT = 0.8 V
100 95 90 85 80
EFFICIENCY (%)
VDD = 5.5V, VIN = 5.5V (PSM)
VDD = 5.5V, VIN = 5.5V
EFFICIENCY (%)
75 70 65 60 55 50 45 40 35 30 25 100
VDD = 5.5V, VIN = 16.5V (PSM)
75 70 65 60 55 50 45 40
VDD = 3.6V, VIN = 5.5V VDD = 5.5V, VIN = 5.5V (PSM) VDD = 5.5V, VIN = 16.5V (PSM) VDD = 5.5V, VIN = 13V (PSM) VDD = 5.5V, VIN = 16.5V VDD = 5.5V, VIN = 13V WURTH INDUCTOR: 744325072, L = 0.72µH, DCR: 1.65mΩ INFINEON FETS: BSC042N03MS G (UPPER/LOWER) RON: 5.4mΩ TA = 25°C
VDD = 3.6V, VIN = 5.5V
WURTH INDUCTOR: 7443252100, L = 1.0µH, DCR: 3.3mΩ INFINEON MOSFETS: BSC042N03MS G (UPPER/LOWER) RON: 5.4mΩ TA = 25°C
08901-005
35 30 25 100
1k
10k
100k
1k
10k
100k
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 5. Efficiency—300 kHz, VOUT = 1.8 V
100 95 90 85 80 EFFICIENCY (%) 75 70 65 60 55 50 45 40 35 30 100
1k
VDD = 2.7V, VIN = 13V VDD = 5.5V, VIN = 13V VDD = 3.6V, VIN = 13V VDD = 5.5V, VIN = 16.5V VDD = 3.6V, VIN = 16.5V TA = 25°C VOUT = 1.8V FSW = 300kHz WURTH INDUCTOR: 744355200, L = 2µH, DCR: 2.5mΩ INFINEON MOSFETS: BSC042N03MS G (UPPER/LOWER) VDD = 2.7V, VIN = 16.5V (PSM) VDD = 5.5V, VIN = 16.5V (PSM)
Figure 8. Efficiency—600 kHz, VOUT = 1.8 V
100 95 90 85
VDD = 3.6V/VIN = 13V VDD = 5.5V/VIN = 13V (PSM)
EFFICIENCY (%)
80 75 70 65 60 55
VDD = 5.5V/VIN = 16.5V
VDD = 5.5V/VIN = 13V TA = 25°C VOUT = 5V, VIN = 13V FSW = 600kHz WURTH INDUCTOR: 7443552100, L = 1.0µH, DCR: 3.3mΩ INFINEON MOSFETS: BSC042N03MS G (UPPER/LOWER)
10k
100k
08901-006
1k
10k
100k
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 6. Efficiency—300 kHz, VOUT = 7 V
Figure 9. Efficiency—600 kHz, VOUT = 5 V
Rev. 0 | Page 7 of 40
08901-009
50 100
08901-008
08901-007
100 VDD = 5.5V, VIN = 5.5V (PSM) 95 V = 5.5V, DD VDD = 5.5V, VIN = 5.5V 90 VIN = 13V (PSM) 85 80 75 70 VDD = 5.5V, VIN = 16.5V (PSM) 65 60 VDD = 5.5V, VIN = 13V 55 VDD = 5.5V, VIN = 16.5V 50 45 40 VDD = 3.6V, VIN = 5.5V 35 30 WURTH INDUCTOR: 744355072, L = 0.72µH, DCR: 1.65mΩ INFINEON FETS: BSC042N03MS G (UPPER/LOWER) 25 RON: 5.4mΩ 20 TA = 25°C 15 100 1k 10k 100k
EFFICIENCY (%)
EFFICIENCY (%)
ADP1882/ADP1883
100 VDD = 5.5V/VIN = 5.5V (PSM) VDD = 3.6V/VIN = 3.6V 95 VDD = 5.5V/VIN = 5.5V 90 85 80 75 70 VDD = 3.6V/VIN = 13V 65 60 VDD = 5.5V/VIN = 16.5V 55 VDD = 5.5V/VIN = 13V 50 TA = 25°C 45 VOUT = 0.8V, VIN = 5.5V 40 FSW = 1MHz 35 WURTH INDUCTOR: 30 744303022, L = 0.22µH, DCR: 0.33mΩ INFINEON MOSFETS: 25 BSC042N03MS G (UPPER/LOWER) 20 100 1k 10k 100k LOAD CURRENT (mA) 0.820 0.818 0.816 0.814 0.812 0.810 0.808 0.806 0.804 0.802 0.800 0.798 0.796 0.794 0.792
08901-010
OUTPUT VOLTAGE (V)
EFFICIENCY (%)
VIN = 5.5V +125°C +25°C –40°C 0 2k 4k 6k
VIN = 13V +125°C +25°C –40°C 8k 10k
VIN = 16.5V +125°C +25°C –40°C 12k 14k 16k
08901-013
08901-015 08901-014
0.790 LOAD CURRENT (mA)
Figure 10. Efficiency—1.0 MHz, VOUT = 0.8 V
100 95 90 85 80 75
VDD = 5.5V/VIN = 5.5V (PSM) VDD = 5.5V/VIN = 5.5V VDD = 5.5V/VIN = 13V
Figure 13. Output Voltage Accuracy—300 kHz, VOUT = 0.8 V
1.809
EFFICIENCY (%)
VDD = 3.6V/VIN = 16.5V VDD = 5.5V/VIN = 16.5V VDD = 3.6V/VIN = 13V
70 65 60 55 50 45 40 35 30 25 20 100 1k
OUTPUT VOLTAGE (V)
1.804
1.799
1.794
TA = 25°C VOUT = 1.8V, VIN = 5.5V FSW = 1MHz WURTH INDUCTOR: 744303022, L = 0.22µH, DCR: 0.33mΩ INFINEON MOSFETS: BSC042N03MS G (UPPER/LOWER)
08901-011
1.789
VIN = 5.5V +125°C +25°C –40°C
0 1.5k 3.0k 4.5k 6.0k
VIN = 13V +125°C +25°C –40°C
7.5k
VIN = 16.5V +125°C +25°C –40°C
1.784
9.0k 10.5k 12.0k 13.5k 15.0k
10k
100k
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 11. Efficiency—1.0 MHz, VOUT = 1.8 V
100 95 90 85 80
VDD = 5.5V/VIN = 16.5V (PSM)
Figure 14. Output Voltage Accuracy—300 kHz, VOUT = 1.8 V
6.970 6.965 6.960 6.955
OUTPUT VOLTAGE (V)
VDD = 3.6V, VIN = 16.5V +125°C +25°C –40°C
VDD = 5.5V, VIN = 13V +125°C +25°C –40°C
6.950 6.945 6.940 6.935 6.930 6.925 6.920 6.915 6.910 VDD = 5.5V, VIN = 16.5V +125°C +25°C –40°C 0 1k 2k 3k VDD = 3.6V, VIN = 13V +125°C +25°C –40°C 4k 5k 6k 7k 8k 9k 10k
EFFICIENCY (%)
75 70 65 60 55 50 45 40 35 30 100
TA = 25°C VOUT = 4V, VIN = 16.5V FSW = 1MHz WURTH INDUCTOR: 744318180, L = 1.4µH, DCR: 3.2mΩ INFINEON MOSFETS: BSC042N03MS G (UPPER/LOWER) VDD = 5.5V/VIN = 13V VDD = 5.5V/VIN = 16.5V
1k LOAD CURRENT (mA)
10k
08901-012
6.905
LOAD CURRENT (mA)
Figure 12. Efficiency—1.0 MHz, VOUT = 4 V
Figure 15. Output Voltage Accuracy—300 kHz, VOUT = 7 V
Rev. 0 | Page 8 of 40
ADP1882/ADP1883
0.829 0.827 0.825 0.823 0.821 0.819 0.817 0.815 0.813 0.811 0.809 0.807 0.805 0.803 0.801 0.799 0.797 0.795
0 VIN = 16.5V +125°C +25°C –40°C VIN = 16.5V +125°C +25°C –40°C VIN = 13V +125°C +25°C –40°C
OUTPUT VOLTAGE (V)
0.820 0.818 0.816 0.814 0.812 0.810 0.808 0.806 0.804 0.802 0.800 0.798 0.796 0.794 0.792
08901-115
OUTPUT VOLTAGE (V)
VIN = 5.5V +125°C +25°C –40°C 0 2k 4k
VIN = 13V +125°C +25°C –40°C 6k 8k
VIN = 16.5V +125°C +25°C –40°C 10k 12k
08901-018 08901-020
2k
4k0
6k
8k
10k
12k
14k
0.790 LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 16. Output Voltage Accuracy—600 kHz, VOUT = 0.8 V
1.806 1.804 1.802
Figure 19. Output Voltage Accuracy—1.0 MHz, VOUT = 0.8 V
1.808 1.806 1.804 1.802
OUTPUT VOLTAGE (V)
1.800 1.798 1.796 1.794 1.792 1.790 1.788 1.786 0 1.5k 3.0k 4.5k 6.0k 7.5k 9.0k 10.5k 12.0k 13.5k 15.0k
08901-016
OUTPUT VOLTAGE (V)
1.800 1.798 1.796 1.794 1.792 1.790 1.788 1.786 1.784 1.782 1.780 0 1.5k 3.0k 4.5k 6.0k 7.5k 9.0k 10.5k 12.0k 13.5k 15.0k LOAD CURRENT (mA) VIN = 5.5V +125°C +25°C –40°C VIN = 13V +125°C +25°C –40°C VIN = 16.5V +125°C +25°C –40°C
08901-019
VIN = 5.5V +125°C +25°C –40°C
VIN = 13V +125°C +25°C –40°C
VIN = 16V +125°C +25°C –40°C
LOAD CURRENT (mA)
Figure 17. Output Voltage Accuracy—600 kHz, VOUT = 1.8 V
5.015 5.010
Figure 20. Output Voltage Accuracy—1.0 MHz, VOUT = 1.8 V
4.060 4.055 4.050
5.005
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
4.045 4.040 4.035 4.030 4.025 4.020 4.015
5.000 4.995 4.990 4.985 4.980 4.975 4.970 0 1k 2k 3k 4k 5k 6k 7k 8k 9k 10k LOAD CURRENT (mA)
VDD = 5.5V, VIN = 13V +125°C +25°C –40°C
VDD = 5.5V, VIN = 16.5V +125°C +25°C –40°C
08901-017
4.010 4.005 4.000 0 8.0k 1.6k 2.4k 3.2k
VIN = 13V +125°C +25°C –40°C 4.0k 4.8k 5.6k
VIN = 16.5V +125°C +25°C –40°C 6.4k 7.2k 8.0k
LOAD CURRENT (mA)
Figure 18. Output Voltage Accuracy—600 kHz, VOUT = 5 V
Figure 21. Output Voltage Accuracy—1.0 MHz, VOUT = 4 V
Rev. 0 | Page 9 of 40
ADP1882/ADP1883
0.804 0.803
FEEDBACK VOLTAGE (V)
1000 950 900 FREQUENCY (kHz) 850 800 750 700 650 VIN = 3.6V +125°C +25°C –40°C VIN = 5.5V +125°C +25°C –40°C
08901-024
08901-026 08901-025
0.802 0.801 0.800 0.799 0.798 0.797 0.796 –40.0 VDD = 2.7V, VDD = 3.6V, VDD = 5.5V, –7.5 VIN = 2.7/3.6V VIN = 3.6V TO 16.5V VIN = 5.5/13V/16.5V 25.0 57.5 90.0 122.5
08901-021
600
550 10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2 VIN (V)
TEMPERATURE (°C)
Figure 22. Feedback Voltage vs. Temperature
Figure 25. Switching Frequency vs. High Input Voltage, 1.0 MHz, ±10% of 12 V
355 340 325 310
FREQUENCY (kHz)
335 325 315
FREQUENCY (kHz)
305 295 285 275 265 255 245 235 VDD = 3.6V +125°C +25°C –40°C VDD = 5.5V +125°C +25°C –40°C
08901-022
295 280 265 250 235 220 205 190 0 2k 4k 6k 8k 10k 12k 14k 16k LOAD CURRENT (mA) VIN = 5.5V +125°C +25°C –40°C VIN = 13V +125°C +25°C –40°C VIN = 16.5V +125°C +25°C –40°C
225 10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2 VIN (V)
Figure 23. Switching Frequency vs. High Input Voltage, 300 kHz, ±10% of 12 V
650
Figure 26. Frequency vs. Load Current, 300 kHz, VOUT = 0.8 V
380 370 VIN = 5.5V +125°C +25°C –40°C
600 FREQUENCY (kHz)
FREQUENCY (kHz)
360 350 340 330 320 310 300 290
550
500
VIN = 13V +125°C +25°C –40°C VIN = 16.5V +125°C +25°C –40°C 0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k
450
VOUT = 1.8V +125°C +25°C –40°C
VDD = 5.5V +125°C +25°C –40°C
08901-023
280 270 260
400 10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2 VIN (V)
LOAD CURRENT (mA)
Figure 24. Switching Frequency vs. High Input Voltage, 600 kHz, VOUT = 1.8 V, ±10% of 12 V
Figure 27. Frequency vs. Load Current, 300 kHz, VOUT = 1.8 V
Rev. 0 | Page 10 of 40
ADP1882/ADP1883
358 354 350 346 342 338 334 330 326 322 318 314 310 306 302 298 294 290 0
750 742 734 726 718 FREQUENCY (kHz)
VIN = 13V +125°C +25°C –40°C VIN = 16.5V +125°C +25°C –40°C
08901-027
FREQUENCY (kHz)
710 702 694 686 678 670 662 654 646 638 630 0 0.8k 1.6k 2.4k 3.2k 4.0k 4.8k 5.6k 6.4k 7.2k 8.0k 8.8k 9.6k LOAD CURRENT (mA) VIN = 13V +125°C +25°C –40°C VIN = 16.5V +125°C +25°C –40°C
08901-030
0.8k 1.6k 2.4k 3.2k 4.0k 4.8k 5.6k 6.4k 7.2k 8.0k 8.8k 9.6k LOAD CURRENT (mA)
Figure 28. Frequency vs. Load Current, 300 kHz, VOUT = 7 V
700 670 640 610 580 550 520 490 460 430 400 370 340 310 280 250 220 190 0 2k
Figure 31. Frequency vs. Load Current, 600 kHz, VOUT =5 V
1300 1225 1150 1075
VIN = 5.5V +125°C +25°C –40°C
VIN = 13V +125°C +25°C –40°C
VIN = 16.5V +125°C +25°C –40°C
FREQUENCY (kHz)
VIN = 5.5V +125°C +25°C –40°C 4k 6k VIN = 13V +125°C +25°C –40°C 8k 10k VIN = 16.5V +125°C +25°C –40°C 12k 14k
08901-028
FREQUENCY (kHz)
1000 925 850 775 700 625 550 475 0 2k 4k 6k 8k 10k 12k
08901-031 08901-032
400 LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 29. Frequency vs. Load Current, 600 kHz, VOUT = 0.8 V
835 815 795 775 755 735 715 695 675 655 635 615 595 575 555 535 515 495 0
Figure 32. Frequency vs. Load Current, VOUT = 1.0 MHz, 0.8 V
VIN = 5.5V +125°C +25°C –40°C
1450 1375 1300 1225
FREQUENCY (kHz)
VIN = 13V +125°C +25°C –40°C
FREQUENCY (kHz)
1150 1075 1000 925 850 775 VIN = 5.5V +125°C +25°C –40°C 0 2k 4k 6k VIN = 13V +125°C +25°C –40°C 8k 10k 12k VIN = 16.5V +125°C +25°C –40°C 14k 16k
VIN = 16.5V +125°C +25°C –40°C 2k 4k 6k 8k 10k 12k 14k 16k 18k
08901-029
700 625 550
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 30. Frequency vs. Load Current, 600 kHz, VOUT = 1.8 V
Figure 33. Frequency vs. Load Current, 1.0 MHz, VOUT = 1.8 V
Rev. 0 | Page 11 of 40
ADP1882/ADP1883
1350 1300 1250
MAXIMUM DUTY CYCLE (%)
1200 1150 1100 1050 1000 950 900 0 0.8k 1.6k 2.4k 3.2k VIN = 13V +125°C +25°C –40°C 4.0k 4.8k 5.6k VIN = 16.5V +125°C +25°C –40°C
08901-033
6.4k
7.2k
8.0k
4.8
6.0
7.2
8.4
9.6
10.8 12.0 13.2 14.4 15.6
LOAD CURRENT (mA)
VIN (V)
Figure 34. Frequency vs. Load Current, 1.0 MHz, VOUT = 4 V
2.658 2.657 2.656 2.655
UVLO (V)
Figure 37. Maximum Duty Cycle vs. High Voltage Input (VIN)
680 630 580
MINUMUM OFF TIME (ns)
VREG = 2.7V VREG = 3.6V VREG = 5.5V
530 480 430 380 330 280 230
2.654 2.653 2.652 2.651 2.650
08901-034
–20
0
20
40
60
80
100
120
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 35. UVLO vs. Temperature
Figure 38. Minimum Off Time vs. Temperature
100 95 90
MAXIMUM DUTY CYCLE (%)
680
VDD = 2.7V VDD = 3.6V VDD = 5.5V
+125°C +25°C –40°C
MINUMUM OFF TIME (ns)
630 580 530 480 430 380 330 280 230
08901-035
+125°C +25°C –40°C
85 80 75 70 65 60 55 50 45 40 300 400 500 600 700 800 900 1000
3.1
3.5
3.9
4.3
4.7
5.1
5.5
FREQUENCY (kHz)
VREG (V)
Figure 36. Maximum Duty Cycle vs. Frequency
Figure 39. Minimum Off Time vs. VDD (Low Input Voltage)
Rev. 0 | Page 12 of 40
08901-038
180 2.7
08901-037
2.649 –40
180 –40
08297-036
84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 3.6
VDD = 3.6V VDD = 5.5V
+125°C +25°C –40°C
FREQUENCY (kHz)
ADP1882/ADP1883
800 720 640
RECTIFIER DROP (mV) BODY DIODE CONDUCTION TIME (ns)
VREG = 2.7V VREG = 3.6V VREG = 5.5V
+125°C +25°C –40°C
80 72 64 56 48 40 32 24 16
300kHz 1MHz
+125°C +25°C –40°C
560 480 400 320 240 160
08901-039
400
500
600
700
800
900
1000
3.1
3.5
3.9
4.3
4.7
5.1
5.5
FREQUENCY (kHz)
VREG (V)
Figure 40. Internal Rectifier Drop vs. Frequency
1280 1200 1120 1040
RECTIFIER DROP (mV)
Figure 43. Lower-Side MOSFET Body Conduction Time vs. VDD (Low Input Voltage)
VIN = 5.5V VIN = 13V VIN = 16.5V
1MHz 300kHz
TA = 25°C OUTPUT VOLTAGE
1
960 880 800 720 640 560 480 400 320 240 160
08901-040
INDUCTOR CURRENT
2
SW NODE
3
LOW SIDE
4
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VREG (V)
CH1 50mV BW CH3 10V BW
CH2 5A Ω CH4 5V
M400ns T 35.8%
A CH2
3.90A
Figure 41. Internal Boost Rectifier Drop vs. VDD (Low Input Voltage) over VIN Variation
Figure 44. Power Saving Mode (PSM) Operational Waveform, 100 mA
720 640 560
300kHz 1MHz
+125°C +25°C –40°C
1
OUTPUT VOLTAGE
RECTIFIER DROP (mV)
INDUCTOR CURRENT 480 400 320 240 160
4
08901-041
2
SW NODE
3
LOW SIDE CH1 50mV BW CH3 10V BW CH2 5A Ω CH4 5V M4.0µs T 35.8% A CH2 3.90A
08901-044
80 2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VREG (V)
Figure 42. Internal Boost Rectifier Drop vs. VDD
Figure 45. PSM Waveform at Light Load, 500 mA
Rev. 0 | Page 13 of 40
08901-043
80 2.7
08901-042
80 300
8 2.7
ADP1882/ADP1883
OUTPUT VOLTAGE
4
2
OUTPUT VOLTAGE
INDUCTOR CURRENT
12A NEGATIVE STEP
1
SW NODE
1
3
SW NODE
3
4
LOW SIDE
CH1 5A Ω CH3 10V
08901-045
CH4 100mV
B W
M400ns T 30.6%
A CH3
2.20V
CH1 10A Ω CH3 20V
CH2 200mV CH4 5V
B W M20µs
A CH1
3.40A
T 48.2%
Figure 46. CCM Operation at Heavy Load, 18 A (See Figure 92 for Applications Circuit)
OUTPUT VOLTAGE
2
Figure 49. Negative Step During Heavy Load Transient Behavior—PSM Enabled, 20 A (See Figure 92 for Applications Circuit)
4
OUTPUT VOLTAGE
12A STEP
1
1
12A STEP
LOW SIDE
SW NODE
3
2
SW NODE
LOW SIDE
4
08901-046
3
CH1 10A Ω CH3 20V
CH2 200mV CH4 5V
B W
M2ms T 75.6%
A CH1
3.40A
CH1 10A Ω CH3 20V
CH2 5V CH4 200mV
B W
M2ms T 15.6%
A CH1
6.20A
Figure 47. Load Transient Step—PSM Enabled, 20 A (See Figure 92 for Applications Circuit)
Figure 50. Load Transient Step—Forced PWM at Light Load, 20 A (See Figure 92 for Applications Circuit)
OUTPUT VOLTAGE
2 4
OUTPUT VOLTAGE
12A POSITIVE STEP 12A POSITIVE STEP
1
SW NODE
1
LOW SIDE
3
2
SW NODE LOW SIDE
4
08901-047
3
CH1 10A Ω CH3 20V
CH2 200mV CH4 5V
B W M20µs
A CH1
3.40A
T 30.6%
CH1 10A Ω CH3 20V
CH2 5V CH4 200mV
M20µs
B W T 43.8%
A CH1
6.20A
Figure 48. Positive Step During Heavy Load Transient Behavior—PSM Enabled, 20 A, VOUT = 1.8 V (See Figure 92 for Applications Circuit)
Figure 51. Positive Step During Heavy Load Transient Behavior—Forced PWM at Light Load, 20 A, VOUT = 1.8 V (See Figure 92 for Applications Circuit)
Rev. 0 | Page 14 of 40
08901-050
08901-049
08901-048
ADP1882/ADP1883
2
OUTPUT VOLTAGE
1
OUTPUT VOLTAGE
INDUCTOR CURRENT
12A NEGATIVE STEP
1
2
SW NODE
LOW SIDE
4
3
CH1 10A Ω CH3 20V
08901-051
CH2 200mV CH4 5V
B W M10µs
A CH1
5.60A
T 23.8%
CH1 2V BW CH2 5A Ω CH3 10V CH4 5V
M2ms T 32.8%
A CH1
720mV
Figure 52. Negative Step During Heavy Load Transient Behavior—Forced PWM at Light Load, 20 A (See Figure 92 for Applications Circuit)
Figure 55. Start-Up Behavior at Heavy Load, 18 A, 300 kHz (See Figure 92 for Applications Circuit)
OUTPUT VOLTAGE
1
1
OUTPUT VOLTAGE
INDUCTOR CURRENT
2
LOW SIDE
4
INDUCTOR CURRENT
2
LOW SIDE
4
SW NODE
3
08901-052
SW NODE
3
CH1 2V BW CH2 5A Ω CH3 10V CH4 5V
M4ms T 49.4%
A CH1
920mV
CH1 2V BW CH2 5A Ω CH3 10V CH4 5V
M4ms T 41.6%
A CH1
720mV
Figure 53. Output Short-Circuit Behavior Leading to Hiccup Mode
Figure 56. Power-Down Waveform During Heavy Load
1
OUTPUT VOLTAGE
1
OUTPUT VOLTAGE
INDUCTOR CURRENT INDUCTOR CURRENT
2
2
SW NODE SW NODE
3 3
LOW SIDE LOW SIDE
4
08901-053
4
CH1 5V BW CH2 10A Ω CH3 10V CH4 5V
M10µs T 36.2%
A CH2
8.20A
CH1 50mV BW CH3 10V BW
CH2 5A Ω CH4 5V
M2µs T 35.8%
A CH2
3.90A
Figure 54. Magnified Waveform During Hiccup Mode
Figure 57. Output Voltage Ripple Waveform During PSM Operation at Light Load, 2 A
Rev. 0 | Page 15 of 40
08901-056
08901-055
08901-054
4
LOW SIDE
SW NODE
3
ADP1882/ADP1883
18ns (tr,DRVL )
OUTPUT VOLTAGE
1 4
LOW SIDE
HIGH SIDE
LOW SIDE
4
24ns (tpdh,DRVL )
HS MINUS SW
SW NODE
3 3 2
11ns (tf,DRVH )
SW NODE
INDUCTOR CURRENT
2
08901-057
M
TA = 25°C
08901-060
08901-062 08901-061
CH1 1V BW CH3 10V BW
CH2 5A Ω CH4 2V
M1ms T 63.2%
A CH1
1.56V
CH2 5V CH3 5V CH4 2V MATH 2V 20ns
M20ns T 39.2%
A CH2
4.20V
Figure 58. Soft Start and RES Detect Waveform
Figure 61. Upper-Side Driver Falling and Lower-Side Rising Edge Waveforms (CIN = 4.3 nF (Upper-Side/Lower-Side MOSFET), QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3))
570 550 530 510 490 470 450 VREG = 5.5V VREG = 3.6V VREG = 2.7V
LOW SIDE
TA = 25°C
4
HIGH SIDE SW NODE
3 2 M
HS MINUS SW CH3 5V MATH 2V 40ns
08901-058
TRANSCONDUCTANCE (µS)
CH2 5V CH4 2V
M40ns T 29.0%
A CH2
4.20V
430 –40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 59. Output Drivers and SW Node Waveforms
Figure 62. Transconductance (GM) vs. Temperature
LOW SIDE
16ns (tf,DRVL )
TA = 25°C
680 630
+125°C +25°C –40°C
TRANSCONDUCTANCE (µS)
08901-059
4
22ns (tpdhDRVH ) HIGH SIDE
580 530 480 430 380 330 2.7
25ns (tr,DRVH) SW NODE
3 2 M
HS MINUS SW CH2 5V CH3 5V CH4 2V MATH 2V 40ns M40ns T 29.0% A CH2 4.20V
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
VREG (V)
Figure 60. Upper-Side Driver Rising and Lower-Side Falling Edge Waveforms (CIN = 4.3 nF (Upper-Side/Lower-Side MOSFET), QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3))
Figure 63. Transconductance (GM) vs. VDD
Rev. 0 | Page 16 of 40
ADP1882/ADP1883
1.30 1.25 1.20
QUIESCENT CURRENT (mA)
1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 0.75 3.1 3.5 3.9 4.3 4.7 5.1 5.5
08901-063
+125°C
+25°C
–40°C
0.70 2.7
VREG (V)
Figure 64. Quiescent Current vs. VDD (VIN = 13 V)
Rev. 0 | Page 17 of 40
ADP1882/ADP1883 ADP1882/ADP1883 BLOCK DIAGRAM
ADP1882/ADP1883
tON-TIMER
PRECISION ENABLE BLOCK TO ENABLE ALL BLOCKS C VDD VIN
VDD BIAS BLOCK AND REF R (TRIMMED) SW INFORMATION
tON = 2RC (VOUT/VIN)
REF_ZERO SW-FILTER PFM ISS SS COMP STATE MACHINE VDD
BST
tON
CSS SS_REF BG_REF PSM IN_SS COMP/EN ERROR AMP FB SW PWM IREV 0.8V PWM VREG DRVL DL_LO LS DRVL PGND DRVH LEVEL SHIFT HS 8kΩ DH_LO 300kΩ SW DRVH
IREV COMP LOWER COMP CLAMP CS AMP RES DETECT AND GAIN SET 0.4V 800kΩ
REF_ZERO
CS GAIN SET
ADC
GND
Figure 65. Block Diagram
Rev. 0 | Page 18 of 40
08901-064
ADP1882/ADP1883 THEORY OF OPERATION
The ADP1882/ADP1883 are versatile current-mode, synchronous step-down controllers that provide superior transient response, optimal stability, and current limit protection by using a constant on-time, pseudo-fixed frequency with a programmable currentsense gain, current-control scheme. In addition, these devices offer optimum performance at low duty cycles by using valley currentmode control architecture. This allows the ADP1882/ADP1883 to drive all N-channel power stages to regulate output voltages as low as 0.8 V. ADP1882/ADP1883, reducing the supply current of the devices to approximately 140 μA. For more information, see Figure 67.
ADP1882/ADP1883
FB VDD
SS ERROR AMPLIFIER PRECISION ENABLE TO ENABLE ALL BLOCKS 250mV
0.8V
COMP/EN CC RC CC2
STARTUP
The ADP1882/ADP1883 have an input low voltage pin (VDD) for biasing and supplying power for the integrated MOSFET drivers. A bypass capacitor should be located directly across the VDD (Pin 5) and PGND (Pin 7) pins. Included in the power-up sequence is the biasing of the current-sense amplifier, the current-sense gain circuit (see the Programming Resistor (RES) Detect Circuit section), the soft start circuit, and the error amplifier. The current-sense blocks provide valley current information (see the Programming Resistor (RES) Detect Circuit section) and are a variable of the compensation equation for loop stability (see the Compensation Network section). The valley current information is extracted by forcing 0.4 V across the DRVL output and the PGND pin, which generates a current depending on the resistor across DRVL and PGND in a process performed by the RES detect circuit. The current through the resistor is used to set the current-sense amplifier gain. This process takes approximately 800 μs, after which the drive signal pulses appear at the DRVL and DRVH pins synchronously and the output voltage begins to rise in a controlled manner through the soft start sequence. The rise time of the output voltage is determined by the soft start and error amplifier blocks (see the Soft Start section). At the beginning of a soft start, the error amplifier charges the external compensation capacitor, causing the COMP/EN pin to rise above the enable threshold of 285 mV, thus enabling the ADP1882/ADP1883.
Figure 66. Release COMP/EN Pin to Enable the ADP1882/ADP1883
COMP/EN
>2.4V 2.4V
HICCUP MODE INITIALIZED MAXIMUM CURRENT (UPPER CLAMP)
0.9V
ZERO CURRENT
USABLE RANGE ONLY AFTER SOFT START PERIOD IF CONTUNUOUS CONDUCTION MODE OF OPERATION IS SELECTED.
500mV
LOWER CLAMP
0V
35mV HYSTERESIS
Figure 67. COMP/EN Voltage Range
UNDERVOLTAGE LOCKOUT
The undervoltage lockout (UVLO) feature prevents the part from operating both the upper-side and lower-side MOSFETs at extremely low or undefined input voltage (VDD) ranges. Operation at an undefined bias voltage may result in the incorrect propagation of signals to the high-side power switches. This, in turn, results in invalid output behavior that can cause damage to the output devices, ultimately destroying the device tied at the output. The UVLO level has been set at 2.65 V (nominal).
SOFT START
The ADP1882/ADP1883 have digital soft start circuitry, which involves a counter that initiates an incremental increase in current, by 1 μA, via a current source on every cycle through a fixed internal capacitor. The output tracks the ramping voltage by producing PWM output pulses to the upper-side MOSFET. The purpose is to limit the in-rush current from the high voltage input supply (VIN) to the output (VOUT).
THERMAL SHUTDOWN
The thermal shutdown is a self-protection feature to prevent the IC from damage due to a very high operating junction temperature. If the junction temperature of the device exceeds 155°C, the part enters the thermal shutdown state. In this state, the device shuts off both the upper-side and lower-side MOSFETs and disables the entire controller immediately, thus reducing the power consumption of the IC. The part resumes operation after the junction temperature of the part cools to less than 140°C.
PRECISION ENABLE CIRCUITRY
The ADP1882/ADP1883 employ precision enable circuitry. The enable threshold is 285 mV typical with 35 mV of hysteresis. The devices are enabled when the COMP/EN pin is released, allowing the error amplifier output to rise above the enable threshold (see Figure 66). Grounding this pin disables the
Rev. 0 | Page 19 of 40
08901-066
285mV
PRECISION ENABLE THRESHOLD
08901-065
ADP1882/ADP1883
PROGRAMMING RESISTOR (RES) DETECT CIRCUIT
Upon startup, one of the first blocks to become active is the RES detect circuit. This block powers up before a soft start begins. It forces a 0.4 V reference value at the DRVL output (see Figure 68) and is programmed to identify four possible resistor values: 47 kΩ, 22 kΩ, open, and 100 kΩ.
ADP1882
Q1 DRVH SW Q2 DRVL CS GAIN PROGRAMMING
08901-067
VALLEY CURRENT-LIMIT SETTING
The architecture of the ADP1882/ADP1883 is based on valley current-mode control. The current limit is determined by three components: the RON of the lower-side MOSFET, the error amplifier output voltage swing (COMP), and the current-sense gain. The COMP range is internally fixed at 1.5 V. The current-sense gain is programmable via an external resistor at the DRVL pin (see the Programming Resistor (RES) Detect Circuit section). The RON of the lower-side MOSFET can vary over temperature and usually has a positive TC (meaning that it increases with temperature); therefore, it is recommended that the currentsense gain resistor be programmed based on the rated RON of the MOSFET at 125°C. Because the ADP1882/ADP1883 are based on valley current control, the relationship between ICLIM and ILOAD is as follows: ICLIM = ILOAD × ⎛1 − K I ⎞ ⎟ ⎜
⎝ 2⎠
RES
Figure 68. Programming Resistor Location
The RES detect circuit digitizes the value of the resistor at the DRVL pin (Pin 6). An internal ADC outputs a 2-bit digital code that is used to program four separate gain configurations in the current-sense amplifier (see Figure 69). Each configuration corresponds to a current-sense gain (ACS) of 3 V/V, 6 V/V, 12 V/V, and 24 V/V, respectively (see Table 5 and Table 6). This variable is used for the valley current-limit setting, which sets up the appropriate current-sense signal gain for a given application and sets the compensation necessary to achieve loop stability (see the Valley Current-Limit Setting and Compensation Network sections).
where: ICLIM is the desired valley current limit. ILOAD is the current load. KI is the ratio between the inductor ripple current and the desired average load current (see Figure 10). Establishing KI helps to determine the inductor value (see the Inductor Selection section), but in most cases, KI = 0.33.
RIPPLE CURRENT =
ILOAD 3
CS AMP ADC 0.4V
SW PGND
LOAD CURRENT
CS GAIN SET
VALLEY CURRENT LIMIT
Figure 70. Valley Current Limit to Average Current Relation
DRVL
RES
08901-068
When the desired valley current limit (ICLIM) has been determined, the current-sense gain can be calculated by using the following expression: ICLIM =
1.5 V ACS × RON
Figure 69. RES Detect Circuit for Current-Sense Gain Programming
Table 5. Current-Sense Gain Programming
Resistor (kΩ) 47 22 Open 100 ACS (V/V) 3.25 6.5 26 13
where: ACS is the current-sense gain multiplier (see Table 5 and Table 6). RON is the channel impedance of the lower-side MOSFET.
Rev. 0 | Page 20 of 40
08901-069
ADP1882/ADP1883
Although the ADP1882/ADP1883 have only four discrete currentsense gain settings for a given RON variable, Table 6 and Figure 71 outline several available options for the valley current setpoint based on various RON values. Table 6. Valley Current Limit Program1
RON (mΩ) 1.5 2 2.5 3 3.5 4.5 5 5.5 10 15 18
1
47 kΩ
ACS = 3.4 V/V
Valley Current Level 22 kΩ Open
ACS = 6.6 V/V ACS = 26.7 V/V
The valley current limit is programmed as outlined in Table 6 and Figure 71. The inductor chosen must be rated to handle the peak current, which is equal to the valley current from Table 6 plus the peak-to-peak inductor ripple current (see the Inductor Selection section). In addition, the peak current value must be used to compute the worst-case power dissipation in the MOSFETs (see Figure 72).
49A
100 kΩ
ACS = 13.4 V/V
30.769 25.641
23.08 15.38 12.82
38.46 32.97 25.64 23.08 20.98 11.54 7.692 6.41
38.5 28.8 23.1 19.2 16.5 12.8 11.5 10.5 5.77 3.85 3.21
MAXIMUM DC LOAD CURRENT
39.5A
INDUCTOR CURRENT
ΔI = 65% OF 37A
35A ΔI = 45% 32.25A OF 32.25A 30A
37A
COMP OUTPUT
ΔI = 33% OF 30A
2.4V VALLEY CURRENT-LIMIT THRESHOLD (SET FOR 25A) COMP OUTPUT SWING
Refer to Figure 71 for more information and a graphical representation.
39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
08901-071
RES = 47kΩ ACS = 6.6V/V
0A
0.9V
Figure 72. Valley Current-Limit Threshold in Relation to Inductor Ripple Current
VALLEY CURRENT LIMIT (A)
HICCUP MODE DURING SHORT CIRCUIT
A current-limit violation occurs when the current across the source and drain of the lower-side MOSFET exceeds the current-limit setpoint. When 32 current-limit violations are detected, the controller enters the idle mode and turns off the MOSFETs for 6 ms, allowing the converter to cool down. Then, the controller reestablishes soft start and begins to cause the output to ramp up again (see Figure 73). While the output ramps up, COMP is monitored to determine if the violation is still present. If it is still present, the idle event occurs again, followed by the full-chip power-down sequence. This cycle continues until the violation no longer exists. If the violation disappears, the converter is allowed to switch normally, maintaining regulation.
RES = 100kΩ ACS = 13.4V/V
RES = 22kΩ ACS = 3.4V/V
RES = OPEN ACS = 26.7V/V
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 RON (mΩ)
Figure 71. Valley Current-Limit Value vs. RON of the Lower-Side MOSFET for Each Programming Resistor (RES)
REPEATED CURRENT-LIMIT VIOLATION DETECTED HS A PREDETERMINED NUMBER SOFT START IS OF PULSES IS COUNTED TO REINITIALIZED TO ALLOW THE CONVERTER MONITOR IF THE TO COOL DOWN VIOLATION STILL EXISTS
CLIM
08901-070
ZERO CURRENT
Figure 73. Idle Mode Entry Sequence Due to Current-Limit Violations
Rev. 0 | Page 21 of 40
08901-072
ADP1882/ADP1883
SYNCHRONOUS RECTIFIER
The ADP1882/ADP1883 employ an internal lower-side MOSFET driver to drive the external upper-side and lower-side MOSFETs. The synchronous rectifier not only improves overall conduction efficiency but also ensures proper charging to the bootstrap capacitor located at the upper-side driver input. This is beneficial during startup to provide a sufficient drive signal to the external upper-side MOSFET and attain a fast turn on response, which is essential for minimizing switching losses. The integrated upperside and lower-side MOSFET drivers operate in complementary fashion with built-in anticross conduction circuitry to prevent unwanted shoot-through current that may potentially damage the MOSFETs or reduce efficiency as a result of excessive power loss. As soon as the forward current through the lower-side MOSFET decreases to a level where 10 mV = IQ2 × RON(Q2) the zero-cross comparator (or IREV comparator) emits a signal to turn off the lower-side MOSFET. From this point, the slope of the inductor current ramping down becomes steeper (see Figure 76) as the body diode of the lower-side MOSFET begins to conduct current and continues conducting current until the remaining energy stored in the inductor has been depleted.
ANOTHER tON EDGE IS TRIGGERED WHEN VOUT FALLS BELOW REGULATION SW
tON
POWER SAVING MODE (PSM) VERSION (ADP1883)
The ADP1883 is the power saving mode version of the ADP1882. The ADP1883 operates in the discontinuous conduction mode (DCM) and pulse skips at light load to midload currents. It outputs pulses, as necessary, to maintain output regulation. Unlike the continuous conduction mode (CCM), DCM operation prevents negative current, thus allowing improved system efficiency at light loads. Current in the reverse direction through this pathway, however, results in power dissipation and, therefore, a decrease in efficiency.
HS
HS AND LS IN IDLE MODE
LS
ILOAD
ZERO-CROSS COMPARATOR DETECTS 10mV OFFSET AND TURNS OFF LS
0A 10mV = RON × ILOAD
tON
Figure 76. 10 mV Offset to Ensure Prevention of Negative Inductor Current
LS
HS AND LS ARE OFF OR IN IDLE MODE
tOFF
The system remains in idle mode until the output voltage drops from within regulation. A PWM pulse is then produced, turning on the upper-side MOSFET to maintain system regulation. The ADP1883 does not have an internal clock; therefore, it switches purely as a hysteretic controller as described in this section.
TIMER OPERATION
AS THE INDUCTOR CURRENT APPROACHES ZERO CURRENT, THE STATE MACHINE TURNS OFF THE LOWER-SIDE MOSFET.
08901-073
ILOAD 0A
Figure 74. Discontinuous Mode of Operation (DCM)
To minimize the chance of negative inductor current buildup, an on-board, zero-cross comparator turns off all upper-side and lower-side switching activities when the inductor current approaches the zero current line, causing the system to enter idle mode, where the upper-side and lower-side MOSFETs are turned off. To ensure idle mode entry, a 10 mV offset, connected in series at the SW node, is implemented (see Figure 75).
ZERO-CROSS COMPARATOR SW IQ2 10mV
The ADP1882/ADP1883 employ a constant on-time architecture that provides a variety of benefits, including improved load and line transient responses when compared with a constant (fixed) frequency current-mode control loop of a comparable loop design. The constant on-time timer, or tON timer, senses the high input voltage (VIN) and the output voltage (VOUT) using SW waveform information to produce an adjustable one-shot PWM pulse that varies the on time of the upper-side MOSFET in response to dynamic changes in input voltage, output voltage, and load current conditions to maintain regulation. It then generates an on-time (tON) pulse that is inversely proportional to VIN. tON = K ×
VOUT VIN
where K is a constant that is trimmed using an RC timer product for the 300 kHz, 600 kHz, and 1.0 MHz frequency options.
Figure 75. Zero-Cross Comparator with 10 mV of Offset
Rev. 0 | Page 22 of 40
08901-074
LS
Q2
08901-075
ADP1882/ADP1883
tON
C I SW INFORMATION R (TRIMMED)
08901-076
VREG
VIN
To illustrate this feature more clearly, this section describes one such load transient event—a positive load step—in detail. During load transient events, the high-side driver output pulse width stays relatively consistent from cycle to cycle; however, the off time (DRVL on time) dynamically adjusts according to the instantaneous changes in the external conditions mentioned. When a positive load step occurs, the error amplifier (out of phase of the output, VOUT) produces new voltage information at its output (COMP). In addition, the current-sense amplifier senses new inductor current information during this positive load transient event. The error amplifier’s output voltage reaction is compared to the new inductor current information that sets the start of the next switching cycle. Because current information is produced from valley current sensing, it is sensed at the down ramp of the inductor current, whereas the voltage loop information is sensed through the counter action upswing of the error amplifier’s output (COMP). The result is a convergence of these two signals (see Figure 78), which allows an instantaneous increase in switching frequency during the positive load transient event. In summary, a positive load step causes VOUT to transient down, which causes COMP to transient up and, therefore, shortens the off time. This resultant increase in frequency during a positive load transient helps to quickly bring VOUT back up in value and within the regulation window. Similarly, a negative load step causes the off time to lengthen in response to VOUT rising. This effectively increases the inductor demagnetizing phase, helping to bring VOUT within regulation. In this case, the switching frequency decreases, or experiences a foldback, to help facilitate output voltage recovery. Because the ADP1882/ADP1883 can respond rapidly to sudden changes in load demand, the recovery period in which the output voltage settles back to its original steady state operating point is much quicker than it would be for a fixed-frequency equivalent. Therefore, using a pseudo-fixed frequency results in significantly better load transient performance than using a fixed frequency.
Figure 77. Constant On-Time Timer
The constant on time (tON) is not strictly constant because it varies with VIN and VOUT. However, this variation occurs in such a way as to keep the switching frequency virtually independent of VIN and VOUT. The tON timer uses a feedforward technique, applied to the constant on-time control loop, making it pseudo-fixed frequency to a first order. Second-order effects, such as dc losses in the external power MOSFETs (see the Efficiency Consideration section), cause some variation in frequency vs. load current and line voltage. These effects are shown in Figure 23 to Figure 34. The variations in frequency are much reduced, compared with the variations generated when the feedforward technique is not used. The feedforward technique establishes the following relationship:
1 K
fSW =
where fSW is the controller switching frequency (300 kHz, 600 kHz, and 1.0 MHz). The tON timer senses VIN and VOUT to minimize frequency variation with VIN and VOUT as previously explained. This provides a pseudo fixed frequency that is explained in the Pseudo-Fixed Frequency section. To allow headroom for VIN and VOUT sensing, adhere to the following two equations: VDD ≥ VIN/8 + 1.5
VDD ≥ VOUT/4
For typical applications where VDD = 5 V, these equations are not relevant; however, for lower VDD inputs, care may be required.
PSEUDO-FIXED FREQUENCY
The ADP1882/ADP1883 employ a constant on-time control scheme. During steady state operation, the switching frequency stays relatively constant, or pseudo-fixed. This is due to the oneshot tON timer, which produces a high-side PWM pulse with a fixed duration, given that external conditions such as input voltage, output voltage, and load current are also at steady state. During load transients, the frequency momentarily changes for the duration of the transient event so that the output comes back within regulation more quickly than if the frequency were fixed or if it were to remain unchanged. After the transient event is complete, the frequency returns to a pseudo-fixed value to a first-order.
LOAD CURRENT DEMAND
CS AMP OUTPUT
ERROR AMP OUTPUT
VALLEY TRIP POINTS
PWM OUTPUT
fSW
>fSW
08901-077
Figure 78. Load Transient Response Operation
Rev. 0 | Page 23 of 40
ADP1882/ADP1883 APPLICATIONS INFORMATION
FEEDBACK RESISTOR DIVIDER
The required resistor divider network can be determined for a given VOUT value because the internal band gap reference (VREF) is fixed at 0.8 V. Selecting values for RT and RB determines the minimum output load current of the converter. Therefore, for a given value of RB, the RT value can be determined using the following expression: Table 7. Recommended Inductors
L (μH) 0.12 0.22 0.47 0.72 0.9 1.2 1.0 1.4 2.0 0.8 DCR (mΩ) 0.33 0.33 0.8 1.65 1.6 1.8 3.3 3.2 2.6 ISAT (A) 55 30 50 35 28 25 20 24 22 27.5 Dimensions (mm) 10.2 × 7 10.2 × 7 14.2 × 12.8 10.5 × 10.2 13 × 12.8 10.5 × 10.2 10.5 × 10.2 14 × 12.8 13.2 × 12.8 Manufacturer Wurth Electronics Wurth Electronics Wurth Electronics Wurth Electronics Wurth Electronics Wurth Electronics Wurth Electronics Wurth Electronics Wurth Electronics Sumida Model Number 744303012 744303022 744355147 744325072 744355090 744325120 7443552100 744318180 7443551200 CEP125U-0R8
RT = RB ×
(VOUT − 0.8 V) 0 .8 V
INDUCTOR SELECTION
The inductor value is inversely proportional to the inductor ripple current. The peak-to-peak ripple current is given by
OUTPUT RIPPLE VOLTAGE (ΔVRR)
The output ripple voltage is the ac component of the dc output voltage during steady state. For a ripple error of 1.0%, the output capacitor value needed to achieve this tolerance can be determined using the following equation. Note that an accuracy of 1.0% is possible only during steady state conditions, not during load transients. ΔVRR = (0.01) × VOUT
ΔI L = K I × I LOAD
I ≈ LOAD 3
where KI is typically 0.33. The equation for the inductor value is given by
L=
(V IN − VOUT ) VOUT × ΔI L × f SW V IN
where: VIN is the high voltage input. VOUT is the desired output voltage. fSW is the controller switching frequency (300 kHz, 600 kHz, and 1.0 MHz). When selecting the inductor, choose an inductor saturation rating that is above the peak current level, and then calculate the inductor current ripple (see the Valley Current-Limit Setting section and Figure 79).
52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 8 10 12 14 16 18 20 ΔI = 50% ΔI = 40%
OUTPUT CAPACITOR SELECTION
The primary objective of the output capacitor is to facilitate the reduction of the output voltage ripple; however, the output capacitor also assists in the output voltage recovery during load transient events. For a given load current step, the output voltage ripple generated during this step event is inversely proportional to the value chosen for the output capacitor. The speed at which the output voltage settles during this recovery period depends on where the crossover frequency (loop bandwidth) is set. This crossover frequency is determined by the output capacitor, the equivalent series resistance (ESR) of the capacitor, and the compensation network. To calculate the small-signal voltage ripple (output ripple voltage) at the steady state operating point, use the following equation:
⎛ ⎞ 1 ⎟ COUT = ΔI L × ⎜ ⎜ 8 × F × [ΔV − (ΔI L × ESR)] ⎟ RIPPLE SW ⎝ ⎠
PEAK INDUCTOR CURRENT (A)
ΔI = 33%
where ESR is the equivalent series resistance of the output capacitors.
22 24 26 28 30
08901-078
To calculate the output load step, use the following equation: COUT = 2 × f SW
VALLEY CURRENT LIMIT (A)
Figure 79. Peak Current vs. Valley Current Threshold for 33%, 40%, and 50% of Inductor Ripple Current
ΔI LOAD × (ΔVDROOP − (ΔI LOAD × ESR))
where ΔVDROOP is the amount that VOUT is allowed to deviate for a given positive load current step (ΔILOAD).
Rev. 0 | Page 24 of 40
ADP1882/ADP1883
Ceramic capacitors are known to have low ESR. However, the trade-off of using X5R technology is that up to 80% of its capacitance may be lost due to derating as the voltage applied across the capacitor is increased (see Figure 80). Although X7R series capacitors can also be used, the available selection is limited to only up to 22 μF.
20 10 X7R (50V) 0
Error Amplifier Output Impedance (ZCOMP)
Assuming CC2 is significantly smaller than CCOMP, CC2 can be omitted from the output impedance equation of the error amplifier. The transfer function simplifies to
Z COMP = R COMP ( f CROSS + f ZERO ) f CROSS
and
fCROSS = 1 × f SW 12
CAPACITANCE CHARGE (%)
–10 –20 –30 –40 –50 X5R (25V) –60 –70 X5R (16V) –80 –90 10µF TDK 25V, X7R, 1210 C3225X7R1E106M 22µF MURATA 25V, X7R, 1210 GRM32ER71E226KE15L 47µF MURATA 16V, X5R, 1210 GRM32ER61C476KE15L 0 5 10 15 20 25 30
08901-079
where fZERO, the zero frequency, is set to be 1/4 of the crossover frequency for the ADP1882.
Error Amplifier Gain (GM)
The error amplifier gain (transconductance) is GM = 500 μA/V
Current-Sense Loop Gain (GCS)
The current-sense loop gain is G CS = 1 (A/V) ACS × RON
–100
DC VOLTAGE (VDC)
Figure 80. Capacitance vs. DC Voltage Characteristics for Ceramic Capacitors
Electrolytic capacitors satisfy the bulk capacitance requirements for most high current applications. Because the ESR of electrolytic capacitors is much higher than that of ceramic capacitors, when using electrolytic capacitors, several MLCCs should be mounted in parallel to reduce the overall series resistance.
where: ACS (V/V) is programmable for 3 V/V, 6 V/V, 12 V/V, and 24 V/V (see the Programming Resistor (RES) Detect Circuit and Valley Current-Limit Setting sections). RON is the channel impedance of the lower-side MOSFET.
COMPENSATION NETWORK
Due to its current-mode architecture, the ADP1882/ADP1883 require Type II compensation. To determine the component values needed for compensation (resistance and capacitance values), it is necessary to examine the overall loop gain (H) of the converter at the unity gain frequency (fSW/10) when H = 1 V/V, as follows:
H = 1 V/V = GM × ACS × VOUT × ZCOMP × ZFILT VREF
Crossover Frequency
The crossover frequency is the frequency at which the overall loop (system) gain is 0 dB (H = 1 V/V). For current-mode converters such as the ADP1882, it is recommended that the user set the crossover frequency between 1/10 and 1/15 of the switching frequency.
fCROSS = 1 f SW 12
Examining each variable at high frequency enables the unitygain transfer function to be simplified to provide expressions for the RCOMP and CCOMP component values.
The relationship between CCOMP and fZERO (zero frequency) is as follows:
f ZERO = 1 2 π × RCOMP × C COMP
)
Output Filter Impedance (ZFILT)
Examining the transfer function of the filter at high frequencies simplifies to
ZFILT =
The zero frequency is set to 1/4 of the crossover frequency. Combining all of the above parameters results in
RCOMP = 2πf CROSS C OUT VOUT f CROSS × × f CROSS + f ZERO G M ACS VREF
1 sC OUT
at the crossover frequency (s = 2πfCROSS).
C COMP =
1 2 × π × RCOMP × f ZERO
Rev. 0 | Page 25 of 40
ADP1882/ADP1883
EFFICIENCY CONSIDERATIONS
One of the important criteria to consider in constructing a dc-to-dc converter is efficiency. By definition, efficiency is the ratio of the output power to the input power. For high power applications at load currents up to 20 A, the following are important MOSFET parameters that aid in the selection process: • • • • • VGS (TH), the MOSFET support voltage applied between the gate and the source RDS (ON), the MOSFET on resistance during channel conduction QG, the total gate charge CN1, the input capacitance of the upper-side switch CN2, the input capacitance of the lower-side switch
800 720 640
RECTIFIER DROP (mV)
VDD = 2.7V VDD = 3.6V VDD = 5.5V
560 480 400 320 240 160 80 300 +125°C +25°C –40°C 400 500 600 700 800 900 1000
08901-080
SWITCHING FREQUENCY (kHz)
The following are the losses experienced through the external component during normal switching operation: • • • • • Channel conduction loss (both MOSFETs) MOSFET driver loss MOSFET switching loss Body diode conduction loss (lower-side MOSFET) Inductor loss (copper and core loss)
Figure 81. Internal Rectifier Voltage Drop vs. Switching Frequency
Switching Loss
The SW node transitions as a result of the switching activities of the upper-side and lower-side MOSFETs. This causes removal and replenishing of charge to and from the gate oxide layer of the MOSFET, as well as to and from the parasitic capacitance that is associated with the gate oxide edge overlap and the drain and source terminals. The current that enters and exits these charge paths presents additional loss during these transition times. This loss can be approximately quantified by using the following equation, which represents the time in which charge enters and exits these capacitive regions: tSW-TRANS = RGATE × CTOTAL where: RGATE is the gate input resistance of the MOSFET. CTOTAL is the CGD + CGS of the external MOSFET used. The ratio of this time constant to the period of one switching cycle is the multiplying factor to be used in the following expression:
PSW ( LOSS) = t SW -TRANS t SW × I LOAD × V IN × 2
Channel Conduction Loss
During normal operation, the bulk of the loss in efficiency is due to the power dissipated through MOSFET channel conduction. Power loss through the upper-side MOSFET is directly proportional to the duty cycle (D) for each switching period, and the power loss through the lower-side MOSFET is directly proportional to 1 − D for each switching period. The selection of MOSFETs is governed by the amount of maximum dc load current that the converter is expected to deliver. In particular, the selection of the lower-side MOSFET is dictated by the maximum load current because a typical high current application employs duty cycles of less than 50%. Therefore, the lower-side MOSFET is in the on state for most of the switching period.
2 PN1,N2(CL) = D × R N1(ON) + (1 − D ) × R N2(ON) × I LOAD
[
]
or PSW(LOSS) = fSW × RGATE × CTOTAL × ILOAD × VIN × 2
MOSFET Driver Loss
Other dissipative elements are the MOSFET drivers. The contributing factors are the dc current flowing through the driver during operation and the QGATE parameter of the external MOSFETs.
PDR ( LOSS ) = VDR × f SW C upperFET VDR + I BIAS + [VDD × ( f SW C lowerFET VDD + I BIAS )]
[
(
)]
where: VDR is the driver bias voltage (that is, the low input voltage (VDD) minus the rectifier drop (see Figure 81)). CupperFET is the input gate capacitance of the upper-side MOSFET. ClowerFET is the input gate capacitance of the lower-side MOSFET. IBIAS is the dc current flowing into the upper and lower-side drivers. VDD is the bias voltage.
Rev. 0 | Page 26 of 40
ADP1882/ADP1883
Diode Conduction Loss
The ADP1882/ADP1883 employ anticross conduction circuitry that prevents the upper-side and lower-side MOSFETs from conducting current simultaneously. This overlap control is beneficial, avoiding large current flow that may lead to irreparable damage to the external components of the power stage. However, this blanking period comes with the trade-off of a diode conduction loss occurring immediately after the MOSFETs change states and continuing well into idle mode. The amount of loss through the body diode of the lower-side MOSFET during the antioverlap state is given by the following expression:
PBODY ( LOSS) = t BODY ( LOSS) t SW × I LOAD × VF × 2
to achieve minimal loss and negligible electromagnetic interference (EMI). PDCR(LOSS) = DCR × I2LOAD + Core Loss
INPUT CAPACITOR SELECTION
The goal in selecting an input capacitor is to reduce or minimize input voltage ripple and to reduce the high frequency source impedance, which is essential for achieving predictable loop stability and transient performance. The problem with using bulk capacitors, other than their physical geometries, is their large equivalent series resistance (ESR) and large equivalent series inductance (ESL). Aluminum electrolytic capacitors have such high ESR that they cause undesired input voltage ripple magnitudes and are generally not effective at high switching frequencies. If bulk capacitors are to be used, it is recommended that multilayered ceramic capacitors (MLCC) be used in parallel, due to their low ESR values. This dramatically reduces the input voltage ripple amplitude as long as the MLCCs are mounted directly across the drain of the upper-side MOSFET and the source terminal of the lower-side MOSFET (see the Layout Considerations section). Improper placement and mounting of these MLCCs may cancel their effectiveness due to stray inductance and an increase in trace impedance.
I CIN , RMS = I LOAD, MAX × VOUT × (V IN − VOUT ) VOUT
where: tBODY(LOSS) is the body conduction time (refer to Figure 82 for dead time periods). tSW is the period per switching cycle. VF is the forward drop of the body diode during conduction (refer to the selected external MOSFET data sheet for more information about the VF parameter).
80 72 64 56 48 40 32 24 16
08901-081
1MHz 300kHz
BODY DIODE CONDUCTION TIME (ns)
+125°C +25°C –40°C
The maximum input voltage ripple and maximum input capacitor rms current occur at the end of the duration of 1 − D while the upper-side MOSFET is in the off state. The input capacitor rms current reaches its maximum at Time D. When calculating the maximum input voltage ripple, account for the ESR of the input capacitor as follows:
3.4 4.1 VDD (V) 4.8 5.5
8 2.7
VMAX,RIPPLE = VRIPP + (ILOAD,MAX × ESR) where: VRIPP is usually 1% of the minimum voltage input. ILOAD,MAX is the maximum load current. ESR is the equivalent series resistance rating of the input capacitor used. Inserting VMAX,RIPPLE into the charge balance equation to calculate the minimum input capacitor requirement gives
C IN,min = I LOAD, MAX VMAX , RIPPLE × D(1 − D) f SW
Figure 82. Body Diode Conduction Time vs. Low Voltage Input (VDD)
Inductor Loss
During normal conduction mode, further power loss is caused by the conduction of current through the inductor windings, which have dc resistance (DCR). Typically, larger sized inductors have smaller DCR values. The inductor core loss is a result of the eddy currents generated within the core material. These eddy currents are induced by the changing flux, which is produced by the current flowing through the windings. The amount of inductor core loss depends on the core material, the flux swing, the frequency, and the core volume. Ferrite inductors have the lowest core losses, whereas powdered iron inductors have higher core losses. It is recommended to use shielded ferrite core material type inductors with the ADP1882/ ADP1883 for a high current, dc-to-dc switching application
or
C IN,min = I LOAD, MAX 4 f SW V MAX , RIPPLE
where D = 50%.
Rev. 0 | Page 27 of 40
ADP1882/ADP1883
THERMAL CONSIDERATIONS
The ADP1882/ADP1883 are used for dc-to-dc, step down, high current applications that have an on-board controller and on-board MOSFET drivers. Because applications may require up to 20 A of load current delivery and be subjected to high ambient temperature surroundings, the selection of external upper-side and lower-side MOSFETs must be associated with careful thermal consideration to not exceed the maximum allowable junction temperature of 125°C. To avoid permanent or irreparable damage if the junction temperature reaches or exceeds 155°C, the part enters thermal shutdown, turning off both external MOSFETs, and does not reenable until the junction temperature cools to 140°C (see the Thermal Shutdown section). The maximum junction temperature allowed for the ADP1882/ ADP1883 ICs is 125°C. This means that the sum of the ambient temperature (TA) and the rise in package temperature (TR), which is caused by the thermal impedance of the package and the internal power dissipation, should not exceed 125°C, as dictated by the following expression: TJ = TR × TA where: TA is the ambient temperature. TJ is the maximum junction temperature. TR is the rise in package temperature due to the power dissipated from within. The rise in package temperature is directly proportional to its thermal impedance characteristics. The following equation represents this proportionality relationship: TR = θJA × PDR(LOSS) where: θJA is the thermal resistance of the package from the junction to the outside surface of the die, where it meets the surrounding air. PDR(LOSS) is the overall power dissipated by the IC. The bulk of the power dissipated is due to the gate capacitance of the external MOSFETs. The power loss equation of the MOSFET drivers (see the MOSFET Driver Loss section in the Efficiency Consideration section) is PDR(LOSS) = [VDR × (fSWCupperFETVDR + IBIAS)] + [VDD × (fSWClowerFETVDD + IBIAS)] where: CupperFET is the input gate capacitance of the upper-side MOSFET. ClowerFET is the input gate capacitance of the lower-side MOSFET. IBIAS is the dc current (2 mA) flowing into the upper-side and lower-side drivers. VDR is the driver bias voltage (that is, the low input voltage (VDD) minus the rectifier drop (see Figure 81)). VDD is the bias voltage For example, if the external MOSFET characteristics are θJA (10-lead MSOP) = 171.2°C/W, fSW = 300 kHz, IBIAS = 2 mA, CupperFET = 3.3 nF, ClowerFET = 3.3 nF, VDR = 5.12 V, and VDD = 5.5 V, then the power loss is PDR(LOSS) = [VDR × (fSWCupperFETVDR + IBIAS)] + [VDD × (fSWClowerFETVDD + IBIAS)] = [5.12 × (300 × 103 × 3.3 × 10−9 × 5.12 + 0.002)] + [5.5 × (300 × 103 ×3.3 × 10−9 × 5.5 + 0.002)] = 77.13 mW The rise in package temperature is TR = θJA × PDR(LOSS) = 171.2°C × 77.13 mW = 13.2°C Assuming a maximum ambient temperature environment of 85°C, the junction temperature is TJ = TR × TA = 13.2°C + 85°C = 98.2°C which is below the maximum junction temperature of 125°C.
DESIGN EXAMPLE
The ADP1882/ADP1883 are easy to use, requiring only a few design criteria. For example, the example outlined in this section uses only four design criteria: VOUT = 1.8 V, ILOAD = 15 A (pulsing), VIN = 12 V (typical), and fSW = 300 kHz.
Input Capacitor
The maximum input voltage ripple is usually 1% of the minimum input voltage (11.8 V × 0.01 = 120 mV). VRIPP = 120 mV VMAX,RIPPLE = VRIPP − (ILOAD,MAX × ESR) = 120 mV − (15 A × 0.001) = 45 mV
C IN,min = I LOAD, MAX
4 f SW V MAX , RIPPLE
=
15 A 4 × 300 × 10 3 × 105 mV
= 120 μF Choose five 22 μF ceramic capacitors. The overall ESR of five 22 μF ceramic capacitors is less than 1 mΩ. IRMS = ILOAD/2 = 7.5 A PCIN = (IRMS)2 × ESR = (7.5A)2 × 1 mΩ = 56.25 mW
Rev. 0 | Page 28 of 40
ADP1882/ADP1883
Inductor
Determine the inductor ripple current amplitude as follows:
ΔI L ≈
Assuming an overshoot of 45 mV, determine if the output capacitor that was calculated previously is adequate.
COUT = =
I LOAD =5A 3
V OUT V IN,MAX
((VOUT
(L × I 2 LOAD ) − ΔVOVSHT )2 − (VOUT )2 )
then calculate for the inductor value
L= = (V IN , MAX − V OUT ) Δ I L × f SW × ×
1 × 10 − 6 × (15 A )2 (1.8 − 45 mV )2 − (1.8)2
= 1.4 mF Choose five 270 μF polymer capacitors. The rms current through the output capacitor is
I RMS = = 1 1 (V IN , MAX − VOUT ) VOUT × × 2 L × f SW V IN , MAX 3
(13 . 2 V − 1 . 8 V ) 5 V × 300 × 10 3
1 .8 V 13 . 2 V
= 1.03 μH The inductor peak current is approximately 15 A + (5 A × 0.5) = 17.5 A Therefore, an appropriate inductor selection is 1.0 μH with DCR = 3.3 mΩ (7443552100) from Table 8, with peak current handling of 20 A.
2 PDCR(LOSS) = DCR × I L = 0.003 × (15 A)2 = 675 mW
1 1 (13.2 V − 1.8 V) 1.8 V × × = 1.49 A 2 3 1 μF × 300 × 10 3 13.2 V
The power loss dissipated through the ESR of the output capacitor is PCOUT = (IRMS)2 × ESR = (1.5 A)2 × 1.4 mΩ = 3.15 mW
Current Limit Programming
The valley current is approximately 15 A − (5 A × 0.5) = 12.5 A Assuming a lower-side MOSFET RON of 4.5 mΩ, choosing 13 A as the valley current limit from Table 7 and Figure 71 indicates that a programming resistor (RES) of 100 kΩ corresponds to an ACS of 24 V/V. Choose a programmable resistor of RRES = 100 kΩ for a currentsense gain of 24 V/V.
Feedback Resistor Network Setup
It is recommended that RB = 15 kΩ be used. Calculate RT as follows: RT = 15 kΩ ×
(1.8 V − 0.6 V) 0. 6 V
= 30 kΩ
Compensation Network
To calculate RCOMP, CCOMP, and CPAR, the transconductance parameter and the current-sense gain variable are required. The transconductance parameter (GM) is 500 μA/V, and the currentsense loop gain is GCS =
1 1 = = 7.7 A/V ACS RON 26 × 0.005
Output Capacitor
Assume a load step of 15 A occurs at the output, and no more than 5% is allowed for the output to deviate from the steady state operating point. Because the frequency is pseudo-fixed, the advantage of the ADP1882 is that the converter is able to respond quickly because of the immediate, though temporary, increase in switching frequency. ΔVDROOP = 0.05 × 1.8 V = 90 mV Assuming the overall ESR of the output capacitor ranges from 5 mΩ to 10 mΩ,
where ACS and RON are taken from setting up the current limit (see the Programming Resistor (RES) Detect Circuit and Valley Current-Limit Setting sections). The crossover frequency is 1/12 of the switching frequency: 300 kHz/12 = 25 kHz The zero frequency is 1/4 of the crossover frequency: 25 kHz/4 = 6.25 kHz
RCOMP = = f CROSS f CROSS + f ZERO
3
C OUT = 2 ×
Δ I LOAD
f SW × ( Δ V DROOP ) 15 A = 2× 300 × 10 3 × ( 90 mV )
×
2πf CROSSCOUT G M ACS
×
VOUT VREF
3
= 1.11 mF Therefore, an appropriate inductor selection is five 270 μF polymer capacitors with a combined ESR of 3.5 mΩ.
25 × 10 2 × 3.141 × 25 × 10 × 1.11 × 10 − 3 × 3 3 25 × 10 + 6.25 × 10 500 × 10 − 6 × 8.3 1.8 × = 75 kΩ 0.8
C COMP = =
1 2πRCOMP f ZERO
1 2 × 3.14 × 75 ×10 3 × 6.25 ×10 3
= 340 pF
Rev. 0 | Page 29 of 40
ADP1882/ADP1883
Loss Calculations
Duty cycle = 1.8/12 V = 0.15. RON (N2) = 5.4 mΩ. tBODY(LOSS) = 20 ns (body conduction time). VF = 0.84 V (MOSFET forward voltage). CIN = 3.3 nF (MOSFET gate input capacitance). QN1,N2 = 17 nC (total MOSFET gate charge). RGATE = 1.5 Ω (MOSFET gate input resistance).
2 PN1,N2(CL) = D × R N1(ON) + (1 − D ) × R N2(ON) × I LOAD
PSW(LOSS) = fSW × RGATE × CTOTAL × ILOAD × VIN × 2 = 300 × 103 × 1.5 Ω × 3.3 × 10 − 9 × 15 A × 12 × 2 = 534.6 mW
PDR ( LOSS ) = VDR × f SW C upperFET VDR + I BIAS
+
[V
DD
×
(f
[
(
SW
CupperFETVDD +
I BIAS )]
)]
= (5.12 × (300 × 103 × 3.3 × 10−9 × 5.12 + 0.002)) + (5.5 × (300 × 103 × 3.3 × 10−9 × 5.5 + 0.002)) = 77.13 mW PCOUT = (IRMS)2 × ESR = (1.5 A)2 × 1.4 mΩ = 3.15 mW
2 PDCR(LOSS) = DCR × I LOAD = 0.003 × (15 A)2 = 675 mW
[
]
= (0.15 × 0.0054 + 0.85 × 0.0054) × (15 A)2 = 1.215 W
PBODY ( LOSS ) = t BODY ( LOSS ) t SW × I LOAD × VF × 2
PCIN = (IRMS)2 × ESR = (7.5 A)2 × 1 mΩ = 56.25 mW PLOSS = PN1,N2 + PBODY(LOSS) + PSW + PDCR + PDR + PCOUT + PCIN = 1.215 W + 151.2 mW + 534.6 mW + 77.13 mW + 3.15 mW + 675 mW + 56.25 mW = 2.62 W
= 20 ns × 300 × 103 × 15 A × 0.84 × 2 = 151.2 mW
Rev. 0 | Page 30 of 40
ADP1882/ADP1883 EXTERNAL COMPONENT RECOMMENDATIONS
The configurations that are listed in Table 8 are with fCROSS = 1/12 × fSW, fZERO = ¼ × fCROSS, RRES = 100 kΩ, RBOT = 15 kΩ, RON = 5.4 mΩ (BSC042N030MS G), VDD = 5 V, and a maximum load current of 14 A. The ADP1883 models that are listed in Table 8 are the PSM versions of the device. Table 8. External Component Values
Marking Code SAP Model ADP1882ARMZ-0.3-R7/ ADP1883ARMZ-0.3-R7 ADP1882 LGF LGF LGF LGF LGF LGF LGF LGF LGF LGF LGF LGF LGF LGG LGG LGG LGG LGG LGG LGG LGG LGG LGG LGG LGG LGG LGG LGG LGH LGH LGH LGH LGH LGH LGH LGH LGH LGH LGH LGH LGH ADP1883 LGJ LGJ LGJ LGJ LGJ LGJ LGJ LGJ LGJ LGJ LGJ LGJ LGJ LGK LGK LGK LGK LGK LGK LGK LGK LGK LGK LGK LGK LGK LGK LGK LGL LGL LGL LGL LGL LGL LGL LGL LGL LGL LGL LGL LGL VOUT (V) 0.8 1.2 1.8 2.5 3.3 5 7 1.2 1.8 2.5 3.3 5 7 0.8 1.2 1.8 2.5 1.2 1.8 2.5 3.3 5 1.2 1.8 2.5 3.3 5 7 0.8 1.2 1.8 2.5 1.2 1.8 2.5 3.3 5 1.2 1.8 2.5 3.3 VIN (V) 13 13 13 13 13 13 13 16.5 16.5 16.5 16.5 16.5 16.5 5.5 5.5 5.5 5.5 13 13 13 13 13 16.5 16.5 16.5 16.5 16.5 16.5 5.5 5.5 5.5 5.5 13 13 13 13 13 16.5 16.5 16.5 16.5 CIN (μF) 5 × 225 5 × 225 5 × 225 5 × 225 5 × 225 4 × 225 4 × 225 5 × 225 4 × 225 4 × 225 4 × 225 3 × 225 3 × 225 5 × 225 5 × 225 5 × 225 5 × 225 5× 225 5 × 109 5 × 109 5 × 109 5 × 109 3 × 109 4 × 109 4 × 109 4 × 109 4 × 109 4 × 109 5 × 225 5 × 225 3 × 225 3 × 225 4 × 109 4 × 109 4 × 109 5 × 109 4 × 109 4 × 109 4 × 109 4 × 109 4 × 109 COUT (μF) 5 × 5602 4 × 5602 5 × 2703 3 × 2703 3 × 3304 3304 225+ (4 × 476) 4 × 5602 4 × 2703 4 × 2703 3 × 3304 2 × 1507 225+ 4 × 476 4 × 5602 4 × 2703 3 × 2703 3 × 1808 5 × 2703 3 × 3304 3 × 2703 2 × 2703 1507 4 × 2703 2 × 3304 3 × 2703 3304 4 × 476 3 × 476 4 × 2703 2 × 3304 3 × 1808 2703 3 × 3304 3 × 2703 2 x 2703 2703 3 × 476 4 × 2703 3 × 2703 3 × 1808 2703 L1 (μH) 0.47 1.0 1.2 1.53 2.0 3.27 3.44 1.0 1.0 1.67 2.00 3.84 4.44 0.22 0.47 0.47 0.47 0.47 0.72 0.90 1.00 1.76 0.47 0.72 0.90 1.0 2.0 2.0 0.22 0.22 0.22 0.22 0.22 0.47 0.47 0.72 1.0 0.47 0.47 0.72 0.72 RC (kΩ) 38.3 38.3 38.3 38.3 38.3 27.4 27.4 38.3 38.3 38.3 38.3 27.4 27.4 38.3 38.3 38.3 38.3 38.3 38.3 38.3 38.3 27.4 38.3 38.3 38.3 38.3 27.4 27.4 38.3 38.3 38.3 38.3 38.3 38.3 38.3 38.3 27.4 38.3 38.3 38.3 38.3 CCOMP (pF) 911 911 703 703 703 985 985 911 729 729 729 1020 1020 418 401 334 334 501 378 378 378 529 445 401 401 364 510 468 275 275 200 200 286 259 259 259 330 401 321 286 267 CPAR (pF) 91 91 70 70 70 98 98 91 73 73 73 102 102 42 40 33 33 50 38 38 38 53 45 40 40 36 51 47 27 27 20 20 29 26 26 26 33 40 32 29 27 RTOP (kΩ) 0.0 7.5 18.75 31.9 46.9 78.8 116.3 7.5 18.8 31.9 46.9 78.8 116.3 0.0 7.5 18.8 31.9 7.5 18.8 31.9 46.9 78.8 7.5 18.8 31.9 46.9 78.8 116.3 0.0 7.5 18.8 31.9 7.5 18.8 31.9 46.9 78.8 7.5 18.8 31.9 46.9
ADP1882ARMZ-0.6-R7/ ADP1883ARMZ-0.6-R7
ADP1882ARMZ-1.0-R7/ ADP1883ARMZ-1.0-R7
Rev. 0 | Page 31 of 40
ADP1882/ADP1883
Marking Code SAP Model ADP1882 LGH LGH ADP1883 LGL LGL VOUT (V) 5 7 VIN (V) 16.5 16.5 CIN (μF) 3 × 109 3 × 109 COUT (μF) 3 × 476 225 + 476 L1 (μH) 1.4 1.4 RC (kΩ) 27.4 27.4 CCOMP (pF) 330 281 CPAR (pF) 33 28 RTOP (kΩ) 78.8 116.3
1 2
See the Inductor Selection section (see Table 9). 560 μF Panasonic (SP-series) 2 V, 7 mΩ, 3.7 A EEFUE0D561LR (4.3 mm × 7.3 mm × 4.2 mm). 3 270 μF Panasonic (SP-series) 4 V, 7 mΩ, 3.7 A EEFUE0G271LR (4.3 mm × 7.3 mm × 4.2 mm). 4 330 μF Panasonic (SP-series) 4 V, 12 mΩ, 3.3 A EEFUE0G331R (4.3 mm × 7.3 mm × 4.2 mm). 5 22 μF Murata 25 V, X7R, 1210 GRM32ER71E226KE15L (3.2 mm × 2.5 mm × 2.5 mm). 6 47 μF Murata 16 V, X5R, 1210 GRM32ER61C476KE15L (3.2 mm × 2.5 mm × 2.5 mm). 7 150 μF Panasonic (SP-series) 6.3 V, 10 mΩ, 3.5 A EEFUE0J151XR (4.3 mm × 7.3 mm × 4.2 mm). 8 180 μF Panasonic (SP-series) 4 V, 10 mΩ, 3.5 A EEFUE0G181XR (4.3 mm × 7.3 mm × 4.2 mm). 9 10 μF TDK 25 V, X7R, 1210 C3225X7R1E106M.
Table 9. Recommended Inductors
L (μH) 0.12 0.22 0.47 0.72 0.9 1.2 1.0 1.4 2.0 0.8 DCR (mΩ) 0.33 0.33 0.8 1.65 1.6 1.8 3.3 3.2 2.6 ISAT (A) 55 30 50 35 28 25 20 24 22 27.5 Dimension (mm) 10.2 × 7 10.2 × 7 14.2 × 12.8 10.5 × 10.2 13 × 12.8 10.5 × 10.2 10.5 × 10.2 14 × 12.8 13.2 × 12.8 Manufacturer Wurth Electronics Wurth Electronics Wurth Electronics Wurth Electronics Wurth Electronics Wurth Electronics Wurth Electronics Wurth Electronics Wurth Electronics Sumida Model Number 744303012 744303022 744355147 744325072 744355090 744325120 7443552100 744318180 7443551200 CEP125U-0R8
Table 10. Recommended MOSFETs
VGS = 4.5 V Upper-Side MOSFET (Q1/Q2) RON (mΩ) 5.4 10.2 6.0 9 5.4 10.2 6.0 ID (A) 47 53 19 14 47 82 19 VDS (V) 30 30 30 30 30 30 30 CIN (nF) 3.2 1.6 2.4 3.2 1.6 QTOTAL (nC) 20 10 35 25 20 10 35 Package PG-TDSON8 PG-TDSON8 SO-8 SO-8 PG-TDSON8 PG-TDSON8 SO-8 Manufacturer Infineon Infineon Vishay International Rectifier Infineon Infineon Vishay Model Number BSC042N03MS G BSC080N03MS G Si4842DY IRF7811 BSC042N030MS G BSC080N030MS G Si4842DY
Lower-Side MOSFET (Q3/Q4)
Rev. 0 | Page 32 of 40
ADP1882/ADP1883 LAYOUT CONSIDERATIONS
The performance of a dc-to-dc converter depends highly on how the voltage and current paths are configured on the printed circuit board (PCB). Optimizing the placement of sensitive analog and power components are essential to minimize output ripple, maintain tight regulation specifications, and reduce PWM jitter and electromagnetic interference.
HIGH VOLTAGE INPUT VDD = 5V JP1
Figure 83 shows the schematic of a typical ADP1882/ADP1883 used for a high power application. Blue traces denote high current pathways. VIN, PGND, and VOUT traces should be wide and possibly replicated, descending down into the multiple layers. Vias should populate, mainly around the positive and negative terminals of the input and output capacitors, alongside the source of Q1/Q2, the drain of Q3/Q4, and the inductor.
HIGH VOLTAGE INPUT VIN = 12V
CF 70pF
CC 700pF RC 38.1kΩ
ADP1882/ ADP1883
1 2
VIN COMP/EN FB GND VDD
BST 10 SW 9 DRVH 8 PGND 7 DRVL 6
C12 100nF
C3 22µF Q1 Q2
C4 22µF
C5 22µF
C6 22µF
C7 22µF
C8 N/A
R1 18.75kΩ VOUT R2 15kΩ
1.0µH R4 0Ω R6 2Ω C13 1.5nF C20 270µF + C21 270µF
VOUT = 1.8V, 15A + C22 270µF + C23 270µF + C24 270µF +
3 4 5
Q3
Q4
C2 0.1µF
C1 1µF
+ C14 TO C19 N/A
R5 100kΩ MURATA: (HIGH VOLTAGE INPUT CAPACITORS) 22µF, 25V, X7R, 1210 GRM32ER71E226KE15 L PANASONIC: (OUTPUT CAPACITORS) 270µF SP-SERIES, 4V, 7mΩ EEFUE0G271LR INFINEON MOSFETs (NO CONNECTION FOR Q2/Q4: BSC042N03MS G (LOWER SIDE) BSC080N03MS G (UPPER SIDE) WURTH INDUCTORS: 1µH, 3.3mΩ, 20A 7443552100
Figure 83. ADP1882 High Current Evaluation Board Schematic (Blue Traces Indicate High Current Paths)
Rev. 0 | Page 33 of 40
08901-082
ADP1882/ADP1883
SENSITIVE ANALOG COMPONENTS LOCATED FAR FROM THE NOISY POWER SECTION.
SEPARATE ANALOG GROUND PLANE FOR THE ANALOG COMPONENTS (THAT IS, COMPENSATION AND FEEDBACK RESISTORS).
BYPASS POWER CAPACITOR (C1) FOR VDD BIAS DECOUPLING AND HIGH FREQUENCY CAPACITOR (C2) AS CLOSE AS POSSIBLE TO THE IC. INPUT CAPACITORS ARE MOUNTED CLOSE TO DRAIN OF Q1/Q2 AND SOURCE OF Q3/Q4.
OUTPUT CAPACITORS ARE MOUNTED ON THE RIGHTMOST AREA OF THE EVB, WRAPPING BACK AROUND TO THE MAIN POWER GROUND PLANE, WHERE IT MEETS WITH THE NEGATIVE TERMINALS OF THE INPUT CAPACITORS.
Figure 84. Overall Layout of the ADP1882 High Current Evaluation Board
Figure 85. Layer 2 of Evaluation Board
Rev. 0 | Page 34 of 40
08901-084
08901-083
ADP1882/ADP1883
BOTTOM RESISTOR TAP TO THE ANALOG GROUND PLANE.
Figure 86. Layer 3 of Evaluation Board
BOTTOM RESISTOR TAP TO THE ANALOG GROUND PLANE.
PGND SENSE TAP FROM NEGATIVE TERMINALS OF OUTPUT BULK CAPACITORS. THIS TRACK PLACEMENT SHOULD BE DIRECTLY BELOW THE VOUT SENSE LINE FROM FIGURE 84.
08901-086
Figure 87. Layer 4 (Bottom Layer) of Evaluation Board
Rev. 0 | Page 35 of 40
08901-085
VOUT SENSE TAP LINE EXTENDING BACK TO THE TOP RESISTOR IN THE FEEDBACK DIVIDER NETWORK (SEE FIGURE 82). THIS OVERLAPS WITH PGND SENSE TAP LINE EXTENDING BACK TO THE ANALOG PLANE (SEE FIGURE 86, LAYER 4 FOR PGND TAP).
ADP1882/ADP1883
IC SECTION (LEFT SIDE OF EVALUATION BOARD)
A dedicated plane for the analog ground plane (GND) should be separate from the main power ground plane (PGND). With the shortest path possible, connect the analog ground plane to the GND pin (Pin 4). This plane should be on only the top layer of the evaluation board. To avoid crosstalk interference, there should not be any other voltage or current pathway directly below this plane on Layer 2, Layer 3, or Layer 4. Connect the negative terminals of all sensitive analog components to the analog ground plane. Examples of such sensitive analog components include the bottom resistor of the resistor divider, the high frequency bypass capacitor for biasing (0.1 μF), and the compensation network. Mount a 1 μF bypass capacitor directly across VDD (Pin 5) and PGND (Pin 7). In addition, a 0.1 μF should be tied across VDD (Pin 5) and GND (Pin 4). The SW node is near the top of the evaluation board. The SW node should use the least amount of area possible and be kept away from any sensitive analog circuitry and components because this is where most sudden changes in flux density occur. When possible, replicate this pad onto Layer 2 and Layer 3 for thermal relief and eliminate any other voltage and current pathways directly beneath the SW node plane. Populate the SW node plane with vias, mainly around the exposed pad of the inductor terminal and around the perimeter of the source of Q1/Q2 and the drain of Q3/Q4. The output voltage power plane (VOUT) is at the rightmost end of the evaluation board. This plane should be replicated, descending down to multiple layers with vias surrounding the inductor terminal and the positive terminals of the output bulk capacitors. Ensure that the negative terminals of the output capacitors are placed close to the main power ground (PGND), as previously mentioned. All of these points form a tight circle (component geometry permitting) that minimizes the area of flux change as the event switches between D and 1 − D.
POWER SECTION
As shown in Figure 84, an appropriate configuration to localize large current transfer from the high voltage input (VIN) to the output (VOUT), and then back to the power ground, puts the VIN plane on the left, the output plane on the right, and the main power ground plane in between the two. Current transfers from the input capacitors to the output capacitors, through Q1/Q2, during the on state (see Figure 88). The direction of this current (yellow arrow) is maintained as Q1/Q2 turns off and Q3/Q4 turns on. When Q3/Q4 turns on, the current direction continues to be maintained (red arrow) as it circles from the power ground terminal of the bulk capacitor to the output capacitors, through the Q3/Q4. Arranging the power planes in this manner minimizes the area in which changes in flux occur if the current through Q1/Q2 stops abruptly. Sudden changes in flux, usually at the source terminals of Q1/Q2 and the drain terminals of Q3/Q4, cause large dV/dt’s at the SW node.
DIFFERENTIAL SENSING
Because the ADP1882/ADP1883 operate in valley currentmode control, a differential voltage reading is taken across the drain and source of the lower-side MOSFET. The drain of the lower-side MOSFET should be connected as close as possible to Pin 9 (SW) of the IC. Likewise, connect the source as close as possible to Pin 7 (PGND) of the IC. When possible, both of these track lines should be narrow and away from any other active device or voltage/current paths.
SW
PGND
SW VOUT
LAYER 1: SENSE LINE FOR SW (DRAIN OF LOWER MOSFET) LAYER 1: SENSE LINE FOR PGND (SOURCE OF LOWER MOSFET)
08901-088
Figure 89. Drain/Source Tracking Tapping of the Lower-Side MOSFET for CS Amp Differential Sensing (Yellow Sense Line on Layer 2)
VIN
PGND
Figure 88. Primary Current Pathways During the On State of the Upper-Side MOSFET (Left Arrow) and the On State of the Lower-Side MOSFET (Right Arrow)
Differential sensing should also be applied between the outermost output capacitor to the feedback resistor divider (see Figure 86 and Figure 87). Connect the positive terminal of the output capacitor to the top resistor (RT). Connect the negative terminal of the output capacitor to the negative terminal of the bottom resistor, which connects to the analog ground plane, as well. Both of these track lines, as previously mentioned, should be narrow and away from any other active device or voltage/ current paths.
08901-087
Rev. 0 | Page 36 of 40
ADP1882/ADP1883 TYPICAL APPLICATIONS CIRCUITS
DUAL-INPUT, 300 kHz HIGH CURRENT APPLICATIONS CIRCUIT
HIGH VOLTAGE INPUT VDD = 5V JP1 HIGH VOLTAGE INPUT VIN = 12V
CF 70pF
CC 700pF RC 38.1kΩ
ADP1882/ ADP1883
1 2
VIN COMP/EN FB GND VDD
BST 10 SW 9 DRVH 8 PGND 7 DRVL 6
C12 100nF
C3 22µF Q1 Q2
C4 22µF
C5 22µF
C6 22µF
C7 22µF
C8 N/A
R1 18.75kΩ VOUT R2 15kΩ
1.0µH R4 0Ω R6 2Ω C13 1.5nF C20 270µF + C21 270µF
VOUT = 1.8V, 15A + C22 270µF + C23 270µF + C24 270µF +
3 4 5
Q3
Q4
C2 0.1µF
C1 1µF
+ C14 TO C19 N/A
R5 100kΩ MURATA: (HIGH VOLTAGE INPUT CAPACITORS) 22µF, 25V, X7R, 1210 GRM32ER71E226KE15 L PANASONIC: (OUTPUT CAPACITORS) 270µF SP-SERIES, 4V, 7mΩ EEFUE0G271LR INFINEON MOSFETs (NO CONNECTION FOR Q2/Q4: BSC042N03MS G (LOWER SIDE) BSC080N03MS G (UPPER SIDE) WURTH INDUCTORS: 1µH, 3.3mΩ, 20A 7443552100
Figure 90. Applications Circuit for 12 V Input, 1.8 V Output, 15 A, 300 kHz (Q2/Q4 No Connect)
SINGLE-INPUT, 600 kHz APPLICATIONS CIRCUIT
HIGH VOLTAGE INPUT VIN = 5.5V JP1
CF 34pF VOUT
CC 33.4pF RC 38.3kΩ
ADP1882/ ADP1883
1 2
VIN COMP/EN FB GND VDD
BST 10 SW 9 DRVH 8 PGND 7 DRVL 6
C12 100nF
C3 22µF Q1 Q2
C4 22µF
C5 22µF
C6 22µF
C7 22µF
C8 N/A
R1 31.6kΩ R2 15kΩ
3 4 5
0.47µH R4 0Ω R6 2Ω C13 1.5nF C20 180µF + C21 180µF
VOUT = 1.8V, 15A + C22 180µF + C23 N/A + C24 N/A +
Q3
Q4
C2 0.1µF
C1 1µF
+ C14 TO C19 N/A
R5 OPEN MURATA: (HIGH VOLTAGE INPUT CAPACITORS) 22µF, 25V, X7R, 1210 GRM32ER71E226KE15 L PANASONIC: (OUTPUT CAPACITORS) 180µF SP-SERIES, 4V, 10mΩ EEFUE0G181XR INFINEON MOSFETs (NO CONNECTION FOR Q2/Q4: BSC042N03MS G (LOWER SIDE) BSC080N03MS G (UPPER SIDE) WURTH INDUCTORS: 0.47µH, 0.8mΩ, 50A 744355147
Figure 91. Applications Circuit for 5.5 V Input, 2.5 V Output, 15 A, 600 kHz (Q2/Q4 No Connect)
Rev. 0 | Page 37 of 40
08901-090
08901-089
ADP1882/ADP1883
DUAL-INPUT, 300 kHz HIGH CURRENT APPLICATIONS CIRCUIT
HIGH VOLTAGE INPUT VDD = 5V JP1 HIGH VOLTAGE INPUT VIN = 13V
CF 70pF VOUT
CC 1000pF RC 24.9kΩ R1 7.5kΩ R2 15kΩ
ADP1882/ ADP1883
1 2 3 4 5
VIN COMP/EN FB GND VDD
BST 10 SW 9 DRVH 8 PGND 7 DRVL 6
C12 100nF
C3 22µF Q1 Q2
C4 22µF
C5 22µF
C6 22µF
C7 22µF
C8 22µF
0.8µH R6 2Ω C13 1.5nF C20 270µF + C21 270µF
VOUT = 1.8V, 20A + C22 270µF + C23 270µF + C24 270µF +
Q3
Q4
C2 0.1µF
C1 1µF
+ C14 TO C19 N/A
R5 100kΩ MURATA: (HIGH VOLTAGE INPUT CAPACITORS) 22µF, 25V, X7R, 1210 GRM32ER71E226KE15 L PANASONIC: (OUTPUT CAPACITORS) 270µF SP-SERIES, 4V, 7mΩ EEFUE0G271LR INFINEON MOSFETs (NO CONNECTION FOR Q2/Q4: BSC042N03MS G (LOWER SIDE) BSC080N03MS G (UPPER SIDE) WURTH INDUCTORS: 0.8µH, 27.5mΩ, SUMIDA CEP125U-0R8
Figure 92. Applications Circuit for 13 V Input, 1.8 V Output, 20 A, 300 kHz (Q2/Q4 No Connect)
Rev. 0 | Page 38 of 40
08901-091
ADP1882/ADP1883 OUTLINE DIMENSIONS
3.10 3.00 2.90
10
6
3.10 3.00 2.90 PIN 1 IDENTIFIER
1
5.15 4.90 4.65
5
0.50 BSC 0.95 0.85 0.75 0.15 0.05 COPLANARITY 0.10 0.30 0.15 15° MAX 1.10 MAX 0.70 0.55 0.40
091709-A
6° 0°
0.23 0.13
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 93. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 ADP1882ARMZ-0.3-R7 ADP1882ARMZ-0.6-R7 ADP1882ARMZ-1.0-R7 ADP1882ARMZ-0.3-EVALZ ADP1882ARMZ-0.6-EVALZ ADP1882ARMZ-1.0-EVALZ ADP1883ARMZ-0.3-R7 ADP1883ARMZ-0.6-R7 ADP1883ARMZ-1.0-R7 ADP1883ARMZ-0.3-EVALZ ADP1883ARMZ-0.6-EVALZ ADP1883ARMZ-1.0-EVALZ
1
Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C
−40°C to +125°C −40°C to +125°C −40°C to +125°C
Package Description 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] Forced PWM, 300 kHz Evaluation Board Forced PWM, 600 kHz Evaluation Board Forced PWM, 1.0 MHz Evaluation Board 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] Power Saving Mode, 300 kHz Evaluation Board Power Saving Mode, 600 kHz Evaluation Board Power Saving Mode, 1.0 MHz Evaluation Board
Package Option RM-10 RM-10 RM-10
Branding LGF LGG LGH
RM-10 RM-10 RM-10
LGJ LGK LGL
Z = RoHS Compliant Part.
Rev. 0 | Page 39 of 40
ADP1882/ADP1883 NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08901-0-4/10(0)
Rev. 0 | Page 40 of 40
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