FEATURES
Ultralow on resistance (RDSON)
50 mΩ @ 3.6 V
55 mΩ @ 2.5 V
65 mΩ @ 1.8 V
100 mΩ @ 1.2 V
Input voltage range: 1.1 V to 3.6 V
1.1 A maximum continuous operating current
Low enable control logic threshold can be operated from
1.2 V to 3.3 V
Low 1 μA (typical) ground current @ 1.8 V
Low 4 μA (maximum) reverse current @ 3.6 V
Ultralow shutdown current: 0.7 μA (typical) @ 1.8 V
Reverse current blocking
Tiny 4-ball wafer level chip scale package (WLCSP)
1.0 mm × 1.0 mm, 0.5 mm pitch
Tiny 6-lead lead frame chip scale package (LFCSP)
2.0 mm × 2.0 mm × 0.55 mm, 0.65 mm pitch
APPLICATIONS
Mobile phones
Digital cameras and audio devices
GPS devices
Personal media players
Portable and battery-powered equipment
TYPICAL APPLICATIONS CIRCUIT
REVERSE
POLARITY
PROTECTION
ADP195
VIN
+
–
VOUT
GND
ON
EN OFF
LEVEL SHIFT
AND SLEW
RATE CONTROL
LOAD
08679-001
Data Sheet
Logic Controlled, High-Side Power Switch
with Reverse Current Blocking
ADP195
Figure 1.
GENERAL DESCRIPTION
The ADP195 is a high-side load switch designed for operation
between 1.1 V to 3.6 V and protected against reverse current
flow from output to input. This load switch provides power
domain isolation helping extended power domain isolation. The
device contains a low on-resistance, P-channel MOSFET that
supports over 1.1 A of continuous current and minimizes power
loss. The low 1 μA of quiescent current and ultralow shutdown
current make the ADP195 ideal for battery-operated portable
equipment. The built-in level shifter for enable logic makes the
ADP195 compatible with many processors and GPIO
controllers.
In addition to operating performance, the ADP195 occupies
minimal printed circuit board (PCB) space with an area of less
than 1.0 mm2 and a height of 0.60 mm.
It is available in an ultrasmall 1 mm × 1 mm, 4-ball, 0.5 mm
pitch WLCSP. A 6-lead 2 mm × 2 mm × 0.55 mm, 0.65 mm
pitch LFCSP is also available.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.
ADP195
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configurations and Function Descriptions ............................5
Applications....................................................................................... 1
Typical Performance Characteristics ..............................................6
Typical Applications Circuit............................................................ 1
Theory of Operation .........................................................................9
General Description ......................................................................... 1
Applications Information .............................................................. 10
Revision History ............................................................................... 2
Ground Current.......................................................................... 10
Specifications..................................................................................... 3
Enable Feature ............................................................................ 10
Timing Diagram ........................................................................... 3
Timing ......................................................................................... 11
Absolute Maximum Ratings............................................................ 4
Outline Dimensions ....................................................................... 12
Thermal Data ................................................................................ 4
Ordering Guide .......................................................................... 12
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
REVISION HISTORY
1/12—Rev. B to Rev. C
Changes to General Description Section ...................................... 1
Changes to Table 2............................................................................ 4
Updated Outline Dimensions ....................................................... 12
2/11—Rev. A to Rev. B
Added 6-Lead LFCSP.........................................................Universal
Changes to Features, Applications, and General Description
Sections .............................................................................................. 1
Added VIN to VOUT Resistance, LFCSP Parameter, Table 1.......... 3
Changes to Table 2 and Table 3....................................................... 4
Added Figure 4; Renumbered Sequentially .................................. 5
Added Table 5; Renumbered Sequentially .................................... 5
Added Figure 6, Figure 8, and Figure 10 ....................................... 6
Changes to Theory of Operation Section...................................... 9
Updated Outline Dimensions ....................................................... 12
Changes to Ordering Guide .......................................................... 12
7/10—Rev. 0 to Rev. A
Changes to Features and Applications Sections ............................1
Changed 10 μA Ground Current to 1 μA Ground Current in
General Description Section............................................................1
Changes to Table 2 and Thermal Resistance Section ...................4
Added Thermal Data Section .........................................................4
3/10—Revision 0: Initial Version
Rev. C | Page 2 of 12
Data Sheet
ADP195
SPECIFICATIONS
VIN = 1.8 V, VEN = VIN, IOUT = 200 mA, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
INPUT VOLTAGE RANGE
EN INPUT
EN Input Threshold
Symbol
VIN
Conditions
TJ = −40°C to +85°C
Min
1.1
VIH
0.29
0.45
EN Input Pull-Down Current
VIN Shutdown Current
REVERSE BLOCKING
VOUT Current
Hysteresis
CURRENT
Ground Current
IEN
1.1 V ≤ VIN < 1.8 V, TJ = −40°C to +85°C
1.8 V ≤ VIN ≤ 3.6 V, TJ = −40°C to +85°C
VIN = 1.8 V
VEN = 0 V, VIN = 0 V, VOUT = 3.6 V
Off State Current
VIN to VOUT RESISTANCE
WLCSP
VEN = 0 V, VIN = 0 V, VOUT = 3.6 V
|VIN − VOUT|
IGND
VOUT = 0, includes VEN pull-down and reverse blocking
bias current, VIN = 3.6 V, TJ = −40°C to +85°C
VOUT = 0, includes VEN pull-down and reverse blocking
bias current, VIN = 1.8 V
VEN = GND (includes reverse blocking bias current), VOUT = 0 V
VEN = GND, TJ = −40°C to +85°C, VOUT = 0 V
IOFF
Max
3.6
Unit
V
1.0
1.2
V
500
−10
nA
nA
4
75
μA
mV
10
1
μA
μA
0.7
5
μA
μA
RDSON
LFCSP
VOUT TURN-ON DELAY TIME
Turn-On Delay Time
Typ
tON_DLY
VIN = 3.6 V, ILOAD = 200 mA, VEN = 3.6 V
VIN = 2.5 V, ILOAD = 200 mA, VEN = 2.5 V
VIN = 1.8 V, ILOAD = 200 mA, VEN = 1.8 V
VIN = 1.8 V, ILOAD = 200 mA, VEN = 1.8 V, TJ = −40°C to +85°C
VIN = 1.5 V, ILOAD = 200 mA, VEN = 1.5 V
VIN = 1.2 V, ILOAD = 200 mA, VEN = 1.2 V
VIN = 3.6 V, ILOAD = 200 mA, VEN = 3.6 V
VIN = 2.5 V, ILOAD = 200 mA, VEN = 2.5 V
VIN = 1.8 V, ILOAD = 200 mA, VEN = 1.8 V
VIN = 1.8 V, ILOAD = 200 mA, VEN = 1.8 V, TJ = −40°C to +85°C
VIN = 1.5 V, ILOAD = 200 mA, VEN = 1.5 V
VIN = 1.2 V, ILOAD = 200 mA, VEN = 1.2 V
0.050
0.055
0.065
0.097
0.125
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
VIN = 1.8 V, ILOAD = 200 mA, VEN = 1.8 V, CLOAD = 1 μF
VIN = 3.6 V, ILOAD = 200 mA, VEN = 3.6 V, CLOAD = 1 μF
5
1.5
μs
μs
TIMING DIAGRAM
VEN
TURN-ON
DELAY
90%
TURN-OFF
DELAY
VOUT
TURN-ON
RISE
TURN-OFF
FALL
Figure 2. Timing Diagram
Rev. C | Page 3 of 12
08679-002
10%
0.095
0.075
0.100
0.070
0.078
0.090
0.130
ADP195
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VIN, VIN1, VIN2 to GND
VOUT, VOUT1, VOUT2 to GND
EN to GND
Continuous Drain Current
TA = 25°C
TA = 85°C
Continuous Diode Current
Storage Temperature Range
Operating Junction Temperature Range
Operating Ambient Temperature Range
Soldering Conditions
Rating
−0.3 V to +4.0 V
−0.3 V to +4.0 V
−0.3 V to +4.0 V
±2 A
±1.1 A
−50 mA
−65°C to +150°C
−40°C to +125°C
−40°C to +85°C
JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP195 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that TJ is within the specified temperature
limits. In applications with high power dissipation and poor
PCB thermal resistance, the maximum ambient temperature
may need to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (TJ) of
the device is dependent on the ambient temperature (TA), the
power dissipation of the device (PD), and the junction-to-ambient
thermal resistance of the package (θJA).
Maximum junction temperature (TJ) is calculated from the
ambient temperature (TA) and power dissipation (PD) using the
formula
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending on
PCB material, layout, and environmental conditions. The specified values of θJA are based on a 4-layer, 4 inch × 3 inch PCB.
See JESD51-7 and JESD51-9 for detailed information regarding
board construction. For additional information, see the AN-617
application note, MicroCSPTM Wafer Level Chip Scale Package.
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a 4-layer board. The JESD51-12 document,
Guidelines for Reporting and Using Electronic Package Thermal
Information, states that thermal characterization parameters are
not the same as thermal resistances. ΨJB measures the component
power flowing through multiple thermal paths rather than through
a single path, as in thermal resistance (θJB). Therefore, ΨJB thermal
paths include convection from the top of the package as well as
radiation from the package, factors that make ΨJB more useful
in real-world applications. Maximum junction temperature (TJ)
is calculated from the board temperature (TB) and the power
dissipation (PD) using the formula
TJ = TB + (PD × ΨJB)
See JESD51-8, JESD51-9, and JESD51-12 for more detailed
information about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
4-Ball, 0.5 mm Pitch WLCSP
6-Lead, 2 mm × 2 mm LFCSP
ESD CAUTION
TJ = TA + (PD × θJA)
Rev. C | Page 4 of 12
θJA
260
72.1
ΨJB
58.4
24.0
Unit
°C/W
°C/W
Data Sheet
ADP195
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
2
VIN
VOUT
VOUT1 1
A
VOUT2 2
TOP VIEW
(Not to Scale)
EN
GND
GND 3
08679-003
B
6 VIN1
ADP195
TOP VIEW
(Not to Scale)
5 VIN2
4 EN
08679-104
1
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO GND.
Figure 3. 4-Ball WLCSP Pin Configuration
Figure 4. 6-Lead LFCSP Pin Configuration
Table 4. WLCSP Pin Function Descriptions
Pin No.
A1
A2
B1
B2
Mnemonic
VIN
VOUT
EN
GND
Description
Input Voltage.
Output Voltage.
Enable Input. Drive EN high to turn on the switch and drive EN low to turn off the switch.
Ground.
Table 5. LFCSP Pin Function Descriptions
Pin No.
1
2
3
4
5
6
EP
Mnemonic
VOUT1
VOUT2
GND
EN
VIN2
VIN1
EP
Description
Output Voltage. Connect VOUT1 and VOUT2 together.
Output Voltage. Connect VOUT1 and VOUT2 together.
Ground.
Enable Input. Drive EN high to turn on the switch and drive EN low to turn off the switch.
Input Voltage. Connect VIN1 and VIN2 together.
Input Voltage. Connect VIN1 and VIN2 together.
The exposed pad must be connected to ground.
Rev. C | Page 5 of 12
ADP195
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 1.8 V, VEN = VIN, CIN = COUT = 1 μF, TA = 25°C, unless otherwise noted.
0.10
0.16
IOUT = 10mA
IOUT = 100mA
IOUT = 200mA
IOUT = 500mA
IOUT = 1000mA
0.14
0.12
RDSON (Ω)
RDSON (Ω)
0.08
0.06
0.04
0.10
0.08
IOUT = 10mA
IOUT = 50mA
IOUT = 100mA
IOUT = 200mA
IOUT = 500mA
IOUT = 1000mA
0.06
0.04
0.02
–40
0
25
85
0
1.2
08679-004
0
0.02
125
TEMPERATURE (°C)
0.12
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VIN = 1.2
VIN = 1.6
VIN = 1.8
VIN = 2.2
VIN = 2.4
VIN = 2.6
VIN = 3.0
VIN = 3.6
0.11
0.10
0.10
0.09
VOLTAGE DROP (V)
0.08
RDSON (Ω)
1.8
Figure 8. RDSON vs. Input Voltage (VIN), LFCSP
0.12
0.04
1.6
VIN (V)
Figure 5. RDSON vs. Temperature, WLCSP
0.06
1.4
08679-108
0.12
IOUT = 10mA
IOUT = 50mA
IOUT = 100mA
IOUT = 200mA
IOUT = 500mA
IOUT = 1000mA
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.02
–5°C
25°C
85°C
0
08679-106
–40°C
125°C
TEMPERATURE (°C)
0
0.16
500
600
700
800
900
1000
0.16
IOUT = 10mA
IOUT = 100mA
IOUT = 200mA
IOUT = 500mA
IOUT = 1000mA
0.14
VIN = 1.2
VIN = 1.6
VIN = 1.8
VIN = 2.0
VIN = 2.4
VIN = 2.8
VIN = 3.0
VIN = 3.2
VIN = 3.4
VIN = 3.6
0.12
VOLTAGE DROP (V)
0.12
0.10
0.08
0.06
0.10
0.08
0.06
0.04
0.04
0.02
0.02
1.6
2.0
2.4
2.8
3.2
VIN (V)
3.6
08679-005
RDSON (Ω)
400
Figure 9. Voltage Drop vs. Load Current, WLCSP
0.14
0
1.2
300
0
0
200
400
600
800
LOAD (mA)
Figure 10. Voltage Drop vs. Load Current, LFCSP
Figure 7. RDSON vs. Input Voltage (VIN), WLCSP
Rev. C | Page 6 of 12
1000
08679-110
0.18
200
LOAD (mA)
Figure 6. RDSON vs. Temperature, LFCSP
0.20
100
08679-006
0.01
0
Data Sheet
ADP195
VEN
VEN
VOUT
1
1
VOUT
2
2
LOAD CURRENT
LOAD CURRENT
CH2 2V
BW
M4µs
T 10%
A CH1
2.32V
08679-007
CH1 2V BW
CH3 1A Ω BW
CH1 2V BW
CH2 1V
CH3 100mA Ω BW
Figure 11. Typical Rise Time and Inrush Current,
VIN = 3.6 V, No Load
6
5
GROUND CURRENT (µA)
VOUT
2
LOAD CURRENT
A CH1
2.32V
IOUT = 10mA
IOUT = 100mA
IOUT = 200mA
IOUT = 300mA
IOUT = 500mA
4
3
2
BW
M4µs
T 10%
A CH1
2.32V
0
20
16
GROUND CURRENT (µA)
1
VOUT
2
85
125
IOUT = 10mA
IOUT = 100mA
IOUT = 200mA
IOUT = 500mA
IOUT = 1000mA
12
8
4
LOAD CURRENT
A CH1
2.32V
0
1.2
08679-010
M10µs
T 10%
25
Figure 15. Ground Current vs. Temperature
VEN
BW
0
TEMPERATURE (°C)
Figure 12. Typical Rise Time and Inrush Current,
VIN = 3.6 V, Load = 200 mA
CH1 2V BW
CH2 1V
CH3 100mA Ω BW
–40
1.6
2.0
2.4
2.8
3.2
VIN (V)
Figure 13. Typical Rise Time and Inrush Current,
VIN = 1.2 V, No Load
Figure 16. Ground Current vs. Input Voltage (VIN)
Rev. C | Page 7 of 12
3.6
08679-012
CH2 2V
08679-009
CH1 2V BW
CH3 1A Ω BW
08679-008
1
3
3
M10µs
T 10%
Figure 14. Typical Rise Time and Inrush Current,
VIN = 1.2 V, Load = 200 mA
VEN
1
BW
08679-011
3
3
ADP195
SHUTDOWN CURRENT (µA)
4
3
9
VIN = 1.2V
VIN = 1.4V
VIN = 2.0V
VIN = 2.4V
VIN = 2.8V
VIN = 3.2V
VIN = 3.4V
VIN = 3.6V
8
SHUTDOWN CURRENT (µA)
5
Data Sheet
2
1
7
6
5
VIN = 1.2V
VIN = 1.4V
VIN = 1.6V
VIN = 1.8V
VIN = 2.0V
VIN = 2.2V
VIN = 2.6V
VIN = 3.0V
VIN = 3.2V
VIN = 3.6V
4
3
2
0
–15
10
35
60
85
110
TEMPERATURE (°C)
0
–40
08679-013
2.0
4.0
VIN = 1.2V
VIN = 1.4V
VIN = 2.0V
VIN = 2.4V
VIN = 2.8V
VIN = 3.2V
VIN = 3.4V
VIN = 3.6V
1.5
1.0
0.5
85
110
VIN = 2.8V
VIN = 3.2V
VIN = 3.4V
VIN = 3.6V
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–40
60
VIN = 1.2V
VIN = 1.4V
VIN = 2.0V
VIN = 2.4V
3.5
SHUTDOWN CURRENT (µA)
2.5
35
Figure 19. Reverse Output Shutdown Current vs. Temperature
–15
10
35
60
85
110
TEMPERATURE (°C)
08679-014
SHUTDOWN CURRENT (µA)
3.0
10
TEMPERATURE (°C)
Figure 17. Shutdown Current vs. Temperature
3.5
–15
0
–40
–15
10
35
60
85
110
TEMPERATURE (°C)
Figure 20. Reverse Shutdown Current vs. Temperature
Figure 18. Reverse Input Shutdown Current vs. Temperature
Rev. C | Page 8 of 12
08679-016
–1
–40
08679-015
1
Data Sheet
ADP195
THEORY OF OPERATION
ADP195
quiescent current device with a nominal 4 MΩ pull-down
resistor on its enable pin (EN).
REVERSE
POLARITY
PROTECTION
VIN
VOUT
The reverse current protection circuitry prevents current flow
backward through the ADP195 when the output voltage is greater
than the input voltage. A comparator senses the difference
between the input and output voltages. When the difference
between the input voltage and output voltage exceeds 75 mV,
the body of the pFET is switched to VOUT and is turned off or
opened; that is, the gate is connected to VOUT.
GND
LEVEL SHIFT
AND SLEW
RATE CONTROL
08679-025
EN
Figure 21. Functional Block Diagram
The ADP195 is a high-side PMOS load switch. It is designed for
supply operation between 1.1 V to 3.6 V. The PMOS load switch
is designed for low on resistance, 65 mΩ at VIN = 1.8 V and
supports greater than 1 A of continuous current. It is a low
The packaging is a space-saving 1.0 mm × 1.0 mm, 4-ball WLCSP.
The ADP195 is also available in a 2 mm × 2 mm × 0.55 mm,
0.65 mm pitch LFCSP.
Rev. C | Page 9 of 12
ADP195
Data Sheet
APPLICATIONS INFORMATION
GROUND CURRENT
ENABLE FEATURE
The major source for ground current in the ADP195 is an internal
4 MΩ pull-down on the enable pin. Figure 22 shows the typical
ground current when VEN = VIN and varies from 1.2 V to 3.6 V.
The ADP195 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. As shown in Figure 24,
when a rising voltage on VEN crosses the active threshold, VOUT
turns on. When a falling voltage on VEN crosses the inactive
threshold, VOUT turns off.
10
VIN = 1.2V
VIN = 1.6V
VIN = 2.0V
VIN = 2.4V
2.0
1.8
1.6
6
1.4
VOUT (V)
GROUND CURRENT (µA)
8
VIN = 2.8V
VIN = 3.2V
VIN = 3.4V
VIN = 3.6V
4
2
1.2
1.0
0.8
0.6
50
100
150
200
250
300
350
400
450
500
LOAD (mA)
0.2
0
Figure 22. Ground Current vs. Load Current
As shown in Figure 23, an increase in quiescent current can occur
when VEN ≠ VIN. This is caused by the CMOS logic nature of the
level shift circuitry as it translates an VEN signal ≥ 1.2 V to a
logic high. This increase is a function of the VIN − VEN delta.
16
VIN = 1.2V
VIN = 1.5V
VIN = 1.8V
VIN = 2.5V
VIN = 3.6V
14
12
0.1
0.2
0.3
0.4
0.5
0.6 0.7
VEN (V)
0.8
0.9
1.0
1.1
1.2
Figure 24. Typical EN Operation
As shown in Figure 24, the EN pin has hysteresis built in. This
prevents on/off oscillations that can occur due to noise on the
EN pin as it passes through the threshold points.
The EN pin active/inactive thresholds derive from the VIN voltage;
therefore, these thresholds vary with the changing input voltage.
Figure 25 shows the typical EN active/inactive thresholds when
the input voltage varies from 1.2 V to 3.6 V.
10
1.15
6
4
2
0.65
EN INACTIVE
0.55
VIN (V)
Figure 25. Typical EN Thresholds vs. Input Voltage (VIN)
Rev. C | Page 10 of 12
3.60
08679-020
3.45
3.30
3.15
3.00
0.35
2.85
0.45
2.70
Figure 23. Typical Ground Current when VEN ≠ VIN
3.6
2.55
3.2
2.25
2.8
2.40
2.4
2.10
2.0
VEN (V)
1.95
1.6
1.80
1.2
0.75
1.65
0.8
EN ACTIVE
0.85
1.50
0.4
0.95
1.35
0
1.05
1.20
0
TYPICAL EN THRESHOLDS (V)
8
08679-018
IGND (µA)
0
08679-019
0
08679-017
0.4
0
Data Sheet
ADP195
TIMING
VEN
Turn-on delay is defined as the delta between the time that VEN
reaches >1.2 V until VOUT rises to ~10% of its final value. The
ADP195 includes circuitry to have typical 5 μs turn-on delay at
3.6 V VIN to limit the VIN inrush current. As shown in Figure 26,
the turn-on delay is dependent on the input voltage.
5.0
2
VEN
VIN = 1.2V
VIN = 1.8V
VIN = 2.5V
VIN = 3.6V
4.5
4.0
LOAD CURRENT
3
3.5
CH1 2V BW
CH2 1V
CH3 200mA Ω BW
2.5
2.0
A CH1
2.32V
Figure 28. Typical Rise Time and Inrush Current,
CLOAD = 1 μF, VIN = 1.8 V, Load = 200 mA
1.5
The turn-off time is defined as the delta between the time from
90% to 10% of VOUT reaching its final value. It is also dependent on
the RC time constant.
1.0
0
5
10
15
20
25
30
35
40
TIME (µs)
08679-021
0.5
0
M4µs
T 10%
08679-023
3.0
5.0
VEN
VOUT AT 200mA
VOUT AT 100mA
4.5
Figure 26. Typical Turn-On Delay Time with Varying Input Voltage
4.0
3.5
VOLTAGE (V)
The rise time is defined as the delta between the time from
10% to 90% of VOUT reaching its final value. It is dependent on
the RC time constant where C = load capacitance (CLOAD) and
R = RDSON||RLOAD. Because RDSON is usually smaller than RLOAD,
an adequate approximation for RC is RDSON × CLOAD. An input
or load capacitor is not needed for the ADP195; however, capacitors
can be used to suppress noise on the board. If significant load
capacitance is connected, inrush current is a concern.
3.0
2.5
2.0
1.5
1.0
0.5
0
VEN
0
20
40
60
TIME (µs)
VOUT
1
Figure 29. Typical Turn-Off Time
2
LOAD CURRENT
CH1 2V BW
CH2 1V
CH3 200mA Ω BW
BW
M4µs
T 10%
A CH1
2.32V
08679-022
3
Figure 27. Typical Rise Time and Inrush Current,
CLOAD = 1 μF, VIN = 1.8 V, No Load
Rev. C | Page 11 of 12
80
100
08679-024
VOLTAGE (V)
VOUT
1
ADP195
Data Sheet
OUTLINE DIMENSIONS
0.640
0.595
0.550
0.370
0.355
0.340
0.990
0.950
0.910
SEATING
PLANE
1
A
0.340
0.320
0.300
1.065
1.025
0.985
BALL A1
IDENTIFIER
2
B
0.50
REF
BOTTOM VIEW
0.270
0.240
0.210
(BALL SIDE UP)
0.05 NOM
COPLANARITY
110309-A
TOP VIEW
(BALL SIDE DOWN)
Figure 30. 4-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-4-4)
Dimensions shown in millimeters
1.70
1.60
1.50
2.00
BSC SQ
0.65 BSC
6
4
1.10
1.00
0.90
EXPOSED
PAD
0.425
0.350
0.275
3
TOP VIEW
0.60
0.55
0.50
SEATING
PLANE
0.05 MAX
0.02 NOM
0.35
0.30
0.25
1
BOTTOM VIEW
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.20 REF
07-11-2011-B
PIN 1 INDEX
AREA
0.175 REF
Figure 31. 6-Lead Lead Frame Chip Scale Package [LFCSP_UD]
2.00 x 2.00 mm Body, Ultra Thin, Dual Lead
(CP-6-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADP195ACBZ-R7
ADP195ACPZ-R7
ADP195-EVALZ
ADP195-CP-EVALZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
4-Ball Wafer Level Chip Scale Package [WLCSP]
6-Lead Lead Frame Chip Scale Package [LFCSP_UD]
Evaluation Board
Evaluation Board
Z = RoHS Compliant Part.
©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08679-0-1/12(C)
Rev. C | Page 12 of 12
Package Option
CB-4-4
CP-6-3
Branding
5Y
LJ6
工商网监
湘ICP备2023018690号
