Configurable, Dual 3 A/Single 6 A,
Synchronous, Step-Down DC-to-DC Regulator
ADP2116
Data Sheet
FEATURES
TYPICAL APPLICATION CIRCUIT
VIN = 5V
10Ω
1µF
100kΩ
22µF
VDD
EN2
VIN4
VIN5
VIN6
PGOOD2
PGOOD2
VOUT2 = 1.2V, 3A
47µF
2.2µH
SW3
SW4
100µF
SW1
10nF
VOUT1 = 2.5V, 3A
47µF
PGND1
22µF
PGND2
FB1
FB2
V2SET
V1SET
SYNC/CLKOUT COMP1
COMP2
SS1
SS2
SCFG
GND
30kΩ
820pF
PGOOD1
3.3µH
ADP2116 SW2
PGND4
SYNC
22µF
VIN2
VIN3
PGOOD1
PGND3
4.7kΩ
EN1
VIN1
OPCFG
100kΩ
FREQ
27kΩ
10nF
30kΩ
820pF
8.2kΩ
08436-001
Configurable 3 A/3 A or 3 A/2 A dual-output load
combinations or 6 A combined single-output load
High efficiency: up to 95%
Input voltage, VIN: 2.75 V to 5.5 V
Selectable fixed output voltage of 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V,
or 3.3 V, or adjustable output voltage to 0.6 V minimum
±1.5% accurate reference voltage
Selectable switching frequency of 300 kHz, 600 kHz, 1.2 MHz,
or synchronized from 200 kHz to 2 MHz
Optimized gate slew rate for reduced EMI
External synchronization input or internal clock output
Dual-phase, 180° phase-shifted PWM channels
Current mode for fast transient response
Pulse skip mode with light loads or forced PWM operation
Input undervoltage lockout (UVLO)
Independent enable inputs and power-good outputs
Overcurrent and thermal overload protection
Programmable soft start
32-lead, 5 mm × 5 mm LFCSP package
Supported by ADIsimPower™ design tool
fSW = 600kHz
Figure 1.
APPLICATIONS
The ADP2116 is a versatile, synchronous, step-down switching
regulator that satisfies a wide range of customer point-of-load
requirements. The two PWM channels can be configured to deliver
independent outputs at 3 A and 3 A (or at 3 A and 2 A) or can be
configured as a single interleaved output capable of delivering 6 A.
The two PWM channels are 180° phase shifted to reduce input
ripple current and input capacitance.
The ADP2116 provides high efficiency and can operate at
switching frequencies of up to 2 MHz. At light loads, the ADP2116
can be set to operate in pulse skip mode for higher efficiency or
in forced PWM mode for noise sensitive applications.
The ADP2116 is designed with an optimized slew rate to reduce
EMI emissions, allowing the device to power sensitive, high performance signal chain circuits. The switching frequency can be set
to 300 kHz, 600 kHz, or 1.2 MHz, or it can be synchronized to an
external clock that minimizes the system noise. The bidirectional
The ADP2116 input voltage range is from 2.75 V to 5.5 V and can
convert to a fixed output of 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V
that can be set independently for each channel using external
resistors. If a resistor divider is used, the output voltage can be
set as low as 0.6 V. The ADP2116 operates over the −40°C to
+125°C junction temperature range.
100
VIN = 5.0V; VOUT = 2.5V
95
VIN = 5.0V; VOUT = 3.3V
90
85
80
75
70
VIN = 3.3V; VOUT = 1.2V
65
fSW = 600kHz
60
10
100
1k
LOAD CURRENT (mA)
10k
08436-002
GENERAL DESCRIPTION
synchronization pin is also configurable as a 90° out-of-phase
output clock, providing the possibility for a stackable multiphase
power solution.
EFFICIENCY (%)
Point-of-load regulation
Telecommunications and networking systems
Consumer electronics
Industrial and instrumentation
Medical
Figure 2. Typical Efficiency vs. Load Current
Rev. B
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ADP2116
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Thermal Overload Protection .................................................. 22
Applications ....................................................................................... 1
Maximum Duty Cycle Operation ............................................ 22
General Description ......................................................................... 1
Synchronization .......................................................................... 22
Typical Application Circuit ............................................................. 1
Converter Configuration ............................................................... 23
Revision History ............................................................................... 2
Selecting the Output Voltage .................................................... 23
Specifications..................................................................................... 3
Setting the Oscillator Frequency .............................................. 24
Absolute Maximum Ratings............................................................ 5
Synchronization and CLKOUT ................................................ 24
ESD Caution .................................................................................. 5
Operation Mode Configuration ............................................... 25
Pin Configuration and Function Descriptions ............................. 6
External Components Selection ................................................... 26
Typical Performance Characteristics ............................................. 8
ADIsimPower Design Tool ....................................................... 26
Line and Load Regulation ........................................................... 9
Input Capacitor Selection .......................................................... 26
Supply Current ............................................................................ 13
VDD RC Filter ............................................................................ 26
Load Transient Response........................................................... 14
Inductor Selection ...................................................................... 26
Basic Functionality ..................................................................... 15
Output Capacitor Selection....................................................... 27
Bode Plots .................................................................................... 18
Control Loop Compensation .................................................... 28
Simplified Block Diagram ............................................................. 19
Design Example .............................................................................. 29
Theory of Operation ...................................................................... 20
Channel 1 Configuration and Components Selection .......... 29
Control Architecture .................................................................. 20
Channel 2 Configuration and Components Selection .......... 30
Undervoltage Lockout (UVLO) ............................................... 20
System Configuration ................................................................ 31
Enable/Disable Control ............................................................. 20
Application Circuits ....................................................................... 32
Soft Start ...................................................................................... 20
Power Dissipation and Thermal Considerations ....................... 34
Power Good................................................................................. 21
Circuit Board Layout Recommendations ................................... 35
Pulse Skip Mode ......................................................................... 21
Outline Dimensions ....................................................................... 36
Hiccup Mode Current Limit ..................................................... 22
Ordering Guide .......................................................................... 36
REVISION HISTORY
3/16—Rev. A to Rev. B
Changed CP-32-2 to CP-32-7 ...................................... Throughout
Changes to Figure 3 .......................................................................... 6
Updated Outline Dimensions ....................................................... 36
Changes to Ordering Guide .......................................................... 36
6/12—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Added ADIsimPower Design Tool Section ................................. 26
Updated Outline Dimensions ....................................................... 36
10/09—Revision 0: Initial Version
Rev. B | Page 2 of 36
Data Sheet
ADP2116
SPECIFICATIONS
If unspecified, VDD = VINx = EN1 = EN2 = 5.0 V. The minimum and maximum specifications are valid for TJ = −40°C to +125°C, unless
otherwise specified. Typical values are at TJ = 25°C. All limits at temperature extremes are guaranteed via correlation using standard
statistical quality control (SQC).
Table 1.
Parameter
POWER SUPPLY
VDD Bias Voltage
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
Quiescent Current
Symbol
VDD
UVLO
IDD,CH1
IDD,CH2
IDD,CH1 + CH2
Shutdown Current
ERROR INTEGRATOR (OPERATIONAL
TRANSCONDUCTANCE AMPLIFIER)
FB1, FB2 Input Bias Current
Transconductance
COMPx VOLTAGE RANGE
COMPx Zero-Current Threshold
COMPx Clamp High Voltage
COMPx Clamp Low Voltage
OUTPUT CHARACTERISTICS
Output Voltage Accuracy
IDD,SD
IFB
Conditions
Min
2.75
VDD rising
VDD falling
2.35
EN1 = VDD = 5 V, EN2 = GND, VFB1 = VDD,
OPCFG = GND
EN2 = VDD = 5 V, EN1 = GND, VFB2 = VDD,
OPCFG = GND
EN1 = EN2 = VDD = 5 V, VFB2 = VFB1 = VDD,
OPCFG = GND
EN1 = EN2 = GND, VDD = VINx = 2.75 V to 5.5 V,
TJ = −40°C to +115°C
Adjustable output, VFBx = 0.6 V,
V1SET, V2SET = VDD or via 82 kΩ to GND
Fixed output, VFBx = 1.2 V,
V1SET, V2SET via 4.7 kΩ to GND
gm
Guaranteed by design
VDD = VINx = 2.75 V to 5.5 V
VDD = VINx = 2.75 V to 5.5 V
VFB
Adjustable output, TJ = 25°C,
V1SET, V2SET = VDD or via 82 kΩ to GND
Adjustable output, TJ = −40°C to +125°C,
V1SET, V2SET = VDD or via 82 kΩ to GND
Fixed output, TJ = 25°C, V1SET, V2SET = GND
or via 4.7 kΩ, 8.2 kΩ, 15 kΩ, 27 kΩ,
47 kΩ to GND
Fixed output, TJ = −40°C to +125°C,
V1SET, V2SET = GND or via 4.7 kΩ, 8.2 kΩ,
15 kΩ, 27 kΩ, 47 kΩ to GND
VDD = VINx = 2.75 V to 5.5 V
VDD = VINx = 2.75 V to 5.5 V
All oscillator parameters provided for
VDD = 2.75 V to 5.5 V
FREQ tied to GND
FREQ via 8.2 kΩ to GND
FREQ via 27 kΩ to GND
fSYNC = 2 × fSW
FREQ tied to GND
FREQ via 8.2 kΩ to GND
FREQ via 27 kΩ to GND
Line Regulation
Load Regulation
OSCILLATOR
Switching Frequency
fSW
SYNC Frequency Range
fSYNC
Max
Unit
2.65
2.47
0.18
1.7
5.5
2.75
V
V
2.5
V
mA
1.7
2.5
mA
3.0
4.0
mA
1.0
10
μA
1
65
nA
11
15
μA
550
VCOMP, ZCT
VCOMP, HI
VCOMP, LO
VFB ERROR
Typ
SYNC Input Pulse Width
Rev. B | Page 3 of 36
μA/V
2.45
0.65
1.12
2.36
0.70
V
V
V
0.597
0.600
0.603
V
0.594
0.600
0.606
V
−1.0
+1.0
%
−1.5
+1.5
%
0.05
0.03
255
510
1020
400
800
1600
100
300
600
1200
%/V
%/A
345
690
1380
kHz
kHz
kHz
1000
2000
4000
kHz
kHz
kHz
ns
ADP2116
Parameter
SYNC Pin Capacitance to GND
SYNC Input Logic Low
SYNC Input Logic High
Phase Shift Between Channels
CLKOUT Frequency
CLKOUT Positive Pulse Time
CLKOUT Rise or Fall Time
CURRENT LIMIT
Data Sheet
Symbol
CSYNC
VIL_SYNC
VIH_SYNC
Conditions
fCLKOUT
fCLKOUT = 2 × fSW
FREQ tied to GND
FREQ via 8.2 kΩ to GND
FREQ via 27 kΩ to GND
Peak Output Current Limit, Channel 2
ILIMIT2
SWON MIN
SWOFF MIN
SWx Maximum Leakage Current
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
SOFT START
SS1, SS2 Pin Current
Soft Start Threshold Voltage
Soft Start Pull-Down Current
POWER GOOD
Overvoltage PGOODx Rising Threshold2
Overvoltage PGOODx Falling Threshold2
Undervoltage PGOODx Rising Threshold2
Undervoltage PGOODx Falling Threshold2
PGOODx Delay
PGOODx Leakage Current
PGOODx Low Saturation Voltage
1
2
0.8
510
1020
2040
100
ENLO
ENHI
IEN_LEAK
690
1380
2760
kHz
kHz
kHz
ns
ns
10
3.5
4.5
5.3
A
OPCFG tied to VDD or via 82 kΩ to GND
OPCFG via 47 kΩ or 27 kΩ to GND
3.5
2.4
5.3
4.0
fSW = 300 kHz
10
4.5
3.3
4
13.6
8
A
A
A/V
ms
Cycles
VDD = VINx = 3.3 V
VDD = VINx = 5.0 V
VDD = VINx = 3.3 V
VDD = VINx = 5.0 V
VDD = VINx = 2.75 V to 5.5 V
VDD = VINx = 5.5 V
VDD = VINx = 2.75 V
VDD = VINx = 2.75 V to 5.5 V, ENx = GND,
TJ = −40°C to +115°C
VDD = VINx = 2.75 V to 5.5 V
VDD = VINx = 2.75 V to 5.5 V
VDD = VINx = ENx = 2.75 V to 5.5 V,
TJ = −40°C to +115°C
68
52
32
27
107
192
255
0.1
17
15
0.8
2.0
0.1
TTMSD
ISS1, ISS2
VSS_THRESH
600
1200
2400
Unit
pF
V
V
Degrees
CCLKOUT = 20 pF
All current-limit parameters provided for
VDD = VINx = 2.75 V to 5.5 V
OPCFG tied to VDD or via 82 kΩ to GND
GCS
Low-Side, N-Channel RDSON1
ENABLE INPUTS
EN1, EN2 Logic Low Level
EN1, EN2 Logic High Level
EN1, EN2 Input Leakage Current
Max
2.0
tCLKOUT
ILIMIT1
SWx Minimum On Time
SWx Minimum Off Time
Typ
5
180
Peak Output Current Limit, Channel 1
Current-Sense Amplifier Gain
Hiccup Time
Number of Cumulative Current-Limit
Cycles to Go into Hiccup Mode
SWITCH NODE CHARACTERISTICS
High-Side, P-Channel RDSON1
Min
1
150
25
VDD = VINx = 2.75 V to 5.5 V, VSS = 0 V
VDD = VINx = 2.75 V to 5.5 V
VDD = VINx = 2.75 V to 5.5 V, EN = GND
All power-good parameters provided for
VDD = VINx = 2.75 V to 5.5 V
4.8
Pin-to-pin measurements.
The thresholds are expressed as a percentage of the nominal output voltage.
Rev. B | Page 4 of 36
116
108
92
84
50
0.1
50
V
V
μA
°C
°C
7.8
0.5
100
85
VPGOODx = VDD
IPGOODx = 1 mA
6.0
0.65
mΩ
mΩ
mΩ
mΩ
ns
ns
ns
μA
114
97
1
110
μA
V
mA
%
%
%
%
μs
μA
mV
Data Sheet
ADP2116
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VDD to GND
VIN1, VIN2, VIN3, VIN4, VIN5, VIN6 to
PGND1, PGND2, PGND3, PGND4
EN1, EN2, SCFG, FREQ, SYNC/CLKOUT,
PGOOD1, PGOOD2, V1SET, V2SET,
COMP1, COMP2, SS1, SS2 to GND
FB1, FB2 to GND
SW1, SW2, SW3, SW4 to PGND1, PGND2,
PGND3, PGND4
PGND1, PGND2, PGND3, PGND4 to GND
VIN1, VIN2, VIN3, VIN4, VIN5, VIN6 to VDD
θJA, JEDEC 1S2P PCB, Natural Convection
Operating Junction Temperature Range
Storage Temperature Range
Maximum Soldering Lead
Temperature (10 sec)
Rating
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to (VDD + 0.3 V)
−0.3 V to +3.6 V
−0.3 V to (VDD + 0.3 V)
0.3 V
0.3 V
34°C/W
−40°C to +125°C
−65°C to +150°C
260°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Absolute maximum ratings apply individually only, not in
combination.
ESD CAUTION
Rev. B | Page 5 of 36
ADP2116
Data Sheet
32
31
30
29
28
27
26
25
FB1
V1SET
SS1
PGOOD1
EN1
VIN1
VIN2
VIN3
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
ADP2116
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
SW1
SW2
PGND1
PGND2
PGND3
PGND4
SW3
SW4
NOTES
1. CONNECT THE EXPOSED THERMAL PAD
TO THE SIGNAL/ANALOG GROUND PLANE.
08436-003
FB2
V2SET
SS2
PGOOD2
EN2
VIN4
VIN5
VIN6
9
10
11
12
13
14
15
16
GND
COMP1
FREQ
SCFG
SYNC/CLKOUT
OPCFG
COMP2
VDD
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
Mnemonic
GND
2
COMP1
3
FREQ
4
SCFG
5
SYNC/CLKOUT
6
OPCFG
7
COMP2
8
VDD
9
FB2
10
V2SET
11
SS2
12
PGOOD2
13
EN2
Description
Ground for the Internal Analog and Digital Circuits. Connect GND to the signal/analog ground plane before connecting
to the power ground.
Error Amplifier Output for Channel 1. Connect a series RC network from COMP1 to GND to compensate the control
loop of Channel 1. For multiphase operation, tie COMP1 and COMP2 together.
Frequency Select Input. Connect this pin through a resistor to GND to set the appropriate switching frequency
(see Table 5).
Synchronization Configuration Input. SCFG configures the SYNC/CLKOUT pin as an input or output. Tie this pin to
VDD to configure SYNC/CLKOUT as an output. Tie this pin to GND to configure SYNC/CLKOUT as an input.
External Synchronization Input/Internal Clock Output. This bidirectional pin is configured with the SCFG pin (see the
Pin 4 description for details). When this pin is configured as an output, a buffered clock of twice the switching frequency
with a phase shift of 90° is available on this pin. When configured as an input, this pin accepts an external clock to which
the converters are synchronized. The frequency select resistor, mentioned in the description of Pin 3, must be selected
to be close to the expected switching frequency for stable operation (see the Setting the Oscillator Frequency
section).
Operation Configuration Input. Connect this pin to VDD or through a resistor to GND to set the system mode of
operation according to Table 7. This pin can be used to select a peak current limit for each power channel and to
enable or disable the pulse skip mode.
Error Amplifier Output for Channel 2. Connect a series RC network from COMP2 to GND to compensate the control
loop of Channel 2. For multiphase operation, tie COMP1 and COMP2 together.
Power Supply Input. The power source for the ADP2116 internal circuitry. Connect VDD and VINx with a 10 Ω resistor
as close as possible to the ADP2116. Bypass VDD to GND with a 1 μF or greater capacitor.
Feedback Voltage Input for Channel 2. For the fixed output voltage option, connect FB2 to VOUT2. For the adjustable
output voltage option, connect this pin to a resistor divider between VOUT2 and GND. The reference voltage for the
adjustable output voltage option is 0.6 V. With multiphase configurations, the FB2 and FB1 pins should be tied
together and then connected to VOUT.
Output Voltage Set Pin for Channel 2. To select a fixed output voltage option (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V)
for VOUT2, connect this pin through a resistor to GND (see Table 4 for details). To select an adjustable output voltage
for VOUT2, connect this pin to GND through an 82 kΩ resistor or tie this pin directly to VDD depending on the
output voltage desired.
Soft Start Input for Channel 2. Place a capacitor from SS2 to GND to set the soft start period. A 10 nF capacitor
sets a 1 ms soft start period. For multiphase configuration, connect SS2 to SS1.
Open-Drain Power-Good Output for Channel 2. Place a 100 kΩ pull-up resistor to VDD or to any other voltage that is
5.5 V or less; PGOOD2 is held low when Channel 2 is out of regulation.
Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 converter; drive EN2 low to turn off the Channel 2
converter. Tie EN2 to VDD for startup with VDD. When using a multiphase configuration, connect EN2 to EN1.
Rev. B | Page 6 of 36
Data Sheet
Pin No.
14
15
16
17
Mnemonic
VIN4
VIN5
VIN6
SW4
18
SW3
19
20
21
22
23
PGND4
PGND3
PGND2
PGND1
SW2
24
SW1
25
26
27
28
VIN3
VIN2
VIN1
EN1
29
PGOOD1
30
SS1
31
V1SET
32
FB1
EP
ADP2116
Description
Power Supply Input. The source of the high-side internal power MOSFET of Channel 2.
Power Supply Input. The source of the high-side internal power MOSFET of Channel 2.
Power Supply Input. The source of the high-side internal power MOSFET of Channel 2.
Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 2.
Tie SW3 to SW4, and then connect the output LC filter between the switching node and the output voltage.
Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 2.
Tie SW3 to SW4, and then connect the output LC filter between the switching node and the output voltage.
Power Ground. The source of the low-side internal power MOSFET of Channel 2.
Power Ground. The source of the low-side internal power MOSFET of Channel 2.
Power Ground. The source of the low-side internal power MOSFET of Channel 1.
Power Ground. The source of the low-side internal power MOSFET of Channel 1.
Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 1.
Tie SW1 to SW2, and then connect the output LC filter between the switching node and the output voltage.
Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 1.
Tie SW1 to SW2, and then connect the output LC filter between the switching node and the output voltage.
Power Supply Input. The source of the high-side internal power MOSFET of Channel 1.
Power Supply Input. The source of the high-side internal power MOSFET of Channel 1.
Power Supply Input. The source of the high-side internal power MOSFET of Channel 1.
Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 converter; drive EN1 low to turn off the Channel 1
converter. Tie EN1 to VDD for startup with VDD. When using a multiphase configuration, connect EN1 to EN2.
Open-Drain Power-Good Output for Channel 1. Place a 100 kΩ pull-up resistor to VDD or to any other voltage that is
5.5 V or less; PGOOD1 is held low when Channel 1 is out of regulation.
Soft Start Input for Channel 1. Place a capacitor from SS1 to GND to set the soft start period. A 10 nF capacitor
sets a 1 ms soft start period. For multiphase configuration, connect SS1 to SS2.
Output Voltage Set Pin for Channel 1. To select a fixed output voltage option (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V)
for VOUT1, connect this pin through a resistor to GND (see Table 4 for details). To select an adjustable output voltage
for VOUT1, connect this pin to GND through an 82 kΩ resistor or tie this pin directly to VDD depending on the
output voltage desired.
Feedback Voltage Input for Channel 1. For the fixed output voltage option, connect FB1 to VOUT1. For the adjustable
output voltage option, connect this pin to a resistor divider between VOUT1 and GND. With multiphase
configurations, the FB1 and FB2 pins should be tied together and then connected to VOUT.
Exposed Thermal Pad. Connect the exposed thermal pad to the signal/analog ground plane.
Rev. B | Page 7 of 36
ADP2116
Data Sheet
95
95
90
90
85
85
80
75
60
10
100
1k
10k
55
10
95
90
90
85
EFFICIENCY (%)
95
80
75
65
60
10
100
1k
10k
VIN = 3.3V
80
VIN = 5V
75
70
65
PULSE SKIP
FORCED PWM
PULSE SKIP
FORCED PWM
60
10k
LOAD CURRENT (mA)
08436-005
VOUT = 2.5V,
VOUT = 2.5V,
VOUT = 1.2V,
VOUT = 1.2V,
1k
Figure 6. Efficiency vs. Load, VOUT = 1.2 V and fSW = 1.2 MHz;
Inductor TOKO FDV0620-1R0M, 1.0 μH, 14 mΩ
100
85
100
LOAD CURRENT (mA)
Figure 4. Efficiency vs. Load, VIN = 5 V and fSW = 300 kHz;
VOUT = 3.3 V, Inductor Cooper Bussmann DR1050-8R2-R, 8.2 μH, 15 mΩ;
VOUT = 1.8 V, Inductor TOKO FDV0620-4R7M, 4.7 μH, 53 mΩ
70
VIN = 5V, PULSE SKIP
VIN = 5V, FORCED PWM
VIN = 3.3V, PULSE SKIP
VIN = 3.3V, FORCED PWM
60
LOAD CURRENT (mA)
EFFICIENCY (%)
70
65
VOUT = 3.3V
VOUT = 3.3V, PULSE SKIP
VOUT = 1.8V
VOUT = 1.8V, PULSE SKIP
65
75
Figure 5. Efficiency vs. Load, VIN = 5 V and fSW = 600 kHz;
VOUT = 2.5 V, Inductor TOKO FDV0620-3R3M, 3.3 μH, 40 mΩ;
VOUT = 1.2 V, Inductor TOKO FDV0620-2R2M, 2.2 μH, 30 mΩ
55
100
1k
10k
LOAD CURRENT (mA)
Figure 7. Efficiency, Combined Dual-Phase Output, VOUT = 1.2 V and
fSW = 1.2 MHz; Inductor TOKO FDV0620-1R0M, 1.0 μH, 14 mΩ
Rev. B | Page 8 of 36
08436-007
70
80
08436-006
EFFICIENCY (%)
100
08436-004
EFFICIENCY (%)
TYPICAL PERFORMANCE CHARACTERISTICS
Data Sheet
ADP2116
0.25
0.25
0.20
0.20
VOUT2 ERROR, NORMALIZED (%)
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
0
–0.05
–0.10
–0.15
1.0
1.5
2.0
2.5
3.0
–0.25
0.4
VOUT2 ERROR, NORMALIZED (%)
0.4
0.1
0
–0.1
–0.2
–0.3
1.5
2.0
2.5
3.0
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.4
4.0
4.5
5.0
5.5
VIN (V)
–0.5
2.5
08436-009
–0.5
3.5
Figure 9. Line Regulation, Channel 1: Load Current = 3 A and fSW = 600 kHz
0.75
0.50
0.50
VOUT2 ERROR (%)
0.75
VIN = 5.5V, NO LOAD
0
–0.25
VIN = 2.75V, 3A LOAD
100
TEMPERATURE (°C)
125
08436-010
75
5.5
Figure 10. Output Voltage Error vs. Temperature,
Channel 1: VOUT = 0.6 V and fSW = 600 kHz
VIN = 2.75V, 2A LOAD
–0.25
–0.75
50
5.0
VIN = 5.5V, NO LOAD
–0.75
25
4.5
0
–0.50
0
4.0
0.25
–0.50
–25
3.5
Figure 12. Line Regulation, Channel 2: Load Current = 3 A and fSW = 600 kHz
1.00
0.25
3.0
VIN (V)
1.00
–1.00
–50
1.0
Figure 11. Load Regulation, Channel 2: VIN = 5 V, fSW = 600 kHz, and TA = 25°C
0.5
0.2
0.5
LOAD CURRENT (A)
0.5
0.3
0
08436-011
0.5
Figure 8. Load Regulation, Channel 1: VIN = 5 V, fSW = 600 kHz, and TA = 25°C
VOUT1 ERROR, NORMALIZED (%)
0.05
08436-012
0
LOAD CURRENT (A)
VOUT1 ERROR (%)
0.10
–0.20
08436-008
–0.25
0.15
–1.00
–50
–25
0
25
50
75
100
TEMPERATURE (°C)
Figure 13. Output Voltage Error vs. Temperature,
Channel 2: VOUT = 1.5 V and fSW = 600 kHz
Rev. B | Page 9 of 36
125
08436-013
VOUT1 ERROR, NORMALIZED (%)
LINE AND LOAD REGULATION
ADP2116
250
330
fSW = 300kHz
fSW = 600kHz
fSW = 1.2MHz
320
200
310
175
fSW (kHz)
150
125
290
100
280
75
3.0
3.5
4.0
4.5
5.0
5.5
VIN (V)
270
2.5
08436-014
50
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VIN (V)
Figure 14. Minimum On Time, Open Loop, Includes Dead Time
Figure 17. Switching Frequency vs. Input Voltage, fSW = 300 kHz
350
660
330
310
fSW = 300kHz
fSW = 600kHz
fSW = 1.2MHz
640
290
620
270
fSW (kHz)
MINIMUM OFF TIME (ns)
300
08436-017
MINIMUM ON TIME (ns)
225
Data Sheet
250
230
600
580
210
190
560
3.0
3.5
4.0
4.5
5.0
5.5
VIN (V)
540
08436-015
150
2.5
4.0
4.5
5.0
5.5
50
+125°C
+115°C
+85°C
+25C
–40°C
45
40
80
NMOS RDSON (mΩ)
PMOS RDSON (mΩ)
3.5
Figure 18. Switching Frequency vs. Input Voltage, fSW = 600 kHz
+125°C
+115°C
+85°C
+25C
–40°C
100
3.0
VIN (V)
Figure 15. Minimum Off Time, Open Loop, Includes Dead Time
120
2.5
08436-018
170
60
40
35
30
25
20
15
10
20
3.0
3.5
4.0
VIN (V)
4.5
5.0
5.5
0
2.5
08436-016
0
2.5
Figure 16. High-Side PMOS Resistance vs. Input Voltage, Includes Bond Wires
3.0
3.5
4.0
VIN (V)
4.5
5.0
5.5
08436-019
5
Figure 19. Low-Side NMOS Resistance vs. Input Voltage, Includes Bond Wires
Rev. B | Page 10 of 36
Data Sheet
ADP2116
330
2.0
1.9
ENABLE/DISABLE THRESHOLD (V)
320
fSW (kHz)
310
VIN = 2.75V
300
VIN = 5.5V
290
280
1.8
1.7
1.6
1.5
ENABLE; VIN = 5.5V
ENABLE; VIN = 2.75V
DISABLE; VIN = 5.5V
DISABLE; VIN = 2.75V
1.4
1.3
1.2
1.1
1.0
25
50
75
100
125
TEMPERATURE (°C)
0.8
–50
75
100
125
125
UVLO THRESHOLD (V)
2.7
620
VIN = 2.75V
600
VIN = 5.5V
580
VDD RISING
2.6
2.5
VDD FALLING
2.4
560
0
25
50
75
100
125
TEMPERATURE (°C)
2.3
–50
08436-021
–25
1280
1280
1260
1260
1240
1240
1220
1220
fSW (kHz)
1300
1200
1180
1140
1120
1120
5.5
VIN (V)
08436-022
1140
5.0
75
100
Figure 22. Switching Frequency vs. Input Voltage, fSW = 1.2 MHz
VIN = 2.75V
VIN = 5.5V
1180
1160
4.5
50
1200
1160
4.0
25
Figure 24. UVLO Threshold vs. Temperature
1300
3.5
0
TEMPERATURE (°C)
Figure 21. Switching Frequency vs. Temperature, fSW = 600 kHz
3.0
–25
1100
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 25. Switching Frequency vs. Temperature, fSW = 1.2 MHz
Rev. B | Page 11 of 36
08436-025
fSW (kHz)
50
2.8
640
fSW (kHz)
25
Figure 23. Enable/Disable Threshold vs. Temperature
660
1100
2.5
0
TEMPERATURE (°C)
Figure 20. Switching Frequency vs. Temperature, fSW = 300 kHz
540
–50
–25
08436-023
0
08436-020
–25
08436-024
0.9
270
–50
ADP2116
Data Sheet
6.0
5.5
115
5.0
CURRENT LIMIT (A)
105
2.5
2.0
1.0
85
0.5
–25
0
25
50
75
100
125
TEMPERATURE (°C)
0
–50
0
25
50
75
100
125
125
Figure 29. Peak Current Limit vs. Temperature, VIN = 5 V
700
10
9
650
8
600
7
550
6
gm (µA/V)
SHUTDOWN CURRENT (µA)
–25
TEMPERATURE (°C)
Figure 26. PGOOD1/PGOOD2 Threshold vs. Temperature
5
4
VIN = 5.5V
3
VIN = 5.5V
500
VIN = 2.75V
450
400
2
VIN = 2.75V
350
0
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
08436-027
1
Figure 27. Shutdown Current vs. Temperature
4
VIN = 5.5V
3
VIN = 2.75V
2
–25
0
25
50
75
100
125
TEMPERATURE (°C)
08436-028
1
0
–50
300
–50
–25
0
25
50
75
TEMPERATURE (°C)
Figure 30. gm vs. Temperature
5
VDD INPUT CURRENT (mA)
2A OPTION
3.0
1.5
90
80
–50
3.5
08436-029
95
OVERVOLTAGE, VOUT RISING
OVERVOLTAGE, VOUT FALLING
UNDERVOLTAGE, VOUT RISING
UNDERVOLTAGE, VOUT FALLING
4.0
08436-030
100
3A OPTION
4.5
110
08436-026
PGOOD1/PGOOD2 THRESHOLD (%)
120
Figure 28. VDD Input Current vs. Temperature, Not Switching
Rev. B | Page 12 of 36
100
Data Sheet
ADP2116
5.0
4.5
4.5
VDD SUPPLY CURRENT (mA)
5.0
4.0
3.5
3.0
FORCED PWM
2.0
PULSE SKIP
1.0
2.5
3.0
3.0
3.5
4.0
4.5
5.0
5.5
2.0
1.0
2.5
4.5
4.5
VDD SUPPLY CURRENT (mA)
5.0
4.0
3.5
3.0
FORCED PWM
2.0
PULSE SKIP
3.0
3.5
4.0
4.0
4.5
5.0
VDD VOLTAGE (V)
4.5
5.0
5.5
4.0
3.5
3.0
2.5
2.0
VDD
VDD
VDD
VDD
1.5
5.5
08436-032
1.0
2.5
3.5
Figure 33. VDD Supply Current, No Load,
Channel 1: VOUT1 = 1.5 V, Channel 2: VOUT2 = 0.8 V, fSW = 1.2 MHz
5.0
1.5
3.0
VDD VOLTAGE (V)
Figure 31. VDD Supply Current, No Load,
Channel 1: VOUT1 = 1.5 V, Channel 2: Off, fSW = 1.2 MHz
2.5
PULSE SKIP
2.5
1.5
VDD VOLTAGE (V)
VDD SUPPLY CURRENT (mA)
3.5
08436-033
1.5
FORCED PWM
4.0
1.0
–50
–25
0
25
= 2.75V, PULSE SKIP
= 5.5V, PULSE SKIP
= 2.75V, FORCED PWM
= 5.5V, FORCED PWM
50
75
100
125
TEMPERATURE (°C)
Figure 34. VDD Supply Current vs. Temperature,
Channel 1: VOUT1 = 1.5 V, Channel 2: VOUT2 = 0.8 V, fSW = 1.2 MHz
Figure 32. VDD Supply Current, No Load,
Channel 2: VOUT2 = 0.8 V, Channel 1: Off, fSW = 1.2 MHz
Rev. B | Page 13 of 36
08436-034
2.5
08436-031
VDD SUPPLY CURRENT (mA)
SUPPLY CURRENT
ADP2116
Data Sheet
LOAD TRANSIENT RESPONSE
VOUT2, AC
VOUT1, AC
2
2
IOUT2
IOUT1
4
4
SW3, SW4
SW1, SW2
2.16A
08436-035
CH3 5.0V BW CH2 100mV BW M400µs 62.5MS/s A CH4
CH4 2.0A
Ω BW 16ns/pt
CH3 5V
Figure 35. Load Transient Response in Pulse Skip Mode,
Channel 1: 0.3 A to 3 A Load Step, VIN = 5 V, VOUT = 2.5 V, fSW = 600 kHz
(See Table 12 for the Circuit Details)
2.16A
Figure 38. Load Transient Response in Pulse Skip Mode,
Channel 2: 0.3 A to 3 A Load Step, VIN = 5 V, VOUT = 1.2 V, fSW = 600 kHz
(See Table 12 for the Circuit Details)
VOUT2, AC
VOUT1, AC
2
IOUT1
IOUT2
4
CH2 200mV BW M400µs 50MS/s
Ω BW 200ns/pt
CH4 1.0A
A CH4
1.7A
08436-036
4
CH2 50mV BW M200µs 125MS/s
CH4 1.0A Ω BW 8ns/pt
Figure 36. Load Transient Response in Pulse Skip Mode,
Channel 1: 0.3 A to 3 A Load Step, VIN = 5 V, VOUT = 3.3 V, fSW = 300 kHz
(See Table 12 for the Circuit Details)
4
CH2 50mV BW M200µs 125MS/s A CH4
CH4 2.0A Ω BW 8ns/pt
A CH4
1.7A
08436-039
2
B
W
08436-038
3
1
Figure 39. Load Transient Response in Pulse Skip Mode,
Channel 2: 0.3 A to 3 A Load Step, VIN = 3.3 V, VOUT = 1.2 V, fSW = 1.2 MHz
(See Table 12 for the Circuit Details)
VOUT , AC
VOUT, AC
2
IOUT
IOUT
2
M200µs
B
W
T 24.00%
A CH2
3.2A
CH2 50mV BW
CH4 2.0A Ω BW
08436-037
CH2 2.0A Ω
CH4 200mV
Figure 37. Load Transient Response in Forced PWM Mode,
Combined Output: 0 A to 6 A Load Step, VIN = 5 V, VOUT = 3.3 V, fSW = 600 kHz
(See Table 12 for the Circuit Details)
M200µs 125MS/s
8ns/pt
A CH4
1.68A
08436-040
4
Figure 40. Load Transient Response in Forced PWM Mode,
Combined Output: 0.6 A to 6 A Load Step, VIN = 5 V, VOUT = 1.2 V, fSW = 600 kHz
(See Table 12 for the Circuit Details)
Rev. B | Page 14 of 36
Data Sheet
ADP2116
BASIC FUNCTIONALITY
VOUT, AC
2
EN1
1
SW
2
3
VOUT1
SS1
4
INDUCTOR CURRENT
SW1, SW2
4
B
W
B
CH2 10mV
W M4µs 1.25GS/s A CH3
CH4 500mA Ω BW IT 400ps/pt
4.32V
CH1 5.0V
CH3 5.0V
Figure 41. Pulse Skip Mode, 110 mA Load
B
W
B
W
CH2 1.0V
CH4 2.0V
B
W
B
W
M1.0ms 10MS/s
100ns/pt
A CH1
2.4V
08436-044
CH3 2.0V
08436-041
3
Figure 44. Soft Start, Channel 1: VOUT = 1.8 V, CSS1 = 10 nF
VOUT, AC
2
EN1
1
SW
VOUT1
2
3
4
SS1
INDUCTOR CURRENT
SW1, SW2
4
B
W
B
CH2 20mV
W M1µs 1.25GS/s A CH3
CH4 500mA Ω BW IT 100ps/pt
2.52V
CH1 5.0V BW CH2 1.0V
CH3 5.0V BW CH4 500mV
Figure 42. Forced PWM Mode, CCM Operation, 200 mA Load, fSW = 600 kHz
B
W
B
W
M200µs 50MS/s
20.0ns/pt
A CH1
2.4V
08436-045
CH3 2.0V
08436-042
3
Figure 45. Soft Start with Precharged Output
VOUT, AC
2
SW
INDUCTOR CURRENT
4
3
4
B
CH2 20mV
W M1µs 1.25MS/s A CH3
CH3 2V BW CH4 500mA Ω BW IT 100ps/pt
4.32V
08436-043
3
VOUT2
SW3, SW4
CH2 1.0V BW M1.0ms 50MS/s A CH2
CH3 5.0V BW CH4 2.0A Ω BW 20ns/pt
Figure 43. Pulse Skip Enabled, DCM Operation, 200 mA Load, fSW = 600 kHz
Rev. B | Page 15 of 36
1.12V
Figure 46. Current Limit Entry,
Channel 2: VOUT = 1.8 V, 2 A Configuration, fSW = 600 kHz
08436-046
2
INDUCTOR CURRENT
ADP2116
Data Sheet
EXTERNAL SYNC
INDUCTOR CURRENT
1
4
CHANNEL 1 SW
VOUT2
4
2
CHANNEL 2 SW
SW3, SW4
B
W
1.12V
08436-047
CH3 5.0V
CH2 1.0V BW M10.0µs 1.25GS/s A CH2
CH4 2.0A Ω BW IT 200ps/pt
CH1 5.0V
CH3 5.0V
B
W
B
W
CH4 5.0V
B
W
M1.0µs 1.25GS/s
IT 100ps/pt
A CH1
3.0V
08436-050
3
3
Figure 50. External Synchronization, fSYNC = 1.5 MHz, fSW = 750 kHz
Figure 47. Current Limit Entry (Zoomed In),
Channel 2: VOUT2 = 1.8 V, 2 A Configuration, fSW = 600 kHz
INDUCTOR CURRENT
CHANNEL 1 SW
4
4
CHANNEL 2 SW
3
VOUT2
2
INTERNAL CLKOUT
1
SW3, SW4
B
W
CH2 1.0V BW M2.0ms 5.0MS/s A CH4
CH4 2.0A Ω BW 200ns/pt
1.72A
CH1 5.0V
CH3 5.0V
Figure 48. Hiccup Mode, fSW = 600 kHz, 6.8 ms Hiccup Cycle
B
W
B
W
CH4 5.0V
B
W
M1.0µs 1.25GS/s
IT 100psns/pt
A CH4
3.0V
08436-051
CH3 5.0V
08436-048
3
Figure 51. Internal Clock Output, fSW = 600 kHz, fCLKOUT = 1.2 MHz
CHANNEL 1 SW
INDUCTOR CURRENT
CHANNEL 3 SW
4
1
2
VOUT2
2
3
CHANNEL 2 SW
4
CHANNEL 4 SW
1.12V
08436-049
CH2 1.0V BW M2.0ms 1.25GS/s A CH2
CH3 5.0V BW CH4 2.0A Ω BW IT 40ns/pt
CH1 2.0V
CH3 2.0V
Figure 49. Exiting Hiccup Mode, Channel 2: VOUT2 = 1.8 V, fSW = 600 kHz
Rev. B | Page 16 of 36
B
W
B
W
CH2 2.0V
CH4 2.0V
B
W
B
W
M1.0µs 1.25GS/s
IT 400ps/pt
A CH1
2.0V
08436-052
SW3, SW4
3
Figure 52. 4-Channel Operation, Two ADP2116 Devices, One Device
Synchronizes the Other, 90° Phase-Shifted Switch Nodes
Data Sheet
ADP2116
PHASE 1 SW
EN1
1
1
PHASE 2 SW
VOUT1
4
2
PGOOD1
3
INDUCTOR CURRENT, PHASE 1
2
3
SS1
INDUCTOR CURRENT, PHASE 2
B
W
CH2 1.0V
CH4 1.0V
B
W
B
W
M1ms 25MS/s
40ns/pt
A CH1
2.2V
CH1 5.0V
CH2 2.0A Ω
CH3 2.0A Ω CH4 5.0V
08436-053
CH1 5.0V
CH3 5.0V
Figure 53. Power-Good Signal
M2.0µs
T 79.6%
A CH1
Figure 54. Combined Dual-Phase Output Operation,
VOUT = 1.2 V, fSW = 300 kHz, 6 A Load
Rev. B | Page 17 of 36
1.9V
08436-054
4
ADP2116
Data Sheet
BODE PLOTS
120
50
120
40
96
40
96
72
30
48
20
24
0
0
MAGNITUDE
–10
–24
–20
–30
48
24
10
MAGNITUDE
0
0
–10
–24
–48
–20
–48
–72
–30
–72
–40
–96
–40
–96
–50
1k
–120
–50
1k
10k
M1
100k
M2
10k
FREQUENCY (Hz)
M1
56.62kHz
0.029dB
55.02°
M2
220.20kHz
–18.743dB
–0.468°
M2 – M1
163.58kHz
–18.772dB
–55.494°
100k
M2
–120
FREQUENCY (Hz)
08436-055
FREQUENCY
MAGNITUDE
PHASE
M1
PHASE (Degrees)
MAGNITUDE (dB)
10
72
PHASE
Figure 55. Magnitude and Phase vs. Frequency, VIN = 5 V, VOUT = 2.5 V, Load = 3 A,
fSW = 600 kHz, Crossover Frequency (fCROSS) = 57 kHz, Phase Margin = 55°
(See Table 12 for the Circuit Details)
FREQUENCY
MAGNITUDE
PHASE
M1
46.12kHz
–0.558dB
47.275°
M2
186.41kHz
–20.906dB
0.065°
M2 – M1
140.29kHz
–20.348dB
–47.210°
08436-056
PHASE
20
PHASE (Degrees)
30
MAGNITUDE (dB)
50
Figure 56. Magnitude and Phase vs. Frequency, VIN = 5 V, VOUT = 1.2 V, Load = 3 A,
fSW = 600 kHz, Crossover Frequency (fCROSS) = 46 kHz, Phase Margin = 47°
(See Table 12 for the Circuit Details)
Rev. B | Page 18 of 36
Data Sheet
ADP2116
SIMPLIFIED BLOCK DIAGRAM
VDD
UVLO
SCFG
FREQ
GND
OSC
SYNC/CLKOUT
UVLO
OSC_CH1
PHASE
SHIFT
OSC_CH2
VFB1
CLIM_CH1
OPCFG
PGOOD1
0.7V
CURRENT LIMIT/
CONFIGURATION
CLIM_CH2
PULSE SKIP ENABLE
VIN1
0.5V
VIN2
VIN3
EN1
COMP1
UVLO
V1SET
VOUT
SELECTOR
FB1
OSC_CH1
VFB1
SS1
ISS =
6µA
–
+
+
PULSE SKIP
ENABLE
OTSD
gm ERROR
AMPLIFIER
VREF = 0.6V
GATE
CONTROL
LOGIC AND
MOSFET
DRIVERS
WITH
ANTI-SHOOTTHROUGH
PROTECTION
PMOS
NMOS
PGND1
PGND2
PWM
COMPARATOR
HICCUP
TIMER
POWER
STAGE
VDD
SLOPE
COMPENSATION/
RAMP GENERATOR
–
+
CURRENTLIMIT
COMPARATOR
CLIM_CH1
CURRENT-SENSE
AMPLIFIER
CHANNEL 1
PGOOD2
0.7V
THERMAL
SHUTDOWN
SW1
SW2
OTSD
VFB2
VIN4
0.5V
VIN5
VIN6
COMP2
UVLO
V2SET
VOUT
SELECTOR
FB2
OSC_CH2
VFB2
SS2
ISS =
6µA
–
+
+
PULSE SKIP
ENABLE
OTSD
gm ERROR
AMPLIFIER
VREF = 0.6V
GATE
CONTROL
LOGIC AND
MOSFET
DRIVERS
WITH
ANTI-SHOOTTHROUGH
PROTECTION
SW3
SW4
NMOS
PGND3
PGND4
PWM
COMPARATOR
HICCUP
TIMER
POWER
STAGE
VDD
SLOPE
COMPENSATION/
RAMP GENERATOR
CURRENTLIMIT
COMPARATOR
PMOS
–
+
CLIM_CH2
Figure 57. Simplified Block Diagram
Rev. B | Page 19 of 36
CURRENT-SENSE
AMPLIFIER
CHANNEL 2
08436-057
EN2
ADP2116
Data Sheet
THEORY OF OPERATION
The ADP2116 also includes undervoltage lockout (UVLO) with
hysteresis, soft start, and power good, as well as protection features
such as output short-circuit protection and thermal shutdown.
The output voltages, current limits, switching frequency, pulse
skip operation, and soft start time are externally programmable
with tiny resistors and capacitors.
CONTROL ARCHITECTURE
The ADP2116 consists of two step-down dc-to-dc converters that
deliver regulated output voltages, VOUT1 and VOUT2 (see Figure 1),
by modulating the duty cycle at which the internal high-side,
P-channel power MOSFET and the low-side, N-channel power
MOSFET are switched on and off.
In steady-state operation, the output voltage VOUT1 or VOUT2 is
sensed on the corresponding feedback pin, FB1 or FB2, and
attenuated in proportion to the selected output voltage on the
V1SET or V2SET pin. An error amplifier integrates the error
between the feedback voltage and the reference voltage (VREF =
0.6 V) to generate an error voltage at the COMP1 or COMP2 pin.
The valley inductor current is sensed by a current-sense amplifier when the low-side, N-channel MOSFET is on. An internal
oscillator turns off the low-side, N-channel MOSFET and turns on
the high-side, P-channel MOSFET at a fixed switching frequency.
Control logic with the anti-shoot-through circuit monitors and
adjusts the low-side and high-side driver outputs to ensure breakbefore-make switching. This monitoring and control prevents
cross-conduction between the internal high-side, P-channel power
MOSFET and the low-side, N-channel power MOSFET.
UNDERVOLTAGE LOCKOUT (UVLO)
The UVLO threshold is 2.65 V when VDD is increasing and
2.47 V when VDD is decreasing. The 180 mV hysteresis prevents
the converter from turning off and on repeatedly in response to
changing load conditions during a slow voltage transition on
VDD that is close to the 2.75 V minimum operational level.
ENABLE/DISABLE CONTROL
The EN1 and EN2 pins are used to independently enable or
disable Channel 1 and Channel 2, respectively. Drive ENx high
to turn on the corresponding channel of the ADP2116. Drive
ENx low to turn off the corresponding channel of the ADP2116,
reducing the input current to less than 1 μA. To force a channel
to start automatically when input power is applied, connect the
corresponding ENx pin to VDD. When shut down, the ADP2116
channels discharge the soft start capacitor, causing a new soft
start cycle every time the converters are reenabled.
SOFT START
The ADP2116 soft start feature allows the output voltage to ramp
up in a controlled manner, eliminating output voltage overshoot
during startup. Soft start begins after the undervoltage lockout
threshold is exceeded and an enable pin, EN1 or EN2, is pulled
high to greater than 2.0 V. External capacitors to ground are
required on both the SS1 and SS2 pins. Each regulating channel
has its own soft start circuit. When the converter powers up and
is enabled, the internal 6 μA current source charges the external
soft start capacitor, establishing a voltage ramp slope at the SS1
or SS2 pin, as shown in Figure 58. The soft start time ends when
the soft start ramp voltage exceeds the internal reference of 0.6 V.
When the high-side, P-channel MOSFET is enabled, the valley
inductor current information is added to an emulated ramp signal
and compared to the error voltage by the PWM comparator.
The output of the PWM comparator modulates the duty cycle
by adjusting the trailing edge of the PWM pulse that switches the
power devices. Slope compensation is programmed internally into
the emulated ramp signal and automatically selected, depending
on the input voltage, output voltage, and switching frequency.
This prevents subharmonic oscillations for greater than 50%
duty cycle operation.
EN
1
VOUT
2
4
SS
SW
3
CH1 5.0V
CH3 5.0V
B
B
W
W
CH2 1.0V
CH4 2.0V
B
W
B
W
M1.0ms
100ns/pt
Figure 58. Soft Start
Rev. B | Page 20 of 36
A CH1
2.4V
08436-058
The ADP2116 is a high efficiency, dual, fixed switching frequency,
synchronous, step-down dc-to-dc converter with flex mode
architecture, which is the Analog Devices, Inc., proprietary version
of peak current mode control architecture. The device operates
over an input voltage range of 2.75 V to 5.5 V. Each output channel
can provide an adjustable output as low as 0.6 V and deliver up
to 3 A of load current. When the output channels are tied together,
they operate 180° out of phase to deliver up to 6 A of load current.
The integrated high-side, P-channel power MOSFET and the
low-side, N-channel power MOSFET yield high efficiency at
medium to heavy loads. Pulse skip mode is available for improved
efficiency at light loads. With a high switching frequency (up to
2 MHz) and integrated power switches, the ADP2116 is optimized
to deliver high performance in a small package for power management solutions.
Data Sheet
ADP2116
The capacitance value of the soft start capacitor defines the soft
start time, tSS, based on
VREF I SS
t SS
CSS
(1)
where:
VREF is the internal reference voltage, 0.6 V.
ISS is the soft start current, 6 μA.
CSS is the soft start capacitor value.
If the output voltage, VOUT1 or VOUT2, is precharged prior to enabling
Channel 1 or Channel 2, respectively, the control logic prevents
inductor current reversal by keeping the power MOSFETs turned
off until the soft start voltage ramp at SS1 or SS2 reaches the
precharged output voltage on VFB1 or VFB2 (see Figure 59).
EN1
1
If the output voltage drops below 84% of the target output voltage,
the corresponding PGOOD1 or PGOOD2 pin is held low. The
PGOOD1 or PGOOD2 pin continues to be held low until the
output voltage rises to within 92% of the target output voltage.
The PGOOD1 or PGOOD2 pin is then released, signaling that
the output voltage is within the power-good window.
The power-good thresholds are shown in Figure 60. The PGOOD1
and PGOOD2 outputs also sink current if an overtemperature
condition is detected. Use these outputs as logic power-good
signals by connecting the pull-up resistor from PGOOD1 or
PGOOD2 to VDD. If the power-good function is not used, the
pins can be left floating.
PULSE SKIP MODE
VOUT1
2
SS1
4
SW1, SW2
CH2 1.0V BW M200µs 50MS/s
CH4 500mV BW 20ns/pt
A CH1
2.4V
Figure 59. Soft Start with a Precharged Output
POWER GOOD
The ADP2116 features open-drain power-good outputs (PGOOD1
and PGOOD2) that indicate when the converter output voltage
is within regulation. The power-good signal transitions low
immediately when the corresponding channel is disabled.
The power-good circuitry monitors the output voltage on the FB1
or FB2 pin and compares it to the rising and falling thresholds
The ADP2116 has built-in pulse skip circuitry that turns on
during light loads, switching only as necessary to maintain the
output voltage within regulation. This allows the converter to
maintain high efficiency during light load operation by reducing
the switching losses. The pulse skip mode can be selected by
configuring the OPCFG pin as indicated in Table 7. In pulse
skip mode, when the output voltage dips below regulation, the
ADP2116 enters PWM mode for a few oscillator cycles to increase
the output voltage so that it is within regulation. During the wait
time between bursts, both power switches are off, and the output
capacitor supplies all of the load current. Because the output voltage
dips and recovers occasionally, the output voltage ripple in this
mode is larger than the ripple in the PWM mode of operation.
If the converter is configured to operate in forced PWM mode
(by selecting this configuration using the OPCFG pin), the device
operates with a fixed switching frequency, even at light loads.
VOUT RISING
VOUT FALLING
108%
100%
100%
92%
84%
UNDERVOLTAGE
POWER
GOOD
OVERVOLTAGE
POWER
GOOD
PGOOD1/PGOOD2
Figure 60. PGOOD1/PGOOD2 Thresholds
Rev. B | Page 21 of 36
UNDERVOLTAGE
08436-060
% OF VOUT SET
116%
% OF VOUT SET
B
W
B
W
08436-059
3
CH1 5.0V
CH3 5.0V
specified in Table 1. If the rising output voltage (VOUT1 or VOUT2)
exceeds 116% of the target output voltage (VOUT1SET or VOUT2SET),
the PGOOD1 or PGOOD2 pin is held low. The PGOOD1 or
PGOOD2 pin continues to be held low until the falling output
voltage returns to 108% of the target value.
ADP2116
Data Sheet
HICCUP MODE CURRENT LIMIT
MAXIMUM DUTY CYCLE OPERATION
The ADP2116 features a hiccup mode current-limit implementation. When the peak inductor current exceeds the preset current
limit for more than eight consecutive clock cycles, the hiccup
mode current-limit condition occurs. The channel then goes to
sleep for 6.8 ms (at a 600 kHz switching frequency), which is
enough time for the output to be discharged and the average
power dissipation to be reduced. After the 6.8 ms elapses, the
channel wakes up with a soft start period (see Figure 61). If the
current-limit condition is subsequently triggered, the channel again
goes to sleep and wakes up after 6.8 ms. The current limits for
the two channels are programmed by configuring the OPCFG pin
(see Table 7). For the 3 A/3 A option, the output current limit is
set to 4.5 A per output. For the 3 A/2 A option, the current limits
are set to 4.5 A and 3.3 A for VOUT1 and VOUT2, respectively.
As the input voltage drops and approaches the output voltage,
the ADP2116 smoothly transitions to maximum duty cycle
operation, with the low-side, N-channel MOSFET switched on
for the minimum off time. In maximum duty cycle operation,
the output voltage dips below regulation because the output
voltage is the product of the input voltage and the maximum
duty cycle limitation. The maximum duty cycle limit is a function
of the switching frequency and the input voltage, as shown in
Figure 64.
INDUCTOR
CURRENT
4
VOUT
2
SW
CH2 1.0V BW M2ms 5MS/s
CH3 5.0V BW CH4 2.0A Ω BW 200ns/pt
A CH4
1.72A
08436-061
3
Figure 61. Hiccup Mode
THERMAL OVERLOAD PROTECTION
The ADP2116 has an internal temperature sensor that monitors
the junction temperature. High current going into the switches
or a hot printed circuit board (PCB) can cause the junction
temperature of the ADP2116 to rise rapidly. When the junction
temperature reaches approximately 150°C, the ADP2116 goes
into thermal shutdown and the converter is turned off. When
the junction temperature cools to less than 125°C, the ADP2116
resumes normal operation after the soft start sequence.
SYNCHRONIZATION
The ADP2116 can be synchronized to an external clock such
that the two channels operate at a switching frequency that is
half of the input synchronization clock. The SYNC/CLKOUT
pin can be configured as an input SYNC pin or an output
CLKOUT pin through the SCFG pin, as detailed in Table 6.
Through the input SYNC pin, the ADP2116 can be synchronized
to an external clock such that the two channels switch at half
the external clock frequency and are 180° out of phase. Through
the output CLKOUT pin, the ADP2116 provides an output clock
that is twice the switching frequency of the channels and 90°
out of phase. Therefore, a single ADP2116 configured for the
CLKOUT option acts as the master converter and provides an
external clock for all other dc-to-dc converters (including other
ADP2116 devices). These other converters are configured as
slaves that accept an external clock and synchronize to it. This clock
distribution approach synchronizes all dc-to-dc converters in the
system and prevents beat harmonics that can lead to EMI issues.
The ADP2116 is optimized to power high performance signal
chain circuits. The slew rate of the switch node is controlled by
the size of the driver devices. Fast slewing of the switch node is
desirable to minimize transition losses but can, in turn, lead to
serious EMI issues due to parasitic inductance. To minimize
EMI generation, the slew rate of the drivers is optimized such
that the ADP2116 can match the performance of low dropout
regulators in supplying sensitive signal chain circuits while also
providing excellent power efficiency.
Rev. B | Page 22 of 36
Data Sheet
ADP2116
CONVERTER CONFIGURATION
To set the output voltage, VOUT1 or VOUT2, select one of the six
fixed voltages, as shown in Table 4, by connecting the V1SET or
V2SET pin to GND through a resistor of an appropriate value
(see Figure 62). V1SET and V2SET set the voltage output levels
for Channel 1 and Channel 2, respectively. The feedback pin,
FB1 or FB2, should be directly connected to VOUT1 or VOUT2.
Table 4. Output Voltage Programming
0 Ω to VDD
VOUT1 (V)
0.8
1.2
1.5
1.8
2.5
3.3
0.6 to
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