ADP2119

2 A/1.25 A, 1.2 MHz, Synchronous, Step-Down DC-to-DC Regulators ADP2119/ADP2120 FEATURES Continuous output current ADP2119: 2 A ADP2120: 1.25 A 145 mΩ and 70 mΩ integrated MOSFETs Input voltage range from 2.3 V to 5.5 V Output voltage from 0.6 V to VIN ±1.5% output accuracy 1.2 MHz fixed switching frequency Synchronizable between 1 MHz and 2 MHz Selectable PWM or PFM mode operation Current mode architecture Precision threshold enable input Power-good flag Voltage tracking Integrated soft start Internal compensation Startup with precharged output UVLO, OVP, OCP, and thermal shutdown 10-lead, 3 mm × 3 mm LFCSP_WD package TYPICAL APPLICATION CIRCUIT C1 0.1µF VIN 5V CIN 22µF X5R 6.3V R1 10Ω ADP2119/ADP2120 1 VIN 2 PVIN EN 10 SYNC/MODE 9 R2 10kΩ PGOOD 8 TRK 7 FB 6 08716-001 VOUT 3.3V COUT 22µF X5R 6.3V RBOT 2.21kΩ L 1.5µH RTOP 10kΩ 3 SW 4 PGND 5 GND Figure 1. APPLICATIONS Point of load conversion Communications and networking equipment Industrial and instrumentation Consumer electronics Medical applications GENERAL DESCRIPTION The ADP2119/ADP2120 are low quiescent current, synchronous, step-down dc-to-dc regulators in a compact 3 mm × 3 mm LFCSP_WD package. Both devices use a current mode, constant frequency pulse-width modulation (PWM) control scheme for excellent stability and transient response. Under light load conditions, they can be configured to operate in a pulse frequency modulation (PFM) mode, which reduces switching frequency to save power. The ADP2119/ADP2120 support input voltages from 2.3 V to 5.5 V. The output voltage can be adjusted from 0.6 V up to the input voltage (VIN) for the adjustable version, whereas the fixed output version is available in preset output voltage options of 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, and 1.0 V. The ADP2119/ADP2120 require minimal external parts and provide a high efficiency solution with their integrated power switches, synchronous rectifiers, and internal compensation. Each IC draws less than 2 μA current from the input source when it is disabled. Other key features include undervoltage lockout (UVLO), integrated soft start to limit inrush current at startup, overvoltage protection (OVP), overcurrent protection (OCP), and thermal shutdown (TSD). Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 100 VIN = 5V 90 VOUT = 1.8V 80 70 EFFICIENCY (%) PFM 60 50 40 FPWM 30 20 10 08716-002 0 0.01 0.1 OUTPUT CURRENT (A) 1 Figure 2. ADP2119 Efficiency vs. Output Current One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. ADP2119/ADP2120 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Typical Application Circuit ............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 Boundary Condition .................................................................... 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 7 Functional Block Diagram ............................................................ 15 Theory of Operation ...................................................................... 16 Control Scheme .......................................................................... 16 PWM Mode Operation.............................................................. 16 PFM Mode Operation................................................................ 16 Slope Compensation .................................................................. 16 Enable/Shutdown ....................................................................... 16 Integrated Soft Start ................................................................... 16 Tracking ....................................................................................... 17 Oscillator and Synchronization ................................................ 17 Current Limit and Short-Circuit Protection .............................. 17 Overvoltage Protection (OVP) ................................................. 17 Undervoltage Lockout (UVLO) ............................................... 17 Thermal Shutdown .................................................................... 17 Power Good (PGOOD) ............................................................. 17 Applications Information .............................................................. 18 Output Voltage Selection........................................................... 18 Inductor Selection ...................................................................... 18 Output Capacitor Selection....................................................... 18 Input Capacitor Selection .......................................................... 19 Voltage Tracking ......................................................................... 19 Typical Application Circuits ......................................................... 20 Outline Dimensions ....................................................................... 22 Ordering Guide .......................................................................... 22 REVISION HISTORY 6/10—Revision 0: Initial Version Rev. 0 | Page 2 of 24 ADP2119/ADP2120 SPECIFICATIONS VIN = VPVIN = 3.3 V, EN = VIN, SYNC/MODE = VIN at TJ = −40°C to +125°C, unless otherwise noted. Table 1. Parameter VIN and PVIN VIN Voltage Range PVIN Voltage Range Quiescent Current Shutdown Current VIN Undervoltage Lockout Threshold OUTPUT CHARACTERISTICS Load Regulation 1 Load Regulation 2 Line Regulation1 Line Regulation2 FB FB Regulation Voltage FB Bias Current SW High-Side On Resistance 3 Low-Side On Resistance3 SW Peak Current Limit SW Maximum Duty Cycle SW Minimum On Time 4 TRK TRK Input Voltage Range TRK-to-FB Offset Voltage TRK Input Bias Current FREQUENCY Oscillator Frequency SYNC/MODE Synchronization Range SYNC Minimum Pulse Width SYNC Minimum Off Time SYNC Input High Voltage SYNC Input Low Voltage INTEGRATED SOFT START Soft Start Time Symbol VIN VPVIN IVIN ISHDN UVLO Test Conditions/Comments Min 2.3 2.3 No switching, SYNC/MODE = GND Switching, no load, SYNC/MODE = VIN VIN = VPVIN = 5.5 V, EN = GND VIN rising VIN falling ADP2119, IO = 0 A to 2 A ADP2120, IO = 0 A to 1.25 A ADP2119, IO = 1 A ADP2120, IO = 1 A VFB IFB VIN = 2.3 V to 5.5 V VIN = 2.3 V to 5.5 V VIN = VPVIN = 3.3 V, ISW = 200 mA VIN = VPVIN = 3.3 V, ISW = 200 mA High-side switch, VIN = VPVIN = 3.3 V (ADP2119) High-side switch, VIN = VPVIN = 3.3 V (ADP2120) VIN = VPVIN = 5.5 V, full frequency VIN = VPVIN = 5.5 V, full frequency 0.591 150 680 0.3 2.2 2.1 0.08 0.08 0.05 0.05 0.6 0.01 145 70 3 2 100 0 −15 600 +15 100 1.2 1.38 2 0.609 0.1 190 100 3.5 2.4 100 Typ Max 5.5 5.5 200 900 2 2.3 Unit V V μA μA μA V V %/A %/A %/V %/V V μA mΩ mΩ A A % ns mV mV nA MHz MHz ns ns V V Clock cycles μs 115 95 % % % % Clock cycles μA mV Ω 2 2.5 1.6 TRK = 0 mV to 500 mV fS 1.02 1 100 100 1.3 0.4 All switching frequencies fS = 1.2 MHz 1024 853 105 85 110 2.5 90 2.5 16 0.1 150 150 PGOOD Power-Good Range Power-Good Deglitch Time PGOOD Leakage Current PGOOD Output Low Voltage PGOOD Output Low Resistor FB rising threshold FB rising hysteresis FB falling threshold FB falling hysteresis From FB to PGOOD VPGOOD = 5 V IPGOOD = 1 mA IPGOOD = 1 mA Rev. 0 | Page 3 of 24 1 200 200 ADP2119/ADP2120 Parameter EN EN Input Rising Threshold EN Input Hysteresis EN Pull-Down Resistor THERMAL Thermal Shutdown Threshold Thermal Shutdown Hysteresis 1 2 Symbol Test Conditions/Comments VIN = 2.3 V to 5.5 V VIN = 2.3 V to 5.5 V Min 1.12 Typ 1.2 100 1 150 25 Max 1.28 Unit V mV MΩ °C °C Specified by the circuit in Figure 54. Specified by the circuit in Figure 58. 3 Pin-to-pin measurements. 4 Guaranteed by design. Rev. 0 | Page 4 of 24 ADP2119/ADP2120 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VIN, PVIN SW FB, SYNC/MODE, EN, TRK, PGOOD PGND to GND Operating Junction Temperature Range Storage Temperature Range Soldering Conditions Rating −0.3 V to +6 V −0.3 V to +6 V −0.3 V to +6 V −0.3 V to +0.3 V −40°C to +125°C −65°C to +150°C JEDEC J-STD-020 THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance Package Type 10-Lead LFCSP_WD θJA 40 Unit °C/W BOUNDARY CONDITION θJA is measured using natural convection on a JEDEC 4-layer board, and the exposed pad is soldered to the printed circuit board (PCB) with thermal vias. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. 0 | Page 5 of 24 ADP2119/ADP2120 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADP2119/ADP2120 VIN PVIN SW PGND GND 1 2 3 4 5 EXPOSED PAD 10 9 8 7 6 EN SYNC/MODE PGOOD TRK FB Figure 3. Pin Configuration (Top View) Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 Mnemonic VIN PVIN SW PGND GND FB TRK PGOOD SYNC/MODE Description Bias Voltage Input Pin. Connect a bypass capacitor (0.1 μF minimum) between this pin and GND and a small (10 Ω) resistor between this pin and PVIN. Power Input Pin. Connect this pin to the input power source. Connect a bypass capacitor between this pin and PGND. Switch Node Output. Connect this pin to the output inductor. Power Ground. Connect this pin to the power ground plane and to the high current return for the power MOSFET. Analog Ground. Connect this pin to the ground plane. Feedback Voltage Sense Input. Connect this pin to a resistor divider from VOUT. For the fixed output version, connect to VOUT directly. Tracking Input. To track a master voltage, drive TRK from a resistor divider from the master voltage. If the tracking function is not used, connect TRK to VIN. Power-Good Output (Open Drain). Connect this pin to a resistor to any pull-up voltage < 5.5 V. Synchronization Input (SYNC). Connect this pin to an external clock between 1 MHz and 2 MHz to synchronize the switching frequency to the external clock (see the Oscillator and Synchronization section for details). FPWM/PFM Selection (MODE). When this pin is connected to VIN, the PFM mode is disabled and the part works in continuous conduction mode (CCM) only. When this pin is connected to ground, the PFM mode is enabled and becomes active at light loads. Precision Threshold Enable Input Pin. An external resistor divider can be used to set the turn-on threshold. To enable the part automatically, connect the EN pin to VIN. This pin has a 1 MΩ pull-down resistor to GND. The exposed pad should be soldered to an external ground plane underneath the IC for thermal dissipation. 10 EPAD EN Exposed Pad Rev. 0 | Page 6 of 24 08716-003 NOTES 1. THE EXPOSED PAD SHOULD BE SOLDERED TO AN EXTERNAL GROUND PLANE UNDERNEATH THE IC FOR THERMAL DISSIPATION. ADP2119/ADP2120 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VIN = VPVIN = 5 V, VOUT = 1.2 V, L = 1.5 μH, CIN = 22 μF, COUT = 2 × 22 μF, unless otherwise noted. 100 90 80 70 EFFICIENCY (%) 100 90 80 70 EFFICIENCY (%) 60 50 40 30 20 10 0 0 INDUCTOR SUMIDA CDRH5D18BHPNP-1R5M 0.2 0.4 0.6 0.8 1.0 1.2 1.4 OUTPUT CURRENT (A) VOUT = 1.0V VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V 08716-004 60 50 40 30 20 10 0 0 INDUCTOR SUMIDA CDRH5D18BHPNP-1R5M 0.2 0.4 0.6 0.8 1.0 1.2 1.4 OUTPUT CURRENT (A) VOUT = 1.0V VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V 1.6 1.8 2.0 08716-007 08716-009 08716-008 1.6 1.8 2.0 Figure 4. Efficiency (ADP2119, VIN = 3.3 V, FPWM) vs. Output Current 100 90 80 70 EFFICIENCY (%) Figure 7. Efficiency (ADP2119, VIN = 3.3 V, PFM) vs. Output Current 100 90 80 70 EFFICIENCY (%) 60 50 40 30 20 10 0 0 INDUCTOR SUMIDA CDRH5D18BHPNP-1R5M 0.2 0.4 0.6 0.8 1.0 1.2 1.4 OUTPUT CURRENT (A) VOUT = 1.0V VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V 1.6 1.8 2.0 08716-005 60 50 40 30 20 10 0 0 INDUCTOR SUMIDA CDRH5D18BHPNP-1R5M 0.2 0.4 0.6 0.8 1.0 1.2 1.4 OUTPUT CURRENT (A) VOUT = 1.0V VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V 1.6 1.8 2.0 Figure 5. Efficiency (ADP2119, VIN = 5 V, FPWM) vs. Output Current 100 90 80 70 EFFICIENCY (%) Figure 8. Efficiency (ADP2119, VIN = 5 V, PFM) vs. Output Current 100 90 80 70 EFFICIENCY (%) 60 50 40 30 20 10 0 0 INDUCTOR SUMIDA CDRH5D18BHPNP-1R5M 0.2 0.4 0.6 0.8 1.0 OUTPUT CURRENT (A) VOUT = 1.0V VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V 1.2 1.4 08716-006 60 50 40 30 20 10 0 0 INDUCTOR SUMIDA CDRH5D18BHPNP-1R5M 0.2 0.4 0.6 0.8 1.0 OUTPUT CURRENT (A) VOUT = 1.0V VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V 1.2 1.4 Figure 6. Efficiency (ADP2120, VIN = 3.3 V, FPWM) vs. Output Current Figure 9. Efficiency (ADP2120, VIN = 3.3 V, PFM) vs. Output Current Rev. 0 | Page 7 of 24 ADP2119/ADP2120 100 90 80 70 60 50 40 30 20 10 0 0 INDUCTOR SUMIDA CDRH5D18BHPNP-1R5M 0.2 0.4 0.6 0.8 1.0 OUTPUT CURRENT (A) VOUT = 1.0V VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V 08716-010 100 90 80 70 EFFICIENCY (%) EFFICIENCY (%) 60 50 40 30 20 10 0 0 INDUCTOR SUMIDA CDRH5D18BHPNP-1R5M 0.2 0.4 0.6 0.8 1.0 OUTPUT CURRENT (A) VOUT = 1.0V VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V 1.2 1.4 08716-013 08716-015 08716-014 1.2 1.4 Figure 10. Efficiency (ADP2120, VIN = 5 V, FPWM) vs. Output Current 900 850 800 QUIESCENT CURRENT (µA) Figure 13. Efficiency (ADP2120, VIN = 5 V, PFM) vs. Output Current 605 604 603 FEEDBACK VOLTAGE (mV) 750 700 650 600 550 500 450 400 2.3 2.7 3.1 3.5 3.9 VIN (V) 4.3 4.7 TJ = +125°C TJ = +25°C TJ = –40°C 5.1 5.5 08716-011 602 601 600 599 598 597 596 595 594 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 11. Quiescent Current vs. VIN (Switching) 275 250 225 TJ = +125°C TJ = +25°C TJ = –40°C Figure 14. Feedback Voltage vs. Temperature (VIN = 3.3 V) 120 110 100 NFET RESISTOR (mΩ) TJ = +125°C TJ = +25°C TJ = –40°C PFET RESISTOR (mΩ) 200 175 150 125 100 75 50 2.3 90 80 70 60 50 40 30 2.3 08716-012 2.7 3.1 3.5 3.9 VIN (V) 4.3 4.7 5.1 5.5 2.7 3.1 3.5 3.9 VIN (V) 4.3 4.7 5.1 5.5 Figure 12. PFET Resistor vs. VIN (Pin-to-Pin Measurements) Figure 15. NFET Resistor vs. VIN (Pin-to-Pin Measurements) Rev. 0 | Page 8 of 24 ADP2119/ADP2120 1.30 2.30 1.25 RISING 1.20 UVLO THRESHOLD (V) 2.25 RISING EN THRESHOLD (V) 2.20 1.15 FALLING 1.10 2.15 FALLING 2.10 1.05 2.05 08716-016 –20 0 20 40 60 80 100 120 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 16. EN Threshold vs. Temperature 3.1 3.5 3.3 PEAK CURRENT LIMIT (A) Figure 19. UVLO Threshold vs. Temperature (VIN = 3.3 V) 3.0 PEAK CURRENT LIMIT (A) TJ = +125°C TJ = +25°C TJ = –40°C 3.1 2.9 2.7 2.5 2.3 2.1 2.3 2.9 2.8 2.7 2.6 08716-017 –20 0 20 40 60 80 100 120 2.7 3.1 3.5 3.9 VIN (V) 4.3 4.7 5.1 5.5 TEMPERATURE (°C) Figure 17. Peak Current Limit vs. Temperature (ADP2119, VIN = 3.3 V) 2.10 2.05 PEAK CURRENT LIMIT (A) Figure 20. Peak Current Limit vs. VIN (ADP2119) 2.2 TJ = +125°C TJ = +25°C TJ = –40°C 2.1 PEAK CURRENT LIMIT (A) 2.00 1.95 1.90 1.85 1.80 1.75 –40 2.0 1.9 1.8 1.7 08716-018 –20 0 20 40 60 80 100 120 2.7 3.1 3.5 3.9 VIN (V) 4.3 4.7 5.1 5.5 TEMPERATURE (°C) Figure 18. Peak Current Limit vs. Temperature (ADP2120, VIN = 3.3 V) Figure 21. Peak Current Limit vs. VIN (ADP2120) Rev. 0 | Page 9 of 24 08716-021 1.6 2.3 08716-020 2.5 –40 08716-019 1.00 –40 2.00 –40 ADP2119/ADP2120 T T EN 3 3 EN VOUT VOUT 1 1 PGOOD 2 2 PGOOD IL 4 4 IL CH1 500mV CH2 5.00V CH3 5.00V CH4 2.00A Ω M400µs T 30.4% A CH3 3.60V CH1 500mV CH2 5.00V CH3 5.00V CH4 2.00A Ω M400µs T 784.0µs A CH3 3.50V Figure 22. Soft Start with Full Load (ADP2119, VIN = 5 V) Figure 25. Soft Start with Precharged Output (ADP2119, VIN = 5 V) T T VOUT (AC) 1 1 VOUT (AC) IO IO 4 4 CH1 50.0mV CH4 1.00A Ω M200µs A CH4 T 596.0µs 880mA CH1 50.0mV CH4 1.00A Ω M200µs A CH4 T 596.0µs 880mA Figure 23. Load Transient (ADP2119, PFM, VIN = 5 V) Figure 26. Load Transient (ADP2119, FPWM, VIN = 5 V) T T VOUT (AC) 1 1 VOUT (AC) IO IO 4 4 08716-024 CH1 50.0mV CH4 1.00A Ω M200µs A CH4 T 396.0µs 960mA CH1 50.0mV CH4 1.00A Ω M200µs A CH4 T 396.0µs 960mA Figure 24. Load Transient (ADP2120, PFM, VIN = 5 V) Figure 27. Load Transient (ADP2120, FPWM, VIN = 5 V) Rev. 0 | Page 10 of 24 08716-027 08716-026 08716-023 08716-025 08716-022 ADP2119/ADP2120 T T VOUT VOUT 1 1 SW SW 2 2 IL 4 4 IL 08716-028 CH1 500mV CH2 5.00V CH4 2.00A Ω M2.0ms A CH1 T 3.92ms 480mV CH1 500mV CH2 5.00V CH4 2.00A Ω M2.0ms A CH1 T –2.08ms 560mV Figure 28. Output Short (ADP2119) Figure 31. Output Short Recovery (ADP2119) T T VOUT VOUT 1 1 SW SW 2 2 IL 4 4 IL 08716-029 CH1 500mV CH2 5.00V CH4 2.00A Ω M2.0ms A CH1 T 3.96ms 200mV CH1 500mV CH2 5.00V CH4 2.00A Ω M2.0ms A CH1 T –2.12ms 560mV Figure 29. Output Short (ADP2120) Figure 32. Output Short Recovery (ADP2120) T T TRK SYNC FB 1 1 2 SW 08716-030 CH1 500mV CH2 500mV M2.0ms T 44.4% A CH2 730mV CH1 2.0V CH2 2.0V M400ns T 0.0s A CH1 4.12V Figure 30. Tracking Function Figure 33. Synchronized to 1 MHz Rev. 0 | Page 11 of 24 08716-033 08716-032 08716-031 ADP2119/ADP2120 VOUT (AC) 1 T 80 64 48 32 200 160 120 80 40 0 –40 –80 –120 –160 100k 1M 08716-037 MAGNITUDE (dB) SW 2 16 0 –16 –32 IL 4 –48 –64 08716-034 CH1 20.0mV CH2 5.00V CH4 500mA Ω M4.0µs A CH4 T –40.0ns 820mA CROSS FREQUENCY: 124kHz PHASE MARGIN: 46° –80 1k 10k –200 FREQUENCY (Hz) Figure 34. PFM Mode Figure 37. ADP2119 Bode Plot at VIN = 5 V, VOUT = 1.0 V, IO = 2 A, L = 1 μH, COUT = 2 × 22 μF 80 64 48 200 160 120 80 40 0 –40 –80 –120 –160 100k 1M 08716-038 T VOUT (AC) 1 MAGNITUDE (dB) 16 0 –16 –32 –48 2 IL 4 –64 08716-035 CH1 5.0mV CH2 5.00V CH4 500mA Ω M1.0µs T –40.0ns A CH2 4.3V CROSS FREQUENCY: 105kHz PHASE MARGIN: 47° –80 1k 10k –200 FREQUENCY (Hz) Figure 35. Discontinuous Conduction Mode (DCM) Figure 38. ADP2119 Bode Plot at VIN = 5 V, VOUT = 1.2 V, IO = 2 A, L = 1.5 μH, COUT = 2 × 22 μF 80 64 48 200 160 120 80 40 0 –40 –80 –120 CROSS FREQUENCY: 112kHz PHASE MARGIN: 48° 10k 100k FREQUENCY (Hz) 1M –160 08716-039 T VOUT (AC) 1 MAGNITUDE (dB) 16 0 –16 –32 –48 2 IL 4 –64 08716-036 CH1 5.0mV CH2 5.00V CH4 1.0A Ω M1.0µs T –40.0ns A CH2 4.3V –80 1k –200 Figure 36. Continuous Conduction Mode (CCM) Figure 39. ADP2119 Bode Plot at VIN = 5 V, VOUT = 1.5 V, IO = 2 A, L = 1.5 μH, COUT = 22 μF +10 μF Rev. 0 | Page 12 of 24 PHASE (Degrees) SW 32 PHASE (Degrees) SW 32 PHASE (Degrees) ADP2119/ADP2120 80 64 48 32 200 160 120 80 80 64 48 32 200 160 120 80 40 0 –40 –80 –120 –160 100k 1M 08716-043 MAGNITUDE (dB) PHASE (Degrees) MAGNITUDE (dB) 16 0 –16 –32 –48 –64 CROSS FREQUENCY: 99kHz PHASE MARGIN: 52° –80 1k 10k 40 0 –40 –80 –120 –160 100k 1M 16 0 –16 –32 –48 –64 CROSS FREQUENCY: 87kHz PHASE MARGIN: 48° –80 1k 10k FREQUENCY (Hz) 08716-040 –200 –200 FREQUENCY (Hz) Figure 40. ADP2119 Bode Plot at VIN = 5 V, VOUT = 1.8 V, IO = 2 A, L = 1.5 μH, COUT = 22 μF + 10 μF 80 64 48 32 200 160 120 80 Figure 43. ADP2120 Bode Plot at VIN = 5 V, VOUT = 1.0 V, IO = 1.25 A, L = 1.5 μH, COUT = 22 μF + 10 μF 80 64 48 32 200 160 120 80 40 0 –40 –80 –120 –160 100k 1M 08716-044 MAGNITUDE (dB) PHASE (Degrees) MAGNITUDE (dB) 16 0 –16 –32 –48 –64 CROSS FREQUENCY: 107kHz PHASE MARGIN: 49° –80 1k 10k 40 0 –40 –80 –120 –160 100k 1M 16 0 –16 –32 –48 –64 CROSS FREQUENCY: 80kHz PHASE MARGIN: 54° –80 1k 10k FREQUENCY (Hz) 08716-041 –200 –200 FREQUENCY (Hz) Figure 41. ADP2119 Bode Plot at VIN = 5 V, VOUT = 2.5 V, IO = 2 A, L = 1.5 μH, COUT = 22 μF 80 64 48 32 200 160 120 80 Figure 44. ADP2120 Bode Plot at VIN = 5 V, VOUT = 1.2 V, IO = 1.25 A, L = 1.5 μH, COUT = 22 μF + 10 μF 80 64 48 32 200 160 120 80 40 0 –40 –80 –120 CROSS FREQUENCY: 67kHz PHASE MARGIN: 51° 10k 100k FREQUENCY (Hz) 1M –160 08716-045 MAGNITUDE (dB) PHASE (Degrees) MAGNITUDE (dB) 16 0 –16 –32 –48 –64 CROSS FREQUENCY: 89kHz PHASE MARGIN: 58° 10k 100k FREQUENCY (Hz) 1M 40 0 –40 –80 –120 –160 16 0 –16 –32 –48 –64 Figure 42. ADP2119 Bode Plot at VIN = 5 V, VOUT = 3.3 V, IO = 2 A, L = 1.5 μH, COUT = 22 μF 08716-042 –80 1k –200 –80 1k –200 Figure 45. ADP2120 Bode Plot at VIN = 5 V, VOUT = 1.5 V, IO = 1.25 A, L = 2.2 μH, COUT = 22 μF + 10 μF Rev. 0 | Page 13 of 24 PHASE (Degrees) PHASE (Degrees) PHASE (Degrees) ADP2119/ADP2120 80 64 48 32 200 160 120 80 80 64 48 32 200 160 120 80 40 0 –40 –80 –120 –160 100k 1M 08716-048 MAGNITUDE (dB) PHASE (Degrees) MAGNITUDE (dB) 16 0 –16 –32 –48 –64 CROSS FREQUENCY: 78kHz PHASE MARGIN: 50° –80 1k 10k 40 0 –40 –80 –120 –160 100k 1M 16 0 –16 –32 –48 –64 CROSS FREQUENCY: 48kHz PHASE MARGIN: 60° –80 1k 10k FREQUENCY (Hz) 08716-046 –200 –200 FREQUENCY (Hz) Figure 46. ADP2120 Bode Plot at VIN = 5 V, VOUT = 1.8 V, IO = 1.25 A, L = 2.2 μH, COUT = 2 ×10 μF 80 64 48 32 200 160 120 80 40 0 –40 –80 –120 –160 100k 1M 08716-047 Figure 48. ADP2120 Bode Plot at VIN = 5 V, VOUT = 3.3 V, IO = 1.25 A, L = 2.2 μH, COUT = 2 ×10 μF MAGNITUDE (dB) 16 0 –16 –32 –48 –64 CROSS FREQUENCY: 61kHz PHASE MARGIN: 54° –80 1k 10k –200 FREQUENCY (Hz) Figure 47. ADP2120 Bode Plot at VIN = 5 V, VOUT = 2.5 V, IO = 1.25 A, L = 2.2 μH, COUT = 2 ×10 μF PHASE (Degrees) Rev. 0 | Page 14 of 24 PHASE (Degrees) ADP2119/ADP2120 FUNCTIONAL BLOCK DIAGRAM VIN EN PVIN ADP2119/ ADP2120 ZCOMP UVLO PMOS CURRENT SENSE AMPLIFIER TRK FB 0.6V SOFT START ERROR AMPLIFIER Gm SKIP MODE THRESHOLD 0.66V SKIP COMPARATOR PWM AND PROTECTION LOGIC CONTROL PFET SW NFET NMOS CURRENT SENSE AMPLIFIER SLOPE COMPENSATION 0.54V PGOOD GND OSCILLATOR CLK ZERO-CROSSING COMPARATOR SYNC/MODE Figure 49. Functional Block Diagram Rev. 0 | Page 15 of 24 08716-049 PGND ADP2119/ADP2120 THEORY OF OPERATION The ADP2119/ADP2120 are step-down, dc-to-dc regulators that use a fixed frequency, peak current mode architecture with integrated high-side switch and low-side synchronous rectifier. The high switching frequency and tiny 10-lead, 3 mm × 3 mm LFCSP_WD package provide a small step-down dc-to-dc regulator solution. The integrated high-side switch (P-channel MOSFET) and synchronous rectifier (N-channel MOSFET) yield high efficiency at medium-to-full loads while light load efficiency is improved using the PFM mode. The ADP2119/ADP2120 support input voltages from 2.3 V to 5.5 V and regulate the output voltage down to 0.6 V. The ADP2119/ADP2120 are also available with preset output voltage options of 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, and 1.0 V. PFM MODE OPERATION When PFM mode is enabled, the regulator smoothly transitions to the variable frequency PFM mode of operation when the load current decreases below the pulse-skipping threshold current. Switching continues only as necessary to maintain the output voltage within regulation. When the output voltage drops below regulation, the part enters PWM mode for a few oscillator cycles to increase the output voltage back to regulation. During the wait time between bursts, both power switches are off, and the output capacitor supplies the load current. Because the output voltage dips and recovers occasionally, the output voltage ripple in this mode is larger than the ripple in the PWM mode of operation. SLOPE COMPENSATION Slope compensation stabilizes the internal current control loop of the ADP2119/ADP2120 when operating close to and beyond the 50% duty cycle to prevent subharmonic oscillations. Slope compensation is implemented by summing an artificial voltage ramp to the current sense signal during the on-time of the P-channel MOSFET switch. This voltage ramp depends on the output voltage. When operating at high output voltages, there is more slope compensation. The slope compensation ramp value determines the minimum inductor that can be used to prevent subharmonic oscillations. CONTROL SCHEME The ADP2119/ADP2120 use a fixed frequency, peak current mode PWM control architecture and operate in PWM mode for medium-to-full loads but shift to PFM mode (if enabled) at light loads to maintain high efficiency. When operating in fixed frequency PWM mode, the duty cycle of the integrated switches is adjusted to regulate the output voltage. When operating in PFM mode at light loads, the switching frequency is adjusted to regulate the output voltage. The ADP2119/ADP2120 operate in PWM mode when the load current is greater than the pulse-skipping threshold current. At load currents below this value, the regulator smoothly transitions to the PFM mode of operation. ENABLE/SHUTDOWN The EN input pin has a precision analog threshold of 1.2 V (typical) with 100 mV of hysteresis. When the enable voltage exceeds 1.2 V, the regulator turns on, and when it falls below 1.1 V (typical), the regulator turns off. To force the part to automatically start when input power is applied, connect EN to VIN. When the ADP2119/ADP2120 are shut down, the soft start capacitor is discharged. This causes a new soft start cycle to begin when the part is reenabled. An internal pull-down resistor (1 MΩ) prevents an accidental enable if EN is left floating. PWM MODE OPERATION In PWM mode, the ADP2119/ADP2120 operate at a fixed frequency. At the start of each oscillator cycle, the P-channel MOSFET switch is turned on, putting a positive voltage across the inductor. Current in the inductor increases until the current sense signal crosses the peak inductor current level, turns off the P-channel MOSFET switch, and turns on the N-channel MOSFET synchronous rectifier. This puts a negative voltage across the inductor, causing the inductor current to decrease. The synchronous rectifier stays on for the rest of the cycle or until the inductor current reaches zero, which causes the zerocrossing comparator to turn off the N-channel MOSFET as well. The peak inductor current level is set by VCOMP. VCOMP is the output of a transconductance error amplifier that compares the feedback voltage with an internal 0.6 V reference. INTEGRATED SOFT START The ADP2119/ADP2120 include integrated soft start circuitry to limit the output voltage rise time and reduce inrush current at startup. The soft start time is fixed at 1024 clock cycles. If the output voltage is precharged prior to turn-on, the part prevents reverse inductor current (which would discharge the output capacitor) by keeping both MOSFETs turned off until the soft start voltage exceeds the voltage on the FB pin. Rev. 0 | Page 16 of 24 ADP2119/ADP2120 TRACKING The ADP2119/ADP2120 have a tracking input, TRK, that allows the output voltage to track another voltage (master voltage). The tracking input is especially useful in core and I/O voltage tracking for FPGAs, DSPs, and ASICs. The internal error amplifier includes three positive inputs: the internal reference voltage, the soft start voltage, and the TRK voltage. The error amplifier regulates the FB voltage to the lowest of the three voltages. To track a master voltage, tie the TRK pin to a resistor divider from the master voltage. If the tracking function is not used, connect the TRK pin to VIN. OVERVOLTAGE PROTECTION (OVP) The output voltage is continuously monitored by a comparator through the FB pin, which is at 0.6 V (typical) under normal operation. This comparator is set to activate when the FB voltage exceeds 0.66 V (typical), thus indicating an output overvoltage condition. If the voltage remains above this threshold for 16 clock cycles, the high-side MOSFET turns off and the low-side MOSFET turns on until the current through the low-side MOSFET reaches the limit (−0.6 A for forced continuous conduction mode and 0 A for PFM mode). Thereafter, both the MOSFETs are held in the off state until FB falls below 0.54 V (typical), at this point, the part restarts. The behavior of PGOOD under this condition is described in the Power Good section. OSCILLATOR AND SYNCHRONIZATION To synchronize the ADP2119/ADP2120, drive an external clock at the SYNC/MODE pin. The frequency of the external clock can be in the 1 MHz to 2 MHz range. During synchronization, the regulator operates in CCM mode only, and the switching frequency is in phase with the external clock. UNDERVOLTAGE LOCKOUT (UVLO) Undervoltage lockout circuitry is integrated in the ADP2119/ ADP2120. If the input voltage drops below 2.1 V, the part shuts down and both the power switch and synchronous rectifier turn off. When the voltage rises again above 2.2 V, the soft start period is initiated, and the part is enabled. CURRENT LIMIT AND SHORT-CIRCUIT PROTECTION The ADP2119/ADP2120 have a peak current limit protection circuit to prevent current runaway. When the inductor peak current reaches the current limit value, the high-side MOSFET turns off and the low-side MOSFET turns on until the next cycle starts. The overcurrent counter increments during this time. If the overcurrent counter count exceeds 10, the part enters hiccup mode and both the high-side MOSFET and low-side MOSFET are turned off. The part remains in this mode for 4096 clock cycles and then attempts to restart from soft start. If the current limit fault has cleared, the part resumes normal operation. Otherwise, it reenters hiccup mode again after counting 10 current limit violations. THERMAL SHUTDOWN If the ADP2119/ADP2120 junction temperatures rise above 150°C, the thermal shutdown circuit turns off the regulators. Extreme junction temperatures can be the result of high current operation, poor circuit board design, and/or high ambient temperature. A 25°C hysteresis is included so that if thermal shutdown occurs, the part does not return to operation until the on-chip temperature drops below 125°C. When coming out of thermal shutdown, soft start is initiated. POWER GOOD (PGOOD) PGOOD is an active high, open-drain output and requires a resistor to pull it up to a voltage. A high indicates that the voltage on the FB pin (and therefore the output voltage) is within ±10% of the desired value. A low on this pin indicates that the voltage on the FB pin is not within ±10% of the desired value. There is a 16 cycle waiting period after FB is detected as being out of bounds. Rev. 0 | Page 17 of 24 ADP2119/ADP2120 APPLICATIONS INFORMATION This section describes the selection of the external components for the ADP2119/ADP2120. The typical application circuit for the ADP2119 is shown in Figure 50. C1 0.1µF VIN 5V The negative current limit (−0.6 A) also limits the minimum inductor value. The inductor current ripple (ΔIL) calculated by the selected inductor should not exceed 1.2 A. The peak inductor current should be kept below the peak current limit threshold value and can be calculated from CIN 22µF X5R 6.3V R1 10Ω 1 VIN ADP2119 EN 10 SYNC/MODE 9 R2 10kΩ PGOOD 8 I PEAK = I O + ΔI L 2 2 PVIN VOUT 2.5V 2A Ensure that the rms current of the selected inductor is greater than the maximum load current and that its saturation current is greater than the peak current limit of the regulator. COUT 22µF X5R 6.3V RBOT 15kΩ L 1.5µH RTOP 47.5kΩ 3 SW 4 PGND 5 GND OUTPUT CAPACITOR SELECTION TRK 7 FB 6 08716-050 The output voltage ripple, load step transient, and loop stability determine the output capacitor selection. The ESR and the capacitance determine the output ripple. ⎛ ⎞ 1 ⎟ ΔVOUT = ΔI L × ⎜ ESR + ⎜ 8 × COUT × f S ⎟ ⎝ ⎠ Figure 50. Typical Application Circuit OUTPUT VOLTAGE SELECTION The output voltage of the adjustable version can be set by an external resistive voltage divider, and the following equation calculates the output voltage. The load transient response depends on the inductor, the output capacitor, and the control loop. The ADP2119/ADP2120 have integrated loop compensation to provide a simple power solution design. Table 5 and Table 6 show the typical recommended inductors and capacitors for the ADP2119/ ADP2120. X5R or X7R ceramic capacitors are highly recommended. Table 5. Recommended L and COUT Values for the ADP2119 VIN ( V) 3.3 3.3 3.3 3.3 3.3 5 5 5 5 5 5 VIN ( V) 3.3 3.3 3.3 3.3 3.3 5 5 5 5 5 5 VOUT (V) 1.0 1.2 1.5 1.8 2.5 1.0 1.2 1.5 1.8 2.5 3.3 VOUT (V) 1.0 1.2 1.5 1.8 2.5 1.0 1.2 1.5 1.8 2.5 3.3 L (μH) 1 1 1 1 1 1 1.5 1.5 1.5 1.5 1.5 L (μH) 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.2 2.2 2.2 2.2 COUT (μF) 22 + 22 22 + 22 22 + 10 22 22 22 + 22 22 + 22 22 +10 22 +10 22 22 COUT (μF) 22 + 10 22 + 10 22 + 10 10 + 10 10 + 10 22 + 10 22 + 10 22 + 10 10 + 10 10 + 10 10 + 10 VOUT = 0.6 × (1 + RTOP ) RBOT To limit the output voltage accuracy degradation due to FB bias current (0.1 μA maximum) to less than 0.5% (maximum), ensure that RBOT is less than 30 kΩ. INDUCTOR SELECTION The inductor value is determined by the operating frequency, input voltage, output voltage, and ripple current. A small inductor value leads to a larger inductor current ripple and provides a faster transient response; however, it degrades efficiency. A large inductor value leads to a smaller current ripple and good efficiency but slows the transient response. As a guideline, the inductor current ripple, ΔIL, is typically set to 1/3 of the maximum load current trade-off between the transient response and efficiency. The inductor value can be calculated using the following equation: L= (VIN − VOUT )× D ΔI L × f S Table 6. Recommended L and COUT Values for the ADP2120 where: VIN is the input voltage. VOUT is the output voltage. ΔIL is the inductor current ripple. D is the duty cycle. D = VOUT/VIN. The regulator uses slope compensation in the current loop to prevent subharmonic oscillations when the duty cycle is larger than 50%. The internal slope compensation limits the minimum inductor value. Rev. 0 | Page 18 of 24 ADP2119/ADP2120 Higher or lower inductor and output capacitor values can be used in the regulator, but the system stability and load transient performance need to be checked. The minimum output capacitor is 22 μF for the ADP2119 and 10 μF for the ADP2120, and the inductor range is 1 μH to 3.3 μH. Table 7. Recommended Inductors Manufacturer Sumida TOKO Coilcraft Part Number CDRH5D18BHPNP, CDR6D23MNNP DE4518C, D62LCB LPS5030, LPS5015 VMASTER A common application is coincident tracking (see Figure 52). Coincident tracking limits the slave output voltage to be the same as the master voltage until it reaches regulation. Connect the TRK pin to a resistor divider from the master voltage. For coincident tracking, set RTRKT = RTOP and RTRKB = RBOT. VOLTAGE VSLAVE Manufacturer Murata Murata TDK TDK Part Number GRM31CR60J226KE19 GRM319R60J106KE19 C3216X5R0J226M C3216X5R0J106M Description 22 μF, 6.3 V, X5R, 1206 10 μF, 6.3 V, X5R, 1206 22 μF, 6.3 V, X5R, 1206 10 μF, 6.3 V, X5R, 1206 TIME Figure 52. Coincident Tracking INPUT CAPACITOR SELECTION The input capacitor reduces the input voltage ripple caused by the switch current on PVIN. Place the input capacitor as close as possible to the PVIN pin. A 10 μF or 22 μF ceramic capacitor is recommended. The rms current rating of the input capacitor should be larger than calculated by the following equation: Ratiometric tracking is shown in Figure 53. The slave output is limited to a fraction of the master voltage. In this application, the slave and master voltages reach the final value at the same time. The ratio of the slave output voltage to the master voltage is a function of the two dividers (see the following equation). VSLAVE VMASTER RTOP RBOT = RTRKT 1+ RTRKB 1+ VMASTER I RMS = IO × D × (1 − D) VOLTAGE VOLTAGE TRACKING The ADP2119/ADP2120 include a tracking feature that allows the output (slave voltage) to be configured to track an external voltage (master voltage), as shown in Figure 51. VMASTER VSLAVE ADP2119/ ADP2120 TRK RTOP FB VSLAVE TIME Figure 53. Ratiometric Tracking RTRKT RTRKB Figure 51. Voltage Tracking 08716-051 RBOT Rev. 0 | Page 19 of 24 08716-053 08716-052 Table 8. Recommended Capacitors ADP2119/ADP2120 TYPICAL APPLICATION CIRCUITS C1 0.1µF VIN 5V CIN 22µF X5R 6.3V R1 10Ω 1 ADP2119 VIN PVIN SW PGND GND EN 10 SYNC/MODE 9 R2 10kΩ PGOOD 8 TRK 7 FB 6 2 VOUT 1.2V 2A COUT1 22µF X5R 6.3V COUT2 22µF X5R 6.3V RBOT 10kΩ L 1.5µH RTOP 10kΩ 3 4 5 L: CDRH5D18BHPNP-1R5M SUMIDA CIN, COUT1, COUT2: GRM31CR60J226KE19 MURATA Figure 54. 1.2 V, 2 A, Step-Down Regulator, Forced Continuous Conduction Mode (ADP2119) C1 0.1µF VIN 5V CIN 22µF X5R 6.3V R1 10Ω 1 ADP2119 VIN PVIN SW PGND GND EN 10 SYNC/MODE 9 PGOOD 8 R2 10kΩ 4 2 VOUT 1.8V 2A COUT1 10µF X5R 6.3V COUT2 22µF X5R 6.3V RBOT 10kΩ L 1.5µH RTOP 20kΩ 3 TRK 7 FB 6 5 Figure 55. 1.8 V, 2 A, Step-Down Regulator, Enable PFM Mode (ADP2119) Rev. 0 | Page 20 of 24 08716-055 L: CDRH5D18BHPNP-1R5M SUMIDA CIN, COUT2: GRM31CR60J226KE19 MURATA COUT1: GRM319R60J106KE19 MURATA 08716-054 ADP2119/ADP2120 C1 0.1µF VIN 5V CIN 22µF X5R 6.3V R1 10Ω 1 ADP2119 VIN PVIN SW PGND GND EN 10 SYNC/MODE 9 R2 10kΩ PGOOD 8 TRK 7 FB 6 EXTERNAL CLOCK 2 VOUT 2.5V 2A COUT 22µF X5R 6.3V RBOT 15kΩ L 1.5µH RTOP 47.5kΩ 3 4 5 L: CDRH5D18BHPNP-1R5M SUMIDA CIN, COUT: GRM31CR60J226KE19 MURATA Figure 56. 2.5 V, 2 A, Step-Down Regulator, Synchronized to External Clock (ADP2119) C1 0.1µF VIN 5V CIN 22µF X5R 6.3V R1 10Ω 1 VIN ADP2120 EN 10 SYNC/MODE 9 R2 10kΩ PGOOD 8 TRK 7 FB 6 RTRKB 10kΩ 2 PVIN VOUT 1.5V 1.25A COUT1 22µF X5R 6.3V COUT2 10µF X5R 6.3V RBOT 10kΩ L 2.2µH RTOP 15kΩ 3 SW 4 PGND 5 GND RTRKT 15kΩ VMASTER Figure 57. 1.5 V, 1.25 A, Step-Down Regulator, Tracking Mode (ADP2120) C1 0.1µF VIN 5V CIN 22µF X5R 6.3V R1 10Ω 1 VIN ADP2120 EN 10 SYNC/MODE 9 R2 10kΩ PGOOD 8 TRK 7 FB 6 2 PVIN VOUT 1.2V 1.25A COUT1 22µF X5R 6.3V COUT2 10µF X5R 6.3V RBOT 10kΩ L 1.5µH RTOP 10kΩ 3 SW 4 PGND 5 GND Figure 58. 1.2 V, 1.25 A, Step-Down Regulator, Forced Continuous Conduction Mode (ADP2120) Rev. 0 | Page 21 of 24 08716-058 L: CDRH5D18BHPNP-1R5M SUMIDA CIN, COUT1: GRM31CR60J226KE19 MURATA COUT2: GRM319R60J106KE19 MURATA 08716-057 L: LPS5030-222MLB COILCRAFT CIN, COUT1: GRM31CR60J226KE19 MURATA COUT2: GRM319R60J106KE19 MURATA 08716-056 ADP2119/ADP2120 OUTLINE DIMENSIONS 3.10 3.00 SQ 2.90 6 2.48 2.38 2.23 0.50 BSC 10 EXPOSED PAD PIN 1 INDEX AREA 0.50 0.40 0.30 TOP VIEW 1.74 1.64 1.49 5 BOTTOM VIEW 1 PIN 1 INDICATOR (R 0.15) 0.80 0.75 0.70 SEATING PLANE 0.30 0.25 0.20 0.05 MAX 0.02 NOM FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 121009-A 0.20 REF Figure 59. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADP2119ACPZ-R7 ADP2119ACPZ-1.0-R7 ADP2119ACPZ-1.2-R7 ADP2119ACPZ-1.5-R7 ADP2119ACPZ-1.8-R7 ADP2119ACPZ-2.5-R7 ADP2119ACPZ-3.3-R7 ADP2120ACPZ-R7 ADP2120ACPZ-1.0-R7 ADP2120ACPZ-1.2-R7 ADP2120ACPZ-1.5-R7 ADP2120ACPZ-1.8-R7 ADP2120ACPZ-2.5-R7 ADP2120ACPZ-3.3-R7 1 Output Current 2A 2A 2A 2A 2A 2A 2A 1.25 A 1.25 A 1.25 A 1.25 A 1.25 A 1.25 A 1.25 A Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Output Voltage ADJ 1.0 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V ADJ 1.0 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V Package Description 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD Package Option CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 Branding LFL LEV LFK LFM LFN LFP LFR LEW LFS LFT LFU LFV LFW LFX Z = RoHS Compliant Part. Rev. 0 | Page 22 of 24 ADP2119/ADP2120 NOTES Rev. 0 | Page 23 of 24 ADP2119/ADP2120 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08716-0-6/10(0) Rev. 0 | Page 24 of 24