TYPICAL APPLICATION CIRCUIT
Continuous output current
ADP2165: 5 A
ADP2166: 6 A
Integrated MOSFET
High-side on resistance: 19 mΩ
Low-side on resistance: 15 mΩ
Reference voltage: 0.6 V ± 1% over temperature range
Input voltage range: 2.7 V to 5.5 V
Current mode architecture
Switching frequency
Fixed frequency: 620 kHz or 1.2 MHz
Adjustable frequency: 250 kHz to 1.4 MHz
Synchronizes to external clock: 250 kHz to 1.4 MHz
Selectable synchronize phase shift: in phase or out of phase
External compensation
Programmable soft start
Startup into a precharged output
Voltage tracking input
Power-good output and precision enable input
Accurate current limit
Available in 24-lead, 4 mm × 4 mm LFCSP package
Supported by ADIsimPower™ design tool
APPLICATIONS
BST
CBST
AVIN
CIN
VOUT
PGOOD
RTOP
SYNC
RRT
COUT
FB
RT
CVREG
L1
SW
EN
COMP
TRK
VREG
SS
GND
PGND
CCP
CSS
RC
RBOT
CC
Figure 1.
The ADP2165/ADP2166 are designed to be extremely flexible
with the addition of a minimal amount of external components
to program soft start and control loop compensation.
The ADP2165/ADP2166 are supplied from an input voltage of
2.7 V to 5.5 V. Output voltage options include 3.3 V, 2.5 V, 1.8 V,
1.5 V, 1.2 V, or 1.0 V fixed outputs and adjustable options capable
of supporting an output voltage range from 0.6 V to 90% of the
input voltage. Protection features include undervoltage lockout
(UVLO), overvoltage protection (OVP), overcurrent protection
(OCP), and thermal shutdown (TSD) for robust performance.
The ADP2165/ADP2166 operate over the −40°C to +125°C
junction temperature range and are available in a 24-lead
LFCSP package.
Point of load regulation
Communications and networking
High end consumer
Industrial, instrumentation, and healthcare
100
VPVIN = 3.3V
GENERAL DESCRIPTION
95
Key features include precision enable, power-good monitor,
and output voltage tracking to facilitate robust sequencing.
The switching frequency can be programmed from 250 kHz
to 1.4 MHz, or it can be fixed at 620 kHz or 1.2 MHz. The
synchronization function allows the switching frequency to
synchronize to an external clock, minimizing the
electromagnetic interference (EMI) of the system.
90
VPVIN = 5V
85
EFFICIENCY (%)
The ADP2165/ADP2166 are high efficiency, current mode
control, step-down dc-to-dc regulators with an integrated 19 mΩ
high-side FET and a 15 mΩ synchronous rectified FET. The
ADP2165/ADP2166 combine a small size, 4 mm × 4 mm LFCSP
package with an accurate current limit, resulting in a smaller
inductor size and a high power density, point of load solution.
Rev. B
ADP2165/
ADP2166
PVIN
VPVIN
10956-001
FEATURES
80
75
70
65
60
55
VOUT = 1.8V
fSW = 600kHz
50
0
1
2
3
4
OUTPUT CURRENT (A)
5
6
10956-002
Data Sheet
5.5 V, 5 A/6 A, High Efficiency, Step-Down
DC-to-DC Regulators with Output Tracking
ADP2165/ADP2166
Figure 2. Efficiency vs. Output Current
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ADP2165/ADP2166
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Undervoltage Lockout ............................................................... 13
Applications ....................................................................................... 1
Thermal Shutdown .................................................................... 13
General Description ......................................................................... 1
Applications Information .............................................................. 14
Typical Application Circuit ............................................................. 1
ADIsimPower Design Tool ....................................................... 14
Revision History ............................................................................... 2
Input Capacitor Selection .......................................................... 14
Functional Block Diagram .............................................................. 3
Output Voltage Setting .............................................................. 14
Specifications..................................................................................... 4
Voltage Conversion Limitations ............................................... 14
Absolute Maximum Ratings ............................................................ 6
Inductor Selection ...................................................................... 15
Thermal Resistance ...................................................................... 6
Output Capacitor Selection....................................................... 15
ESD Caution .................................................................................. 6
Compensation Design ............................................................... 16
Pin Configuration and Function Descriptions ............................. 7
Design Example .............................................................................. 17
Typical Performance Characteristics ............................................. 8
Output Voltage Setting .............................................................. 17
Theory of Operation ...................................................................... 12
Frequency Setting ....................................................................... 17
Control Scheme .......................................................................... 12
Inductor Selection ...................................................................... 17
PWM Mode ................................................................................. 12
Output Capacitor Selection....................................................... 18
Enable/Shutdown ....................................................................... 12
Compensation Components ..................................................... 18
Internal Regulator (VREG) ....................................................... 12
Soft Start Time Program ........................................................... 18
Bootstrap Circuitry .................................................................... 12
Input Capacitor Selection .......................................................... 18
Oscillator and Synchronization ................................................ 12
Recommended External Components .................................... 19
Soft Start ...................................................................................... 13
Printed Circuit Board Layout Recommendations ..................... 20
Tracking ....................................................................................... 13
Reference Designs .......................................................................... 21
Power-Good (PGOOD) ............................................................. 13
Outline Dimensions ....................................................................... 23
Peak Current-Limit and Short-Circuit Protection................. 13
Ordering Guide .......................................................................... 23
Overvoltage Protection .............................................................. 13
REVISION HISTORY
8/2017—Rev. A to Rev. B
Changed LFCSP_WQ to LFCSP ..........................................Throughout
Updated Outline Dimensions ................................................................. 23
Changes to Ordering Guide..................................................................... 23
9/2016—Rev. 0 to Rev. A
Change to Compensation Components Section ........................ 18
Change to Table 8 ........................................................................... 19
8/2014—Revision 0: Initial Version
Rev. B | Page 2 of 23
Data Sheet
ADP2165/ADP2166
FUNCTIONAL BLOCK DIAGRAM
EN
EN_BUF
UVLO
1.2V
PVIN
ACS
SLOPE RAMP
Σ
+
OCP
–
IMAX
HICCUP
MODE
VPVIN
BST
COMP
ISS
0.6V
+
SS
+
TRK
+
FB
–
AMP
0.66V
–
DRIVER
SW
CLK
0.7V
0.54V
NFET1
+
CMP
–
–
OVP
CONTROL
LOGIC
VPVIN
NFET2
+
DRIVER
–
PGND
+
NEG CURRENT
+
CMP
–
+
INEG
PGOOD
AVIN
DEGLITCH
EN_BUF
CLK
OSC
RT
VREG
GND
SLOPE RAMP
10956-018
SYNC
3.3V
REGULATOR
Figure 3. ADP2165/ADP2166 Functional Block Diagram
Rev. B | Page 3 of 23
ADP2165/ADP2166
Data Sheet
SPECIFICATIONS
VPVIN = VAVIN = 5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise
noted.
Table 1.
Parameter
PVIN AND AVIN
VPVIN Voltage Range
VAVIN Voltage Range
Quiescent Current
Shutdown Current
VAVIN Undervoltage Lockout Threshold
FB
FB Regulation Voltage
Fixed Output Version
FB Bias Current
ERROR AMPLIFIER (EA)
Transconductance
EA Source Current
EA Sink Current
INTERNAL REGULATOR (VREG)
VREG Voltage
Dropout Voltage
Regulator Current Limit
SW
High-Side On Resistance 1
Symbol
VPVIN
VAVIN
IQ
ISHDN
UVLO
VFB
VOUT
IFB
No switching, fSW = 600 kHz
EN = 0 V
VAVIN rising
VAVIN falling
VPVIN = 2.7 V to 5.5 V
2.35
0.594
−1
VBST − VSW = 5 V
VBST − VSW = 3.3 V
VPVIN = 5 V
VPVIN = 3.3 V
ADP2165
ADP2166
2
25
2.6
2.5
0.6
RT pin floating
RT pin connected to VREG
RRT = 95.3 kΩ
Rev. B | Page 4 of 23
5.5
5.5
10
150
2.7
V
V
mA
µA
V
V
0.606
+1
0.1
V
%
µA
570
µS
µA
µA
3.1
3.3
140
50
3.5
V
mV
mA
19
22
15
16
8
9
2.4
100
100
29
34
23
26
9.5
10.5
mΩ
mΩ
mΩ
mΩ
A
A
A
ns
ns
620
1.2
590
715
1.32
680
1400
kHz
MHz
kHz
kHz
1400
0.4
kHz
ns
ns
V
V
4.3
µA
600
+9
100
mV
mV
nA
6.5
7.5
525
1.08
500
250
2.7
TRK = 300 mV to 500 mV
Unit
500
75
85
250
100
100
1.3
ISS
Max
430
tOFF_MIN
tON_MIN
fSW
Typ
0.01
IVREG = 10 mA
High-Side Peak Current Limit
Switching Frequency Range
SYNC
Synchronization Range
SYNC Minimum Pulse Width
SYNC Minimum Off Time
SYNC Input High Voltage
SYNC Input Low Voltage
SOFT START (SS)
SS Pull-Up Current
TRK
TRK Input Voltage Range
TRK-to-FB Offset Voltage
TRK Input Bias Current
Min
2.7
2.7
gm
ISOURCE
ISINK
Low-Side On Resistance1
Low-Side Negative Current Limit
SW Minimum Off Time 2
SW Minimum On Time2
OSCILLATOR (RT)
Switching Frequency
Test Conditions/Comments
0
−9
3.5
Data Sheet
Parameter
PGOOD
Power-Good Range
Power-Good Deglitch Time
PGOOD Leakage Current
PGOOD Output Low Voltage
EN
EN Threshold
EN Hysteresis
EN Pull-Down Resistor
THERMAL
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
1
2
ADP2165/ADP2166
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
FB rising threshold
FB rising hysteresis
FB falling threshold
FB falling hysteresis
From FB to PGOOD
VPGOOD = 5 V
IPGOOD = 1 mA
107
111
3
90.5
3
16
0.1
27
115
%
%
%
%
Clock cycles
µA
mV
1.2
100
1
1.28
87
1.12
150
25
Pin-to-pin measurement.
Guaranteed by design.
Rev. B | Page 5 of 23
94.5
1
45
V
mV
MΩ
°C
°C
ADP2165/ADP2166
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
PVIN, AVIN, EN, PGOOD, FB
SW
BST
SS, COMP, TRK, VREG, SYNC, RT
PGND to GND
Operating Junction Temperature Range
Storage Temperature Range
Soldering Conditions
Rating
−0.3 V to +6 V
−1 V to +6 V
SW + 6 V
−0.3 V to +6 V
−0.3 V to +0.3 V
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board (4-layer, JEDEC standard board) for
surface-mount packages.
Table 3. Thermal Resistance
Package Type
24-Lead LFCSP
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 6 of 23
θJA
38.3
Unit
°C/W
Data Sheet
ADP2165/ADP2166
20 PVIN
19 PVIN
22 AVIN
21 PVIN
24 VREG
23 EN
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
18 PVIN
SYNC 1
RT 2
TRK 3
ADP2165/
ADP2166
SS 4
TOP VIEW
(Not to Scale)
COMP 5
17 SW
16 SW
15 SW
14 SW
FB 6
NOTES
1. EXPOSED PAD. SOLDER THE EXPOSED
PAD TO AN EXTERNAL GROUND PLANE
UNDERNEATH THE IC FOR THERMAL
DISSIPATION.
10956-003
PGND 11
PGND 12
9
BST
PGND 10
7
8
GND
PGOOD
13 PGND
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
Mnemonic
SYNC
2
RT
3
TRK
4
5
6
7
8
9
10, 11,
12, 13
14, 15,
16, 17
18, 19,
20, 21
22
SS
COMP
FB
GND
PGOOD
BST
PGND
Description
Synchronization Input. Connect this pin to an external clock between 250 kHz and 1.4 MHz to synchronize the
switching frequency to the external clock. RT can be used to program the phase shift when synchronizing the
external clock.
Frequency Setting. Connect a resistor between the RT and GND pins to program the switching frequency between
250 kHz to 1.4 MHz. When the RT pin is floating, the frequency is set to 620 kHz, and when the RT pin is connected
to VREG, the frequency is set to 1.2 MHz.
Tracking Input. This pin can be used for tracking and sequencing. If the tracking function is not used, connect TRK
to VREG.
Soft Start Control. Connect a capacitor from the SS pin to the GND pin to program the soft start time.
Error Amplifier Output. Connect a compensation network from the COMP pin to the GND pin.
Feedback Voltage Sense Input. Connect to a resistor divider from VOUT.
Analog Ground. Connect to the ground plane.
Power-Good Output (Open-Drain). A pull-up resistor of 100 kΩ is recommended.
Supply Rail for the High-Side MOSFET Gate Drive. Place a 0.1 µF capacitor between the SW pin and the BST pin.
Power Ground. Connect this pin to the ground plane and to the output return side of the output capacitor.
SW
Switching Node.
PVIN
23
EN
24
VREG
Power Input. Connect this pin to the input power source and connect a bypass capacitor between this pin and
ground.
Bias Voltage Input Pin. Connect a bypass capacitor between this pin and GND and a small (10 Ω) resistor between
this pin and PVIN.
Precision Enable Input Pin. An external resistor divider can be used to set the turn-on threshold. To enable the
device automatically, connect the EN pin to PVIN. This pin has a 1 MΩ pull-down resistor to GND.
Internal Bias Regulator Output. It supplies the regulated voltage to the internal circuitry. Bypass the VREG pin to
the GND pin with a high quality, low ESR 1 µF ceramic capacitor.
Exposed Pad. Solder the exposed pad to an external ground plane underneath the IC for thermal dissipation.
AVIN
EPAD
Rev. B | Page 7 of 23
ADP2165/ADP2166
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VPVIN = VAVIN = 5 V, VOUT = 1.2 V, L = 1 µH, CIN = 47 µF, COUT = 100 µF, fSW = 600 kHz, unless otherwise noted.
100
100
VOUT = 2.5V
90
VOUT = 1.5V
VOUT = 1.8V V
OUT = 1.5V
85
VOUT = 1.2V
EFFICIENCY (%)
VOUT = 1.0V
80
75
70
VOUT = 1.2V
80
VOUT = 1.0V
75
70
65
65
60
60
55
55
1
2
3
4
5
6
OUTPUT CURRENT (A)
50
10956-104
0
0
1
2
3
4
5
6
OUTPUT CURRENT (A)
Figure 5. Efficiency (fSW = 600 kHz, VPVIN = 3.3 V) vs. Output Current
10956-107
INDUCTOR: WÜRTH ELEKTRONIK 744311100
INDUCTOR: WÜRTH ELEKTRONIK 744311100
50
Figure 8. Efficiency (fSW = 600 kHz, VPVIN = 5 V) vs. Output Current
100
100
95
90
90
VOUT = 2.5V
VOUT = 3.3V
VOUT = 2.5V
95
85
VOUT = 1.8V VOUT = 1.5V
80
EFFICIENCY (%)
85
VOUT = 1.2V
VOUT = 1.0V
75
70
VOUT = 1.5V
80
VOUT = 1.2V
VOUT = 1.8V
VOUT = 1.0V
75
70
65
65
60
60
55
55
INDUCTOR: WÜRTH ELEKTRONIK 744314047
INDUCTOR: WÜRTH ELEKTRONIK 744314047
0
1
2
3
4
5
6
OUTPUT CURRENT (A)
50
10956-105
50
0
1
2
3
4
5
6
OUTPUT CURRENT (A)
Figure 6. Efficiency (fSW = 1.2 MHz, VPVIN = 3.3 V) vs. Output Current
10956-108
EFFICIENCY (%)
90
VOUT = 1.8V
85
EFFICIENCY (%)
VOUT = 2.5V
VOUT = 3.3V
95
95
Figure 9. Efficiency (fSW = 1.2 MHz, VPVIN = 5 V) vs. Output Current
40
2.3
2.2
SHUTDOWN CURRENT (µA)
2.1
+125ºC
2.0
+25ºC
1.9
–40ºC
1.8
1.7
+125ºC
30
25
+25ºC
20
–40ºC
15
1.5
2.7
3.1
3.5
3.9
4.3
4.7
5.1
VPVIN (V)
5.5
10
2.7
3.1
3.5
3.9
4.3
4.7
VPVIN (V)
Figure 10. Shutdown Current vs. VPVIN
Figure 7. Quiescent Current vs. VPVIN (No Switching)
Rev. B | Page 8 of 23
5.1
5.5
10956-109
1.6
10956-106
QUIESCENT CURRENT (mA)
35
ADP2165/ADP2166
30
35
25
+125ºC
30
+25ºC
25
–40ºC
20
15
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VPVIN (V)
Figure 11. High-Side NFET Resistor vs. VPVIN (Pin-to-Pin Measurements)
–40ºC
10
5
0
2.7
3.5
3.9
4.3
4.7
5.1
5.5
Figure 14. Low-Side NFET Resistor vs. VPVIN (Pin-to-Pin Measurements)
610
604
600
SWITCHING FREQUENCY (kHz)
603
602
601
600
599
598
597
+125ºC
590
+25ºC
580
570
–40ºC
560
550
540
596
–40
0
25
85
530
2.7
10956-111
595
125
TEMPERATURE (°C)
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VPVIN (V)
Figure 12. Feedback Voltage vs. Temperature, VPVIN = 5 V
Figure 15. Switching Frequency vs. VPVIN (RRT = 95.3 kΩ)
1300
660
650
1250
640
SWITCHING FREQUENCY (kHz)
1275
+125ºC
1225
+25ºC
1200
–40°C
1175
1150
1125
+125ºC
630
620
+25ºC
610
–40ºC
600
590
580
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VPVIN (V)
Figure 13. Switching Frequency vs. VPVIN at 1.2 MHz (RT = VREG)
560
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VPVIN (V)
Figure 16. Switching Frequency vs. VPVIN at 620 kHz (RT Floating)
Rev. B | Page 9 of 23
10956-115
570
1100
2.7
10956-112
SWITCHING FREQUENCY (kHz)
3.1
VPVIN (V)
605
FEEDBACK VOLTAGE (mV)
+25ºC
15
10956-114
10
2.7
+125ºC
20
10956-113
LOW-SIDE NFET RESISTOR (mΩ)
40
10956-110
HIGH-SIDE NFET RESISTOR (mΩ)
Data Sheet
Data Sheet
9.0
10.0
8.8
9.8
8.6
9.6
+125ºC
8.2
+25ºC
8.0
7.8
–40ºC
7.6
9.2
8.8
–40ºC
8.6
8.4
7.2
8.2
3.5
3.9
4.3
4.7
5.1
5.5
VPVIN (V)
8.0
2.7
10956-116
3.1
+25ºC
9.0
7.4
7.0
2.7
+125ºC
9.4
3.1
3.9
4.3
4.7
5.1
5.5
VPVIN (V)
Figure 17. ADP2165 Peak Current Limit vs. VPVIN
Figure 20. ADP2166 Peak Current Limit vs. VPVIN
T
2
3.5
T
EN
2
EN
VOUT
VOUT
1
1
3
4
CH1 500mV BW CH2 5.00V BW
M1.00ms A CH2
CH3 5.00V BW CH4 5.00A Ω BW T 10.00%
3.80V
10956-006
4
IL
PGOOD
IL
CH1 500mV BW
CH3 5.00V BW
Figure 18. Soft Start with Full Load (600 kHz, VPVIN = 5 V)
CH2 5.0V BW
M1.00ms A CH2
CH4 2.00A Ω BW T 10.00%
3.80V
10956-009
3
PGOOD
Figure 21. Soft Start with Precharge (600 kHz, VPVIN = 5 V)
T
T
VOUT (AC)
VOUT (AC)
1
1
IOUT
IOUT
4
B
W
M200µs
A CH4
CH4 2.00A Ω BW T 30.20%
2.80A
CH1 50.0mV
B
W
M200µs
A CH4
CH4 5.00A Ω BW T 20.60%
4.60A
Figure 22. Load Transient (1.2 MHz, 0.5 A to 5.5 A Load Step)
Figure 19. Load Transient (600 kHz, 1.5 A to 4.5 A Load Step)
Rev. B | Page 10 of 23
10956-033
CH1 50.0mV
10956-016
4
10956-119
8.4
PEAK CURRENT LIMIT (A)
PEAK CURRENT LIMIT (A)
ADP2165/ADP2166
Data Sheet
ADP2165/ADP2166
T
T
1
VOUT (AC)
TRK
2
SW
FB
2
3
IL
CH4 5.00A Ω
M1.00µs
T 40.20%
A CH2
4.00V
CH2 500mV
CH3 500mV
Figure 23. Steady Waveform
M2.00ms
T 20.20%
A CH3
300mV
10956-017
B
W CH2 5.00V
CH1 5.00mV
10956-010
4
Figure 26. Tracing Function
T
T
VOUT
2
VOUT
2
SW
1
SW
1
IL
IL
4
A CH2
600mV
CH2 500mV BW
CH4 5.00A Ω
CH1 5.00V
Figure 24. Output Short
M10.0ms
T 80.40%
A CH2
600mV
10956-014
M10.0ms
T 20.40%
400mV
10956-015
CH2 500mV BW
CH4 5.00A Ω
CH1 5.00V
10956-011
4
Figure 27. Output Short Recovery
T
T
3
SYNC
3
SYNC
SW
SW
2
CH2 2.00V
CH3 5.00V
M400ns
T 20.40%
A CH3
400mV
10956-012
2
CH2 2.00V
CH3 5.00V
Figure 25. Synchronized to 1 MHz in Phase
M400ns
T 20.40%
A CH3
Figure 28. Synchronized to 1 MHz 180° Out of Phase
Rev. B | Page 11 of 23
ADP2165/ADP2166
Data Sheet
THEORY OF OPERATION
The ADP2165/ADP2166 are step-down, dc-to-dc regulators.
They use a current mode architecture with an integrated high-side
and low-side switch. They target high performance applications
that require high efficiency and design simplicity.
The ADP2165/ADP2166 can operate with an input voltage from
2.7 V to 5.5 V and regulate the output voltage down to 0.6 V.
Additional features for flexible design include programmable
switching frequency, programmable soft start, external
compensation, and enable and power-good pins. The
ADP2165/ADP2166 are also available with preset output
voltage options of 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, and 1.0 V.
CONTROL SCHEME
The ADP2165/ADP2166 use a fixed frequency, current mode
PWM control architecture for good line and load transient
performance. In fixed frequency PWM mode, adjust the duty
cycle of the integrated MOSFET to regulate the output voltage
that has a low output ripple voltage.
PWM MODE
At the start of each oscillator cycle, the high-side NFET (Nchannel MOSFET) switch turns on and transmits a positive
voltage across the inductor. Current in the inductor increases
until the current sense signal crosses the peak inductor current
level set by the voltage on the COMP pin. The high-side NFET
then turns off, and the low-side NFET synchronous rectifier
then turns on. This puts a negative voltage across the inductor,
causing the inductor current to decrease. The synchronous
rectifier stays on for the rest of the cycle.
INTERNAL REGULATOR (VREG)
The internal regulator provides a stable supply for the internal
control circuits. It is recommended to place a 1 μF ceramic
capacitor between the VREG and GND pins. The internal
regulator also includes a current-limit circuit to protect the
circuit if the maximum external load is added.
The AVIN pin provides the power supply for the internal regulator.
When device is enabled, the internal regulator is active.
BOOTSTRAP CIRCUITRY
The ADP2165/ADP2166 integrate the boot regulator to provide
the gate drive voltage for the high-side NFET. A capacitor between
the BST and SW pins is charged from the PVIN pin while the
low-side NFET is on.
Placing an X7R or X5R 0.1 μF ceramic capacitor between the
BST and SW pins is recommended.
OSCILLATOR AND SYNCHRONIZATION
The switching frequency of the ADP2165/ADP2166 can be set
by connecting a resistor between the RT pin and the GND pin.
Use the following equation to set the switching frequency:
RRT (kΩ) = 60,000/[fSW (kHz) + 10] − 5
A 191 kΩ resistor sets the frequency to 300 kHz, and a 93.1 kΩ
resistor sets frequency to 600 kHz. Figure 29 shows the typical
relationship between RRT and fSW.
1600
1400
ENABLE/SHUTDOWN
1200
FREQUENCY (kHz)
The EN input pin has a precision analog threshold of 1.2 V
(typical) with 100 mV of hysteresis. When the enable voltage
exceeds 1.2 V, the regulator turns on, and when it falls below
1.1 V (typical), the regulator turns off. To force the devices to
automatically start when input power is applied, connect the EN
pin to the PVIN pin.
1000
800
600
When the ADP2165/ADP2166 are shut down, the soft start
capacitor discharges. When the devices are reenabled, a new
soft start cycle begins.
200
20
40
60
80
100
120
140
RRT (kΩ)
If the EN pin is not externally connected, an internal pull-down
resistor (1 MΩ) prevents an accidental enable.
160
180
10956-019
400
Figure 29. Frequency (fSW) vs. RT Resistor
To synchronize the ADP2165/ADP2166, drive an external clock
at the SYNC pin. The frequency of the external clock can be in
the 250 kHz to 1.4 MHz range.
During the synchronization, the RT pin can be used to program
the phase shift. When the RT pin is connected to the VREG pin,
the rising edge of the SW pin is 180° out of phase with the external
clock. If the RT pin is floating, the rising edge of the SW pin is in
phase with the external clock.
Rev. B | Page 12 of 23
Data Sheet
ADP2165/ADP2166
SOFT START
The SS pin is used to program the soft start time. By connecting
a capacitor between the SS and GND pins, the internal current
then charges this capacitor and establishes the soft start ramp-up.
The soft start time can be calculated by the following equation:
t SS =
0.6V × CSS
I SS
where:
CSS is the soft start capacitance.
ISS is the soft start pull-up current (3.5 µA).
If the output voltage is precharged prior to startup, the
ADP2165/ADP2166 prevent reverse inductor current that
discharges the output capacitor until the soft start voltage
exceeds the voltage on the FB pin.
PEAK CURRENT-LIMIT AND SHORT-CIRCUIT
PROTECTION
The ADP2165/ADP2166 have a peak current-limit protection
circuit to prevent current runaway. When the inductor peak
current reaches the current-limit value, the high-side NFET
turns off, and the low-side NFET turns on until the next cycle,
while the overcurrent counter increments. If the overcurrent
counter count exceeds 10, the device enters hiccup mode, and
the high-side NFET and low-side NFET both turn off. The
devices remain in this mode for seven times the soft start time
and then attempt to restart from the soft start. If the currentlimit fault clears, the devices resume normal operation.
Otherwise, they reenter hiccup mode after counting 10 currentlimit violations.
OVERVOLTAGE PROTECTION
When the channel is disabled or a current fault happens, the
soft start capacitor discharges.
TRACKING
The ADP2165/ADP2166 have a tracking input feature, TRK,
that allows the output voltage to track another voltage (master
voltage). It is especially useful in core and I/O voltage tracking for
field programmable gate arrays (FPGAs), digital signal processors
(DSPs), and application specific integrated circuits (ASICs).
The internal error amplifier includes three positive inputs: the
internal reference voltage, the soft start voltage, and the TRK
voltage. The error amplifier regulates the FB voltage to the
lowest of the three voltages. To track a master voltage, tie the
TRK pin to a resistor divider from the master voltage.
If the TRK function is not used, connect the TRK pin to the VREG.
POWER-GOOD (PGOOD)
The PGOOD pin is an active high, open-drain output that requires
a pull-up resistor. A logic high on the PGOOD pin indicates
that the voltage on the FB pin (and, therefore, the output
voltage) is within ±10% of the desired value. In addition, there is a
16-cycle waiting period after the FB pin is detected as being
within the ±10% range. A logic low on the PGOOD pin indicates
that the voltage on the FB pin is not within ±10% of the desired
value. Similarly, there is a 16-cycle delay to deassert PGOOD.
The ADP2165/ADP2166 provide an overvoltage protection
feature that protects the system from an output short to a higher
voltage supply or from a strong unload transient. If the feedback
voltage increases to 0.7 V, the internal high-side NFET turns off
and the low-side NFET turns on until the current through the
low-side NFET reaches the negative current limit. Thereafter, both
the high-side and low-side NFET are held in the off state until
the voltage at FB decreases to 0.63 V, and the devices resume
normal operation.
UNDERVOLTAGE LOCKOUT
Undervoltage lockout circuitry is integrated in the ADP2165/
ADP2166. If AVIN drops below 2.5 V, the devices turn off.
When the AVIN voltage rises above 2.6 V, the soft start period
initiates, and the devices are enabled.
THERMAL SHUTDOWN
In the event that the junction temperatures of the ADP2165/
ADP2166 rise above 150°C, the thermal shutdown circuit turns
the regulator off. Extreme junction temperatures can be the result
of high current operation, poor circuit board design, and/or
high ambient temperature. A 25°C hysteresis is included so that
when thermal shutdown occurs, the ADP2165/ADP2166 do not
return to operation until the on-chip temperature drops below
125°C. When coming out of thermal shutdown, soft start initiates.
Rev. B | Page 13 of 23
ADP2165/ADP2166
Data Sheet
APPLICATIONS INFORMATION
ADIsimPOWER DESIGN TOOL
VOLTAGE CONVERSION LIMITATIONS
The ADP2165/ADP2166 are supported by the ADIsimPower
design tool set. ADIsimPower is a collection of tools that produce
complete power designs optimized to a specific design goal. The
tools allow the user to generate a full schematic, bill of materials,
and calculate performance in minutes. ADIsimPower can optimize
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into consideration the operating conditions and limitations of
the IC and all real external components. The ADIsimPower tool
can be found at www.analog.com/ADIsimPower, and the user
can request an unpopulated board through the tool.
The minimum output voltage for a given input voltage and
switching frequency is constrained by the minimum on time.
The minimum on time of the ADP2165/ADP2166 is typically
100 ns. The minimum output voltage at a given input voltage
and frequency can be calculated using the following equation:
INPUT CAPACITOR SELECTION
The input capacitor reduces the input voltage ripple caused by
the switch current on the PVIN pin. Place the input capacitor as
close as possible to the PVIN pin. A ceramic capacitor in the 10 µF
to 47 µF range is recommended. The loop that is composed of
this input capacitor, the high-side NFET, and the low-side NFET
must be kept as small as possible.
The voltage rating of the input capacitor must be greater than the
maximum input voltage. The rms current rating of the input
capacitor must be larger than the value calculated by the
following equation:
I C IN_RMS = I OUT × D × (1 − D)
OUTPUT VOLTAGE SETTING
To limit the output voltage accuracy degradation due to FB bias
current (0.1 µA maximum) to less than 0.5% (maximum), ensure
that RBOT < 30 kΩ.
Table 5 lists the recommended resistor divider for various output
voltages.
VOUT (V)
1.0
1.2
1.5
1.8
2.5
3.3
RTOP ± 1% (kΩ)
10
10
15
20
47.5
10
RBOT ± 1% (kΩ)
15
10
10
10
15
2.21
The maximum output voltage for a given input voltage and
switching frequency is constrained by the minimum off time
and the maximum duty cycle. The minimum off time is typically
100 ns, and the maximum duty cycle of the ADP2165/ADP2166
is typically 90%.
The maximum output voltage, limited by the minimum off time
at a given input voltage and frequency, can be calculated using
the following equation:
where:
VOUT_MAX is the maximum output voltage.
tOFF_MIN is the minimum off time.
IOUT_MAX is the maximum output current.
Table 5. Resistor Divider for Various Output Voltages
where:
VOUT_MIN is the minimum output voltage.
tON_MIN is the minimum on time.
IOUT_MIN is the minimum output current.
fSW is the switching frequency.
RDSON_HS is the high-side MOSFET on resistance.
RDSON_LS is the low-side MOSFET on resistance.
RL is the series resistance of the output inductor.
VOUT_MAX = VPVIN × (1 − tOFF_MIN × fSW) − (RDSON_HS − RDSON_LS) ×
IOUT_MAX × (1 − tOFF_MIN × fSW) − (RDSON_LS + RL) × IOUT_MAX (2)
The output voltage of the ADP2165/ADP2166 is set by an
external resistive divider. The resistor values are calculated
using the following equation:
R
VOUT = 0.6 × 1 + TOP
R
BOT
VOUT_MIN = VPVIN × tON_MIN × fSW − (RDSON_HS − RDSON_LS) ×
IOUT_MIN × tON_MIN × fSW − (RDSON_LS + RL) × IOUT_MIN
(1)
The maximum output voltage, limited by the maximum duty
cycle at a given input voltage, can be calculated using the
following equation:
VOUT_MAX = DMAX × VPVIN
where DMAX is the maximum duty cycle.
As Equation 1 to Equation 3 show, reducing the switching
frequency alleviates the minimum on time and minimum off
time limitation.
Rev. B | Page 14 of 23
(3)
Data Sheet
ADP2165/ADP2166
INDUCTOR SELECTION
The inductor value is determined by the operating frequency,
input voltage, output voltage, and inductor ripple current. Using
a small inductor leads to a faster transient response; however, it
degrades efficiency due to a larger inductor ripple current.
Conversely, using a large inductor value leads to a smaller ripple
current and better efficiency; however, it results in a slower
transient response.
Shielded ferrite core materials are recommended for low core
loss and low EMI. Table 6 lists some recommended inductors.
Table 6. Recommended Inductors
Vendor
Würth
Elektronik
As a guideline, the inductor ripple current, ΔIL, is typically set
to one-third of the maximum load current. The inductor value
is calculated using the following equation:
L=
(VPVIN − VOUT ) × D
Coilcraft
∆I L × f SW
where:
VPVIN is the input voltage.
VOUT is the output voltage.
ΔIL is the inductor ripple current.
fSW is the switching frequency.
D is the duty cycle, D = VOUT/VPVIN.
The ADP2165/ADP2166 use adaptive slope compensation in
the current loop to prevent subharmonic oscillations when the
duty cycle is larger than 50%. The internal slope compensation
limits the minimum inductor value.
For a duty cycle that is larger than 50%, the minimum inductor
value is determined by using the following equation:
L (Minimum) =
VOUT × (1 − D)
4 × f SW
The saturation current of the inductor must be larger than the peak
inductor current. For ferrite core inductors with a quick saturation
characteristic, the saturation current rating of the inductor must
be higher than the current limit threshold of the switch. This
prevents the inductor from reaching saturation.
The rms current of the inductor is calculated from the following
equation:
IRMS =
I OUT 2 +
∆I L 2
12
L
(µH)
0.22
0.47
0.76
1.0
1.5
2.2
3.3
0.27
0.33
0.47
0.68
1.0
1.5
2.2
ISAT
(A)
32
20
15
19
14
12.5
8.5
30
28
24.3
22.3
16.4
23.5
18
IRMS
(A)
21
18
15.5
15
11
16.5
14
21
20
17
13
11
15
12.9
DCR
(mΩ)
1.10
1.35
2.25
4.6
6.6
4.4
6.5
2.9
4.0
4.75
7.9
9.8
7.6
13.7
OUTPUT CAPACITOR SELECTION
The output capacitor selection affects the output ripple voltage
load step transient and the loop stability of the regulator.
For example, during a load step transient where the load is
suddenly increased, the output capacitor supplies the load until
the control loop can ramp up the inductor current. The delay
caused by the control loop causes the output to undershoot. The
output capacitance that is required to satisfy the voltage droop
requirement can be calculated by using the following equation:
The peak inductor current is calculated by using the following
equation:
∆I L
IPEAK = IOUT +
2
Part No.
744311022
744314047
744314076
744311100
744311150
7443340220
7443340330
XAL7020-271ME
XAL7020-331ME
XAL7020-471ME
XAL7020-681ME
XAL7020-102ME
XAL7030-152ME
XAL7030-222ME
COUT_UV =
K UV × ∆I STEP 2 × L
2 × (VPVIN − VOUT ) × ∆VOUT _UV
where:
KUV is a factor, with a typical setting of KUV = 2.
ΔISTEP is the load step.
ΔVOUT_UV is the allowable undershoot on the output voltage.
Another example occurs when a load is suddenly removed from
the output, and the energy stored in the inductor rushes into
the output capacitor, causing the output to overshoot.
The output capacitance that is required to meet the overshoot
requirement can be calculated using the following equation:
COUT_OV =
K OV × ∆I STEP 2 × L
(VOUT + ∆VOUT _ OV )2 − VOUT 2
where:
KOV is a factor, with a typical setting of KOV = 2.
ΔVOUT_OV is the allowable overshoot on the output voltage.
Rev. B | Page 15 of 23
ADP2165/ADP2166
Data Sheet
The ESR and the value of the capacitance determine the output
ripple. Use the following equation to select a capacitor that can
meet the output ripple requirements:
∆I L
COUT_RIPPLE =
8 × f SW × ∆VOUT _ RIPPLE
RESR =
TV (S) =
The following design guideline shows how to select the RC, CC,
and CCP compensation components for the ceramic output
capacitor applications:
1.
The selected output capacitor voltage rating must be greater
than the output voltage. The rms current rating of the output
capacitor must be larger than the value calculated by
∆I
ICOUT_RMS = L
12
2.
3.
For peak current mode control, the power stage can be simplified
as a voltage controlled current source supplying current to the
output capacitor and load resistor. It is composed of one domain
pole and a zero that is contributed by the output capacitor ESR.
The control to output transfer function is based on the following:
s
1+
2× π× fZ
V (s )
GVD (S) = OUT
= AVI × R ×
s
VCOMP (s)
1+
2× π× fP
4.
2 × π × RESR × COUT
VOUT
R ESR × COUT
RC
The fixed output version IC must consider the feedforward
capacitance of feedback resistor (RTOP) to calculate CCP.
The total internal feedback resistance is 1 MΩ.
f FBZ =
AVI
1
2π × C F × ( 1 R
R
RESR
10956-020
CC
Figure 30. Simplified Peak Current Mode Control, Small Signal Circuit
Rev. B | Page 16 of 23
+ 1R )
BOT
1
2π × RTOP × C F
(
C C × min f P , f FBP × f FBZ
(
)
RC × C C − C C × min f P , f FBP × f FBZ
where CF = 8.14 pF.
COUT
f FBP × f FBZ .
Then, determine CCP by
C CP =
RTOP
–
CCP =
TOP
VOUT
CCP
RC
CCP is optional. It can be used to cancel the zero caused by
the ESR of the output capacitor.
f FBP =
The ADP2165/ADP2166 use a transconductance amplifier for the
error amplifier, which compensates for the system loop. Figure 30
shows the simplified, peak current mode control, small signal circuit.
RC
(R + R ESR ) × COUT
between the domain pole, fP, and
where:
AVI = 10 A/V.
R is the load resistance.
COUT is the output capacitance.
RESR is the equivalent series resistance of the output capacitor.
RBOT
0.6 V × g m × AVI
First, place the compensation pole at the minimum value
1
2 × π × (R + RESR ) × COUT
+
2 × π × VOUT × COUT × f C
Place the compensation zero at the domain pole, fP; then
determine CC by using the following equation:
CC =
1
VCOMP
Determine the cross frequency, fC. Generally, fC is between
fSW/12 and fSW/6.
Calculate RC by using the following equation:
RC =
COMPENSATION DESIGN
–
gm
+
RBOT
−gm
×
×
RBOT + RTOP CC + CCP
1 + RC × CC × s
× GVD ( s )
R × CC × CCP
s × (1 + C
× s)
CC + CCP
Select the largest output capacitance given by COUT_UV, COUT_OV,
and COUT_RIPPLE to meet both the load transient and the output
ripple performance.
fP =
The loop gain transfer equation is as follows:
∆VOUT _ RIPPLE
∆I L
where:
ΔVOUT_RIPPLE is the allowable output ripple voltage.
RESR is the equivalent series resistance of the output capacitor
in ohms (Ω).
fZ =
The compensation components, RC and CC, contribute a zero,
and the optional CCP and RC contribute an optional pole.
)
Data Sheet
ADP2165/ADP2166
DESIGN EXAMPLE
ADP2166
CIN
47µF
16V
BST
PVIN
CBST
0.1µF
AVIN
L1
0.47µH
SYNC
COUT2
100µF
6.3V
FB
RT
COMP
CCP
4.7pF
TRK
CVREG
1µF
COUT1
100µF
6.3V
RTOP
10kΩ
PGOOD
VREG
GND
VOUT = 1.2V
SW
EN
SS
CSS
22nF
PGND
RC
RBOT
36kΩ
10kΩ
CC
680pF
10956-021
VPVIN = 5V
Figure 31. Schematic for Design Example
This section describes the procedures for selecting the external
components based on the example specifications listed in Table 7.
See Figure 31 for the schematic of this design example.
Table 7. Step-Down DC-to-DC Regulator Requirements
Parameter
Input Voltage
Output Voltage
Output Current
Output Voltage Ripple
Load Transient
Switching Frequency
Specification
VPVIN = 5.0 V ± 10%
VOUT = 1.2 V
IOUT = 6 A
∆VOUT_RIPPLE = 12 mV
±5%, 1 A to 5 A, 2 A/µs
fSW = 1.2 MHz
This calculation results in L = 0.422 µH. Choose the standard
inductor value of 0.47 µH.
The peak-to-peak inductor ripple current can be calculated by
using the following equation:
ΔIL =
Use the following equation to calculate the peak inductor
current:
IPEAK = IOUT +
Choose a 10 kΩ resistor as the top feedback resistor (RTOP)
and calculate the bottom feedback resistor (RBOT) by using the
following equation:
∆I L
2
This calculation results in IPEAK = 6.809 A.
Use the following equation to calculate the rms current flowing
through the inductor:
0. 6
RBOT = RTOP ×
V
OUT − 0.6
IRMS =
IOUT 2 +
∆I L 2
12
This calculation results in IRMS = 6.018 A.
To set the output voltage to 1.2 V, the resistor values are as
follows: RTOP = 10 kΩ and RBOT = 10 kΩ.
FREQUENCY SETTING
To use the fixed 1.2 MHz switching frequency, connect the RT
pin to the VREG pin.
INDUCTOR SELECTION
The peak-to-peak inductor ripple current, ∆IL, is set to 30% of
the maximum output current. Use the following equation to
estimate the inductor value:
(VPVIN − VOUT ) × D
L × f SW
This calculation results in ∆IL = 1.617 A.
OUTPUT VOLTAGE SETTING
L=
(VIN − VOUT ) × D
Based on the calculated current value, select an inductor with
a minimum rms current rating of 6.03 A and a minimum
saturation current rating of 6.9 A.
However, to protect the inductor from reaching its saturation
point under the current-limit condition, use an inductor that is
rated for at least a 9 A saturation current for reliable operation.
Based on the requirements described previously, select a 0.47 µH
inductor, such as the 744314047 from Würth, which has a 1.35 mΩ
DCR and a 20 A saturation current.
∆I L × f SW
where:
VPVIN = 5 V.
VOUT = 1.2 V.
D = 0.24.
∆IL = 1.8 A.
fSW = 1.2 MHz.
Rev. B | Page 17 of 23
ADP2165/ADP2166
Data Sheet
OUTPUT CAPACITOR SELECTION
COMPENSATION COMPONENTS
The output capacitor is required to meet both the output voltage
ripple and load transient response requirements.
For better load transient and stability performance, set the cross
frequency, fC, to fSW/10. In this case, fSW is running at 1200 kHz;
therefore, the fC is set to 120 kHz.
To meet the output voltage ripple requirement, use the following
equation to calculate the ESR and capacitance value of the output
capacitor:
COUT_RIPPLE =
RESR =
The 100 µF and 47 µF ceramic output capacitors have a derated
value of 62 µF and 32 µF.
∆I L
8 × f S × ∆VOUT _ RIPPLE
RC =
∆VOUT _ RIPPLE
CC =
∆I L
This calculation results in COUT_RIPPLE = 14 µF and RESR = 7.4 mΩ.
To meet the ±5% overshoot and undershoot transient
requirements, use the following equations to calculate the
capacitance:
COUT_OV =
COUT_UV =
CCP =
2 × π × 1.2 V × 94 μF × 120 kHz
0.6 V × 500 μs × 10 A/V
(0.2 Ω + 0.002 Ω) × 94 μF
28.35 kΩ
0.002 Ω × 94 μF
28.35 kΩ
= 28.35 kΩ
= 669.8 pF
= 6.63 pF
Choose standard components as follows: RC = 27 kΩ, CC = 680 pF,
and CCP = 4.7 pF.
K OV × ∆I STEP 2 × L
SOFT START TIME PROGRAM
(VOUT + ∆VOUT _ OV )2 − VOUT 2
The soft start feature allows the output voltage to ramp up in a
controlled manner, eliminating output voltage overshoot during
soft start and limiting the inrush current. Set the soft start time
to 4 ms.
K UV × ∆I STEP 2 × L
2 × (VPVIN − VOUT ) × ∆VOUT _UV
where:
KOV = KUV = 2, the coefficients for estimation purposes.
∆ISTEP = 4 A, the load transient step.
∆VOUT_OV = 5% × VOUT, the overshoot voltage.
∆VOUT_UV = 5% × VOUT, the undershoot voltage.
CSS =
t SS _ EXT × I SS _ UP
0. 6
=
4 ms × 3.5 μA
0. 6 V
= 23.3 nF
Choose a standard component value as follows: CSS = 22 nF.
This calculation results in COUT_OV = 100 µF and COUT_UV = 33 µF.
According to the calculation, the output capacitance must be
greater than 100 µF, and the ESR of the output capacitor must be
smaller than 7.4 mΩ. It is recommended that one 100 µF, X5R,
6.3 V ceramic capacitor and one 47 µF, X5R, 6.3 V ceramic
capacitor be used, such as the GRM32ER60J107ME20 and
GRM32ER60J476ME20 from Murata, with an ESR of 2 mΩ.
INPUT CAPACITOR SELECTION
A minimum 22 µF ceramic capacitor must be placed near the
PVIN pin. In this application, it is recommended that one 47 µF,
X5R, 16 V ceramic capacitor be used.
Rev. B | Page 18 of 23
Data Sheet
ADP2165/ADP2166
RECOMMENDED EXTERNAL COMPONENTS
Table 8. Recommended External Components for Typical Applications with 6 A Output Current
fSW (kHz)
300
600
1200
1
VPVIN (V)
3.3
3.3
3.3
3.3
3.3
5
5
5
5
5
5
3.3
3.3
3.3
3.3
3.3
5
5
5
5
5
5
3.3
3.3
3.3
3.3
3.3
5
5
5
5
5
5
VOUT (V)
1
1.2
1.5
1.8
2.5
1
1.2
1.5
1.8
2.5
3.3
1
1.2
1.5
1.8
2.5
1
1.2
1.5
1.8
2.5
3.3
1
1.2
1.5
1.8
2.5
1
1.2
1.5
1.8
2.5
3.3
L (µH)
1.5
1.5
2.2
2.2
1.5
1.5
2.2
2.2
2.2
3.3
2.2
0.6
0.82
0.82
0.82
0.6
0.82
0.82
1
1
1.5
1
0.33
0.47
0.47
0.47
0.33
0.47
0.47
0.47
0.6
0.6
0.6
COUT (µF) 1
680 + 330
680 + 47
680
470 + 100
470 + 47
680 + 330
680 + 470
680
470
330 + 47
3 × 100
330 + 47
330 + 47
2 × 100 + 47
2 × 100
2 × 100
470 + 100
330 + 47
330
2 × 100
100 + 47
100
2 × 100
2 × 100
100 + 47
100
100
330
2 × 100
100 + 47
100
100
100
RTOP (kΩ)
10
10
15
20
47.5
10
10
15
20
47.5
10
10
10
15
20
47.5
10
10
15
20
47.5
10
10
10
15
20
47.5
10
10
15
20
47.5
10
RBOT (kΩ)
15
10
10
10
15
15
10
10
10
15
2.21
15
10
10
10
15
15
10
10
10
15
2.21
15
10
10
10
15
15
10
10
10
15
2.21
RC (kΩ)
52.9
44.7
53.4
50.1
65.7
52.9
72.3
53.4
44.3
47.4
32.1
45.5
54.6
29.4
28.0
39.0
66.9
54.6
62.2
28.0
39.0
25.7
31.2
37.4
35.4
28.0
39.0
82.9
37.4
35.4
28.0
19.6
51.4
CC (pF)
3300
3300
3300
3300
3300
3300
3300
3300
3300
3300
3300
1600
1500
1300
1300
1300
1300
1500
1500
1300
1300
1300
680
680
680
680
680
680
680
680
680
680
680
CCP (pF)
134
111
89
85
61
668
64
89
85
267
12
279
232
11
9
6
64
232
186
9
6
5
8
7
5
4
3
139
7
5
4
3
2
680 µF: 2.5 V, KEMET T520D687M2R5ATE010; 470 µF: 2.5 V, KEMET T520D477M2R5ATE006; 330 µF: 2.5 V, KEMET T520D337M2R5ATE006; 220 µF: 2.5 V, KEMET
T520D227M2R5ATE007; 330 µF: 4 V, KEMET T520D337M004ATE006; 100 µF: 6.3 V, X5R, Murata GRM32ER60J107ME20; 47 µF: 6.3 V, X5R, Murata GRM32ER60J476ME20.
VOUT is higher than 1.5 V, and COUT must use a 4 V tantalum capacitor.
Rev. B | Page 19 of 23
ADP2165/ADP2166
Data Sheet
PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS
•
Good circuit board layout is essential for obtaining the best
performance from the ADP2165/ADP2166. Poor printed
circuit board (PCB) layout degrades the output regulation as
well as the electromagnetic interface (EMI) and electromagnetic
compatibility (EMC) performance. Figure 32 shows a PCB layout
example. For optimum layout, use the following guidelines:
ANALOG GROUND PLANE
VIA
CCS
CC
BOTTOM LAYER
TRACE
GND
SYNC
RT
TRK
SS
COMP
FB
RTOP
PULL-UP
CVREG
COPPER PLANE
RC
CCP
POWER GROUND PLANE
VREG
EN
GND
PGOOD
PVIN
PGND
PVIN
PGND
PVIN
SW
PVIN
OUTPUT
CAPACITOR
SW
AVIN
SW
POWER GROUND
PLANE
BST
CBST
PGND
SW
SW
PGND
INPUT
BYPASS
CAPACITOR
INPUT
BULK
CAPACITOR
PVIN
SW
INDUCTOR
10956-022
•
Place the feedback resistor divider network as close as possible to
the FB pin to prevent noise pickup. Try to minimize the length of
the trace that connects the top of the feedback resistor divider
to the output while keeping the trace away from the high current
traces and the switching node to avoid noise pickup. To further
reduce noise pickup, place an analog ground plane on either side of
the FB trace and ensure that the trace is as short as possible to
reduce parasitic capacitance pickup.
Use separate analog ground and power ground planes.
Connect the ground reference of sensitive analog circuitry,
such as output voltage divider components, to analog
ground. In addition, connect the ground reference of
power components, such as input and output capacitors, to
power ground. Connect both ground planes to the exposed
pad of the ADP2165/ADP2166.
Place the input capacitor, inductor, and output capacitor as
close to the IC as possible and use short traces.
Ensure that the high current loop traces are as short and as
wide as possible. Make the high current path from the input
capacitor through the inductor, the output capacitor, and the
power ground plane back to the input capacitor as short as
possible. To accomplish this, ensure that the input and output
capacitors share a common power ground plane.
RBOT
•
Connect the exposed pad of the ADP2165/ADP2166 to
a large copper plane to maximize its power dissipation
capability for better thermal dissipation.
VOUT
Figure 32. Recommended PCB Layout
Rev. B | Page 20 of 23
Data Sheet
ADP2165/ADP2166
REFERENCE DESIGNS
See Figure 33 through Figure 36 for the detailed reference designs.
ADP2165/
ADP2166
PVIN
CIN
47µF
16V
BST
CBST
0.1µF
AVIN
L1
0.82µH
COUT
470µF
6.3V
RTOP
10kΩ
PGOOD
RT
FB
SYNC
COMP
TRK
CVREG
1µF
VOUT = 1.2V
SW
EN
RC
RBOT
33kΩ
10kΩ
CC
1.5nF
CCP
33pF
SS
VREG
GND
CSS
22nF
PGND
10956-023
VPVIN = 5V
Figure 33. 1.2 V, 5 A/6 A, 620 kHz by Floating the RT Pin Step-Down Regulator Application
ADP2165/
ADP2166
PVIN
CIN
47µF
16V
BST
CBST
0.1µF
AVIN
L1
0.6µH
SYNC
FB
RT
COMP
TRK
CVREG
1µF
COUT
100µF
6.3V
RTOP
20kΩ
PGOOD
1.2MHz
EXT CLOCK
VOUT = 1.8V
SW
EN
CCP
3.3pF
SS
VREG
GND
CSS
22nF
PGND
RC
RBOT
27kΩ
10kΩ
CC
680pF
10956-024
VPVIN = 5V
Figure 34. 1.8 V, 5 A/6 A Step-Down Regulator Application, Synchronized to 1.2 MHz, 180° Out of Phase with the External Clock
CIN
47µF
16V
PVIN
BST
AVIN
CBST
0.1µF
EN
RTRKT
10kΩ
SYNC
TRK
RTRKB
2.21kΩ
RT
CVREG
1µF
VREG
GND
VOUT = 3.3V
RTOP
10kΩ
PGOOD
VMASTER
L1
0.82µH
SW
COUT
100µF
6.3V
FB
COMP
SS
PGND
CCP
1.8pF
CSS
22nF
RC
RBOT
51kΩ
2.21kΩ
CC
680pF
Figure 35. 3.3 V, 5 A/6 A, 1.2 MHz Step-Down Regulator Application, Tracking Mode
Rev. B | Page 21 of 23
10956-025
VPVIN = 5V
ADP2165/
ADP2166
ADP2165/ADP2166
Data Sheet
CIN
47µF
16V
PVIN
BST
AVIN
CBST
0.1µF
L1
0.47µH
SW
EN
COUT1
100µF
6.3V
PGOOD
SYNC
RT
RT
43.5kΩ
CVREG
1µF
COUT2
100µF
6.3V
FB
COMP
TRK
VREG
GND
VOUT = 1.2V
SS
PGND
CCP
4.7pF
CSS
22nF
RC
36kΩ
CC
680pF
Figure 36. Fixed Output 1.2 V, 5 A/6 A, 1.2 MHz Step-Down Regulator Application
Rev. B | Page 22 of 23
10956-026
VPVIN = 5V
ADP2165/
ADP2166
Data Sheet
ADP2165/ADP2166
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
4.10
4.00 SQ
3.90
1
0.50
BSC
2.70
2.60 SQ
2.50
EXPOSED
PAD
13
0.50
0.40
0.30
TOP VIEW
0.80
0.75
0.70
6
12
7
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
PKG-004273/5069
SEATING
PLANE
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
24
19
18
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8
03-02-2017-A
PIN 1
INDICATOR
0.30
0.25
0.18
Figure 37. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-15)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADP2165ACPZ-R7
ADP2165ACPZ-1.0-R7
ADP2165ACPZ-1.2-R7
ADP2165ACPZ-1.5-R7
ADP2165ACPZ-1.8-R7
ADP2165ACPZ-2.5-R7
ADP2165ACPZ-3.3-R7
ADP2165-EVALZ
ADP2166ACPZ-R7
ADP2166ACPZ-1.0-R7
ADP2166ACPZ-1.2-R7
ADP2166ACPZ-1.5-R7
ADP2166ACPZ-1.8-R7
ADP2166ACPZ-2.5-R7
ADP2166ACPZ-3.3-R7
ADP2166-EVALZ
1
Output Current (A)
5
5
5
5
5
5
5
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Output Voltage
ADJ
1.0 V
1.2 V
1.5V
1.8 V
2.5 V
3.3 V
6
6
6
6
6
6
6
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
ADJ
1.0 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
Z = RoHS Compliant Part.
©2014–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10956-0-8/17(B)
Rev. B | Page 23 of 23
Package Description
24-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
Evaluation Board
24-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
Evaluation Board
Package Option
CP-24-15
CP-24-15
CP-24-15
CP-24-15
CP-24-15
CP-24-15
CP-24-15
CP-24-15
CP-24-15
CP-24-15
CP-24-15
CP-24-15
CP-24-15
CP-24-15
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