50 mA, 60 V,
High Efficiency Buck Regulator
ADP2360
Data Sheet
FEATURES
TYPICAL APPLICATION CIRCUIT
ADP2360
VIN
8
L1
VIN
RPG
PG
ON
OFF
CSS
VOUT
SW 7
CIN
FB 4
2
PG
1
EN
5
SS
COUT
ITH 3
RITH
PGND
AGND
(EPAD)
6
9
13944-001
Input voltage supply range: 4.5 V to 60 V
Adjustable output voltage range: 0.8 V to VIN
Factory-programmable fixed output voltage options of
3.3 V and 5.0 V
Continuous output current up to 50 mA
Adjustable peak inductor current limit up to 140 mA
Pulse frequency modulation (PFM) control
Very high efficiency
90% at VIN = 9 V, VOUT = 3.3 V, IOUT = 10 mA
87% at VIN = 9 V, VOUT = 3.3 V, IOUT = 1 mA
Low shutdown current: VFB_RISING
During switching cycle, FB < VFB_FALLING
VEN = 0 V, TJ = −40°C to +85°C
IQ_ACTIVE
IQ_SHUTDOWN
VUVLO_RISING
VUVLO_FALLING
ISS
VSS = 0 V
VEN
VEN_RISING
VEN_HYS
IEN_LEAKAGE
VEN_SHUTDOWN
VOUT
VFB_FALLING
FB Rising Threshold
VFB_RISING
FB Pin Current
IFB
SWITCH (SW) PARAMETERS
On Resistance
Positive Metal Oxide Semiconductor (PMOS)
Negative Metal Oxide Semiconductor (NMOS)
Leakage Current
PMOS
NMOS
Discharge Resistor
INDUCTOR CURRENT LIMIT
ITH Threshold Voltage
Peak Current Limit
Minimum PMOS on Time
POWER GOOD (PG)
PG Pin Voltage Range
PG Pin Pull-Down Resistance
Rising Threshold
RDSON_P
RDSON_N
Min
4.5
Typ
Max
60
Unit
V
12
23
µA
140
0.8
165
4
µA
µA
4.3
4.1
4.4
4.2
4.5
4.3
V
V
0.75
1
1.25
µA
60
1.05
0.5
0.7
V
V
mV
µA
V
0.800
3.300
5.000
0.803
3.317
5.025
0.005
1.15
VIN
0.808
3.333
5.050
0.812
3.349
5.075
0.1
1.5
V
V
V
V
V
V
V
µA
µA
4
2
8
4
Ω
Ω
1
1
µA
µA
kΩ
1.018
154
55
V
mA
mA
ns
60
1.5
0.760
3.135
4.750
V
kΩ
V
V
V
0
0.95
VIN = VEN = 60 V
0.35
Adjustable output voltage model
Fixed 3.3 V output voltage model
Fixed 5.0 V output voltage model
Adjustable output voltage model
Fixed 3.3 V output voltage model
Fixed 5.0 V output voltage model
Adjustable output voltage models
Fixed output voltage models
0.8
0.792
3.267
4.950
0.794
3.284
4.975
ISW = 50 mA
ISW = 50 mA
VSW = 0 V
VSW = 24 V
EN = 0 V
VITH
IPEAK
tPMOS (MIN)
VPG
RPG
VPG_RISING
RITH = 0 Ω, at power-up
RITH = open, at power-up
ISW = 20 mA, RITH = open
1
50
0.1
0.57
100
0.967
126
45
1
140
50
35
0
Adjustable output voltage model
Fixed 3.3 V output voltage model
Fixed 5.0 V output voltage model
Rev. A | Page 3 of 15
1.0
0.740
3.053
4.625
ADP2360
Data Sheet
Parameters
Hysteresis
Symbol
VPG_HYS
Leakage Current
THERMAL SHUTDOWN
Rising Threshold
Hysteresis
IPG_LEAKAGE
Test Conditions/Comments
Adjustable output voltage model
Fixed 3.3 V output voltage model
Fixed 5.0 V output voltage model
VPG = 24 V
TSHDN
THYS
Min
Typ
40
165
250
0.06
150
15
Rev. A | Page 4 of 15
Max
0.5
Unit
mV
mV
mV
µA
°C
°C
Data Sheet
ADP2360
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
VIN, EN, PG, to AGND, PGND
FB to AGND, PGND
SW to AGND, PGND
ITH, SS to AGND, PGND
Operating Junction Temperature Range
Storage Temperature Range
Soldering Conditions
Rating
−0.3 V to +61 V
−0.3 V to +5.5 V
−0.3 V to VIN + 0.3 V
−0.3 V to +4 V
−40°C to +125°C
–65°C to +150°C
JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
θJA is specified for the worst case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
For additional information on thermal resistance, refer to
Application Note AN-000, Thermal Characteristics of IC
Assembly.
Table 3. Thermal Resistance
Package Type
8-Lead LFCSP
θJA
62.7
ΨJB
33.60
Unit
°C/W
θJA and ΨJB and are modeled using a standard 4-layer JEDEC printed
circuit board (PCB) (2S2P) with the exposed pad soldered to
the board with a 2 × 2 array of thermal vias and still air.
ESD CAUTION
Rev. A | Page 5 of 15
ADP2360
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
EN 1
ITH 3
FB 4
8 VIN
ADP2360
TOP VIEW
9
AGND
7 SW
6 PGND
5 SS
NOTES
1. ANALOG GROUND. THE EXPOSED
PAD MUST BE CONNECTED AND
SOLDERED TO AN EXTERNAL
GROUND PLANE.
13944-002
PG 2
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
Mnemonic
EN
PG
ITH
FB
SS
PGND
SW
VIN
AGND (EPAD)
Description
Enable Input. This pin enables control for the ADP2360 with precision thresholds.
Power-Good Output. This pin is an open-drain, power-good indicator.
IPEAK Threshold Programming Pin. Connect a resistor to ground to adjust the IPEAK level in the application.
Output Voltage Feedback Input. Use this pin to set the output voltage.
Soft Start. Connect a capacitor from SS to AGND to adjust the soft start time of the device.
Power Ground. NMOS power device and driver ground connection.
Switch Node. This pin is the drain of the power NMOS and power PMOS devices.
Input Voltage. An input capacitor must be placed between this pin and PGND.
Analog Ground. The exposed pad must be connected and soldered to an external ground plane.
Rev. A | Page 6 of 15
Data Sheet
ADP2360
100
100
90
90
80
80
70
70
EFFICIENCY (%)
60
50
40
60
50
40
30
20
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
LOAD (A)
0
0.02
0.04
0.03
0.05
0.06
0.07
Figure 6. Efficiency vs. Load over Temperature, VIN = 9 V,
VOUT = 3.3 V Fixed, RITH = 0 Ω
100
90
90
80
80
70
70
EFFICIENCY (%)
100
60
50
40
60
50
40
30
30
20
20
VIN = 9V
VIN = 12V
VIN = 24V
VIN = 48V
0
0.02
0.01
0.03
0.05
0.04
0.06
LOAD (A)
47µH
100µH
150µH
10
0
13944-004
10
0
0.01
0
LOAD (A)
Figure 3. Efficiency vs. Load, VOUT = 3.3 V Fixed, RITH = 0 Ω, TA = 25°C
EFFICIENCY (%)
+125°C
+85°C
+25°C
–40°C
10
13944-003
0
20
VIN = 9V
VIN = 12V
VIN = 24V
VIN = 48V
10
0
0.01
0.02
0.03
0.04
220µH
330µH
470µH
0.05
0.06
0.07
LOAD (A)
Figure 7. Efficiency vs. Load over Inductor Size, VIN = 9 V, VOUT = 3.3 V Fixed,
RITH = 0 Ω, TA = 25°C
Figure 4. Efficiency vs. Load, VOUT = 5 V Fixed, RITH = 0 Ω, TA = 25°C
100
T
90
VFB
3
80
VSW
60
4
50
40
30
ISW
1
VOUT
VIN = 9V
VIN = 12V
VIN = 24V
VIN = 48V
10
0
0.005
0.010
0.015
0.020
0.025
0.030
0.035
0.040
LOAD (A)
2
CH1 100mA Ω BW
B
CH3 50mV
W
CH2 50.0mV
CH4 5.0V
B
W
B
W
M 200µs 25.0MS/s
A CH1
40.0mA
40.0ns/pt
Figure 8. Switching Waveforms, VIN = 9 V, VOUT = 3.3 V Fixed,
RITH = 0 Ω, Load = 1 mA
Figure 5. Efficiency vs. Load, VOUT = 3.3 V Fixed, RITH = Open, TA = 25°C
Rev. A | Page 7 of 15
13944-008
20
13944-005
EFFICIENCY (%)
70
0
13944-006
30
13944-007
EFFICIENCY (%)
TYPICAL PERFORMANCE CHARACTERISTICS
ADP2360
Data Sheet
T
3
T
VFB
4
VSW
VSW
1
4
IOUT (1mV = 1mA)
ISW
1
ISW
2
VOUT
3
2
M 20.0µs 250MS/s
A CH1
40.0mA
4.0ns/pt
CH1 100mA Ω BW
B
CH3 50mV
W
13944-009
CH2 50.0mV
CH4 5.0V
B
W
B
W
Figure 9. Switching Waveforms, VIN = 9 V, VOUT = 3.3 V Fixed,
RITH = 0 Ω, Load = 10 mA
VFB
CH2 10.0mV Ω BW
B
CH4 5.0V
W
M 100µs 50.0MS/s
A CH2
13.2mV
20.0ns/pt
13944-012
VOUT
CH1 100mA Ω BW
B
CH3 50mV
W
Figure 12. Load Transient, VIN = 9 V, VOUT = 3.3 V Fixed, RITH = 0 Ω,
Load Step 15 mA to 10 mA
T
T
VSW
3
4
VSW
1
4
ISW
ISW
IOUT (1mV = 1mA)
2
VOUT
3
2
CH2 50.0mV
CH4 5.0V
B
W
B
W
M 4.0µs 1.25GS/s
A CH1
40.0mA
800ps/pt
CH1 100mA Ω BW
B
CH3 50mV
W
13944-010
CH1 100mA Ω BW
B
CH3 50mV
W
VOUT
Figure 10. Switching Waveforms, VIN = 9 V, VOUT = 3.3 V Fixed,
RITH = 0 Ω, Load = 50 mA
CH2 50.0mV Ω BW
B
CH4 5.0V
W
M 400µs 12.5MS/s
A CH2
30.0mV
80.0ns/pt
13944-013
1
Figure 13. Load Transient, VIN = 9 V, VOUT = 3.3 V Fixed, RITH = 0 Ω,
Load Step 1 mA to 50 mA
T
T
VSW
4
4
VSW
1
ISW
1
ISW
IOUT (1mV = 1mA)
IOUT (1mV = 1mA)
2
2
3
3
CH2 10.0mV Ω BW
B
CH4 5.0V
W
M 100µs 50.0MS/s
A CH2
13.2mV
20.0ns/pt
CH1 100mA Ω BW
B
CH3 50mV
W
13944-011
CH1 100mA Ω BW
B
CH3 50mV
W
Figure 11. Load Transient, VIN = 9 V, VOUT = 3.3 V Fixed, RITH = 0 Ω,
Load Step 10 mA to 15 mA
CH2 50.0mV Ω BW
B
CH4 5.0V
W
M 400µs 12.5MS/s
A CH2
30.0mV
80.0ns/pt
13944-014
VOUT
VOUT
Figure 14. Load Transient, VIN = 9 V, VOUT = 3.3 V Fixed, RITH = 0 Ω,
Load Step 50 mA to 1 mA
Rev. A | Page 8 of 15
Data Sheet
ADP2360
T
4
1
T
VSW
VSW
4
ISW
1
ISW
VIN
VIN
VOUT
VOUT
3
CH2 50.0mV Ω BW
CH4 10.0V BW
M 1.0ms 1MS/s
A CH3
10.5V
1000ns/pt
CH1 100mA Ω BW
CH3 20.0V BW
13944-015
CH1 100mA Ω BW
CH3 5.0V BW
Figure 15. Line Transient, VOUT = 3.3 V Fixed, RITH = 0 Ω, Load = 10 mA
Line Step 9 V to 12 V
M 4.0ms 2.5MS/s
A CH3
20.0V
400ns/pt
Figure 18. Line Transient, VOUT = 3.3 V Fixed, RITH = 0 Ω, Load = 10 mA
Line Step 60 V to 12 V
1.0
4
VOUT VARIATION FROM AVERAGE (%)
T
VSW
1
ISW
VIN
VOUT
3
CH2 50.0mV BW
CH4 10.0V BW
M 10.0ms 1.0MS/s
A CH3
10.5V
1000ns/pt
Figure 16. Line Transient, VOUT = 3.3 V Fixed, RITH = 0 Ω, Load = 10 mA
Line Step 12 V to 9 V
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
13944-016
2
CH1 100mA Ω BW
CH3 5.0V BW
CH2 50.0mV BW
CH4 50.0V BW
13944-018
2
2
0
10
20
30
40
50
60
VIN (V)
13944-019
3
Figure 19. Line Regulation, VOUT = 3.3 V Fixed, RITH = 0 Ω, Load = 10 mA
4.0
T
VSW
3.5
4
3.0
VIN
2.0
1.5
OPEN
1.5MΩ
825kΩ
576kΩ
435kΩ
365kΩ
287kΩ
SHORT
1.0
VOUT
3
0.5
2
CH2 50.0mV BW
CH4 50.0V BW
M 4.0ms 2.5MS/s
A CH3
56.6V
400ns/pt
0
13944-017
CH1 100mA Ω BW
CH3 20.0V BW
Figure 17. Line Transient, VOUT = 3.3 V Fixed, RITH = 0 Ω, Load = 10 mA
Line Step 12 V to 60 V
0
0.01
0.02
0.03
0.04
LOAD (A)
0.05
0.06
0.07
13944-020
ISW
VOUT (V)
2.5
1
Figure 20. Load Current Capability, VOUT vs. Load for Various RITH Values, VIN =
9 V (VOUT Drops to 0 V when Current Limit Reached)
Rev. A | Page 9 of 15
ADP2360
Data Sheet
THEORY OF OPERATION
VIN
CIN
VIN
VREG
0µA TO
5µA
ITH
3
RITH
VITH
BG
0.8V
TSD
TSD
UVLO
VREG
VREG
IPEAK
COMPARATOR
ADP2360
1µA
IPEAK
CONTROL
SS
5
LEVEL
SHIFT
CSS
FB
4
7
R2
0.8V
FEEDBACK
COMPARATOR
VOUT
ZERO CROSSING
DETECTOR
COMPARATOR
UVLO
TSD
4
L1
COUT
CONTROL
LOGIC
FIXED OUTPUT
VOLTAGE
FB
SW
6
VOUT
PGND
VIN
R1
R2
EN
PG
VPG_RISING
1
VEN_RISING
POWER GOOD
COMPARATOR
ENABLE
RPG
2
9
AGND
NOTES
1. THE PORTIONS IN THE DASHED BOXES DISPLAY THE DIFFERENCE OF THE FUNCTIONALITY OF PIN 4
FOR THE ADJUSTABLE AND FIXED OUTPUT VOLTAGES.
13944-021
VOUT
R1
UVLO
gM
VREG
ADJUSTABLE OUTPUT
VOLTAGE
BAND GAP
8
Figure 21. Block Diagram
When the PMOS turns off, the NMOS turns on, reducing the
energy stored in the inductor until the inductor current reaches
zero. At this point, the NMOS also turns off.
OVERVIEW
The ADP2360 is a high efficiency, high input voltage, DCM
synchronous, step-down, dc-to-dc switching regulator.
The ADP2360 uses a single-pulse PFM architecture with adjustable
IPEAK control to adjust the frequency variation within the application
and to minimize the input and output ripple.
The ADP2360 further offers a power-good (PG) pin with an
open-drain output signal to indicate when the output voltage is
stable. Other key features include 100% duty cycle operation,
precision enable control, external soft start control, undervoltage
lockout, and thermal shutdown.
When both the NMOS and PMOS are off, the ADP2360 enters
into sleep mode. During this phase of operation, the stored energy
in COUT delivers the load current, and thus VOUT and VFB decrease.
When VFB drops below the VFB_FALLING threshold, another
switching cycle begins.
IPEAK
IL
tSLEEP
CONTROL SCHEME
PMOS
NMOS
FBVFB_FALLING
VOUT
13944-022
The ADP2360 uses a single-pulse, peak current PFM control
scheme. A switching cycle is started when the FB pin voltage,
VFB, is less than the VFB_FALLING threshold, and the PMOS is turned
on. While the PMOS is on, the current through the inductor
increases to charge the output capacitor (COUT) and store energy
in the inductor. The current through the inductor continues to
increase until it reaches the IPEAK programmed via the ITH pin.
When IPEAK is reached, or if the VFB voltage rises above VFB_RISING,
the PMOS turns off.
Figure 22. Control Scheme Typical Waveforms
Rev. A | Page 10 of 15
Data Sheet
ADP2360
100% Duty Cycle
Adjustable Peak Current Threshold (ITH)
The control method of the ADP2360 means that the maximum
output current is slightly less than half of IPEAK. This peak current
value is resistor programmable with RITH.
The IPEAK value set by RITH on the ITH pin is determined at
startup and is reset only if the device is disabled and reenabled
using the EN pin or a VIN power cycle.
DEVICE FEATURES
Fixed and Adjustable Output Models
Both fixed and adjustable output models are available. The fixed
output models provide the feedback resistors internally.
Shutdown/Precision Enable
The EN pin of the ADP2360 tolerates the full supply voltage range
and provides three states of operation for the device: shutdown,
sleep, and active. When the EN pin voltage (VEN) is less than
VEN_SHUTDOWN, the ADP2360 is in shutdown mode and the VIN
supply current is at the lowest value (IQ_SHUTDOWN).
When VEN rises above VEN_SHUTDOWN but is below VEN_RISING, some
internal circuitry is enabled and the device is in standby mode.
This circuitry enables the references that provide the precision
enable threshold.
The precision enable turns on the regulator when the EN pin
voltage rises above VEN_RISING and returns to standby mode when
the voltage falls below VEN_RISING − VEN_HYS.
Soft Start
When the ADP2360 is enabled, an internal current source supplies
current (ISS) to the soft start capacitor (CSS) until it reaches
approximately 1 V at startup. During this time, VSS replaces the
internal feedback reference for the feedback comparator. This
reference rises at the same rate as VSS to the 0.8 V regulation level.
After VSS reaches 0.8 V, the feedback voltage reference is switched to
an 0.8 V internal reference. When VSS reaches approximately 1 V,
the SS pin is connected to an internal pull-down resistor and
discharged to 0 V. See Figure 23 for a diagram showing the soft
start time period and the behavior of the SS pin.
1V
0.8V
tSS
VSS
13944-023
Because the PMOS turns off only if the peak current is reached or
if the feedback voltage exceeds VFB_RISING, the ADP2360 seamlessly
operates up to 100% duty cycle. This situation arises when the
input and output voltage are nearly equal. If the input voltage drops
below the output voltage, the output is maintained with a small
voltage drop across the PMOS device. When operating in 100%
duty cycle, the output current limit is approximately equal to IPEAK.
Steps must be taken to ensure that the load does not exceed 50% of
IPEAK to avoid the current limit when the input voltage rises above
the output voltage.
Figure 23. Soft Start Voltage Time Period
Calculate the soft start time using the following equation:
t SS =
C SS × 0.8 V
I SS
(1)
When the ADP2360 is disabled via the EN pin, a UVLO event,
or a TSD event, the SS pin is reset. When the device is enabled
or the condition causing the UVLO or TSD event is removed,
the full soft start sequence occurs.
Thermal Shutdown (TSD)
The ADP2360 includes an internal TSD protection circuit. If the
junction temperature exceeds TSHDN, the TSD disables switching
and reduces the power dissipation in the device. While in thermal
shutdown, the power PMOS and NMOS devices are turned off
and the soft start capacitor, CSS, is discharged to AGND. When
the junction temperature decreases to TSHDN – THYS, the ADP2360
initiates a soft start and resumes switching to regulate the
output voltage.
Undervoltage Lockout (UVLO)
The ADP2360 has an internal UVLO on the VIN pin. If the input
voltage is falls below the VUVLO_FALLING threshold, the ADP2360
is disabled. The ADP2360 does not resume operation until the
input voltage rises above the VUVLO_RISING threshold.
Power Good
The ADP2360 has an active high, internal, open-drain, 60 V,
NMOS device connected to the power-good pin (PG) that is
used as a flag to indicate the status of the output voltage. To
configure the PG output, connect a pull-up resistor from PG
to an external voltage rail. An internal current limit prevents
damage to this pin.
When the feedback pin voltage (VFB) is less than VPG_RISING, the
open-drain NMOS is on, and PG is pulled to ground. When the
internal feedback voltage exceeds VPG_RISING, the open-drain
NMOS turns off.
The PG pin has hysteresis to prevent glitching. The NMOS
remains off until the internal feedback voltage falls below the
VPG_FALLING threshold.
If EN is low or a TSD or UVLO event occurs, an internal discharge
resistor is internally connected from the SW node to PGND. This
resistor pulls the output voltage to ground when the regulator is
disabled, even when there is no load on the output.
Rev. A | Page 11 of 15
ADP2360
Data Sheet
APPLICATIONS INFORMATION
ESTIMATING THE SWITCHING FREQUENCY
Compatible components for the step-down application circuits
in Figure 24 and Figure 25 are identified using the guidelines in
this section.
The ADP2360 switching frequency (fSW) can be estimated with
the following equation:
ADP2360
VIN
VIN
8
SW 7
CIN
RPG
2
PG
1
EN
5
SS
CSS
D≈
ITH 3
RITH
PGND
AGND
(EPAD)
6
9
VIN
SW
RPG
PG
OFF
ON
CSS
FB
2
PG
1
EN
5
SS
L1
VOUT
7
RFB1
4
RFB2
ITH
CFF
COUT
3
RITH
PGND
AGND
(EPAD)
6
9
Figure 25. Typical Application Circuit Adjustable Output Voltage
SETTING THE OUTPUT VOLTAGE
The ADP2360 is available with 3.3 V and 5.0 V fixed output voltage
options. For the fixed options, an internal resistive feedback divider
sets the output voltage and no external resistors are necessary,
as shown in Figure 24.
The ADP2360 is also available with an adjustable output voltage
and can be configured for output voltages between 0.8 V and
VIN. Use the following equation to determine RFB1 and RFB2 for
the desired VOUT:
R
VOUT = 1 + FB1 × VFB _ FALLING
RFB2
VOUT
VIN
(4)
The control method of the ADP2360 means that the maximum
output current is slightly less than half of IPEAK. The peak current
limit must be programmed to at least twice the desired
maximum output current.
The value of the selected IPEAK current in the ADP2360 application
affects the efficiency, switching frequency, and output voltage
ripple. Larger IPEAK values tend to give improved efficiency. Using a
smaller IPEAK value gives a higher switching frequency and reduced
output voltage ripple.
13944-025
8
(3)
SETTING THE PEAK INDUCTOR CURRENT
ADP2360
CIN
L × I PEAK 2
Note that the switching frequency changes in direct proportion
to the output current. The maximum frequency can be controlled
by the inductor value and the peak current control resistor RITH.
Figure 24. Typical Application Circuit Fixed Output Voltage
VIN
2 × (VIN – VOUT ) × D × I OUT
where the duty cycle, D, is approximated by
COUT
13944-024
ON
f SW ≈
VOUT
FB 4
PG
OFF
L1
(2)
When using an external resistor divider, the optional feedforward
capacitor CFF may be placed across RFB1.
INPUT CAPACITOR SELECTION
An input capacitor must be placed between the VIN pin and
PGND. Ceramic capacitors greater than or equal to 4.7 µF are
recommended. The input capacitor reduces the input voltage
ripple caused by the switching current. Place the input capacitor
as close as possible to the VIN pin to reduce input voltage spikes.
The voltage rating of the input capacitor must be greater than
the maximum input voltage.
The desired peak current limit (IPEAK) is programmed to a discrete
value between 50 mA and 140 mA with an external resistor from
ITH to AGND. This external resistor, RITH, is chosen using the
values in Table 5.
Table 5. Peak Inductor Current Settings
RITH (kΩ)
Open
1500
825
576
453
365
287
0
IPEAK (mA)
50
60
70
80
90
100
120
140
The values given in Table 5 correspond to standard 1% E96
resistor values. A 1% tolerance resistor of the specified value
must be used to ensure the correct IPEAK value is selected. The
IPEAK value set by RITH on the ITH pin is determined upon startup
and is reset only if the device is disabled and reenabled using the
EN pin or a VIN power cycle.
Rev. A | Page 12 of 15
Data Sheet
ADP2360
INDUCTOR SELECTION
DESIGN OPTIMIZATION
The value of the selected inductor in the ADP2360 application
affects the efficiency, switching frequency, and output voltage
ripple. Larger value inductors tend to give improved efficiency
although for a given package size, the increased DCR and core
losses eventually dominate. Using a smaller value inductor gives a
higher switching frequency and reduced output voltage ripple, but
may decrease the overall efficiency due to increased switching losses.
For designs where the highest efficiency is desired, set the IPEAK
level to the maximum and use a high value low dc resistance
inductor (330 µH to 470µH are recommended). These choices
lead to a larger output voltage ripple that may be reduced with a
larger value, low ESR output capacitor.
The ADP2360 is designed with an adjustable IPEAK current limit
that allows the designer to optimize the efficiency for the application operating conditions and reduce the required inductor size.
Inductors in the 100 µH to 600 µH range are recommended.
Take care to select a compatible inductor with a sufficient
current rating, saturation current, and low dc resistance. The
current rating of the inductor must be greater than the maximum
IPEAK current limit set by the ITH pin, as specified in Table 1.
OUTPUT CAPACITOR SELECTION
The output capacitor selection affects the output voltage ripple
according to the following equation:
∆VOUT =
I OUT
For designs where the highest switching frequency is desired,
set IPEAK to just above double the required maximum output
current. Use a 100 µH inductor with low dc resistance.
For designs where the lowest ripple is desired, set IPEAK to just
above double the required maximum output current. Use a
100 µH inductor with low dc resistance and a large value, low
ESR output capacitor.
RECOMMENDED COMPONENTS
The components specified in Table 6 are recommended for operation across the full input voltage range. All typical performance
characteristic data was measured using these components and
the adjustable voltage option of the ADP2360 with appropriately
chosen feedback resistors to select the required output voltage.
(5)
C OUT × f SW
The ADP2360 is designed for operation with ceramic capacitors,
because these have a small footprint and low equivalent series
resistance (ESR) values, giving the lowest output voltage ripple.
An output capacitance of 10 µF is suggested for most applications.
This value can be increased to reduce output voltage ripple.
Table 6. Recommended Components
Component
COUT
L1
CIN
CFF
Value
10 μF, 50 V
100 μH
10 μF, 100 V
10 pF, 50 V
Part Number
GRM32ER71H106KA12L
744043101
C5750X7S2A106M230KB
GRM1885C1H100JA01D
Rev. A | Page 13 of 15
Manufacturer
Murata
Würth
TDK
Murata
ADP2360
Data Sheet
PCB LAYOUT CONSIDERATIONS
For high efficiency, good regulation, and stability with the
ADP2360, a well designed PCB is required. Poor layout can
affect the ADP2360 buck performance, causing electromagnetic
interference (EMI), poor electromagnetic compatibility (EMC),
ground bounce, and voltage losses.
•
•
•
•
•
•
•
Keep the low ESR input and output capacitors, CIN and COUT,
and the inductor, L1, as close as possible to the ADP2360.
Avoid long trace lengths from the device to the capacitors
that add series inductance and may cause EMI issues or
increased ripple.
Keep RFB1, RFB2, and CFF as close as possible to the FB pin.
Route the output voltage path away from the inductor and
SW node to minimize noise and magnetic interference.
Keep high current traces as short and as wide as possible.
Avoid routing high impedance traces near any node
connected to SW or near the inductor to prevent radiated
noise injection.
Use a ground plane with several vias connected to the
component side ground to reduce noise interference on
sensitive circuit nodes.
Be aware that traces may carry up to 60 V and leave
adequate separation between traces where necessary.
Because up to 60 V may be present between the EPAD and
device pins, the EPAD must be solder mask defined and
reduced slightly in size to prevent the risk of bridging if the
device is misaligned. To help ensure alignment during
reflow processes, traces must exit the pads perpendicular to
the device edge as shown in Figure 26. See the AN-772
Application Note, A Design and Manufacturing Guide for
the Lead Frame Chip Scale Package (LFCSP), for further
guidance on layout, footprint, and manufacturing.
Figure 26. PCB Layout, Top
13944-027
•
13944-026
Use the following guidelines when designing PCBs:
Figure 27. PCB Layout, Bottom
Rev. A | Page 14 of 15
Data Sheet
ADP2360
OUTLINE DIMENSIONS
2.54
2.44
2.34
3.10
3.00 SQ
2.90
8
PIN 1 INDEX
AREA
0.45
0.40
0.35
TOP VIEW
PKG-004263
SEATING
PLANE
1.70
1.60
1.50
EXPOSED
PAD
SIDE VIEW
0.35
0.30
0.20
4
BOTTOM VIEW
0.05 MAX
0.02 NOM
0.203 REF
1
0.20 MIN
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET
03-10-2017-A
5
0.80
0.75
0.70
DETAIL A
(JEDEC 95)
0.65 BSC
Figure 28. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-8-19)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
Temperature
Range
−40°C to +125°C
ADP2360ACPZ-3.3-R7
Output Voltage
0.8 V to VIN
adjustable
3.3 V fixed
−40°C to +125°C
ADP2360ACPZ-5.0-R7
5.0 V fixed
−40°C to +125°C
ADP2360CP-EVALZ
0.8 V to VIN
adjustable
ADP2360ACPZ-R7
1
Package Description
8-Lead Lead Frame Chip Scale Package
[LFCSP]
8-Lead Lead Frame Chip Scale Package
[LFCSP]
8-Lead Lead Frame Chip Scale Package
[LFCSP]
Evaluation Board
Z = RoHS Compliant Part.
©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13944-0-10/17(A)
Rev. A | Page 15 of 15
Package
Option
CP-8-19
Branding
LTK
CP-8-19
LTH
CP-8-19
LTJ
