ADP2441ACPZ

36 V,1 A, Synchronous, Step-Down DC-to-DC Regulator ADP2441 Data Sheet FEATURES TYPICAL CIRCUIT CONFIGURATION APPLICATIONS CBST C4 RBOTTOM COMP EN FREQ VIN ADP2441 SS/TRK FB RCOMP VCC AGND RTOP BST VOUT VIN VIN VOUT SW CIN COUT PGND 10581-001 CCOMP RFREQ Figure 1. 100 90 VOUT = 12V VOUT = 5V 80 GENERAL DESCRIPTION EFFICIENCY (%) 70 Point of load applications Distributed power systems Industrial control supplies Standard rail conversion to 24 V/12 V/5 V/3.3 V VOUT = 3.3V 60 50 40 30 VIN = 24V fSW = 300kHz 20 The output voltage can be adjusted from 0.6 V to 0.9 V × VIN. High efficiency is obtained with integrated low resistance Nchannel MOSFETs for both high-side and low-side devices. The switching frequency is adjustable from 300 kHz to 1 MHz with an external resistor. The ADP2441 also has an accurate power-good (PGOOD) open-drain output signal. At light load conditions, the regulator operates in pulse skip mode by skipping pulses and reducing switching losses to improve energy efficiency. In addition, at medium to heavy load conditions, the regulator operates in fixed frequency pulse-width modulation (PWM) mode to reduce electromagnetic interference (EMI). 10 0 0.02 0.2 LOAD (A) 1 10581-002 The ADP2441 is a constant frequency, current mode control, synchronous, step-down dc-to-dc regulator that is capable of driving loads up to 1 A with excellent line and load regulation characteristics. The ADP2441 operates with a wide input voltage range of 4.5 V to 36 V, which makes it ideal for regulating power from a wide variety of sources. In addition, the ADP2441 has very low minimum on time (50 ns) and is, therefore, suitable for applications requiring a very high step-down ratio. Rev. C C3 PGOOD Wide input voltage range of 4.5 V to 36 V Low minimum on time of 50 ns Maximum load current of 1 A High efficiency of up to 94% Adjustable output down to 0.6 V ±1% output voltage accuracy Adjustable switching frequency of 300 kHz to 1 MHz Pulse skip mode at light load for power saving Precision enable input pin Open-drain power good External soft start with tracking Overcurrent-limit protection Shutdown current of less than 15 µA UVLO and thermal shutdown 12-lead, 3 mm × 3 mm LFCSP package Reference similar product ADP2442 with synchronization capability Figure 2. Efficiency vs. Load Current, VIN = 24 V The ADP2441 uses hiccup mode to protect the IC from short circuits or from overcurrent conditions on the output. The external programmable soft start limits inrush current during startup for a wide variety of load capacitances. Other key features include tracking, input undervoltage lockout (UVLO), thermal shutdown (TSD), and precision enable (EN), which can also be used as a logic level shutdown input. The ADP2441 is available in a 3 mm × 3 mm, 12-lead LFCSP package and is rated for a junction temperature range of −40°C to +125°C. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADP2441 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 18 Applications ....................................................................................... 1 Selecting the Output Voltage .................................................... 18 General Description ......................................................................... 1 Setting the Switching Frequency .............................................. 18 Typical Circuit Configuration......................................................... 1 Soft Start ...................................................................................... 19 Revision History ............................................................................... 2 External Components Selection ............................................... 19 Specifications..................................................................................... 3 Boost Capacitor .......................................................................... 21 Absolute Maximum Ratings ............................................................ 5 VCC Capacitor............................................................................ 21 Thermal Resistance ...................................................................... 5 Loop Compensation .................................................................. 21 ESD Caution .................................................................................. 5 Large Signal Analysis of the Loop Compensation ................. 21 Pin Configuration and Function Descriptions ............................. 6 Design Example .............................................................................. 23 Typical Performance Characteristics ............................................. 7 Configuration and Components Selection ............................. 23 Internal Block Diagram ................................................................. 14 System Configuration ................................................................ 24 Theory of Operation ...................................................................... 15 Typical Application Circuits ......................................................... 25 Control Architecure ................................................................... 15 Design Example .......................................................................... 25 Adjustable Frequency................................................................. 16 Other Typical Circuit Configurations ..................................... 26 Power Good ................................................................................. 16 Power Dissipation and Thermal Considerations ....................... 29 Soft Start ...................................................................................... 16 Power Dissipation....................................................................... 29 Tracking ....................................................................................... 16 Thermal Considerations............................................................ 29 Undervoltage Lockout (UVLO) ............................................... 17 Evaluation Board Thermal Performance .................................... 30 Precision Enable/Shutdown ...................................................... 17 Circuit Board Layout Recommendations ................................... 31 Current-Limit and Short-Circuit Protection .......................... 17 Outline Dimensions ....................................................................... 32 Thermal Shutdown ..................................................................... 17 Ordering Guide .......................................................................... 32 REVISION HISTORY 8/15—Rev. B to Rev. C Changes to Figure 45 ...................................................................... 14 6/14—Rev. A to Rev. B Change to Features Section ............................................................. 1 11/12—Rev. 0 to Rev. A Changes to Figure 1 .......................................................................... 1 Changed IVIN Maximum Parameter from 2.2 mA to2 mA.......... 3 Changes to Pin 3 and Pin 5 Descriptions ...................................... 6 Changes to Boost Capacitor Section ............................................ 21 Changes to Figure 66 ...................................................................... 31 Changes to Ordering Guide .......................................................... 32 6/12—Revision 0: Initial Version Rev. C | Page 2 of 32 Data Sheet ADP2441 SPECIFICATIONS VIN = 4.5 V to 36 V, TJ = −40°C to +125°C, unless otherwise noted. Table 1. Parameter POWER SUPPLY Input Voltage Range Supply Current Shutdown Current UVLO Threshold Hysteresis INTERNAL REGULATOR Regulator Output Voltage OUTPUT Output Voltage Range Maximum Output Current Feedback Regulation Voltage Line Regulation Load Regulation ERROR AMPLIFIER Feedback Bias Current Transconductance Open-Loop Voltage Gain 1 MOSFETS High-Side Switch On Resistance 2 Low-Side Switch On Resistance2 Leakage Current Minimum On Time 3 Minimum Off Time 4 CURRENT SENSE Current Sense Amplifier Gain Hiccup Time Number Of Cumulative Current-Limit Cycles to Go into Hiccup Mode Peak Current Limit FREQUENCY Switching Frequency Range Frequency Set Accuracy SOFT START Soft Start Current PRECISION ENABLE Input Threshold Hysteresis Leakage Current Thermal Shutdown Rising Hysteresis Symbol Test Conditions/Comments VIN IVIN ISHDN VEN = 1.5 V not switching VEN = AGND VUVLO VIN falling VCC VIN = 5 V to 36 V VOUT IOUT VFB Min 3.8 TJ = −40°C to +85°C TJ = −40°C to +125°C IFB_BIAS gm AVOL VFB = 0.6 V ICOMP = ±20 µA 200 RDS_H(ON) RDS_L(ON) ILKG tON_MIN tOFF_MIN BST − SW = 5 V VCC = 5 V VEN = AGND All switching frequencies Unit 1.7 10 36 2 15 V mA µA 4 200 4.2 V mV 5 5.5 V 0.9 × VIN V A V V %/V %/A 0.6 0.6 0.005 0.05 0.606 0.609 50 250 65 200 300 nA µA/V dB 170 120 1 50 165 270 180 25 65 175 mΩ mΩ μA ns ns 1.6 2 6 8 2.4 A/V ms Events 1.4 1.6 1.8 A FREQ pin = 308 kΩ FREQ pin = 92.5 kΩ 300 270 900 300 1000 1000 330 1100 kHz kHz kHz VSS = 0 V 0.9 1 1.2 µA 1.15 1.20 100 0.1 1.25 V mV µA GCS fSW = 300 kHz to1 MHz ICL fSW VEN(RISING) VEN(HYST) IIEN_LEAK Max 4.5 0.6 1 0.594 0.591 ISS Typ VIN = VEN TSD TSD(HYST) 150 25 Rev. C | Page 3 of 32 1 °C °C ADP2441 Parameter POWER GOOD PGOOD High, FB Rising Threshold 5 PGOOD Low, FB Rising Threshold5 PGOOD High, FB Falling Threshold5 PGOOD Low, FB Falling Threshold5 PGOOD Delay High Leakage Current Pull-Down Resistor TRK TRK Input Voltage Range TRK to FB Offset Voltage Data Sheet Symbol tPGOOD IPGOOD(SRC) IPGOOD(SNK) Test Conditions/Comments Min Typ Max Unit 89 111 106 83 92 115 109 86 95 118 112 89 % % % % 50 1 0.5 10 0.7 µs µA kΩ VPGOOD = VCC FB = 0 V 0 TRK = 0 mV to 500 mV 600 10 mV mV Guaranteed by design. Measured between VIN and SW pins—includes bond wires and pin resistance. 3 Based on bench characterization. Measured with VIN = 12 V, VOUT = 1.2 V, load = 1 A, fSW = 1 MHz, and the output in regulation. Measurement does not include dead time. 4 Based on bench characterization. Measured with VIN = 15 V, VOUT = 12 V, load = 1 A, fSW = 600 kHz, and the output in regulation. Measurement does not include dead time. 5 This threshold is expressed as a percentage of the nominal output voltage. 1 2 Rev. C | Page 4 of 32 Data Sheet ADP2441 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter VIN to PGND EN to AGND SW to PGND BST to PGND VCC to AGND BST to SW FREQ, PGOOD, SS/TRK, COMP, FB to AGND PGND to AGND Operating Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering, 10 sec) θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages, and is based on a 4-layer standard JEDEC board. Rating −0.3 V to +40 V −0.3 V to +40 V −0.3 V to +40 V −0.3 V to +45 V −0.3 V to +6 V −0.3 V to +6 V −0.3 V to +6 V ±0.3 V −40°C to +125°C −65°C to +150°C 260°C Table 3. Thermal Resistance Package Type 12-Lead LFCSP ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. C | Page 5 of 32 θJA 40 θJC 2.4 Unit °C/W ADP2441 Data Sheet 10 BST 11 VCC 12 AGND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS FB 1 9 VIN ADP2441 COMP 2 8 SW TOP VIEW NOTES 1. THE EXPOSED PAD SHOULD BE CONNECTED TO THE SYSTEM AGND PLANE AND PGND PLANE. 10581-003 SS/TRK 6 FREQ 5 7 PGND PGOOD 4 EN 3 Figure 3. Pin Configuration, Top View Table 4. Pin Function Descriptions Pin No. 1 2 3 Mnemonic FB COMP EN 4 5 PGOOD FREQ 6 SS/TRK 7 PGND 8 SW 9 VIN 10 BST 11 VCC 12 AGND EP Description Feedback Regulation Voltage is 0.6 V. Connect this pin to a resistor divider from the output of the dc-to-dc regulator. Error Amplifier Compensation. Connect a resistor and capacitor in series to ground. Precision Enable. This features offers ±5% accuracy when using a 1.25 V reference voltage. Pull this pin high to enable the regulator and low to disable the regulator. Do not leave the EN pin floating. Active High Power-Good Output. This pin is pulled low when the output is out of regulation. Switching Frequency. A resistor to AGND sets the switching frequency (see the Setting the Switching Frequency section). Do not leave the FREQ pin floating. Soft Start/Tracking Input. A capacitor to ground is required to program the soft start time, which gradually ramps up the output. A resistive divider to an external reference is required on this pin to track an external voltage. Power Ground. Connect a decoupling ceramic capacitor as close as possible between the VIN pin and this pin. Connect this pin directly to the exposed pad. Switch. The midpoint for the drain of the low-side N-channel power MOSFET switch and the source for the high-side N-channel power MOSFET switch. Power Supply Input. Connect this pin to the input power source, and connect a bypass ceramic capacitor directly from this pin to PGND, as close as possible to the IC. The operation voltage is 4.5 V to 36 V. Boost. Connect a 10 nF ceramic capacitor between the BST and SW pins as close to the IC as possible to form a floating supply for the high-side N-Channel power MOSFET driver. This capacitor is needed to drive the gate of the N-channel power MOSFET above the supply voltage. Output of the Internal Low Dropout Regulator. This pin supplies power for the internal controller and driver circuitry. Connect a 1 µF ceramic capacitor between VCC and AGND and a 1 µF ceramic capacitor between VCC and PGND. The VCC output is active when the EN pin voltage is more than 0.7 V. Analog Ground. This pin is the internal ground for the control functions. Connect this pin directly to the exposed pad. Exposed Thermal Pad. The exposed pad should be connected to AGND and PGND. Rev. C | Page 6 of 32 Data Sheet ADP2441 TYPICAL PERFORMANCE CHARACTERISTICS 100 100 90 80 80 VIN = 12V 70 EFFICIENCY (%) 60 VIN = 24V 50 40 40 30 20 10 1 10581-004 0.1 LOAD (A) 0 0.01 90 VIN = 24V VIN = 36V 50 40 VOUT = 5V fSW = 300kHz COILCRAFT MSS1038 50 40 20 1 10581-006 0.1 LOAD (A) VOUT = 5V fSW = 700kHz COILCRAFT MSS1038 0 0.01 0.1 LOAD (A) Figure 5. Efficiency vs. Load Current, VOUT = 5 V, fSW = 300 kHz Figure 8. Efficiency vs. Load Current, VOUT = 5 V, fSW = 700 kHz 100 100 VIN = 24V 90 80 VIN = 24V 80 VIN = 36V EFFICIENCY (%) 70 60 50 40 VOUT = 12V fSW = 300kHz COILCRAFT MSS1038 VIN = 36V 60 50 40 30 VOUT = 12V fSW = 600kHz 20 10 COILCRAFT MSS1038 10 0.1 LOAD (A) 1 10581-008 EFFICIENCY (%) VIN = 36V 10 0 0.01 0 0.01 VIN = 24V 60 30 10 20 1 70 EFFICIENCY (%) EFFICIENCY (%) 60 30 VIN = 12V 80 70 70 1 100 VIN = 12V 80 90 1 Figure 7. Efficiency vs. Load Current, VOUT = 3.3 V, fSW = 700 kHz 100 20 0.1 LOAD (A) Figure 4. Efficiency vs. Load Current, VOUT = 3.3 V, fSW = 300 kHz 30 VOUT = 3.3V fSW = 700kHz COILCRAFT MSS1038 10 0 0.01 90 VIN = 24V 50 10581-005 20 VOUT = 3.3V fSW = 300kHz COILCRAFT MSS1038 VIN = 12V 60 10581-007 EFFICIENCY (%) 70 30 VIN = 5V 10581-009 90 VIN = 5V 0 0.01 0.1 LOAD (A) Figure 6. Efficiency vs. Load Current, VOUT = 12 V, fSW = 300 kHz Figure 9. Efficiency vs. Load Current, VOUT = 12 V, fSW = 600 kHz Rev. C | Page 7 of 32 ADP2441 Data Sheet 0.5 400 0.3 0.1 0 –0.1 VOUT = 5V fSW = 700kHz –0.2 –0.3 –0.4 0 0.2 0.4 0.6 0.8 1.0 LOAD (A) 250 fSW = 700kHz 200 150 100 VOUT = 3.3V 50 0 10581-010 –0.5 300 5 20 25 30 35 40 Figure 13. Pulse Skip Threshold, VOUT = 3.3 V 1.0 0.6 0.4 TA = +25°C TA = –40°C 0.2 0 –0.2 –0.4 TA = +125°C –0.8 –1.0 0 0.2 0.4 0.6 0.8 1.0 LOAD (A) 200 fSW = 700kHz 150 100 50 VOUT = 5V 0 10581-011 VIN = 24V VOUT = 5V fSW = 700kHz –0.6 fSW = 300kHz 250 10 15 20 25 30 35 40 VIN (V) 10581-014 PSKIP THRESHOLD LOAD CURRENT (mA) 300 0.8 VOUT ERROR (%) 15 VIN (V) Figure 10. Load Regulation for Different Supplies Figure 14. Pulse Skip Threshold, VOUT = 5 V Figure 11. Load Regulation for Different Temperatures 300 PSKIP THRESHOLD LOAD CURRENT (mA) 0.5 0.4 0.3 0.2 LOAD = 500mA 0.1 0 LOAD = 1A –0.1 VIN = 24V VOUT = 5V fSW = 700kHz –0.2 –0.3 –0.4 –0.5 7 12 17 22 27 32 VIN (V) 37 10581-012 VOUT ERROR (%) 10 250 fSW = 300kHz 200 150 fSW = 600kHz 100 50 VOUT = 12V 0 15 20 25 30 35 VIN (V) Figure 15. Pulse Skip Threshold, VOUT = 12 V Figure 12. Line Regulation, VOUT = 5 V for Different Loads Rev. C | Page 8 of 32 40 10581-015 VOUT ERROR (%) 0.2 fSW = 300kHz 350 10581-013 0.4 PSKIP THRESHOLD LOAD CURRENT (mA) VIN = 12V VIN = 24V VIN = 36V Data Sheet ADP2441 2.25 12 2.05 VIN = 36V 1.85 SUPPLY CURRENT (mA) SHUTDOWN CURENT (µA) 10 8 6 4 1.65 1.45 VIN = 4.5V VIN = 12V 1.25 1.05 VIN = 24V 0.85 VIN = 36V 0.65 VIN = 4.5V 2 0.45 0 –50 0.05 –50 50 100 150 TEMPERATURE (°C) –30 –10 10 30 50 70 90 110 130 150 TEMPERATURE (°C) Figure 16. Shutdown Current vs. Temperature 10581-016 0 10581-017 0.25 Figure 19. Supply Current vs. Temperature 4.5 1.24 1.22 ENABLE RISING THRESHOLD 1.20 ENABLE VOLTAGE (V) UVLO THRESHOLD (V) 4.4 UVLO, RISING VIN 4.3 4.2 4.1 UVLO, FALLING VIN 1.18 1.16 1.14 1.12 ENABLE FALLING THRESHOLD 1.10 1.08 4.0 0 25 50 75 100 1.04 –50 125 –30 –10 10 TEMPERATURE (°C) 130 0.6 120 PGOOD THRESHOLD (%) 0.7 0.4 0.3 0.2 0.1 0.2 0.3 0.4 0.5 TRACK (V) 70 90 110 130 150 130 150 110 100 90 80 PGOOD FALL, FB INCREASING PGOOD RISE, FB DECREASING PGOOD RISE, FB INCREASING PGOOD FALL, FB DECREASING 70 0.1 0.6 0.7 0.8 60 –50 10581-118 FB (V) 0.5 0 50 Figure 20. Enable Threshold vs. Temperature Figure 17. UVLO Threshold vs. Temperature 0 30 TEMPERATURE (°C) –30 –10 10 30 50 70 90 110 TEMPERATURE (°C) Figure 21. PGOOD Threshold vs. Temperature Figure 18. Tracking Range Rev. C | Page 9 of 32 10581-021 –25 10581-019 10581-018 3.9 –50 1.06 ADP2441 Data Sheet 1200 1200 1100 fSW = 1MHz 1000 800 FREQUENCY (kHz) SWITCHING FREQUENCY (kHz) fSW = 1MHz 1000 fSW = 700kHz 600 400 900 800 fSW = 700kHz 700 600 500 fSW = 300kHz 400 200 fSW = 300kHz 0 5 10 15 20 25 30 35 40 VIN (V) 200 –50 10581-022 0 –30 –10 10 30 50 70 90 110 130 150 TEMPERATURE (°C) 10581-023 300 Figure 25. Switching Frequency vs. Temperature Figure 22. Switching Frequency vs. Supply 1.80 200 1.78 1.76 MINIMUM OFF 1.74 150 1.72 1.70 CURRENT (A) ON TIME AND OFF TIME (ns) 175 125 100 75 1.68 VIN = 36V 1.66 1.64 1.62 VIN = 4.5V 1.60 1.58 MINIMUM ON 50 1.56 1.54 25 10 –10 30 50 70 90 130 110 150 TEMPERATURE (°C) 1.50 –50 10581-024 –30 150 Figure 26. Current Limit vs. Temperature 260 180 240 160 140 LOW-SIDE RDS(ON) (mΩ) 220 200 180 160 140 120 100 80 60 40 120 –25 0 25 50 75 100 125 TEMPERATURE (°C) 150 0 –50 –30 –10 10 30 50 70 90 TEMPERATURE (°C) 110 Figure 27. Low-Side RDS(ON) vs. Temperature Figure 24. High-Side RDS(ON) vs. Temperature Rev. C | Page 10 of 32 130 150 10581-026 20 10581-027 HIGH-SIDE RDS(ON) (mΩ) 100 TEMPERATURE (°C) Figure 23. Minimum On Time and Minimum Off Time vs. Temperature 100 –50 50 0 10581-126 1.52 0 –50 Data Sheet 1 ADP2441 VOUT VOUT 1 VIN = 24V VOUT = 3.3V fSW = 500kHz LOAD = 100mA INDUCTOR CURRENT INDUCTOR CURRENT 4 4 VIN = 24V VOUT = 3.3V FSW = 500kHz 2 CH1 20.0mV B W CH2 10.0V CH4 200mA Ω M4.00µs A CH4 T 41.40% 10581-029 10581-028 SW SW 2 CH1 20.0mV 120mA Figure 28. Pulse Skip Mode, VIN = 24 V, VOUT = 3.3 V, fSW = 500 kHz, No Load B W CH2 10.0V M4.00µs A CH4 CH4 500mA Ω T 41.40% 120mA Figure 31. Pulse Skip Mode, VIN = 24 V, VOUT = 3.3 V, fSW = 500 kHz, Load = 100 mA VOUT VOUT 1 1 INDUCTOR CURRENT INDUCTOR CURRENT VIN = 24V VOUT = 3.3V fSW = 500kHz LOAD = 1A 4 4 10581-030 CH1 20.0mV B W CH2 10.0V CH4 500mA Ω M1.00µs A CH2 T 41.40% 10581-031 SW SW 2 2 CH1 200mV 9.80V Figure 29. PWM Mode, VIN = 24 V, VOUT = 3.3 V, fSW = 500 kHz, Load = 1 A B W CH2 10.0V CH4 1.00A Ω M2.00ms A CH1 T 49.40% 60.0mV Figure 32. Hiccup Mode, VIN = 24 V, VOUT = 3.3 V, fSW = 500 kHz, Output Short to PGND VIN = 24V fSW = 700kHz VOUT = 5V LOAD STEP = 300mA VOUT 1 VOUT VIN = 24V VOUT = 5V fSW = 700kHz LOAD STEP = 500mA 1 LOAD LOAD SW SW 4 CH1 100mV B W M200µs A CH4 CH2 10V CH4 500mA Ω T 79.80% 10581-033 4 10581-032 2 2 CH1 50.0mV 690mA B W CH2 10.0V M200µs CH4 200mA Ω A CH4 604mA Figure 33. Load Transient Response, VIN = 24 V, VOUT = 5 V, fSW = 700 kHz, Load Step = 300 mA Figure 30. Load Transient Response, VIN = 24 V, VOUT = 5 V, fSW = 700 kHz, Load Step = 500 mA Rev. C | Page 11 of 32 ADP2441 Data Sheet VOUT 1 VOUT VIN = 12V VOUT = 5V fSW = 300kHz LOAD STEP = 500mA 1 LOAD SW 4 10581-034 4 2 B CH1 100mV W M200µs CH2 5.00V CH4 500mA Ω A CH4 VIN = 24V VOUT = 12V fSW = 600kHz LOAD STEP = 500mA SW 10581-037 LOAD 2 690mA B CH1 200mV Figure 34. Load Transient Response, VIN = 12 V, VOUT = 5 V, fSW = 300 kHz, Load Step = 500 mA W M200µs CH2 10.0V CH4 500mA Ω A CH4 600mA Figure 37. Load Transient Response, VIN = 24 V, VOUT = 12 V, fSW = 600 kHz, Load Step = 500 mA ENABLE VOUT 1 3 VOUT PGOOD LOAD 4 VIN = 24V VOUT = 12V fSW = 300kHz LOAD STEP = 500mA SW 1 2 B CH1 200mV W CH2 10.0V M200µs CH4 500mA Ω A CH4 10581-038 VIN = 24V VOUT = 5V fSW = 700kHz 10581-035 4 CH1 2.00V BW CH3 5.00V 550mA Figure 35. Load Transient Response, VIN = 24 V, VOUT = 12 V, fSW = 300 kHz, Load Step = 500 mA M 200µs A CH3 1.60V CH4 2.00V Figure 38. Power-Good Shutdown, VIN = 24 V, VOUT = 5 V, fSW = 700 kHz VIN ENABLE VIN = 24V VOUT = 5V fSW = 700kHz VOUT 3 VIN = 36V VOUT = 5V fSW = 700kHz 3 VOUT 1 1 SW PGOOD CH1 2.00V BW CH3 2.00V M1.00ms A CH3 10581-039 10581-036 4 2 CH1 2.00V BW CH3 10.0V 1.64V CH4 2.00V Figure 36. Power Good Startup, VIN = 24 V, VOUT = 5 V, fSW = 700 kHz CH2 10.0V BW M4.00ms A CH3 Figure 39. Startup with VIN, VIN = 36 V, VOUT = 5 V, fSW = 700 kHz, No Load Rev. C | Page 12 of 32 5.00V Data Sheet ADP2441 ENABLE VIN VIN = 36V VOUT = 5V fSW = 700kHz LOAD = 5Ω 3 VIN = 24V VOUT = 5V fSW = 700kHz VOUT VOUT 3 SS 1 SW 1 4 CH2 10.0V BW M4.00ms CH1 2.00V BW CH3 10.0V A CH3 10581-143 SW 10581-040 2 2 CH1 2.00V BW CH3 5.00V 9.00V Figure 40. Startup with VIN, VIN = 36 V, VOUT = 5 V, fSW = 700 kHz, Load = 5 Ω CH2 10.0V CH4 2.00V M1.00ms A CH3 1.40V Figure 43. Soft Start Startup with Precision Enable, VIN = 24 V, VOUT = 5 V, fSW = 700 kHz, No Load, Internal SS 110 200 90 160 70 120 50 80 30 40 10 0 VOUT SS MAGNITUDE (dB) VIN = 24V VOUT = 5V fSW = 700kHz LOAD = 5Ω SW 1 –40 –10 CROSSOVER = 58kHz: 1/12 fSW PHASE MARGIN = 55° VIN = 24V VOUT = 5V fSW = 700kHz LOAD = 1A –30 4 10581-041 –50 2 CH1 2.00V CH3 5.00V B CH2 10.0V CH4 2.00V W M200µs A CH3 –70 –80 –120 –160 –200 –90 2.20V 1 10 100 FREQUENCY (kHz) Figure 41. Shutdown with Precision Enable, VIN = 24 V, VOUT = 5 V, fSW = 700 kHz, Load = 5 Ω Figure 44. Magnitude and Phase vs. Frequency ENABLE 3 VOUT 1 VIN = 24V VOUT = 5V fSW = 700kHz LOAD = 5Ω SS = 10nF SS 4 10581-042 SW 2 CH1 2.00V BW CH3 5.00V CH2 10.0V CH4 500mV M2.00ms A CH3 2.20V Figure 42. Startup with Precision Enable, VIN = 24 V, VOUT = 5 V, fSW = 700 kHz, Load = 5 Ω, SS = 10 nF Rev. C | Page 13 of 32 10581-144 3 PHASE (Degrees) ENABLE ADP2441 Data Sheet INTERNAL BLOCK DIAGRAM VIN AGND VCC INTERNAL LDO BST EN UVLO + 1.25V BAND GAP REFERENCE OSC FREQ ENABLE COMP POWER STAGE ISS CLOCK + FB – SS/TRK + PULSE SKIP ENABLE 1V NMOS STATE MACHINE GATE CONTROL LOGIC COMP THRESHOLD SW + VCC + PWM VREF = 0.6V NMOS – PWM COMPARATOR PGND HICCUP HICCUP TIMER – SLOPE COMPENSATION/ RAMP GENERATOR + CURRENT SENSE AMPLIFIER PGOOD 115% OF FEEDBACK REFERENCE CURRENT VFB 86%OF FEEDBACK Figure 45. Block Diagram Rev. C | Page 14 of 32 10581-043 CURRENT-LIMIT COMPARATOR Data Sheet ADP2441 THEORY OF OPERATION CONTROL ARCHITECURE The ADP2441 is based on the emulated peak current mode control architecture. Fixed Frequency Mode A basic block diagram of the control architecture is shown in Figure 46. With medium to heavy loads, the ADP2441 operates in the fixed switching frequency PWM mode. The output voltage, VOUT, is sensed on the feedback pin, FB. An error amplifier integrates the error between the feedback voltage and the reference voltage (VREF = 0.6 V) to generate an error voltage at the COMP pin. A current sense amplifier senses the valley inductor current (IL) during the off period when the low-side power MOSFET is on and the high-side power MOSFET is off. An internal oscillator initiates a PWM pulse to turn off the low-side power MOSFET and turn on the high-side power MOSFET at a fixed switching frequency. When the high-side N-channel power MOSFET is enabled, the valley inductor current information is added to an emulated ramp signal, and then the PWM comparator compares this value to the error voltage on the COMP pin. The output of the PWM comparator modulates the duty cycle by adjusting the trailing edge of the PWM pulse that turns off the high-side power MOSFET and turns on the low-side power MOSFET. Slope compensation is programmed internally into the emulated ramp signal and is automatically selected, depending on the input voltage, output voltage, and switching frequency. This prevents subharmonic oscillations for near or greater than 50% duty cycle operation. The one restriction of this feature is that the inductor ripple current must be set between 0.2 A and 0.5 A to provide sufficient current information to the loop. CLOCK COMP VC S Q VOUT PWM DRIVER R QB IL COMPARATOR RSWL × IL REF gm V FB RAMP EMULATION SENSE_ BLOCK OUT GCS VRAMP 10581-044 The ADP2441 includes programmable features, such as soft start, output voltage, switching frequency, and power good. These features are programmed externally via tiny resistors and capacitors. The ADP2441 also includes protection features, such as UVLO with hysteresis, output short-circuit protection, and thermal shutdown. VIN Figure 46. Control Architecture Block Diagram Pulse Skip Mode The ADP2441 has built-in pulse skip circuitry that turns on during light loads, switching only as necessary so that the output voltage remains within regulation. This allows the regulator to maintain high efficiency during operation with light loads by reducing switching losses. The pulse skip circuitry includes a comparator, which compares the COMP voltage to a fixed pulse skip threshold. COMP PULSE SKIP THRESHOLD DC CONTROL LOGIC ADP2441 1V 10581-045 The ADP2441 is a fixed frequency, current mode control, stepdown, synchronous switching regulator that is capable of driving 1 A loads. The device operates with a wide input voltage range from 4.5 V to 36 V, and its output is adjustable from 0.6 V to 0.9 V × VIN. The integrated high-side N-channel power MOSFET and the low-side N-channel power MOSFET yield high efficiency with medium to heavy loads. Pulse skip mode is available to improve efficiency at light loads. Figure 47. Pulse Skip Comparator With light loads, the output voltage discharges at a very slow rate (load dependent). When the output voltage is within regulation, the device enters sleep mode and draws a very small quiescent current. As the output voltage drops below the regulation voltage, the COMP voltage rises above the pulse skip threshold. The device wakes up and starts switching until the output voltage is within regulation. As the load increases, the settling value of the COMP voltage increases. At a particular load, COMP settles above the pulse skip threshold, and the device enters the fixed frequency PWM mode. Therefore, the load current at which COMP exceeds the pulse skip threshold is defined as the pulse skip current threshold; the value varies with the duty cycle and the inductor ripple current. The measured value of pulse skip threshold over VIN is given in Figure 13, Figure 14, and Figure 15. Rev. C | Page 15 of 32 ADP2441 Data Sheet ADJUSTABLE FREQUENCY The ADP2441 features a programmable oscillator frequency with a resistor connected between the FREQ and AGND pins. At power-up, the FREQ pin is forced to 1.2 V and current flows from the FREQ pin to AGND; the current value is based on the resistor value on the FREQ pin. Then, the same current replicates in the oscillator to set the switching frequency. Note that the resistor connected to the FREQ pin should be placed as close as possible to the FREQ pin (see the Applications Information section for more information). The soft start period ends when the soft start ramp voltage exceeds the internal reference of 0.6 V. The ADP2441 also features an internal default soft start time of 2 ms. For more information, see the Applications Information section. ENABLE 3 POWER GOOD SS Likewise, the PGOOD pin is pulled low to AGND when the input voltage is below the internal UVLO threshold, when the EN pin is low, or when a thermal shutdown event has occurred. VOUT FALLING 116 110 100 90 84 POWER GOOD 10581-149 A CH1 2.52V TRACKING The ADP2441 has a tracking feature that allows the output voltage to track an external voltage. This feature is especially useful in a system where power supply sequencing and tracking is required. UNDERVOLTAGE MASTER VOLTAGE PGOOD COMP SW SS/TRK FB RTOP RTRK_TOP Figure 48. PGOOD Threshold In a typical application, a pull-up resistor connected between the PGOOD pin and an external supply is used to generate a logic signal. This pull-up resistor should range in value from 30 kΩ to 100 kΩ, and the external supply should be less than 5.5 V. SOFT START RTRK_BOT VOUT ADP2441 RBOTTOM 10581-048 OVERVOLAGE M10.0ms Figure 49. External Soft Start 10581-047 POWER GOOD CH2 1.00V CH1 2.00V BW CH3 5.00V REF 100 2 The ADP2441 SS/TRK pin is connected to the internal error amplifier. The internal error amplifier includes three inputs: the internal reference voltage, the SS/TRK voltage, and the feedback voltage. The error amplifier regulates the feedback voltage to the lower of the other two voltages. To track a master voltage, tie the SS/TRK pin to a resistor divider from the master voltage as shown in Figure 50. % OF VOUT SET VOUT RISING % OF VOUT SET VIN = 24V VOUT = 5V fSW = 700kHz LOAD = 1A EXTERNAL SS = 10nF 1 The PGOOD pin is an open-drain output that indicates the status of the output voltage. When the voltage of the FB pin is between 92% and 109% of the internal reference voltage, the PGOOD output is pulled high, provided there is a pull-up resistor connected to the pin. When the voltage of the FB pin is not within this range, the PGOOD output is pulled low to AGND. The PGOOD threshold is shown in Figure 48. UNDERVOLTAGE VOUT Figure 50. Tracking Feature Block Diagram The ratio of the slave output voltage to the master voltage is a function of the two dividers as follows: The ADP2441 soft start feature allows the output voltage to ramp up in a controlled manner, limiting the inrush current during startup. An external capacitor connected between the SS/TRK and AGND pins is required to program the soft start time. The programmable soft start feature is useful when a load requires a controlled voltage slew rate at startup. When the regulator powers up and soft start is enabled, the internal 1 μA current source charges the external soft start capacitor, establishing a voltage ramp slope at the SS pin, as shown in Figure 49. Rev. C | Page 16 of 32 VOUT VMASTER  RTOP  1 +   R  BOTTOM   =   R 1 + TRK _ TOP    R TRK _ BOT   (1) Data Sheet ADP2441 Coincident Tracking PRECISION ENABLE/SHUTDOWN The most common mode of tracking is coincident tracking. In this method, the slope of the slave voltage matches that of the master voltage, as shown in Figure 51. As the master voltage rises, the slave voltage rises identically. Eventually, the slave voltage reaches its regulation voltage, at which point the internal reference takes over the regulation while the SS/TRK input continues to increase, thus preventing itself from influencing the output voltage. The ADP2441 features a precision enable pin (EN) that can be used to enable or shut down the device. The ±5% accuracy lends itself to using a resistor divider from the VIN pin (or another external supply) to program a desired UVLO threshold that is higher than the fixed internal UVLO of 4.2 V. The hysteresis is 100 mV. VOLTAGE (V) MASTER VOLTAGE SLAVE VOLTAGE If a resistor divider is not used, a logic signal can be applied. A logic high enables the device, and a logic low forces the device into shutdown mode. VIN BST VIN SW 10581-049 TIME VOUT ADP2441 R1 EN FB Figure 51. Coincident Tracking R2 FREQ AGND COMP Ratiometric Tracking 10581-051 For coincident tracking, select resistor values such that RTRK_TOP = RTOP and RTRK_BOT = RBOTTOM in Equation 1. Figure 53. Precision Enable Used as a Programmable UVLO In the ratiometric tracking scheme, the master and the slave voltages rise with different slopes. CURRENT-LIMIT AND SHORT-CIRCUIT PROTECTION The ADP2441 has a current-limit comparator that compares the current sensed across the low-side power MOSFET to the internally set reference current. If the sensed current exceeds the reference current, the high-side power MOSFET is not turned on in the next cycle and the low-side power MOSFET stays on until the inductor current ramps down below the current-limit level. VOLTAGE (V) MASTER VOLTAGE TIME 10581-050 SLAVE VOLTAGE Figure 52. Ratiometric Tracking For ratiometric tracking in which the master voltage rises faster than the slave voltage (as shown in Figure 52), select RTRK_TOP ≥ RTOP and RTRK_BOT = RBOTTOM in Equation 1. UNDERVOLTAGE LOCKOUT (UVLO) The UVLO function prevents the IC from turning on while the input voltage is below the specified operating range to avoid an undesired operating mode. If the input voltage drops below the specified range, the UVLO function shuts off the device. The rising input voltage threshold for the UVLO function is 4.2 V with 200 mV hysteresis. The 200 mV of hysteresis prevents the regulator from turning on and off repeatedly with slow voltage ramp on the VIN pin. If the output is overloaded and the peak inductor current exceeds the preset current limit for more than eight consecutive clock cycles, the hiccup mode current-limit condition occurs. The output goes to sleep for 6 ms, during which time the output is discharged, the average power dissipation is reduced, and the device wakes up with a soft start period. If the current-limit condition is triggered again, the output goes to sleep and wakes up after 6 ms. Figure 32 shows the current-limit hiccup mode when the output is shorted to PGND. THERMAL SHUTDOWN If the ADP2441 junction temperature rises above 150°C, the thermal shutdown circuit turns off the switching regulator. Extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. A 25°C hysteresis is included so that when a thermal shutdown occurs, the ADP2441 does not return to normal operation until the junction temperature drops below 125°C. Soft start is active upon each restart cycle. Rev. C | Page 17 of 32 ADP2441 Data Sheet APPLICATIONS INFORMATION The ratio of the resistive voltage divider sets the output voltage, and the absolute value of the resistors sets the divider string current. For lower divider string currents, the small 50 nA (0.1 μA maximum) FB bias current should be taken into account when calculating the resistor values. The FB bias current can be ignored for a higher divider string current; however, using small feedback resistors degrades efficiency at very light loads. To limit degradation of the output voltage accuracy due to FB bias current to less than 0.005% (0.5% maximum), ensure that the divider string current is greater than 20 μA. To calculate the desired resistor values, first determine the value of the bottom resistor, RBOTTOM, as follows: (2) I STRING 70 60 50 40 30 20 0 0 200 400 600 800 1000 1200 FREQUENCY (kHz) Figure 55. Duty Cycle vs. Switching Frequency Calculate the value of the frequency resistor using the following equation: 92,500 f SW (4) Table 6 and Figure 56 provide examples of frequency resistor values, which are based on the switching frequency.     (3) Table 6. Frequency Resistor Selection RFREQ (kΩ) 308 132 92.5 VOUT ADP2441 FB Frequency 300 kHz 700 kHz 1 MHz 1200 RBOTTOM SS/TRK RFREQ 1100 1000 CSS EXTERNAL SUPPLY FREQUENCY (kHz) FREQ 10581-052 PGOOD Figure 54. Voltage Divider Table 5. Output Voltage Selection Voltage (V) 12 5 3.3 1.2 DMIN 10 where RFREQ is in kΩ, and fSW is in kHz. Then calculate the value of the top resistor, RTOP, as follows: RTOP DMAX 80 RFREQ = where: VREF is the internal reference and equals 0.6 V. ISTRING is the resistor divider string current. V − VREF RTOP = R BOTTOM ×  OUT VREF  90 RTOP (kΩ) 190 73 45 10 RBOTTOM (kΩ) 10 10 10 10 900 800 700 600 500 400 10581-053 R BOTTOM = VREF 100 10581-155 The output voltage is set using a resistor divider connected between the output voltage and the FB pin (see Figure 54). The resistor divider divides down the output voltage to the 0.6 V FB regulation voltage. The output voltage can be set to as low as 0.6 V and as high as 90% of the power input voltage. However, the choice is also influenced by whether there is a need for small external components. For example, for small, area limited power solutions, higher switching frequencies are required. DUTY CYCLE (%) SELECTING THE OUTPUT VOLTAGE 300 200 50 100 150 200 250 RESISTANCE (kΩ) SETTING THE SWITCHING FREQUENCY The choice of the switching frequency depends on the required dc-to-dc conversion ratio and is limited by the minimum and maximum controllable duty cycle, as shown in Figure 55. This is due to the requirement of minimum on time and minimum off time for current sensing and robust operation. Rev. C | Page 18 of 32 Figure 56. Frequency vs. Resistance 300 350 Data Sheet ADP2441 SOFT START The soft start function limits the input inrush current and prevents output overshoot at startup. The soft start time is programmed by connecting a small ceramic capacitor between the SS/TRK and AGND pins, with the value of this capacitor defining the soft start time, tSS, as follows: I VREF = SS t SS C SS (5) where: VREF is the internal reference voltage and equals 0.6 V. ISS is the soft start current and equals 1 μA. CSS is the soft start capacitor value. Table 7. Soft Start Time Selection Soft Start Capacitor (nF) 5 10 20 Soft Start Time (ms) 3 6 12 Alternatively, the user can float the SS/TRK pin and use the internal soft start time of 2 ms. EXTERNAL COMPONENTS SELECTION Input Capacitor Selection The input current to a buck regulator is pulsating in nature. The current is zero when the high-side switch is off and is approximately equal to the load current when the switch is on. Because switching occurs at reasonably high frequencies (300 kHz to 1 MHz), the input bypass capacitor usually supplies most of the high frequency current (ripple current), allowing the input power source to supply only the average (dc) current. The input capacitor needs a sufficient ripple current rating to handle the input ripple and needs an ESR that is low enough to mitigate the input voltage ripple. In many cases, different types of capacitors are placed in parallel to minimize the effective ESR and ESL. Table 10 shows a list of recommended MLCC capacitors from Murata and Taiyo Yuden. For large step load transients, add more bulk capacitance by, for example, using electrolytic or polymer capacitors. Make sure that the ripple current rating of the bulk capacitor exceeds the minimum input ripple current of a particular design. Inductor Selection The high switching frequency of the ADP2441 allows for minimal output voltage ripple even when small inductors are used. Selecting the size of the inductor involves considering the trade-off between efficiency and transient response. A smaller inductor results in larger inductor current ripple, which provides excellent transient response but degrades efficiency. Due to the high switching frequency of the ADP2441, using shielded ferrite core inductors is recommended because of their low core losses and low EMI. The inductor ripple current also affects the stability of the loop because the ADP2441 uses the emulated peak current mode architecture. In the traditional approach of slope compensation, the user sets the inductor ripple current and then sets the slope compensation using an external ramp resistor. In most cases, the inductor ripple current is typically set to be 1/3 of the maximum load current for optimal transient response and efficiency. The ADP2441 has internal slope compensation, which assumes that the inductor ripple current is set to 0.3 A (30% of the maximum load of 1 A), eliminating the need for an external ramp resistor. For the ADP2441, choose an inductor such that the peak-to-peak ripple current of the inductor is between 0.2 A and 0.5 A for stable operation. Therefore, calculate the inductor value as follows: ∆I L = I OUT × D × (1 − D) (VPP − I OUT × D × RESR ) f SW 2 × VOUT × (VIN − VOUT ) 5 × VOUT × (VIN − VOUT ) ≤L≤ VIN × f SW VIN × f SW (6) where: VPP is the desired input ripple voltage. RESR is the equivalent series resistance of the capacitor. IOUT is the maximum load current. C IN _ MIN = I OUT × D × (1 − D) VPP × f SW LIDEAL = 3.3 × VOUT × (VIN − VOUT ) VIN × f SW where: VIN is the input voltage. VOUT is the desired output voltage. fSW is the regulator switching frequency. It is recommended to use a ceramic bypass capacitor because the ESR associated with this type of capacitor is near zero, simplifying the equation to For applications with a wide input (VIN) range, choose the inductor based on the geometric mean of the input voltage extremes. (7) In addition, it is recommended to use a ceramic capacitor with a voltage rating that is 1.5 times the input voltage with X5R and X7R dielectrics. Using Y5V and Z5U dielectrics is not recommended due to their poor temperature and dc bias characteristics. (8) 0.2 A ≤ ΔIL ≤ 0.5 A The minimum input capacitance required for a particular load is C IN _ MIN = VOUT × (VIN − VOUT ) VIN × f SW × L VIN (GEOMETRIC ) = VIN _ MAX × VIN _ MIN where: VIN_MAX is the maximum input voltage. VIN_MIN is the minimum input voltage. Rev. C | Page 19 of 32 (9) ADP2441 Data Sheet The inductor value is based on VIN(GEOMETRIC) as follows: LIDEAL = Output Capacitor Selection 3.3 × VOUT × (VIN (GEOMETRIC ) − VOUT ) VIN (GEOMETRIC ) × f SW Table 8. Inductor Values for Various VIN, VOUT, and fSW Combinations fSW (kHz) 300 300 300 300 300 300 300 300 600 600 600 600 600 600 600 1000 1000 1000 1000 VIN (V) 12 12 24 24 24 36 36 36 12 12 24 24 24 36 36 12 24 24 36 VOUT (V) 3.3 5 3.3 5 12 3.3 5 12 3.3 5 3.3 5 12 3.3 5 5 5 12 5 Inductor Value Min (µH) Max (µH) 22 27 27 33 27 33 39 47 56 68 27 33 39 47 68 82 12 15 15 18 15 18 18 22 27 33 15 18 22 27 6.8 10 10 12 18 22 12 15 To avoid inductor saturation and ensure proper operation, choose the inductor value so that neither the saturation current nor the maximum temperature rated current ratings are exceeded. Inductor manufacturers specify both of these ratings in data sheets or the rating can be calculated as follows: I L _ PEAK ∆I = I LOAD( MAX ) + L 2 (10) where: ILOAD(MAX) is the maximum dc load current. ΔIL is the peak-to-peak inductor ripple current. Table 9. Recommended Inductors Value (µH) 10 18 33 15 Small Size Inductors (10 mm × 10 mm) MSS1260 MSS1260 MSS1260 MSS1260 The output capacitor selection affects both the output voltage ripple and the loop dynamics of the regulator. The ADP2441 is designed to operate with small ceramic output capacitors that have low ESR and ESL; therefore, the device can easily meet tight output voltage ripple specifications. For best performance, use X5R or X7R dielectric capacitors with a voltage rating that is 1.5 times the output voltage and avoid using Y5V and Z5U dielectric capacitors, which have poor temperature and dc bias characteristics. Table 10 lists some recommended capacitor from Murata and Taiyo Yuden. For acceptable maximum output voltage ripple, determine the minimum output capacitance, COUT(MIN), as follows:  1 ∆VRIPPLE ≅ ∆I L ×  ESR +  8 × f × COUT ( MIN ) SW      (11) Therefore, COUT ( MIN ) ≅ ∆I L 8 × f SW × (∆VRIPPLE − ∆I L × ESR) (12) where: ΔVRIPPLE is the allowable peak-to-peak output voltage ripple. ΔIL is the inductor ripple current. ESR is the equivalent series resistance of the capacitor. fSW is the switching frequency of the regulator. If there is a step load requirement, choose the output capacitor value based on the value of the step load. For the maximum acceptable output voltage droop/overshoot caused by the step load,  3 COUT ( MIN ) ≅ ∆I OUT (STEP ) ×   f SW × ∆VDROOP     (13) where: ΔIOUT(STEP) is the load step. fSW is the switching frequency of the regulator. ΔVDROOP is the maximum allowable output voltage droop/overshoot. Select the largest output capacitance given by Equation 12 and Equation 13. When choosing the type of ceramic capacitor for the output filter of the regulator, select one with a nominal capacitance that is 20% to 30% larger than the calculated value because the effective capacitance degrades with dc voltage and temperature. Figure 57 shows the capacitance loss due to the output voltage dc bias for three X7R MLCC capacitors from Murata. Rev. C | Page 20 of 32 Data Sheet ADP2441 LOOP COMPENSATION 30.0 The ADP2441 uses peak current mode control architecture for excellent load and line transient response. This control architecture has two loops: an external voltage loop and an inner current loop. The inner current loop senses the current in the low-side switch and controls the duty cycle to maintain the average inductor current. Slope compensation is added to the inner current loop to ensure stable operation when the duty cycle is above 50%. 19.2 22µF/25V 13.8 10µF/25V 3.00 0 5 10 15 DC BIAS VOLTAGE (V) 20 25 10581-157 8.40 The external voltage loop senses the output voltage and adjusts the duty cycle to regulate the output voltage to the desired value. A transconductance amplifier with an external series RC network connected to the COMP pin compensates the external voltage loop. ADP2441 Figure 57. Capacitance vs. DC Bias Voltage COMP For example, to attain 20 μF of output capacitance with an output voltage of 5 V while providing some margin for temperature variation, use a 22 μF capacitor with a voltage rating of 25 V and a 10 μF capacitor with a voltage rating of 25 V in parallel. This configuration ensures that the output capacitance is sufficient under all conditions and, therefore, that the device exhibits stable behavior. gm 0.6V BOOST CAPACITOR The boost pin (BST) is used to power up the internal driver for the high-side power MOSFET. In the ADP2441, the high-side power MOSFET is an N-channel device to achieve high efficiency in mid and high duty cycle applications. To power up the high-side driver, a capacitor is required between the BST and SW pins. The size of this boost capacitor is critical because it affects the light load functionality and efficiency of the device. Therefore, choose a boost ceramic capacitor with a value between 10 nF to 22 nF with a voltage rating of 50 V and place the capacitor as close as possible to the IC. It is recommended to use a boost capacitor within this range because a capacitor beyond 22 nF can cause the LDO to reach the current-limit threshold. Figure 58. RC Compensation Network LARGE SIGNAL ANALYSIS OF THE LOOP COMPENSATION The control loop can be broken down into the following three sections: • • • VOUT to VCOMP VCOMP to IL IL to VOUT VIN INDUCTOR CURRENT SENSE PULSE-WIDTH MODULATOR VOUT COUT VCOMP VCC CAPACITOR IL RLOAD Gmgm VREF = 0.6V The ADP2441 has an internal regulator to power up the internal controller and the low-side driver. The VCC pin is the output of the internal regulator. The internal regulator provides the pulse current when the low-side driver turns on. Therefore, it is recommended that a 1 µF ceramic capacitor be placed between the VCC and PGND pins as close as possible to the IC and that a 1 µF ceramic capacitor be placed between the VCC and AGND pins. Rev. C | Page 21 of 32 ADP2441 RCOMP CCOMP 10581-055 Capacitor 10 µF/25 V 22 µF/25 V 47 µF/6.3 V 4.7 µF/50 V CCOMP AGND Table 10. Recommended Output Capacitors for ADP2441 Vendor Murata Taiyo Yuden GRM32DR71E106KA12L TMK325B7106KN-TR GRM32ER71E226KE15L TMK325B7226MM-TR GCM32ER70J476KE19L JMK325B7476MM-TR GRM31CR71H475KA12L UMK325B7475MMT RCOMP VFB 10581-054 CAPACITANCE (µF) 24.6 Figure 59. Large Signal Model ADP2441 Data Sheet Correspondingly, there are three transfer functions: VCOMP (s) VREF = × g m × Z COMP (s) VOUT (s) VOUT (14) I L (s ) = GCS VCOMP (s) (15) VOUT (s) = Z FILT (s) I L (s ) (16) where: gm is the transconductance of the error amplifier and equals 250 µA/V. GCS is the current sense gain and equals 2 A/V. VOUT is the output voltage of the regulator. VREF is the internal reference voltage and equals 0.6 V. ZCOMP(s) is the impedance of the RC compensation network that forms a pole at the origin and a zero as expressed in Equation 17. 1 + s × RCOMP × CCOMP ZCOMP (s) = s × CCOMP (17) ZFILT(s) is the impedance of the output filter and is expressed as Z FILT (s) = RLOAD 1 + s × RLOAD × COUT At the crossover frequency, the gain of the open-loop transfer function is unity. H(fCROSSOVER) = 1 This yields Equation 21 for the RC compensation network impedance at the crossover frequency. ZCOMP ( fCROSSOVER ) = ZCOMP ( fCROSSOVER ) = f ZERO = 1 + 2 × π × fCROSSOVER × RCOMP × CCOMP 2 × π × fCROSSOVER × CCOMP (22) 1 2 × π × RCOMP × CCOMP ≈ fCROSSOVER 8 (23) Solving Equation 21, Equation 22, and Equation 23 yields the value for the resistor and capacitor in the RC compensation network, as shown in Equation 24 and Equation 25. (18) (19) (21) To ensure that there is sufficient phase margin at the crossover frequency, place the compensator zero at 1/8 of the crossover frequency, as shown in the following equation: RCOMP = 0.9 × CCOMP = The overall loop gain, H(s), is obtained by multiplying the three transfer functions previously mentioned as follows: VREF × Z COMP (s) × Z FILT (s) VOUT 2 × π × fCROSSOVER × COUT VOUT × VREF g m × GCS Placing s = fCROSSOVER in Equation 17, where s is the angular frequency, which can be written as s = 2πf. H (s) = g m × GCS × (20) 2 × π × f CROSSOVER COUT × VOUT × g m × GCS VREF 1 2 × π × f ZERO × RCOMP (24) (25) Using these equations allows calculating the compensations for the voltage loop. When the switching frequency (fSW), output voltage (VOUT), output inductor (L), and output capacitor (COUT) values are selected, the unity crossover frequency can be set to 1/12 of the switching frequency. Rev. C | Page 22 of 32 Data Sheet ADP2441 DESIGN EXAMPLE Consider an application with the following specifications: Soft Start Capacitor • • • • • • • For a given soft start time, the soft start capacitor can be calculated using Equation 5, VIN =24 V ± 10% VOUT = 5 V ± 1% Switching frequency = 700 kHz Load = 800 mA typical Maximum load current = 1 A Soft start time = 6 ms Overshoot ≤ 2% under all load transient conditions I VREF = SS t SS C SS C SS = CONFIGURATION AND COMPONENTS SELECTION CSS = Resistor Divider L IDEAL = VREF 0. 6 = = 10 kΩ I STRING 60 μA     Choosing the switching frequency involves considering the trade-off between efficiency and component size. Low frequency improves the efficiency by reducing the gate losses but requires a large inductor. The choice of high frequency is limited by the minimum and maximum duty cycle. = 18.66 μH ≈ 18.3 μH The input filter consists of a small 0.1 µF ceramic capacitor placed as close as possible to the IC. The minimum input capacitance required for a particular load is CIN _ MIN = Duty Cycle DNOMINAL = 20.8% DMIN = 19% DMAX = 23% Based on the estimated duty cycle range, choose the switching frequency according to the minimum and maximum duty cycle limitations, as shown in Figure 55. For example, a 700 kHz, frequency is well within the maximum and minimum duty cycle limitations. RFREQ 24 V × 700 kHz Input Capacitor Selection Table 11. Duty Cycle 92,500 = f SW 3.3 × 5 V × (24 − 5) V In Equation 9, VIN = 24 V, VOUT = 5 V, ILOAD(MAX) = 1 A, and fSW = 700 kHz, which results in L = 18.66 µH. When L = 18 μH (the closest standard value) in Equation 8, ΔIL = 0.314 A. Although the maximum output current required is 1 A, the maximum peak current is 1.6 A. Therefore, the inductor should be rated for higher than 1.6 A current. Switching Frequency Using Equation 4, = 10 nF 3.3 × VOUT × (VIN − VOUT ) VIN × f SW LIDEAL =  5 V − 0. 6 V   = 73.3 kΩ RTOP = 10 kΩ ×   0. 6 V    VIN 24 V (Nominal) 26 V (10% Above Nominal) 22 V (10% Less than Nominal) 0. 6 V Select the inductor by using Equation 9. Using Equation 2 and Equation 3, V − VREF RTOP = R BOTTOM ×  OUT VREF  1 μA × 6 ms Inductor Selection The first step in selecting the external components is to calculate the resistance of the resistor divider that sets the output voltage. RBOTTOM = I SS × t SS VREF IOUT × D × (1 − D) VPP × f SW where: VPP = 50 mV. IOUT = 1 A. D = 0.23. fSW = 700 kHz. Therefore, C IN _ MIN = 1 A × 0.22 × (1 − 0.22) 0.05 V × 700 kHz ≈ 4.9 μF Choosing an input capacitor of 10 µF with a voltage rating of 50 V ensures sufficient capacitance over voltage and temperature. RFREQ = 132 kΩ Rev. C | Page 23 of 32 ADP2441 Data Sheet Output Capacitor Selection Select the output capacitor by using Equation 12 and Equation 13: COUT ( MIN ) ≅ ∆I L Table 13. Calculated Parameter Value 8 × f SW × (∆VRIPPLE − ∆I L × ESR) Parameter fCROSSOVER fZERO VREF gm Equation 12 is based on the output voltage ripple (ΔVRIPPLE), which is 1% of the output voltage.  3 COUT ( MIN ) ≅ ∆I OUT (STEP )   f SW × ∆VDROOP Selecting the crossover frequency to be 1/12 of the switching frequency and placing the zero frequency at 1/8 of the crossover frequency ensures that there is enough phase margin in the system.     Equation 13 calculates the capacitor selection based on the transient load performance requirement of 2%. Perform these calculations, and then use the equation that yields the larger capacitor size to select a capacitor. In this example, the values listed in Table 12 are substituted for the variables in Equation 12 and Equation 13. GCS COUT VOUT Test Conditions/Comments Fixed at 0.3 A for the ADP2441 1% of VOUT 2% of VOUT Value 0.3 A 50 mV 100 mV 5 mΩ 700 kHz The calculation based on the output voltage ripple (see Equation 12) dictates that the minimum output capacitance is COUT ( MIN ) ≅ 0. 3 A 8 × 700 kHz × (50 mV − 0.3 A × 5 mΩ) = 1.1 μF whereas the calculation based on the transient load (see Equation 13) dictates that the minimum output capacitance is COUT ( MIN ) ≅ 0.5 × 3 ≈ 22 µF 700 kHz × 0.1 V RCOMP = 0.9 × COUT = 1.5 × 22 µF = 32 µF Compensation Selection CCOMP = CCOMP = 2 × π × 58.3 22 × 5 × ≈ 121 kΩ 250 × 2 0. 6 1 = 185 pF ≈ 180 pF 2 × π × 7.3 × 118 SYSTEM CONFIGURATION Configure the system as follows: 1. 2. 3. 5. Connect a capacitor of 1 µF between the VCC and PGND pins and another capacitor of 1 µF between the VCC and AGND pins. For best performance, use ceramic X5R or X7R capacitors with a 25 V voltage rating. Connect a ceramic capacitor of 10 nF with a 50 V voltage rating between the BST and SW pins. Connect a resistor between the FREQ and AGND pins as close as possible to the IC. If using the power-good feature, connect a pull-up resistor of 50 kΩ to an external supply of 5 V. Connect a capacitor of 10 nF between the SS and AGND pins. If the tracking feature is needed, connect a resistor divider between the TRK pin and another supply, as shown in Figure 50. See Figure 60 for a schematic of this design example and Table 14 for the calculated component values. Calculate the compensation component values for the feedback loop by using the following equations: RCOMP = 0.9 × 2 A/V 22 µF 5V The closest standard resistor value is 118 kΩ. Therefore, 4. To meet both requirements, use the value determined by the latter equation. As shown in Figure 57, capacitance degrades with dc bias; therefore, choose a capacitor that is 1.5 times the calculated value. Value 58.3 kHz 7.3 kHz 0.6 V 250 µA/V Based on the values listed in Table 13, calculate the compensation value: Table 12. Requirements Parameter Ripple Current Voltage Ripple Voltage Droop Due to Load Transient ESR fSW Test Conditions/Comments 1/12 of fSW 1/8 of fCROSSOVER Fixed reference Transconductance of error amplifier Current sense gain Output capacitor Output voltage 2 × π × f CROSSOVER COUT × VOUT × g m × GCS VREF 1 2 × π × f ZERO × RCOMP Rev. C | Page 24 of 32 Data Sheet ADP2441 TYPICAL APPLICATION CIRCUITS DESIGN EXAMPLE VIN = 24 V ± 10%, VOUT = 5 V, fSW = 700 kHz. C3 1µF/25V BST VCC VIN SS/TRK FREQ C1 4.7µF/ 50V L1 18µH VOUT 5V, 1A SW C6 0.1µF C7 22µF C8 10µF PGND EXT R7 50kΩ PGOOD R9 132kΩ C11 10nF TRK 10581-057 R2 73.3kΩ COMP EN C2 4.7µF/ 50V ADP2441 PGOOD C10 180pF AGND FB R5 118kΩ R3 10kΩ VIN 24V C5 10nF/50V C4 1µF/25V Figure 60. ADP2441 Typical Application Circuit, VIN = 24 V ± 10%, VOUT = 5 V, fSW = 700 kHz Table 14. Calculated Component Values for Figure 60 Qty. 2 2 2 1 1 1 1 1 1 1 1 1 1 Reference Designator C1, C2 C3, C4 C5, C11 C7 C8 L1 C6 C10 R9 R5 R2 R3 R7 Value 4.7 µF 1 µF 10 nF 22 µF 10 µF 18.3 µH 0.1 µF 185 pF 132 kΩ 118 kΩ 74 kΩ 10 kΩ 50 kΩ Description Capacitor ceramic, X7R, 50 V Capacitor ceramic, 1 µF, 25 V, X7R, 10%, 0603 Capacitor ceramic, 10,000 pF, 50 V, 10%, X7R, 603 Capacitor ceramic, 22 µF, 25 V, X7R, 1210 Capacitor ceramic, 10 µF, 25 V, X7R, 1210 Inductor, 18.3 µH Capacitor ceramic, 0.1 µF, 50 V, X7R, 0805 Capacitor ceramic, 50 V Resistor, 1/10 W, 1%, 0603, SMD Resistor, 1/10 W, 1%, 0603, SMD Resistor, 1/10 W, 1%, 0603, SMD Resistor, 1/10 W, 1%, 0603, SMD Resistor, 1/10 W, 1%, 0603, SMD Rev. C | Page 25 of 32 Part Number GRM31CR71H475KA12L GRM188R71E105KA12D ECJ-1VB1H103K GRM32ER71E226K GRM32DR71E106KA12L CoilCraft MSS1260T-183NLB ECJ-2FB1H104K Vishay, Panasonic ADP2441 Data Sheet OTHER TYPICAL CIRCUIT CONFIGURATIONS VIN = 24 V ± 10%, VOUT = 12 V, fSW = 600 kHz. C3 1µF/25V C4 1µF/25V R2 191kΩ VIN 24V C2 4.7µF/ 50V C1 4.7µF/ 50V BST VCC SS/TRK FREQ COMP EN VIN ADP2441 PGOOD C10 220pF AGND FB R5 121kΩ R3 10kΩ C5 10nF/50V L1 33.3µH VOUT 12V, 1A SW C6 0.1µF PGND C7 22µF/ 25V EXT R7 50kΩ FSW 600kHz PGOOD C11 10nF TRK 10581-058 R9 154kΩ Figure 61. ADP2441 Typical Application Circuit, VIN = 24 V ± 10%, VOUT = 12 V, fSW = 600 kHz Table 15. Calculated Component Values for Figure 61 Qty. 2 2 2 1 1 1 1 1 1 1 1 1 Reference Designator C1, C2 C3, C4 C5, C11 C7 L1 C6 C10 R9 R5 R2 R3 R7 Value 4.7 µF 1 µF 10 nF 22 µF 33.3 µH 0.1 µF 220 pF 154 kΩ 121 kΩ 191 kΩ 10 kΩ 50 kΩ Description Capacitor ceramic, X7R, 50 V Capacitor ceramic, 1 µF, 25 V, X7R, 10%, 0603 Capacitor ceramic, 10,000 pF, 50 V, 10%, X7R, 0603 Capacitor ceramic, 22 µF, 25 V, X7R, 1210 Inductor, 33.3 µH Capacitor ceramic, 0.1 µF, 50 V, X7R, 0805 Capacitor ceramic, 50 V Resistor, 1/10 W, 1%, 0603, SMD Resistor, 1/10 W, 1%, 0603, SMD Resistor, 1/10 W, 1%, 0603, SMD Resistor, 1/10 W, 1%, 0603, SMD Resistor, 1/10 W, 1%, 0603, SMD Rev. C | Page 26 of 32 Part Number GRM31CR71H475KA12L GRM188R71E105KA12D ECJ-1VB1H103K GRM32ER71E226K CoilCraft MSS1038-333ML ECJ-2FB1H104K Vishay, Panasonic Data Sheet ADP2441 VIN = 12 V ± 10%, VOUT = 5 V, fSW = 500 kHz. C3 1µF/25V C4 1µF/25V R2 73.3kΩ C2 4.7µF/ 50V C1 4.7µF/ 50V L1 18µH VOUT 5V, 1A SW C6 0.1µF PGND EXT R7 50kΩ VIN 12V BST VCC FREQ SS/TRK COMP EN VIN ADP2441 PGOOD C10 270pF AGND FB R5 118kΩ R3 10kΩ C5 10nF/50V C7 22µF C8 22µF FSW 500kHz PGOOD TRK 10581-059 R9 185kΩ C11 10nF Figure 62. ADP2441 Typical Application Circuit, VIN = 12 V ± 10%, VOUT = 5 V, fSW = 500 kHz Table 16. Calculated Component Values for Figure 62 Qty. 2 2 2 1 1 1 1 1 1 1 1 1 1 Reference Designator C1, C2 C3, C4 C5, C11 C7 C8 L1 C6 C10 R9 R5 R2 R3 R7 Value 4.7 µF 1 µF 10 nF 22 µF 22 µF 18.3 µH 0.1 µF 270 pF 185 kΩ 118 kΩ 74 kΩ 10 kΩ 50 kΩ Description Capacitor ceramic, X7R, 50 V Capacitor ceramic, 1 µF, 25 V, X7R, 10%, 0603 Capacitor ceramic, 10,000 pF, 50 V, 10%, X7R, 0603 Capacitor ceramic, 22 µF, 25 V, X7R, 1210 Capacitor ceramic, 22 µF, 25 V, X7R, 1210 Inductor, 18.3 µH Capacitor ceramic, 0.1 µF, 50 V, X7R, 0805 Capacitor ceramic, 50 V Resistor, 1/10 W, 1%, 0603, SMD Resistor, 1/10 W, 1%, 0603, SMD Resistor, 1/10 W, 1%, 0603, SMD Resistor, 1/10 W, 1%, 0603, SMD Resistor, 1/10 W, 1%, 0603, SMD Rev. C | Page 27 of 32 Part Number GRM31CR71H475KA12L GRM188R71E105KA12D ECJ-1VB1H103K GRM32ER71E226K CoilCraft MSS1038-183ML ECJ-2FB1H104K Vishay, Panasonic ADP2441 Data Sheet VIN = 36 V ± 10%, VOUT = 3.3 V, fSW = 300 kHz. C3 1µF/25V C4 1µF/25V R2 45kΩ EXT R7 50kΩ VIN 36V C2 4.7µF/ 50V C1 4.7µF/ 50V BST VCC SS/TRK FREQ COMP EN VIN ADP2441 PGOOD C10 560pF AGND FB R5 91kΩ R3 10kΩ C5 10nF/50V L1 33.3µH VOUT 3.3V, 1A SW C6 0.1µF PGND C7 47µF C8 47µF FSW 300kHz PGOOD C11 10nF TRK 10581-060 R9 300kΩ Figure 63. ADP2441 Typical Application Circuit, VIN = 36 V ± 10%, VOUT = 3.3 V, fSW = 300 kHz Table 17. Calculated Component Values for Figure 63 Qty. 2 2 2 1 1 1 1 1 1 1 1 1 1 Reference Designator C1, C2 C3, C4 C5, C11 C7 C8 L1 C6 C10 R9 R5 R2 R3 R7 Value 4.7 µF 1 µF 10 nF 47 µF 47 µF 33.3 µH 0.1 µF 560 pF 300 kΩ 91 kΩ 45 kΩ 10 kΩ 50 kΩ Description Capacitor ceramic, X7R, 50 V Capacitor ceramic, 1 µF, 25 V, X7R, 10%, 0603 Capacitor ceramic, 10,000 pF, 50 V, 10%, X7R, 0603 Capacitor ceramic, 47 µF, 6.3 V, X7R, 1210 Capacitor ceramic, 47 µF, 6.3 V, X7R, 1210 Inductor, 33.3 µH Capacitor ceramic, 0.1 µF, 50 V, X7R, 0805 Capacitor ceramic, 50 V Resistor, 1/10 W, 1%, 0603, SMD Resistor, 1/10 W, 1%, 0603, SMD Resistor, 1/10 W, 1%, 0603, SMD Resistor, 1/10 W, 1%, 0603, SMD Resistor, 1/10 W, 1%, 0603, SMD Rev. C | Page 28 of 32 Part Number GRM31CR71H475KA12L GRM188R71E105KA12D ECJ-1VB1H103K GRM32ER70J476KE20L GRM32ER70J476KE20L CoilCraft MSS1038T-333ML ECJ-2FB1H104K Vishay, Panasonic Data Sheet ADP2441 POWER DISSIPATION AND THERMAL CONSIDERATIONS POWER DISSIPATION Transition Losses The efficiency of a dc-to-dc regulator is where: PIN is the input power. POUT is the output power. Transition losses occur because the N-channel MOSFET power switch cannot turn on or off instantaneously. During a switch node transition, the power switch provides all of the inductor current, and the source-to-drain voltage of the power switch is half the input, resulting in power loss. Transition losses increase as the load current and input voltage increase, and these losses occur twice for each switching cycle. The power loss of a dc-to-dc regulator is The transition losses can be calculated as follows: Efficiency  POUT  100% PIN (26) PLOSS = PIN − POUT PTRANS  There are four main sources of power loss in a dc-to-dc regulator:     THERMAL CONSIDERATIONS The power dissipated by the regulator increases the die junction temperature, TJ, above the ambient temperature, TA, as follows: Inductor Losses Inductor conduction losses are caused by the flow of current through the inductor DCR (internal resistance). The inductor power loss (excluding core loss) is (27) Power Switch Conduction Losses Power switch conductive losses are due to the output current, IOUT, flowing through the N-channel MOSFET power switches that have internal resistance, RDS(ON). The amount of power loss can be approximated as follows: PCOND = [RDS(ON) – High Side × D + RDS(ON) − Low Side × (1 − D)] × IOUT2 (28) Switching Losses Switching losses are associated with the current drawn by the driver to turn the power devices on and off at the switching frequency. Each time a power device gate is turned on and off, the driver transfers a charge (ΔQ) from the input supply to the gate and then from the gate to ground. The amount of switching loss can by calculated as follows: PSW = QG_TOTAL × VIN × fSW (30) where tON and tOFF are the rise time and fall time of the switch node and are each approximately 10 ns for a 24 V input. Inductor losses Power switch conduction losses Switching losses Transition losses PL = IOUT2 × DCRL VIN  I OUT  (t ON  t OFF ) f SW 2 (29) TJ = TA + TR (31) where the temperature rise, TR, is proportional to the power dissipation, PD, in the package. The proportionality coefficient is defined as the thermal resistance from the junction temperature of the die to the ambient temperature as follows: TR = θJA + PD (32) where θJA is the junction-to-ambient thermal resistance and equals 40°C/W for the JEDEC board (see Table 3). When designing an application for a particular ambient temperature range, calculate the expected ADP2441 power dissipation (PD) due to the conduction, switching, and transition losses using Equation 28, Equation 29, and Equation 30, and then estimate the temperature rise using Equation 31 and Equation 32. Improved thermal performance can be achieved by implementing good board layout. For example, on the ADP2441 evaluation board (ADP2441-EVALZ), the measured θJA is