Power Management IC for
Circuit Breaker Applications
ADP2450
Data Sheet
TYPICAL APPLICATION CIRCUIT
CT CURRENT
VOUT1
DIODE
ADP2450
BOOST
SHUNT
CONTROL
COUT1
ACTUATOR
RBOT1
ACTUATOR
DRIVER
MCU
VOUT1
CIN2
SENSED
VOLTAGE
BUCK
REGULATOR
VOUT2
CBST
L
VCORE
COUT2
ADCs
PGAs
GPIO1
GAIN
SELECTION
RGAIN
RTRP
ANALOG
TRIP
GPIO2
17088-001
Boost shunt controller
Adjustable output voltage range: 4.5 V to 36 V
Integrated boost shunt driver
Programmable power detection threshold
Buck regulator
Input voltage range: 4.5 V to 36 V
Continuous output current: 500 mA
Adjustable output voltage down to 0.6 V
Fixed output options: 3.3 V and 5 V
1.2 MHz fixed switching frequency
Voltage monitoring and open-drain reset output
4 programmable gain amplifiers
Low power consumption
Programmable gain and output dc common voltage
Low offset operation amplifier for leakage and grounding
fault current detection
Analog trip circuit with programmable trip threshold
Actuator driver output
RTOP1
FEATURES
Figure 1.
APPLICATIONS
Low voltage circuit breaker
CT powered supply
GENERAL DESCRIPTION
The ADP2450 integrates one boost shunt controller with power
detection, one high efficiency buck regulator, four low offset,
low power consumption programmable gain amplifiers (PGAs),
one low offset operation amplifier, a fast analog trip circuit, and
an actuator driver. The ADP2450 is targeted for low voltage
circuit breakers, such as the molded case circuit breaker (MCCB),
and current transformer (CT) powered supply applications.
reset signal is pulled low and can be used to reset the
microprocessor. The monitoring supervisory circuit makes the
system more reliable.
The boost output voltage can be up to 36 V and integrates a power
detection circuit that prevents the circuit from power hiccups.
The power detection threshold is programmable with resistors.
A low offset operation amplifier is integrated in the ADP2450
for leakage current detection.
The buck regulator operates over a wide input voltage range of
4.5 V to 36 V, and the output voltage can be adjusted down to
0.6 V. The buck regulator provides output currents of up to
500 mA. The buck regulator works in pulse-width modulation
(PWM) mode with a fixed 1.2 MHz switching frequency,
providing low output ripple voltage to the system.
Additional protection includes buck overcurrent protection
(OCP) and system thermal shutdown (TSD).
The output voltage of the buck regulator is monitored by the
supervisory circuit. When the output voltage is below the
monitoring threshold, 88% of VFB2 (FB2 regulation voltage), the
Rev. B
The ADP2450 integrates four low offset, low power consumption
amplifiers. With the programmable gain features, the ADP2450
provides accuracy measurement over a wide current input range
based on the CT turn ratio.
The ADP2450 also integrates an analog trip circuit, which
provides fast trip response and enhances system reliability.
The ADP2450 operates over the −40°C to +125°C junction
temperature range and is available in either a 32-lead LFCSP
package or a 48-lead LQFP package.
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ADP2450
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
External MOSFET for Boost Shunt Controller ...................... 27
Applications ....................................................................................... 1
Boost Shunt Diode Selection .................................................... 27
Typical Application Circuit ............................................................. 1
Input Capacitor of Buck Regulator .......................................... 27
General Description ......................................................................... 1
Inductor Selection ...................................................................... 27
Revision History ............................................................................... 2
Output Capacitor of Buck Regulator ....................................... 28
Functional Block Diagram .............................................................. 4
Output Voltage Setting .............................................................. 28
Specifications..................................................................................... 5
External MOSFET for Actuator ............................................... 29
Boost Shunt Controller and Power Detection Specifications . 5
Design Example .............................................................................. 30
Buck Regulator Specifications .................................................... 6
Boost Shunt Output Voltage Setting ........................................ 30
Programmable Gain Amplifier and Analog Trip
Specifications ................................................................................ 6
Boost Shunt Output Capacitor Setting .................................... 30
Operation Amplifier Specifications ........................................... 8
Boost Shunt Diode Setting ........................................................ 30
Absolute Maximum Ratings............................................................ 9
Buck Regulator Output Voltage Setting .................................. 30
Thermal Resistance ...................................................................... 9
Inductor Setting .......................................................................... 30
ESD Caution .................................................................................. 9
Buck Regulator Output Capacitor Setting .............................. 31
Pin Configurations and Function Descriptions ......................... 10
VPTH Resistor Divider Setting ................................................ 31
Typical Performance Characteristics ........................................... 12
Dummy Load Resistor Setting.................................................. 31
Theory of Operation ...................................................................... 22
PGA Gain Setting ....................................................................... 31
Boost Shunt Controller .............................................................. 22
Sense Resistor Setting ................................................................ 31
Power Detection ......................................................................... 22
Analog Trip Threshold Setting ................................................. 31
Internal Regulator ...................................................................... 22
Actuator MOSFET Setting ........................................................ 31
Buck Regulator ............................................................................ 23
Circuit Board Layout Recommendations ................................... 33
Bootstrap Circuit ........................................................................ 23
Ground Planes ............................................................................ 33
Power Monitor and Reset .......................................................... 23
Switch Node ................................................................................ 33
Programmable Gain Amplifier ................................................. 23
Feedback Paths ........................................................................... 33
Operational Amplifier ............................................................... 24
Power Traces ............................................................................... 33
Analog Trip Protection .............................................................. 24
Signal Paths ................................................................................. 33
Actuator Driver ........................................................................... 24
Gate Driver Paths ....................................................................... 33
Thermal Shutdown..................................................................... 25
Typical Application Circuits ..................................................... 35
Applications Information .............................................................. 26
Factory-Programmable Options .................................................. 37
Output Capacitor of Boost Shunt Controller ......................... 26
Outline Dimensions ....................................................................... 38
Bridge Rectifier ........................................................................... 26
Ordering Guide .......................................................................... 39
Boost Shunt MOSFET Setting .................................................. 30
Sense Resistor Selection ............................................................. 26
REVISION HISTORY
7/2019—Rev. A to Rev. B
Changes to Ordering Guide .......................................................... 39
4/2019—Rev. 0 to Rev. A
Added 48-lead LQFP .......................................................... Universal
Change to General Description Section ........................................ 1
Change to Figure 2 ........................................................................... 4
Change to DET Output Low Voltage Parameter, Table 1 ................ 5
Changes to Switch Node Parameter, Valley Current Limit
Parameter, and Reset Threshold Hysteresis Parameter, Table 2........ 6
Change to Gain Drift Parameter, Table 3 .......................................7
Added VTRPL Current Parameter, Table 3 and Endnote 3 to
Analog Trip, VTRPL Current Parameter, Table 3; Renumbered
Sequentially ........................................................................................7
Change to Input Offset Parameter, Table 4 ....................................8
Changes to Table 5 and Table 6 .......................................................9
Rev. B | Page 2 of 40
Data Sheet
ADP2450
Added Figure 4; Renumbered Sequentially .................................10
Changes to Table 7 ..........................................................................10
Changes to Typical Performance Characteristics Section,
Figure 6, and Figure 9 .....................................................................12
Change to Figure 13 ........................................................................13
Change to Figure 18 and Figure 21 ...............................................14
Replaced Figure 23 ..........................................................................15
Changes to Theory of Operation Section and Power
Detection Section ............................................................................22
Changes to Analog Trip Protection Section and Figure 68 ............. 24
Added Endnote 1 and Endnote 2 to Table 13 ..............................27
Changes to Boost Shunt Controller Output Voltage Section
and Buck Regulator Output Voltage Section ............................... 28
Changes to VPTH Resistor Divider Section, Dummy Load
Resistor Setting Section, and Sense Resistor Setting Section .... 31
Changes to Circuit Board Layout Recommendations Section....... 33
Changes to Figure 75 ...................................................................... 36
Updated Outline Dimensions........................................................ 38
Changes to Ordering Guide ........................................................... 38
9/2018—Revision 0: Initial Version
Rev. B | Page 3 of 40
ADP2450
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
8V
BOOST SHUNT CONTROLLER
+
DRIVER
DRV
PGND1
FB1
VREF1
–
UVLO_BOOST
DET
PW_OK
CONTROL
LOGIC
–
CMP
1.22V
+
8V
REGULATOR
UVLO
VPTH
UVLO_BUCK
UVLO_BOOST
5V
REGULATOR
VREG
GND
8V
POWER DETECTION
VREG
BUCK REGULATOR
SOFT
START
VREF2
FB2
VIN
BST
+
+ EA
–
–
CMP
+
PW_OK
TSD
CONTROL
LOGIC AND
MOSFET
DRIVER
WITH
ANTICROSS
PROTECTION
DRIVER
SW
VREG
UVLO_BUCK
DRIVER
CLK
PGND2
SLOPE
COMPENSATION
AND RAMP
GENERATOR
+
OCP
–
–
+
ILIM
LOW-SIDE
CURRENT SENSE
RSTO
+
89% × VREF2
GAIN0
GAIN1
RESET GENERATOR
–
GAIN
SETTING
AVDD
PGA1
–
EIN1
EOUT1
+
PGA2
–
EIN2
EOUT2
+
PGA3
–
EIN3
EOUT3
+
PGA4
–
EIN4
EOUT4
+
RCOM
VCOM
EIN5_N
–
EIN5_P
+
EOUT1
EOUT2
EOUT3
EOUT4
AMPLIFIER 5
EOUT5
VTRP
ANALOG TRIP
VTRPL
VREG
ACTUATOR
DRIVER CONTROL
DRIVER
GATE
17088-002
TRG
Figure 2. Functional Block Diagram
Rev. B | Page 4 of 40
Data Sheet
ADP2450
SPECIFICATIONS
BOOST SHUNT CONTROLLER AND POWER DETECTION SPECIFICATIONS
VIN = 12 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 1.
Parameter
POWER INPUT
Input Voltage Range
Quiescent Current1
Undervoltage Lockout Threshold (UVLO)2
VIN Rising
VIN Falling
FEEDBACK (FB1)
FB1 Regulation Voltage
FB1 Hysteresis
FB1 Bias Current
Hysteresis Comparator Response Time
BOOST SHUNT DRIVER (DRV)
Rising Time3
Falling Time3
Sourcing Resistor
Sinking Resistor
Peak Source Current4
Sink Source Current4
DRV Output High Voltage
INTERNAL REGULATOR (VREG)
VREG Voltage
Dropout Voltage
Regulator Current Limit
POWER DETECTION
VPTH Rising Threshold
VPTH Falling Threshold
VPTH Source Current
Power Detection Deglitch Time
DET Output Low Voltage
Maximum Sink Current on DET
ACTUATOR DRIVER (TRG AND GATE)
Input High Voltage
Input Low Voltage
Deglitch Time
GATE Maximum Source Current
GATE Driver Output Voltage
THERMAL
Thermal Shutdown Threshold4
Thermal Shutdown Hysteresis4
Symbol
VIN
IQ_VIN
Test Conditions/Comments
VIN pin
Min
Unit
36
V
mA
2.5
2.4
2.7
V
V
1.2
19
0.01
100
1.218
V
mV
μA
ns
1.35
Falling
1.182
IFB1
CDRV = 2.2 nF, from 0.8 V to 7.2 V
CDRV = 2.2 nF, from 7.2 V to 0.8 V
VDRV_H
VVREG
Max
4.5
VIN =12 V, FB1 = GND, FB2 = 0.65 V, no switching
2.2
VFB1
Typ
7.6
IVREG = 5 mA
IVREG = 5 mA
VPTH_R
VPTH_F
4.7
1.05
VPTH voltage < 1.09 V
VPTH voltage > 1.22 V
IDET = 20 mA
IDET_MAX
TRG pin
TRG pin
TRG pin
GATE pin
GATE pin
1
This current is measured from the VIN pin.
This UVLO threshold is only for the boost control block.
3
Bench measurement result.
4
Guaranteed by design, not production tested.
2
Rev. B | Page 5 of 40
80
35
4
2
1
1
8
0.1
8.4
ns
ns
Ω
Ω
A
A
V
5
27
200
5.3
V
mV
mA
1.22
1.09
4.8
1
10
0.3
100
1.25
V
V
μA
μA
μs
V
mA
0.55
1.2
30
85
5
V
V
μs
mA
V
150
15
°C
°C
0.4
ADP2450
Data Sheet
BUCK REGULATOR SPECIFICATIONS
VIN = 12 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 2.
Parameter
POWER INPUT
Undervoltage Lockout Threshold1
VIN Rising
VIN Falling
FEEDBACK (FB2)
FB2 Regulation Voltage
Fixed Output Accuracy
FB2 Bias Current
Symbol
VFB2
RDSON_H_LFCSP
RDSON_L_LFCSP
RDSON_H_LQFP
RDSON_L_LQFP
ISW_LK_HS
ISW_LK_LS
tON_MIN
tOFF_MIN
Minimum On Time
Minimum Off Time
BST
Bootstrap Voltage
CURRENT LIMIT
Valley Current Limit
Low-Side Sink Current Limit
PWM SWITCHING FREQUENCY
SOFT START TIME
fSW
tSS
2
Typ
Max
Unit
4.2
3.65
4.4
3.5
V
V
0.6
0.609
+1.5
0.1
5
V
%
μA
μA
700
380
750
430
0.1
42
42
150
1070
540
1210
620
mΩ
mΩ
mΩ
mΩ
μA
μA
ns
ns
4.7
5
5.3
V
0.65
0.8
0.2
1.2
400
1.6
0.98
A
A
MHz
μs
ms
0.01
4.3
ISW_SOURCE = 0.5 A
ISW_SINK = 0.5 A
SW = PGND2
SW = VIN
1.0
Fixed output version
Adjustable output version
tRST_DELAY_R
Reset Falling Delay
RSTO Output Low Voltage
RSTO Leakage Current
Min
0.591
−1.5
VBOOT
RESET (RSTO)
Reset Rising Threshold Voltage
Reset Threshold Hysteresis
Reset Rising Delay
1
Adjustable output version
Fixed output version
Adjustable output version
Fixed output version
IFB2
SWITCH NODE
High-Side On Resistance (LFCSP)2
Low-Side On Resistance (LFCSP)2
High-Side On Resistance (LQFP)2
Low-Side On Resistance (LQFP)2
SW Leakage Current
Test Conditions/Comments
VIN pin
Refer to VFB2
85
Option 1, default
Option 2
Option 3
Option 4
0.42
0.85
1.72
4.2
89
1
0.5
1
2
5
10
40
0.01
tRST_DELAY_F
IRSTO = 3 mA
VRSTO = 5 V
1.4
94
0.56
1.12
2.3
5.6
100
0.3
%
%
ms
ms
ms
ms
μs
mV
μA
This UVLO threshold is only for the buck control block.
Pin to pin measurement.
PROGRAMMABLE GAIN AMPLIFIER AND ANALOG TRIP SPECIFICATIONS
VIN = 12 V, VAVDD = 5 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications, unless
otherwise noted.
Table 3.
Parameter
POWER INPUT
Input Voltage Range
Quiescent Current
Undervoltage Lockout Threshold
Symbol
Test Conditions/Comments
AVDD pin
VAVDD
IQ_AVDD
Min
Typ
2.7
575
Rev. B | Page 6 of 40
Max
Unit
5.5
V
μA
Data Sheet
Parameter
AVDD Rising
AVDD Falling
INPUT CHARACTERISTICS
Input Voltage Range
Input Offset
Input Offset Temperature Drift
Input Capacitance1
Input Impedance
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
Close-Loop Output Impedance2
DYNAMIC PERFORMANCE
Slew Rate2
Gain Bandwidth Product1
Phase Margin1
NOISE PERFORMANCE
Input Voltage Noise Density2
Input Voltage Noise2
GAIN PROGRAM (GAIN0, GAIN1)
Input High Voltage
Input Low Voltage
Voltage on GAIN1
Gain Error
Gain Drift
ANALOG TRIP
Analog Trip Disable Voltage Threshold
Rising
Falling
VTRP Current
VTRPL Current3
Analog Trip Deglitch Time
ADP2450
Symbol
Test Conditions/Comments
Min
2.4
Typ
2.6
2.5
Max
2.7
Unit
V
V
0
+3.3
0.5
17
9.5
V
V
mV
μV/°C
μV/°C
pF
MΩ
VVCOM = GND
VVCOM = VAVDD
TJ = 25°C, trimmed at gain = 1
Gain < 4
Gain ≥ 4
−6.6
−3.3
VOH_PGA
VOL_PGA
ISC_H_PGA
ISC_L_PGA
ZOUT_PGA
IOH_PGA = −250 μA
IOL_PGA = 250 μA
Short to AVDD
Short to GND
f = 100 Hz, gain = 1
VAVDD – 0.3 V
SRPGA
GBPPGA
ΦM_PGA
RL_PGA = 10 kΩ , CL_PGA = 35 pF, gain = 1
RL_PGA = 10 kΩ , CL_PGA = 35 pF
RL_PGA = 10 kΩ , CL_PGA = 35 pF
1.7
1
60
V/μs
MHz
Degrees
eni_PGA
en_PGA p-p
f = 1 kHz, gain = 1
f = 0.1 Hz to 10 Hz, gain = 1
180
34
nV/√Hz
μV p-p
VOS_PGA
5.5
3.5
2
1
CIN_PGA
RIN_PGA
For GAIN0 pin
For GAIN0 pin
VAVDD – 0.1 V
25
17
10
18
40
1.2
0.792
0.8
TJ = 25 °C
Gain < 4
Gain ≥ 4
7
4
Option 1 (default)
Option 2
Option 3
Option 4
Option 5
Option 6
Option 7
Option 8
4.75
4.65
10
10
200
350
500
750
1
2
3
4
V
mV
mA
mA
Ω
0.4
0.808
0.5
12
8.5
V
V
V
%
ppm/°C
ppm/°C
10.4
10.4
223
387
552
826
1.1
2.2
3.3
4.4
V
V
μA
μA
μs
μs
μs
μs
ms
ms
ms
ms
VTRP_DIS
ITRP
ITRPL
tTRP
1
Guaranteed by design, not production tested.
Bench measurement result.
3
Only available in the 48-lead LQFP package.
2
Rev. B | Page 7 of 40
9.5
9.5
178
310
440
660
0.88
1.75
2.6
3.5
ADP2450
Data Sheet
OPERATION AMPLIFIER SPECIFICATIONS
VIN = 12 V, VAVDD = 5 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications, unless
otherwise noted.
Table 4.
Parameter
INPUT CHARACTERISTICS
Input Voltage Range
Input Offset
Input Offset Temperature Drift
Input Bias Current1
Input Capacitance1
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
DYNAMIC PERFORMANCE2
Slew Rate
Gain Bandwidth Product
Phase Margin
NOISE PERFORMANCE2
Input Voltage Noise Density
Input Voltage Noise
1
2
Symbol
Test Conditions/Comments
VOS_EA
TJ = 25°C
Min
Typ
0
20
5.5
1
2
CIN_EA
VAVDD
850
19
1000
V
μV
μV/°C
pA
pF
IOH_EA = −250 μA
IOL_EA = +250 μA
Short to AVDD
Short to GND
SREA
GBPEA
ΦM_EA
RL_EA = 10 kΩ, CL_EA = 35 pF
RL_EA = 10 kΩ, CL_EA = 35 pF
RL_EA = 10 kΩ, CL_EA = 35 pF
0.5
1.6
56
V/μs
MHz
Degrees
eni_EA
en_EA p-p
f = 1 kHz
f = 0.1 Hz to 10 Hz
240
46
nV/√Hz
μV p-p
Rev. B | Page 8 of 40
VAVDD – 0.1 V
15
30
15
Unit
VOH_EA
VOL_EA
ISC_H_EA
ISC_L_EA
Guaranteed by design, not production tested.
Bench measurement result.
VAVDD – 0.3 V
Max
35
V
mV
mA
mA
Data Sheet
ADP2450
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
Parameter
VIN, SW, DET, VPTH
AVDD
BST
DRV
EIN1, EIN2, EIN3, EIN4
EIN5_P, EIN5_N
EOUT1, EOUT2, EOUT3, EOUT4,
EOUT5, VCOM, RCOM
VREG, FB1, FB2, VTRP, VTRPL,
RSTO, TRG, GATE, GAIN0,
GAIN1
PGNDx to GND
Operating Temperature Range
(Junction)
Storage Temperature Range
Soldering Conditions
Electrostatic Discharge (ESD)
Human Body Mode
Charged Device Mode
Rating
−0.3 V to +40 V
−0.3 V to +6 V
The SW pin voltage (VSW) + 6 V
−0.3 V to +12 V
−8 V to +8 V
−8 V to +8 V
−0.3 V to VAVDD
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Close attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure.
θJC is the junction to case thermal resistance.
Table 6. Thermal Resistance
Package Type
CP-32-71
ST-481
−0.3 V to +6 V
−0.3 V to +0.3 V
−40°C to +125°C
1
θJC
1.4
3.41
Unit
°C/W
°C/W
θJA is measured using natural convection on a JEDEC 4-layer board with the
exposed pad soldered to the PCB and with thermal vias.
ESD CAUTION
−65°C to +150°C
JEDEC J-STD-020
θJA
32.7
66.68
4000 V (for EIN1, EIN2, EIN3,
EIN4, EIN5_P, and EIN5_N pins),
2000 V (for the rest of pins)
500 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 9 of 40
ADP2450
Data Sheet
NIC
PGND2
SW
VIN
BST
NIC
DET
VPTH
FB1
NIC
NIC
NIC
1
36
NIC
PGND1
2
35
FB2
GATE
3
34
RSTO
TRG
4
33
GAIN0
NIC
5
32
GAIN1
VTRP
6
31
NIC
VTRPL
7
30
NIC
9
10
11
12
13
14
15
16
DRV
DRV
FB1
VPTH
DET
BST
VIN
SW
PGND2
48 47 46 45 44 43 42 41 40 39 38 37
VREG
8
29
EOUT5
EOUT1
EIN2
EOUT2
EIN3
EOUT3
EIN4
EOUT4
RCOM
GND
9
28
EIN5_N
AVDD 10
27
EIN5_P
EIN1 11
26
VCOM
NIC 12
25
NIC
1
2
3
4
5
6
7
8
ADP2450
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
FB2
RSTO
GAIN0
GAIN1
EOUT5
EIN5_N
EIN5_P
VCOM
NOTES
1. EXPOSED PAD. SOLDER THE EXPOSED
PAD TO AN EXTERNAL GND PLANE.
17088-003
PGND1
GATE
TRG
VTRP
VREG
GND
AVDD
EIN1
32
31
30
29
28
27
26
25
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADP2450
TOP VIEW
(Not to Scale)
NOTES
1. NIC = NOT INTERNALLY CONNECTED. LEAVE THIS PIN OPEN.
17088-104
NIC
RCOM
EOUT4
EIN4
NIC
EOUT3
EIN3
NIC
EOUT2
EIN2
NIC
EOUT1
13 14 15 16 17 18 19 20 21 22 23 24
Figure 4. 48-Lead LQFP Package Pin Configuration (Top View)
Figure 3. 32-Lead LFCSP Package Pin Configuration (Top View)
Table 7. Pin Function Descriptions
Pin No.
LFCSP
LQFP
32-Lead
48-Lead
1
2
2
3
Mnemonic
PGND1
GATE
3
4
4
6
TRG
VTRP
7
VTRPL
5
8
VREG
6
7
8
9
10
11
12
13
14
15
16
17
9
10
11
13
15
16
18
19
21
22
23
26
GND
AVDD
EIN1
EOUT1
EIN2
EOUT2
EIN3
EOUT3
EIN4
EOUT4
RCOM
VCOM
18
19
20
21
27
28
29
32
EIN5_P
EIN5_N
EOUT5
GAIN1
Description
Boost Shunt Driver and Actuator Driver Ground.
Actuator Driver. This pin drives the silicon controlled rectifier (SCR), field-effect transistor
(FET), or transistor.
Actuator Trigger Signal. This signal comes from the microcontroller unit (MCU).
Analog Trip High Threshold Setting. Connect a resistor between this pin and ground to set
the analog trip high threshold.
Analog Trip Low Threshold Setting. Connect a resistor between this pin and ground to set
the analog trip low threshold.
Internal 5 V Regulator Output. The IC control circuits are powered from this voltage. Place a
1 μF ceramic capacitor between VREG and GND.
Analog Ground. Connect this pin to the ground plane.
Power Supply for the Amplifier Block.
Input of the Programmable Gain Amplifier 1.
Output of the Programmable Gain Amplifier 1.
Input of the Programmable Gain Amplifier 2.
Output of the Programmable Gain Amplifier 2.
Input of the Programmable Gain Amplifier 3.
Output of the Programmable Gain Amplifier 3.
Input of the Programmable Gain Amplifier 4.
Output of the Programmable Gain Amplifier 4.
External Resistance Compensation for Programmable Gain Amplifier 1 to Amplifier 4.
Setting for the Output Common Voltage of the Programmable Gain Amplifiers. This pin is
connected to an external reference voltage.
Positive Input of Amplifier 5.
Negative Input of Amplifier 5.
Output of the Amplifier 5.
Gain Setting for Programmable Gain Amplifier 1 to Amplifier 4. This pin is combined with
GAIN0 to set the gain of the amplifier.
Rev. B | Page 10 of 40
Data Sheet
LFCSP
32-Lead
22
Pin No.
LQFP
48-Lead
33
ADP2450
23
24
34
35
RSTO
FB2
25
26
27
38
39
40
PGND2
SW
VIN
28
29
30
41
43
44
BST
DET
VPTH
31
32
45
47
1, 5, 12, 14,
17, 20, 24, 25,
30, 31, 36, 37,
42, 46, 48
FB1
DRV
NIC
Description
Gain Setting for Programmable Gain Amplifier 1 to Amplifier 4. This pin is combined with
GAIN1 to set the gain of the amplifier.
Reset Output (Open Drain). Connect this pin to a resistor to any pull-up voltage < 5.5 V.
Feedback Voltage Sense Input for Buck Regulator. Connect this pin to a resistor divider from
buck output voltage, VOUT2, for adjustable version. For the fixed output version, connect this
pin to VOUT2 directly.
Power Ground for Buck Regulator.
Switch Node for Buck Regulator.
Power Input for Buck Regulator and Internal VREG. This voltage is monitored by the power
detection circuit. Connect a bypass capacitor between this pin and PGND2.
Supply Rail for the Gate Drive of Buck. Place a 0.1 μF capacitor between SW and BST.
Power Detection Output.
Power Detection Voltage Threshold Setting. Connect a resistor between this pin and ground
to set the power rating detection voltage threshold.
Feedback Voltage Sense Input for boost shunt. Connect this pin to a resistor divider from VOUT1.
Boost Shunt Driver.
Not Internally Connected. Leave the pin open.
EP
Exposed Pad. Solder the exposed pad to an external GND plane.
33
Mnemonic
GAIN0
Rev. B | Page 11 of 40
ADP2450
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 12 V, VAVDD = 5 V, VVCOM = VRCOM (the RCOM pin voltage) = 0 V, unless otherwise noted.
1.50
1.25
VPTH THRESHOLD (V)
1.20
1.40
1.35
1.30
1.05
VIN = 36V
VIN = 24V
VIN = 12V
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
1.10
RISING
FALLING
1.00
–40
0
20
40
60
80
BUCK VIN UVLO THRESHOLD (V)
4.4
2.50
2.45
2.40
2.35
4.2
4.0
3.8
3.6
0
20
40
60
80
100
120
TEMPERATURE (°C)
3.4
–40
17088-005
–20
RISING
FALLING
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 6. VIN UVLO Threshold for Boost Controller vs. Temperature
Figure 9. VIN UVLO Threshold for Buck Regulator vs. Temperature
0.606
1.24
0.604
1.22
0.602
FB2 VOLTAGE (V)
1.26
1.20
1.18
1.16
0.600
0.598
0.596
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
0.594
–40
17088-006
FB1 VOLTAGE (V)
–20
17088-008
RISING
FALLING
1.14
–40
120
Figure 8. VPTH Threshold vs. Temperature
2.55
2.30
–40
100
TEMPERATURE (°C)
Figure 5. Quiescent Current vs. Temperature
BOOST VIN UVLO THRESHOLD (V)
–20
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 7. FB1 Voltage vs. Temperature
Figure 10. FB2 Voltage vs. Temperature
Rev. B | Page 12 of 40
100
120
17088-009
1.20
–40
1.15
17088-007
1.25
17088-004
QUIESCENT CURRENT (mA)
1.45
Data Sheet
ADP2450
0.6
DET OUTPUT LOW VOLTAGE (V)
DRV OUTPUT HIGH VOLTAGE (V)
8.00
7.95
7.90
7.85
7.80
0.5
0.4
0.3
0.2
0
20
40
60
80
100
120
TEMPERATURE (°C)
17088-010
–20
0.1
–40
20
40
60
80
100
120
Figure 14. DET Output Low Voltage vs. Temperature
1200
4.98
4.97
BOOTSTRAP VOLTAGE (V)
1000
800
600
400
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
4.95
4.94
4.93
4.92
HIGH SIDE
LOW SIDE
0
–40
4.96
4.91
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 12. MOSFET On Resistance vs. Temperature
17088-014
200
17088-011
Figure 15. Bootstrap Voltage vs. Temperature
1.25
1.00
SWITCHING FREQUENCY (MHz)
0.95
0.90
0.85
0.80
0.75
0.70
1.23
1.21
1.19
1.17
0.65
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
1.15
–40
17088-012
0.60
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 13. Valley Current-Limit Threshold vs. Temperature
Figure 16. Switching Frequency vs. Temperature
Rev. B | Page 13 of 40
120
17088-015
MOSFET ON RESISTANCE (mΩ)
0
TEMPERATURE (°C)
Figure 11. DRV Output High Voltage vs. Temperature
VALLEY CURRENT-LIMIT THRESHOLD (A)
–20
17088-013
IDET = 20mA
7.75
–40
Data Sheet
6
1.2
5
RESET RISING DELAY TIME (ms)
1.4
1.0
0.8
0.6
OPTION 1
OPTION 2
0.2
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
2
1
0
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 20. Reset Rising Delay Time (Option 3, Option 4) vs. Temperature
396
1.58
392
390
388
386
384
VOUT2 = 3.3V
VOUT2 = 5.0V
382
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 18. Fixed Output Version Soft Start Time vs. Temperature
1.57
1.56
1.55
1.54
1.53
1.52
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
17088-020
ADJUSTABLE OUTPUT VERSION
SOFT START TIME (ms)
394
17088-017
Figure 21. Adjustable Output Version Soft Start Time vs. Temperature
2.70
800
2.65
AVDD UVLO THRESHOLD (V)
900
700
600
500
2.60
2.55
2.50
2.45
400
RISING
FALLING
–20
0
20
40
60
80
100
TEMPERATURE (°C)
120
2.40
–40
17088-018
300
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 22. AVDD UVLO Threshold vs. Temperature
Figure 19. AVDD Quiescent Current vs. Temperature
Rev. B | Page 14 of 40
120
17088-021
FIXED OUTPUT VERSION SOFT START TIME (µs)
3
OPTION 3
OPTION 4
Figure 17. Reset Rising Delay Time (Option1, Option 2) vs. Temperature
AVDD QUIESCENT CURRENT (µA)
4
17088-019
0.4
17088-016
RESET RISING DELAY TIME (ms)
ADP2450
Data Sheet
ADP2450
1000
ANALOG TRIP DEGLITCH TIME (µs)
10.3
10.2
10.1
10.0
9.9
700
600
500
400
300
200
0
20
40
60
80
100
120
0
–40
Figure 23. Analog Trip Pin (VTRP and VTRPL) Current vs. Temperature
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
17088-025
–20
TEMPERATURE (°C)
Figure 26. Analog Trip Deglitch Time vs. Temperature (Option 1 to Option 4)
4.5
40
4.0
35
3.5
GAIN = 1
596 PGAs
NUMBER OF PGAs
30
3.0
2.5
2.0
1.5
25
20
15
10
1.0
OPTION 8
OPTION 7
OPTION 6
OPTION 5
PGA VOS (µV)
17088-026
180
200
160
140
120
80
60
40
100
TEMPERATURE (°C)
0
0
20
120
–20
100
–40
80
–60
60
–80
40
–100
20
–120
0
–140
–20
–180
–160
0
–40
5
–200
0.5
17088-023
Figure 27. PGA Input Offset Voltage Distribution
Figure 24. Analog Trip Deglitch Time vs. Temperature (Option 5 to Option 8)
200
140
180
GAIN = 1
596 PGAs
120
GAIN = 4
596 PGAs
160
NUMBER OF PGAs
100
80
60
40
140
120
100
80
60
40
20
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PGA VOS TEMPERATURE DRIFT (µV/°C)
17088-024
0
20
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PGA VOS TEMPERATURE DRIFT (µV/°C)
Figure 28. PGA Input Offset Voltage Drift Distribution, Gain = 4
Figure 25. PGA Input Offset Voltage Drift Distribution, Gain = 1
Rev. B | Page 15 of 40
17088-027
ANALOG TRIP DEGLITCH TIME (ms)
800
100
9.8
–40
NUMBER OF PGAs
OPTION 1
OPTION 2
OPTION 3
OPTION 4
900
VTRPL CURRENT
VTRP CURRENT
10.4
17088-022
ANALOG TRIP PIN (VTRP AND VTRPL)
CURRENT (µA)
10.5
ADP2450
Data Sheet
35
33
PGA1
PGA2
PGA3
PGA4
4.955
PGA OUTPUT LOW VOLTAGE (mV)
PGA OUTPUT HIGH VOLTAGE (V)
4.960
4.950
4.945
4.940
4.935
31
29
27
25
23
PGA1
PGA2
PGA3
PGA4
21
19
0
20
40
60
80
100
120
TEMPERATURE (°C)
15
–40
17088-028
–20
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 29. PGA Output High Voltage vs. Temperature
17088-031
17
4.930
–40
Figure 32. PGA Output Low Voltage vs. Temperature
250
0
596 PGAs
–10
200
PGAx PSRR (dB)
NUMBER OF PGAs
–20
150
100
–30
–40
–50
–60
50
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
GAIN ERROR (%)
–80
10
17088-029
0
Figure 30. PGA Gain Error Distribution
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
17088-032
–70
Figure 33. PGAx Power Supply Rejection Ratio (PSRR) vs. Frequency
250
350
GAIN = 1
596 PGAs
200
GAIN = 4
596 PGAs
300
NUMBER OF PGAs
150
100
200
150
100
50
0
0
1
2
3
4
5
6
7
8
9
10
PGA GAIN DRIFT (ppm/°C)
11
12
Figure 31. PGA Gain Drift Distribution, Gain = 1
0
0
1
2
3
4
5
6
7
8
PGA GAIN DRIFT (ppm/°C)
Figure 34. PGA Gain Drift Distribution, Gain = 4
Rev. B | Page 16 of 40
9
10
17088-033
50
17088-030
NUMBER OF PGAs
250
Data Sheet
ADP2450
40
RL = 10kΩ
CL = 35pF
PGA CLOSED-LOOP GAIN (dB)
30
T
EINx
20
10
0
2
–10
1
AV = 1
AV = 4
AV = 16
–20
EOUTx
100
1k
10k
100k
1M
FREQUENCY (Hz)
CH1 2.00V BW
CH2 200mV BW
17088-034
–40
10
10
NOISE = 335mV p-p
T
1
1
0.1
0.001
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
CH1 100mV
CH1
1.00s
120mV
Figure 39. PGA 0.1 Hz to 10 Hz Noise, Amplification = 10,000×
Figure 36. PGA Input Voltage Noise Density vs. Frequency
30
30
149 OP AMPs
NUMBER OF OP AMPs
25
20
15
10
20
15
10
17088-036
450
500
400
350
300
250
200
150
100
0
50
–50
–100
–150
–200
–250
0
–300
0
–350
5
–450
–400
5
OP AMP VOS (µV)
Figure 37. Operational Amplifier (Op Amp) Input Offset Voltage Distribution
149 OP AMPs
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
OP AMP VOS TEMPERATURE DRIFT (µV/°C)
17088-039
25
–500
100kS/s
1M PTS
17088-038
0.01
17088-035
PGA INPUT VOLTAGE NOISE DENSITY (µV/√Hz)
10.0ms 1.0MS/s
CH1
2.80V
Figure 38. PGA No Phase Reversal, VVCOM = VAVDD = 4 V, AV = −10
Figure 35. PGA Closed-Loop Gain vs. Frequency
NUMBER OF OP AMPs
100k PTS
T
–180.0000µs
17088-037
–30
Figure 40. Op Amp Input Offset Voltage Temperature Drift Distribution
Rev. B | Page 17 of 40
ADP2450
Data Sheet
22
OP AMP OUTPUT LOW VOLTAGE (mV)
OP AMP OUTPUT HIGH VOLTAGE (V)
4.975
4.970
4.965
4.960
4.955
4.950
4.945
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
18
16
14
12
10
8
–40
17088-040
4.940
–40
20
150
40
50
0
–50
GAIN
PHASE
–20
60
60
OP AMP CLOSED-LOOP GAIN (dB)
100
0
40
80
100
120
RL = 10kΩ
50
60
20
20
Figure 44. Op Amp Output Low Voltage vs. Temperature
PHASE SHIFT (Degrees)
OP AMP OPEN-LOOP GAIN (dB)
RL = 10kΩ
CL = 10pF
0
TEMPERATURE (°C)
Figure 41. Op Amp Output High Voltage vs. Temperature
80
–20
17088-043
4.980
–100
40
30
20
10
0
–10
–20
AV = 1
AV = 10
AV = 100
100k
1M
–40
10
17088-041
10k
–150
10M
FREQUENCY (Hz)
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 42. Op Amp Open-Loop Gain and Phase Shift vs. Frequency
17088-044
–30
–40
1k
Figure 45. Op Amp Close-Loop Gain vs. Frequency
0
90
80
–20
OP AMP CMRR (dB)
–40
–60
–80
60
50
40
30
20
–100
–120
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 43. Op Amp PSRR vs. Frequency
1M
10M
0
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
17088-045
10
17088-042
OP AMP PSRR (dB)
70
Figure 46. Op Amp Common-Mode Rejection Ratio (CMRR) vs. Frequency
Rev. B | Page 18 of 40
ADP2450
EIN5_N
2
1
CH1 2.00V BW
CH2 200mV BW
100k PTS
T
–180.0000µs
10.0ms 1.0MSPS
CH1
2.80V
17088-046
EOUT5
10
1
0.1
0.01
0.001
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 47. Op Amp No Phase Reversal, VAVDD = 4 V, AV = −10
Figure 50. Op Amp Input Voltage Noise Density vs. Frequency
T
T
NOISE = 459mV p-p
VOUT1
3
1
VOUT2
1
RSTO
4
DRV
100kSPS
1M PTS
CH1
1.00s
120mV
CH1 2.00V BW
CH3 5.00V BW
CH2 5.00V BW
CH4 5.00V BW
T
–180.0000µs
10ms 10.0MSPS
CH1
2.80V
1M PTS
17088-050
CH1 100mV
17088-047
2
Figure 51. Start Up with AC Current Source, VCOM = GND
Figure 48. Op Amp 0.1 Hz to 10 Hz Noise,
Amplification = 10,000×
T
T
VOUT1
VOUT1
EINx
3
1
VOUT2
3
RSTO
1
EOUTx
4
2
2
CH2 200mV BW
T
–100.0000µs
10.0ms 10.0MSPS
CH2
148mV
1M PTS
CH1 2.00V BW
CH3 5.00V BW
17088-048
CH1 200mV BW
CH3 5.00V BW
CH2 5.00V BW
CH4 5.00V BW
100ms 1.0MS/s
CH1
1.64V
1M PTS
Figure 52. System Shutdown Waveform
Figure 49. PGA Working Waveform, Gain = 1
Rev. B | Page 19 of 40
17088-051
DRV
17088-049
T
OP AMP INPUT VOLTAGE NOISE DENSITY (µV/√Hz)
Data Sheet
ADP2450
Data Sheet
T
T
EINx
2
EINx
EOUTx
EOUTx
B
W
B
W
100k PTS
T
1.800000ms
10.0ms 1.00MSPS
CH1
1.54V
17088-052
CH1 500mV
CH2 500mV
CH1 500mV BW CH2 500mV BW M10.0ms
CH3
2.24V
100k PTS
1.00MSPS T
1.800000ms
Figure 53. PGA Gain Switching from Gain = 1 to Gain = 4
Figure 56. PGA Gain Switching from Gain = 4 to Gain = 1
T
2
17088-055
1
1
T
EINx
2
EINx
EOUTx
EOUTx
1
CH1 1.00V BW CH2 200mV BW M10.0ms
CH3
2.24V
1.800000ms
1.00MSPS T
100k PTS
17088-053
1
CH1 1.00V BW
Figure 54. PGA Gain Switching from Gain = 4 to Gain = 16
CH2 200mV BW M10.0ms
CH3
2.24V
100k PTS
1.00MSPS T
1.800000ms
17088-056
2
Figure 57. PGA Gain Switching from Gain = 16 to Gain = 4
T
T
EINx
1
TRG
3
GATE
GATE
4
M10.0ms 1.00MSPS CH4
2.16V
CH4 2.00V BW T
100k PTS
19.90000ms
CH3 2.00V BW
Figure 55. Analog Trip Threshold Triggered, VCOM = RCOM = 0 V
CH4 2.00V BW
M2.00ms 5.00MSPS CH3
3.56V
100k PTS
T
23.20000µs
Figure 58. TRG Trigger Analog Trip Function
Rev. B | Page 20 of 40
17088-057
CH1 1.00V BW
17088-054
4
Data Sheet
ADP2450
T
T
VOUT1
VOUT1
1
1
VOUT2
3
VOUT2
3
IOUT2
IOUT2
4
4
RSTO
RSTO
CH1 5.00V BW CH2 2.00V BW M1.00ms
CH1
3.20V
CH3 2.00V BW CH4 200mA BW T
1M PTS
2.568000ms
CH1 5.00V BW CH2 5.00V BW M400µs
CH1
4.40V
CH3 2.00V BW CH4 200mA BW T
1M PTS
680.0000µs
Figure 59. Buck Regulator Soft Start with Full Load
(VOUT2 = 3.3 V, Adjustable Version)
17088-061
2
17088-058
2
Figure 62. Buck Regulator Soft Start with Full Load
(VOUT2 = 5 V, Fixed Version)
T
T
VOUT2
VOUT2
1
1
SW
SW
3
3
IOUT2
IOUT2
CH1 2.00V BW
CH3 10.0V BW
M1.00ms
CH1
2.92V
CH4 1.00A BW T
1M PTS
2.990000ms
CH1 2.00V BW
CH3 10.0V BW
Figure 60. Buck Regulator OCP Triggered
M1.00ms
CH1
2.92V
CH4 1.00A BW T
1M PTS
2.590000ms
17088-062
4
17088-059
4
Figure 63. Buck Regulator OCP Recovery
T
T
VOUT2 (AC)
2
2
VOUT2 (AC)
VIN
IOUT2
1
SW
CH2 200mV BW
CH4 200mA BW
M200µs
CH4
T
598.0000µs
236mA
1M PTS
Figure 61. Buck Regulator Load Transient (50 mA to 450 mA)
CH1 10.0V BW CH2 50.0mV
CH3 10.0V BW
B
W
M2.00ms
CH1
21.0V
1M PTS
T
4.716000ms
17088-063
3
17088-060
4
Figure 64. Buck Regulator Line Transient, VIN from 8 V to 24 V, Full Load
Rev. B | Page 21 of 40
ADP2450
Data Sheet
THEORY OF OPERATION
The ADP2450 is a power management IC for circuit breaker
and CT powered supply applications. The ADP2450 integrates
one boost shunt controller with power detection, one high
efficiency buck regulator, four programmable gain amplifiers, one
low offset operation amplifier, a fast analog trip circuit, and an
actuator driver in a 32-lead LFCSP or 48-lead LQFP package. With
the high integration rate, the ADP2450 provides a compact, robust
power supply and signal conditioning solution for size limited,
high reliability systems.
BOOST SHUNT CONTROLLER
The ADP2450 integrates a boost shunt controller with a field-effect
transistor (FET) driver. The boost shunt controller uses a hysteresis
control scheme to regulate the output voltage. When the feedback
voltage on the FB1 pin is lower than the reference voltage (typically
1.2 V), the FET driver turns off the external FET, and then the
current from CT charges the output capacitor storing energy in
the capacitor. When the output voltage rises and the feedback
voltage on the FB1 pin is higher than the rising threshold
(typically 1.219 V), the FET driver turns on the external FET
and bypasses the CT current to ground through the external FET.
Use the following equation to calculate RTOP_VP and RBOT_VP:
RTOP _ VP
1.09 V VOUT1 _ RISING 1.22 V VOUT1 _ FALLING
1.09 V 4.8 A 1.22 V 1 A
RBOT _ VP
1.22 V RTOP _ VP
VOUT1 _ RISING RTOP _ VP 4.8 A 1.22 V
where:
RTOP_VP is the top side resistor connected between the VOUT1 and
VPTH pin.
RBOT_VP is the bottom side resistor connected between the
VPTH pin and ground.
VOUT1_RISING is the VOUT1 rising threshold.
VOUT1_FALLING is the VOUT1 falling threshold.
A dummy resistor load (RPOWER) connected between VOUT1 and
the DET pin ensures that the whole system is not enabled until
there is enough power provided to the system by the current
transformer, as shown in Figure 66.
VOUT1
ADP2450
DET
RPOWER
POWER DETECTION
When the voltage on the VPTH pin falls below the VPTH
falling threshold (typically 1.09 V), the power detection FET is
turned on again, which pulls the DET pin to ground, and the
3.8 μA current source is added between VPTH and ground again.
The voltage threshold and hysteresis for power detection is
programmable with external resistors on the VPTH pin, as
shown in Figure 65.
GND
17088-065
The ADP2450 integrates an input power detection function.
During startup, when the voltage on the VPTH pin is lower
than the VPTH rising threshold (typically 1.22 V), the power
detection FET is turned on and the DET pin is pulled down to
ground. Both the 1 μA and 3.8 μA internal current sources are
added between VPTH and ground. When the voltage on the
VPTH pin rises above the VPTH rising threshold (typical 1.22 V),
the power detection FET is turned off and the DET pin is open.
The 3.8 μA current source is removed and only the 1 μA current
source is added.
Figure 66. Dummy Load Connection
Calculate the dummy load resistor value using the following
equation:
RPOWER
where IDUMMY is the minimum required current value before
enabling the system.
Ensure that the selected dummy load resistor can handle the
power before the DET pin is open. The power consumption
on the dummy load resistor (PDUMMY) is calculated using the
following equation:
PDUMMY I DUMMY 2 RPOWER
VOUT1
ADP2450
INTERNAL REGULATOR
CMP
VPTH
+
1µA
3.8µA
Figure 65. Programmable Voltage of Power Detection
17088-064
1.22V
RBOT_VP
–
RTOP_VP
VOUT1_RISING
I DUMMY
The internal 5 V regulator (VREG) provides a stable voltage
supply for the internal control circuits. It is recommended to
place a 1 μF ceramic capacitor between VREG and GND. The
internal regulator also includes a current-limit circuit for overcurrent protection.
The internal 8 V regulator provides the voltage supply for the
boost shunt driver.
The VIN pin provides power supply for both the 5 V and 8 V
internal regulators.
Rev. B | Page 22 of 40
Data Sheet
ADP2450
BUCK REGULATOR
PROGRAMMABLE GAIN AMPLIFIER
The buck regulator in the ADP2450 uses a current mode
control scheme for stability and transient response.
The ADP2450 integrates four low offset, low power programmable
gain amplifiers (PGA1, PGA2, PGA3, and PGA4). The gain of
these amplifiers is programmable through the GAIN0 and
GAIN1 pins.
The buck regulator operates in a 1.2 MHz fixed switching
frequency. The regulator integrates the soft start and
compensation circuit to reduce the external components and
provide an easy to use solution. The soft-start time is 400 μs for
the fixed output version and is 1.6 ms for the adjustable output
version.
Connect a resistor between the GAIN1 pin and ground to set
different gains.
Pull up the GAIN0 pin to high or pull down the GAIN0 pin to
low to choose different gain ranges.
The ADP2450 uses the emulated current ramp voltage for cycle
by cycle current-limit protection to prevent current runaway.
When the emulated current ramp voltage reaches the currentlimit threshold, the high-side MOSFET turns off and the lowside MOSFET turns on until the next cycle. The overcurrent
counter increments during this cycling process. If the overcurrent
does not occur in the next cycle, the overcurrent counter decreases.
If the overcurrent counter reaches 10 or the voltage on the
FB2 pin drops below 0.2 V after soft start, the buck regulator
enters into hiccup mode. During hiccup mode, both the highside MOSFET and low-side MOSFET are turned off. The buck
regulator remains in hiccup mode for 1024 clock cycles and
then attempts to restart with a soft start. If the current-limit
fault is cleared, the buck regulator resumes normal operation.
Otherwise, the buck regulator reenters hiccup mode.
A total of 15 gains can be obtained via different combinations
of GAIN0 and GAIN1 settings. Table 8 shows the relationship
between the gain and the GAIN0 and GAIN1 configurations.
The low-side MOSFET in the buck regulator also sinks current
from the load. If the low-side sink current exceeds the sink
current-limit threshold, both the low-side and high-side
MOSFETs are turned off until the next cycle starts.
The AVDD pin provides the voltage supply for the programmable
gain amplifiers, and the output voltage of the amplifiers are
clamped between zero and VAVDD.
The buck regulator only works when the voltage on the VPTH pin
is higher than the VPTH rising threshold.
Table 8. Gain Setting for PGAx
Resistance on GAIN1 (kΩ )
0
42.2
63.4
95.3
143
215
324
AVDD
VEOUTx
It is recommended to place a 0.1 μF, X7R or X5R ceramic
capacitor between the BST and the SW pins.
POWER MONITOR AND RESET
The output voltage of the buck regulator is monitored through
the FB2 pin. When the voltage on FB2 pin is below the reset
threshold, the RSTO pin is pulled down. When the voltage on
FB2 pin is above the reset threshold, the RSTO pin is released
and can be pulled up by an external voltage source. A delay time
is designed for the RSTO pin to ensure that no glitch occurs on
the RSTO pin. There are four following options for the rising
delay time: 0.5 ms, 1 ms, 2 ms, and 5 ms. The falling delay time is
fixed at 10 μs.
GAIN
GAIN0 = High
3
4
5
6
7
8
10
16
The output voltage of PGAx is calculated with the following
equation:
BOOTSTRAP CIRCUIT
The ADP2450 includes a regulator to provide the gate driver
voltage for the high-side N-MOSFET of the buck regulator. It
uses differential sensing method to generate a 5 V bootstrap
voltage between the BST and the SW pins.
GAIN0 = Low
0.75
1
1.25
1.5
1.75
2
2.5
4
VVCOM
VEINx GAIN
2
where:
VEOUTx is the voltage on the EOUTx pin.
VVCOM is the voltage on VCOM pin.
VEINx is the voltage on the EINx pin.
GAIN is the gain value programmed by the GAIN0 and
GAIN1 pins according to Table 8.
In a Rogowski application, as shown in Figure 75, connect a
resistor between RCOM and ground to compensate for the
passive, integrated dc resistor. Connect VCOM to AVDD or to a
reference voltage derived from AVDD for the proper start-up
sequence.
In the CT current sense application, connect both the VCOM
and RCOM pins to ground.
Rev. B | Page 23 of 40
ADP2450
Data Sheet
The analog trip thresholds are programmable with external
resistors and can be calculated using the following equations:
OPERATIONAL AMPLIFIER
The operational amplifier is a low offset amplifier. The amplifier
is used for leakage current detection in circuit breaker application.
VTRP V 0.01 RTRP kΩ
Figure 67 shows the circuit configuration with the operational
amplifier for leakage current detection as well as R1 and R2. The
output voltage of the operational amplifier is calculated with the
following equation:
VEOUT 5
VREF I LK
R
RZCT 2
N
R1
2
where:
VEOUT5 is the voltage on the EOUT5 pin.
VREF is the external reference voltage.
ILK is the leakage current.
N is the turn ratio of the zero-current transformer (ZCT).
RZCT is the current sense resistor at the secondary side of the ZCT.
ZCT
RZCT
R1
EIN5_N
R1
EIN5_P
where:
VTRP is the high analog trip threshold voltage.
VTRPL is the low analog trip threshold voltage.
RTRP is the resistance connected between the VTRP pin and
ground.
RTRPL is the resistance connected between the VTRPL pin and
ground.
Note that there are limitations when choosing the RTRP and RTRPL
values to set the analog trip thresholds. The following
requirements must be met.
For RTRP selection,
R2
ILK
VTRPL V 0.01 RTRPL kΩ
RTRP VVREG 0.5 100 kΩ
ADP2450
–
EA5
+
and
EOUT5
RTRP VAVDD 0.1 100 kΩ
1:N
2R2
For RTRP selection,
VREF
RTRPL 30 kΩ
17088-066
2R2
If the analog trip function is not used, connect both VTRP and
VTRPL to VREG to disable the analog trip function.
Figure 67. Typical Configuration for Leakage Current Detection
ANALOG TRIP PROTECTION
The ADP2450 integrates an analog trip circuit for fast
protection in circuit breaker applications. The analog trip
circuit monitors the output of each PGA. When any of the four
PGA outputs exceeds the analog trip threshold, VTRP or VTRPL,
for the deglitch time, tTRP, the analog trip protection is triggered.
Two programmable analog trip thresholds, VTRP and VTRPL,
support both half-sinusoid and bipolar sinusoid input signal
application. VTRP is the high threshold and VTRPL is the low
threshold. The PGAx output signal is compared with the two
analog trip thresholds. If the PGAx output signal is either
higher than VTRP or lower than VTRPL, the analog trip protection
is triggered as shown in Figure 68.
AVDD
EINx
INPUT
SIGNAL
VCOM/2
VTRP
OUTPUT
SIGNAL
VTRPL
ANALOG
TRIP
AVDD
EOUTx
ADP2450
17088-067
0
PGAx
In the CT current sense application where the input signal is
half-sinusoid, only VTRP, the high analog trip threshold, is
needed. Connect VTRPL to VREG to disable VTRPL, the low analog
trip threshold. Connect RCOM and VCOM to ground in this
CT current sense application.
ACTUATOR DRIVER
The actuator driver receives the input signal either from the
TRG pin or from the output of the analog trip control circuit.
The driver also provides the gate drive voltage for the external
thyristor through the GATE pin, as shown in Figure 69. When
the analog trip protection is triggered, the analog trip control
circuit outputs a 10 ms high, 6 ms low pulse signal. This pulse
signal performs an OR logic with the signal on the TRG pin and
inputs to the actuator driver circuit to provide the gate drive
signal for the external thyristor or MOSFET. During this 16 ms
period, the 10 ms high, 6 ms low pulse signal, any analog trip
signal is ignored. If the analog trip signal is still active after the
16 ms period, another pulse that is 10 ms high, 6 ms low is
generated. If the analog trip signal is cleared after the 16 ms
period, the output of the analog trip control circuit latches to
low. The GATE pin can be pulled up to VREG.
Figure 68. Analog Trip Circuit
Rev. B | Page 24 of 40
Data Sheet
ANALOG TRIP
COMPARATOR
OUTPUT
ANALOG TRIP
CONTROL
10ms
6ms
ACTUATOR
DRIVER
TRG
GATE
17088-068
ADP2450
ADP2450
MCU
GPIO
Figure 69. Actuator Driver Control Circuit
THERMAL SHUTDOWN
In the event that the ADP2450 junction temperature exceeds
150°C, the thermal shutdown circuit turns off most of the
internal blocks but pulls the boost driver voltage (DRV pin) to
high. A 15°C hysteresis is included so that the ADP2450 does
not recover from thermal shutdown until the on-chip temperature
drops below 135°C. Upon recovery, a soft start and power-up
sequence is initiated prior to normal operation.
Rev. B | Page 25 of 40
ADP2450
Data Sheet
APPLICATIONS INFORMATION
OUTPUT CAPACITOR OF BOOST SHUNT
CONTROLLER
Table 10. Recommended Bridge Rectifiers
The output capacitor stores the energy coming from the CT and
provides the input voltage of the buck regulator as well as power
to the actuator. Depending on the VOUT1 setting and actuator
specification, the capacitance must be large enough so that it
can provide sufficient power to trigger the actuator when the
analog trip occurs and prevent the VOUT1 voltage from dropping.
The voltage rating of the boost shunt output capacitor must be
higher than the output voltage of the boost shunt controller
(VOUT1). A margin of at least 20% must be reserved. Polymer,
tantalum, and aluminum electrolytic capacitors are recommended
for the balance between capacitance, voltage rating, and size.
It is recommended to use a ceramic capacitor in the range from
1 μF to 10 μF in parallel with the output capacitor to reduce the
total effective series resistance (ESR), thus reducing the output
voltage ripple. Table 9 lists several recommended output
capacitors for the boost shunt controller.
Table 9. Recommended Output Capacitors
Vendor
KEMET
Panasonic
Part Number
T521X336M050ATE075
T521X476M035ATE070
T494E476M035AT7280
A767KN476M1HLAE029
EEFCX1V220R
35SVPF39M
50SVPF39M
EEHZA1H680P
EEHZA1H330XP
Capacitance
(μF)
33
47
47
47
22
39
39
68
33
Voltage
(V)
50
35
35
50
35
35
50
50
50
Vendor
Bourns
Fairchild
Part Number
CD2320-B1200
CD2320-B1400
CD2320-B1600
CD2320-B1800
CD2320-B11000
MDB6S
MDB8S
MDB10S
IF (A)
1
1
1
1
1
1
1
1
VDC (V)
200
400
600
800
1000
600
800
1000
VF (V)
1
1
1
1
1
1.1
1.1
1.1
IFSM (A)
30
30
30
30
30
30
30
30
SENSE RESISTOR SELECTION
In a typical MCCB application, a sense resistor is connected
between the negative output of the bridge rectifier and ground
to convert the half sinusoid current signal to the half sinusoid
voltage signal as the PGA input for signal coordination. The
resistor value depends on the system rated current (IN), the turn
ratio of the current transformer, the PGA gain setting, and the
PGA output low voltage.
A large resistor value provides a large input and output voltage
signal of the PGA for easy sampling. However, a large resistor
value increases the power loss on the sense resistor. A small
resistor value reduces the power loss. However, a small resistor
value decreases the PGA input and output voltage signal. Ensure
that the lowest PGA output signal for the ADC sampling is
higher than the output low voltage of the PGA so that the
sampling accuracy of the small signal is not affected.
The resistor power must be high enough to handle the large
current flowing through the sense resistor when the analog trip
occurs. Table 11 lists several recommended sense resistors.
Table 11. Recommended Sense Resistors
BRIDGE RECTIFIER
The bridge rectifier converts the sinusoid current of the CT
secondary side to a half sinusoid current to provide power to
the ADP2450. The average forward rectified current of the
bridge rectifier diode (IF) must be higher than the rms current
of the CT secondary side during normal operation. The
maximum dc blocking voltage of the bridge rectifier diode
(VDC) must be higher than the boost shunt controller output
voltage (VOUT1) of the ADP2450. Ensure that the peak forward
surge current of the bridge rectifier diode (IFSM) can handle the
peak current of the CT secondary side when a fault occurs, such
as when an analog trip is triggered.
Vendor
Vishay Dale
Rohm
Bourns
Bridge rectifier diodes with low forward voltage are recommended.
A low forward voltage reduces the power loss on the bridge
rectifier diodes. However, the package size of the bridge rectifier
increases. Table 10 lists several recommended bridge rectifiers
for general applications.
Rev. B | Page 26 of 40
Part Number
WSC2515R5000FEA
WSC25151R000FEA
WSC25152R000FEA
MCR100JZHFLR510
LTR50UZPF1R00
MCR100JZHFL2R00
PWR2615WR500FE
CRL2512-FW-1R00ELF
CRL2512-FW-2R00ELF
CRM2512-FX-2R00ELF
Value (Ω)
0.5
1
2
0.51
1
2
0.5
1
2
2
Power (W)
1
1
1
1
1
1
1
1
1
2
Data Sheet
ADP2450
Table 13. Recommended Schottky Diodes
EXTERNAL MOSFET FOR BOOST SHUNT
CONTROLLER
An N-channel external MOSFET is needed to control the CT
current in the boost shunt controller.
When the external MOSFET is turned off, the current from the CT
charges the output capacitor to VOUT1 through the boost shunt
diode. The voltage added on the drain and source nodes of the
MOSFET is equal to VOUT1 plus the diode forward voltage.
When the external MOSFET is turned on, it bypasses the CT
current to ground. It is recommended to choose a MOSFET
with a breakdown voltage (VDSS) at least twice that of the output
voltage of boost shunt controller (VOUT1). It is also recommended
that the continuous drain current (ID) be larger than the CT
secondary root mean square (rms) current when the analog trip
occurs.
The MOFSET driver integrated in the ADP2450 has an 8 V output
high voltage (VDRV_H). Ensure that the gate to source voltage (VGS) of
the selected MOSFET is greater than 8 V, and that the gate
threshold voltage (VGS_TH) is lower than 8 V. Table 12 lists several
recommended MOSFETs for the boost shunt controller.
Table 12. Recommended External MOSFETs
Vendor
Infineon
DIODES
ON Semiconductor
Part Number
IRFR3505PBF
IRFR3518TRPBF
BSC340N08NS3GATMA1
DMN6068LK3-13
DMN6013LFG-7
DMT8012LFG-13
FDMC86340
NTTFS5820NLTAG
FDS5670
FDS3572
VDSS
(V)
55
80
80
60
60
80
80
60
60
80
ID
(A)
30
30
23
8.5
10.3
35
14
37
10
8.9
BOOST SHUNT DIODE SELECTION
The ADP2450 integrates a boost shunt controller that requires
an external Schottky rectifier to conduct the CT current to the
output capacitor of the boost shunt circuit when the external
boost shunt MOSFET is turned off. Ensure that the Schottky
diode peak current rating is larger than the maximum CT
secondary current. The peak reverse voltage of the Schottky
diode must be greater than the output voltage of boost shunt
controller. To achieve the best efficiency, select a Schottky diode
with a low forward voltage (VF).
Vendor
DIODES
ON Semiconductor
Rohm
Bourns
1
2
Part Number
B360A
B350A
B260A
MBRS360BT3G
MBRS260T3G
NRVBS260T3G
RB055LAM-60TR
RB068LAM-60TR
CD214A-B360LF
VRRM1 (V)
60
50
60
60
60
60
60
60
60
IO2 (A)
3
3
2
3
2
2
3
2
3
VRRM is the peak repetitive reverse voltage of the diodes.
IO is the forward current of the diodes.
INPUT CAPACITOR OF BUCK REGULATOR
The input capacitor reduces the input voltage ripple of the buck
regulator caused by the switching current on VIN. Place the
input capacitor as close as possible to the VIN pin. A 10 μF
ceramic capacitor is recommended. The loop that is composed
of this input capacitor, the high-side N-MOSFET, and the lowside N-MOSFET must be kept as small as possible.
The voltage rating of the input capacitor must be greater than
the maximum input voltage. Ensure that the rms current rating
of the input capacitor is larger than the value calculated from
the following equation:
I CIN _ RMS I OUT 2 D 1 D
where:
ICIN_RMS is the rms current of the input capacitor of buck regulator.
IOUT2 is the output current of the buck regulator.
D is the duty cycle of the buck regulator (D = VOUT2/VIN).
INDUCTOR SELECTION
The inductor value of the buck regulator is determined by the
operating frequency, input voltage, output voltage, and inductor
ripple current. Using a small inductor leads to a faster transient
response but degrades efficiency due to a larger inductor ripple
current, whereas using a large inductor value leads to smaller
ripple current and improved efficiency but results in a slower
transient response.
As a guideline, the inductor ripple current, ΔIL, is typically set
to one-third of the maximum load current. The inductor value
is calculated using the following equation:
L
VIN VOUT 2 D
I L f SW
where:
VIN is the input voltage of the buck regulator.
VOUT2 is the output voltage of the buck regulator.
ΔIL is the inductor current ripple.
fSW is the switching frequency of buck regulator.
Rev. B | Page 27 of 40
ADP2450
Data Sheet
The peak inductor current (IPEAK) is calculated with the
following equation:
Both the output voltage of boost shunt controller (VOUT1) and
buck regulator (VOUT2) are set by the external resistor dividers,
as shown in Figure 70 and Figure 71.
I
IOUT 2 L
2
The saturation current of the inductor must be larger than the
peak inductor current. For ferrite core inductors with a quick
saturation characteristic, the saturation current rating of the
inductor must be greater than the current-limit threshold of the
switch. This greater saturation current rating prevents the
inductor from reaching saturation.
The rms current of the inductor (IL_RMS) is calculated with the
following equation:
I L 2
12
Shielded ferrite core materials are recommended for low core
loss and low electromagnetic interference (EMI).
The resistor values are calculated using the following equation:
R
VOUT 1 1.2 1 TOP1
RBOT 1
where:
RTOP1 is the top side feedback resistor of VOUT1.
RBOT1 is the bottom side feedback resistor of VOUT1.
To limit the output voltage accuracy degradation due to the FB1
bias current (0.1 μA maximum) to less than 0.5% (maximum),
ensure that RBOT1 < 60 kΩ.
VOUT1
ADP2450
OUTPUT CAPACITOR OF BUCK REGULATOR
RBOT1
The output capacitor selection affects the output ripple voltage
of the buck regulator.
The output ripple is determined by the ESR and the capacitance
value. Use the following equation to select a capacitor that
meets the output ripple requirements (COUT2_RIPPLE):
COUT 2 _ RIPPLE
I L
8 f SW VOUT 2 _ RIPPLE
where:
ΔVOUT2_RIPPLE is the allowable output ripple voltage of the buck
regulator.
RESR
VOUT 2 _ RIPPLE
I L
where RESR is the maximum equivalent series resistance of the
buck regulator output capacitor in ohms (Ω).
GND
Figure 70. Boost Shunt Controller Output Voltage Setting
Buck Regulator Output Voltage
The buck regulator has the following two output voltage
settings: adjustable output and fixed output.
For adjustable output voltage, connect the external resistor
divider as shown Figure 71. The resistor values are calculated
using the following equation:
R
VOUT 2 0.6 1 TOP 2
RBOT 2
where:
RTOP2 is the top side feedback resistor of VOUT2.
RBOT2 is the bottom side feedback resistor of VOUT2.
Select the output capacitance to be larger than COUT2_RIPPLE and
select the ESR value to be smaller than RESR to meet the output
ripple.
VOUT2
ADP2450
I COUT 2 _ RMS
RTOP2
FB2
RBOT2
The selected output capacitor voltage rating must be greater
than the output voltage. The rms current rating of the output
capacitor (ICOUT2_RMS) must be greater than the value that is
calculated using the following equation:
I
L
12
RTOP1
FB1
17088-069
I L _ RMS IOUT 22
Boost Shunt Controller Output Voltage
GND
17088-070
I PEAK
OUTPUT VOLTAGE SETTING
Figure 71. Buck Regulator Adjustable Output Voltage Setting
To limit the output voltage accuracy degradation due to FB2
bias current (0.1 μA maximum) to less than 0.5% (maximum),
ensure that RBOT2 < 30 kΩ.
For fixed output voltage, connect FB2 to VOUT2 directly.
Rev. B | Page 28 of 40
Data Sheet
ADP2450
Buck Regulator Voltage Conversion Limitations
EXTERNAL MOSFET FOR ACTUATOR
The minimum output voltage of a buck regulator for a given
input voltage and switching frequency is constrained by the
minimum on time. The minimum on time of the ADP2450
buck regulator is typically 50 ns. The minimum output voltage
at a given input voltage and frequency is calculated using the
following equation:
The ADP2450 has an integrated actuator driver. When the
analog trip is triggered or the TRG pin is pulled up high, the
internal actuator driver outputs a 5 V driver signal on the
GATE pin and turns on the external MOSFET to trigger the
actuator. The instantaneous current when the actuator is
triggered is equal to VOUT1 divided by the resistance of the
actuator. The continuous drain current of the MOSFET must be
larger than the instantaneous current when the actuator is
triggered. In normal operation where the MOSFET is turned
off, VOUT1 the voltage added onto the drain and source nodes of
the MOSFET. It is recommended to select a MOSFET with a
VDSS that is twice as large as VOUT1 to provide enough margin.
VOUT2_MIN = VIN × tMIN_ON × fSW − (RDSON_HS − RDSON_LS) ×
IOUT2_MIN × tMIN_ON × fSW − (RDSON_LS + RL) × IOUT2_MIN
(1)
where:
VOUT2_MIN is the minimum output voltage.
tMIN_ON is the minimum on time.
fSW is the switching frequency.
RDSON_HS is the high-side MOSFET on resistance.
RDSON_LS is the low-side MOSFET on resistance.
IOUT2_MIN is the minimum output current.
RL is the series resistance of the output inductor.
The recommended MOSFETs listed in Table 12 can also be used
as the MOSFET for the actuator.
The maximum output voltage of a buck regulator for a given
input voltage and switching frequency is constrained by the
minimum off time. The minimum off time of the ADP2450
buck regulator is typically 150 ns.
The maximum output voltage, limited by the minimum off time
at a given input voltage and frequency, is calculated using the
following equation:
VOUT2_MAX =
VIN × (1 − tMIN_OFF × fSW) − (RDSON_HS − RDSON_LS) × IOUT2_MAX ×
(2)
(1 − tMIN_OFF × fSW) − (RDSON_LS + RL) × IOUT2_MAX
where:
VOUT2_MAX is the maximum output voltage.
tMIN_OFF is the minimum off time.
IOUT2_MAX is the maximum output current.
Rev. B | Page 29 of 40
ADP2450
Data Sheet
DESIGN EXAMPLE
This section describes the procedures for selecting the external
components, based on a typical MCCB design example. The
system specifications are listed in Table 14. See Figure 72 for the
schematic for this design example.
Table 14. MCCB System Requirements
Parameter
Boost Shunt Controller Output Voltage
System Enable Threshold Voltage
System Disable Threshold Voltage
Minimum System Consumption Current
Buck Regulator Output Voltage
Buck Regulator Output Voltage Ripple
Buck Regulator Output Current
Single CT Secondary Current Under IN
(Rated Current)
Actuator Resistance
Analog Trip Current at CT Secondary Side
Specification
VOUT1 = 12 V
VSYS_RISING = 9 V
VSYS_FALLING = 7 V
ISYS_MIN = 15 mA
VOUT2 = 3.3 V
VOUT2_RIPPLE = 10 mV
IOUT2 = 100 mA
IN_SEC = 75 mA
RACT = 4 Ω
ITRP_SEC = 11 × IN_SEC
BOOST SHUNT DIODE SETTING
The VRRM of the diode must be twice as large as VOUT1 to provide
enough margin. Choose a Schottky diode with VRRM > 24 V.
The peak current rating of the diode must be higher than 3 ×
ITRP_SEC = 2.475 A to cover the worst case scenario. Choose a
Schottky diode with IO ≥ 3 A.
It is recommended to select the MBRAF360T3G from ON
Semiconductor as the boost shunt diode.
BUCK REGULATOR OUTPUT VOLTAGE SETTING
According to the system requirement, the output voltage of the
buck regulator is 3.3 V. Select the ADP2450ACPZ-1-R7 model
for a fixed 3.3 V output voltage of the buck regulator.
INDUCTOR SETTING
The peak-to-peak inductor ripple current, ΔIL, is set to 30% of
the rated output current of the buck regulator. Use the following
equation to estimate the inductor value:
BOOST SHUNT OUTPUT VOLTAGE SETTING
L
Choose a 11.3 kΩ resistor as the bottom feedback resistor
(RBOT1), and calculate the top feedback resistor using the
following equation:
RTOP 1
VOUT 1 RBOT 1
RBOT 1
1.2
To set the output voltage of boost shunt controller to 12 V,
the resistor values are as follows: RTOP1 = 102 kΩ, and RBOT1 =
11.3 kΩ.
BOOST SHUNT OUTPUT CAPACITOR SETTING
The output capacitor of the boost shunt controller provides
energy to the actuator. The value of the capacitor depends on
the actuator specification and requirement. The capacitor value
also affects the total system start-up time. A small value
capacitor has fast system start-up time but may not provide
enough energy for the actuator when the trip occurs. A large
value capacitor has sufficient energy for the actuator but
extends the system start-up time.
A capacitor value from 100 μF to 220 μF satisfies most of the
actuator requirements in the MCCB application.
BOOST SHUNT MOSFET SETTING
VIN 2 VOUT 2 D
I L f SW
where:
VIN2 = VOUT1 = 12 V.
VOUT2 = 3.3 V.
D = 0.275.
ΔIL = 0.15 A.
fSW = 1.2 MHz.
This calculation results in L = 13.3 μH. Choose the standard
inductor value of 15 μH.
The inductor peak current is calculated by using the following
equation:
I PEAK IOUT 2
VIN 2 VOUT 2 D 1
15 μH f SW
2
This calculation results in IPEAK = 166 mA.
Based on the calculated current value, select an inductor with a
minimum rms current rating of 200 mA. A shield inductor is
preferred for improved system EMI performance.
It is recommended to select the LPS3015-153 from Coilcraft as
the inductor of the buck regulator.
The VDSS of the MOSFET must be twice as large as VOUT1 to
provide enough margin. Choose a MOSFET with VDSS > 24 V.
In a worst case scenario where the analog trip occurs on all
three phases, the current flowing through the MOSFET is 3 ×
ITRP_SEC = 2.475 A. Choose a MOSFET with ID > 3 A.
The VGS voltage of the MOSFET must be higher than 8 V.
It is recommended to select the FDMC86340 from ON
Semiconductor as the boost shunt MOSFET.
Rev. B | Page 30 of 40
Data Sheet
ADP2450
BUCK REGULATOR OUTPUT CAPACITOR SETTING
PGA GAIN SETTING
The output of the buck regulator provides the power supply for the
PGAs, MCU, and LCD display. In most MCCB applications, the
output voltage ripple requirement is important.
Set the PGA gain to ×1 as a start point. According to Table 8,
connect a 42.2 kΩ resistor between the GAIN1 pin and ground.
Connect the GAIN0 pin to an input/output (I/O) pin of the
MCU. If needed, switch the PGA gain between ×1 and ×4 by
setting the GAIN0 pin to low and high, respectively.
To meet the output voltage ripple requirement, use the following
equations to calculate the ESR and capacitance values of the
output capacitor of buck regulator:
COUT 2 _ RIPPLE
ESR
I L
8 f SW VOUT 2 _ RIPPLE
Choose a 2 Ω resistor as the sense resistor for each phase to set
the input voltage of PGA to 150 mV under the rated current, IN.
The power consumption on the sense resistor (PSENSE_MAX) when
the analog trip occurs is calculated using the following equation
(see Table 14 for the ITRP_SEC value):
VOUT 2 _ RIPPLE
I L
This calculation results in COUT2_RIPPLE = 1.56 μF and ESR =
66 mΩ. The output capacitance must be larger than 1.56 μF, and
the output capacitor ESR value must be smaller than 66 mΩ to
meet the output voltage ripple requirement. It is recommended
to use a one piece, 10 μF ceramic capacitor (such as the
GRM21BR70J106KE76 from Murata) as the output capacitor of
the buck regulator.
VPTH RESISTOR DIVIDER SETTING
1.09 V VSYS _ RISING 1.22 V VSYS _ FALLING
1.09 V 4.8 μA 1.22 V 1 μA
RBOT _ VP
1.22 V RTOP _ VP
VSYS _ RISING RTOP _ VP 4.8 μA 1.22 V
PSENSE _ MAX ITRP _ SEC 2 RSENSE
where:
RSENSE is the sense resistor value.
This calculation results in PSENSE_MAX = 1.36 W. Select a 2 Ω, 2 W
resistor, such as the CRM2512-FX-2R00ELF from Bourns, as
the sense resistor.
ANALOG TRIP THRESHOLD SETTING
According to the system enable and disable voltage threshold
requirements, use the following equation to calculate the VPTH
resistor divider values (see Table 14 for the VSYS_RISING and
VSYS_FALLING values):
RTOP _ VP
SENSE RESISTOR SETTING
The PGA output voltage is a half-sinusoid waveform. Calculate
the PGA output voltage peak value (VPGA_PEAK) when the analog
trip is triggered by using the following equation:
VPGA _ PEAK ITRP _ SEC RSENSE 2 GAIN
where GAIN = 1.
This calculation results in VPGA_PEAK = 2.333 V.
This calculation results in RTOP_VP = 316.6 kΩ and RBOT_VP =
61.7 kΩ. Select a standard resistor value of 316 kΩ for RTOP_VP
and 61.9 kΩ for RBOT_VP.
Consider that the analog trip has a default 200 μs delay time, which
results in a 3.6° phase delay of the half-sinusoid waveform. Set
the analog trip threshold voltage using the following equation:
VTRP VPGA _ PEAK sin86.4
DUMMY LOAD RESISTOR SETTING
This calculation results in VTRP = 2.328 V.
The dummy load, together with the power detection function,
ensures that the system is not enabled until there is sufficient
current provided by the CT.
Calculate the trip resistor value (RTRP) using the following equation:
Calculate the dummy load resistor value using the following
equation:
RPOWER
RTRP
VTRP
ITRP
This calculation results in RTRP = 232.8 kΩ. Choose a standard
resistor value of 232 kΩ as the analog trip resistor.
VSYS _ RISING
I SYS _ MIN
ACTUATOR MOSFET SETTING
This calculation results in RPOWER = 600 Ω. Choose the standard
resistor value 604 Ω for RPOWER.
Calculate the power consumption on the dummy load resistor
using the following equation (see Table 14 for the ISYS_MIN value):
PDUMMY I SYS _ MIN 2 RPOWER
The VDSS of the MOSFET must be twice as large as VOUT1 to
provide enough margin. Choose a MOSFET with VDSS > 24 V.
When the actuator is triggered, the instantaneous current
flowing through the MOSFET is VOUT1/RACT = 3 A. Select a
MOSFET with ID > 3 A.
The VGS voltage of the MOSFET must be higher than 5 V.
This calculation results in PDUMMY = 0.136 W. Select one 604 Ω
resistor with a 0805 package or two parallel 1.21 kΩ resistors
with 0603 packages as the dummy load.
It is recommended to select the FDMC86340 from ON
Semiconductor as the actuator MOSFET.
Rev. B | Page 31 of 40
ADP2450
Data Sheet
D1
MBRAF360T3G
BRIDGE1 IA
M1
FDMC86340
–
RSENSE1
2Ω/2W
CT2
BRIDGE2 IB
+
–
RSENSE2
2Ω/2W
CT3
BRIDGE3 IC
+
DRV
VOUT1
RTOP_VP
316kΩ
FB1
RBOT1
11.3kΩ
VIN
M2
FDMC86340
ACTUATOR
GATE
BST
SW
VPTH
CBST
100nF
L
15μH
MCU
VOUT2 = 3.3V
VCORE
COUT2
10μF
FB2
PGND2
VOUT2
AVDD
CAVDD
1μF
A
CVREG
1μF
RTRP
232kΩ
RSTO
RESET
GAIN0
GPIO1
GAIN1
–
B
RPOWER
604Ω
DET
CIN2
10μF
RBOT_VP
61.9kΩ
COUT1
220μF
RTOP1
102kΩ
ADP2450
PGND1
RSENSE3
2Ω/2W
C
VOUT1 = 12V
+
RGAIN
42.2kΩ
EIN1
EOUT1
ADC1
EIN2
EOUT2
ADC2
EIN3
EOUT3
ADC3
EIN4
EOUT4
EIN5_N
EOUT5
EIN5_P
RCOM
VREG
VCOM
VTRP
TRG
GND
Figure 72. Schematic for Design Example, Single Coil, Three Phases Sense
Rev. B | Page 32 of 40
GPIO2
17088-071
CT1
Data Sheet
ADP2450
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
In any switching power supply, there are some circuit paths that
carry high dI/dt, the current changing rate, which creates spikes
and noises. Some circuit paths are sensitive to noise, such as
feedback traces, error amplifier input and output traces, which
must be devoid of spikes and noises. The key to proper PCB
layout is to identify these critical paths and arrange the
components and the copper area accordingly to keep the paths
away from noise sources. When designing PCB layouts, be sure
to keep high current loops small. In addition, keep sensitive
trances and components away from the switching nodes and
their associated components.
The following sections describe the recommended layout rules
for the ADP2450. Figure 73 shows a recommended PCB layout
for single coil application.
GROUND PLANES
Use separate analog ground planes and power ground planes.
Connect the ground reference of sensitive analog circuitry, such
as output voltage divider components, amplifier output resistor
and capacitor (RC) filters, and a common voltage reference, to
analog ground. Connect the ground reference of the power
components, such as input and output capacitors, and external
MOSFETs to power ground. Use internal ground planes to connect
the analog ground plane and the power ground plane together.
In addition, connect the exposed pad of the ADP2450 to a large,
external copper ground plane to maximize the power
dissipation capability and minimize junction temperature.
SWITCH NODE
The switch node is the noisiest location in the switch power
supply circuit with large ac and dc voltages and currents. The
following two switch nodes are in the ADP2450 circuit: the
external MOSFET drain of the boost shunt controller and the
SW pin of the buck regulator. These nodes must be wide to
prevent the resistive voltage from dropping. To minimize the
generation of capacitively coupled noise, the total area of each
switch node must be small.
For the boost shunt controller, place the bridge rectifiers, the
MOSFET, the rectifier diode, and the output capacitors as close
as possible to each other, and use wide short traces or copper
planes. Ensure that the high current loop traces are as short and
as wide as possible.
For the buck regulator, place the input capacitor, the inductor,
and the output capacitor as close as possible to the IC, and use
short traces. Make the high current path from the input
capacitor through the inductor, the output capacitor, and the
power ground plane back to the input capacitor as short as
possible. In addition, ensure that the high current path from the
power ground plane through the inductor and output capacitor
back to the power ground plane is as short as possible by tying
the ADP2450 PGND2 pin to the power ground plane as close as
possible to the input and output capacitors.
FEEDBACK PATHS
The feedback traces of FB1 and FB2 are very sensitive to noise.
Place the feedback resistor divider networks as close as possible
to the FBx pins to prevent noise pickup. Minimize the length of
the feedback traces that connect the top of the feedback resistor
dividers to the output while keeping these traces away from the
high current traces and the switching nodes to avoid noise
pickup. To further reduce noise pickup, place an analog ground
plane on either side of the FBx traces and ensure that the traces
are as short as possible to reduce the parasitic capacitance pickup.
POWER TRACES
In the ADP2450 circuit design, the output of the boost shunt
controller, VOUT1, is connected to the input of buck regulator.
The output of buck regulator, VOUT2, is connected to the AVDD
providing power to the internal PGAs. These two traces are
power traces and may carry high currents. Use internal power
planes for the power trace connections and keep these power
traces as short and wide as possible to minimize the voltage
drops on them under high current situations.
SIGNAL PATHS
The input and output of all the amplifiers, the common voltage
input, the TRG trace, and the VTRP signals are all signal paths.
Keep these signal paths away from switch nodes and high
current paths to avoid noise pickup. Connect the ground
reference of these signal paths to the analog ground plane using
short and wide traces.
GATE DRIVER PATHS
The gate drive traces, DRV and GATE, of external MOSFETs
handle high dI/dt and tend to produce noise and ringing. The
gate drive traces must be as short and direct as possible. Avoid
using feedthrough vias in the gate drive traces. If vias are
needed, it is recommended to use two relatively large ones in
parallel to reduce the peak current density and the current in
each via. If the overall PCB layout is less than optimal, slowing
down the gate drive slightly can help reduce noise and ringing.
It may be helpful to place small value resistors, between 2 Ω and
10 Ω, on the DRV and GATE pins. These locations can be
populated with 0 Ω resistors if resistance is not needed. Note
that the added gate resistance increases the switching rise and
fall times, as well as switching power loss in the MOSFETs.
Rev. B | Page 33 of 40
ADP2450
Data Sheet
INPUT CURRENT
PLANE
VOUT1
PGND
PLANE
PGND2
DRV
FB1
VPTH
DET
BST
VIN
PGND
PLANE
SW
VOUT2
PGND1
GATE
TRG
VTRP
VREG
ADP2450
GND
GND
AVDD
RESET
GPIO
EOUT1
EIN2
EOUT2
EIN3
EOUT3
EIN4
EOUT4
RCOM
EIN1
FB2
RSTO
GAIN0
GAIN1
EOUT5
EIN5_N
EIN5_P
VCOM
AGND PLANE
Figure 73. Recommended PCB Layout for Single Coil Application, 32-Lead LFCSP Package
Rev. B | Page 34 of 40
17088-072
ADCs
VIA
BOTTOM LAYER TRACE
COPPER PLANE
Data Sheet
ADP2450
TYPICAL APPLICATION CIRCUITS
CT1
RECT BRIDGE
DIODE
DRV
RCS1
PGND1
CT2
COUT1
ADP2450
BOOST SHUNT
CONTROL
FB1
RBOT_VP
VPTH
POWER
DETECTION
DET
RTOP_VP
BST
SW
RECT BRIDGE
VOUT1
VIN
BUCK
REGULATOR
CIN2
RTOP1
RPOWER
RBOT1
RECT BRIDGE
RCS2
CT3
VOUT1
CBST
MCU
L
VOUT2
VCORE
COUT2
FB2
PGND2
RCS3
CT4
VOLTAGE
MONITORING
RECT BRIDGE
VOUT2
AVDD
EIN1
RCS4
EIN2
EIN3
EIN4
RSTO
RESET
GAIN0
GAIN SELECTION
PGA 1
PGA 2
PGA 3
PGA 4
GAIN1
GPIO1
RGAIN
EOUT1
ADC1
EOUT2
ADC2
EOUT3
ADC3
EOUT4
ADC4
VCOM
RCOM
DC OFFSET AND
COMPENSTION
R2
EIN5_N
R3
EIN5_P
R5
ZCT
R4
VTRP
RTRP
GATE
VREG
ACTUATOR
EOUT5
ADC5
AMPLIFIER 5
VREF
VOUT1
EA5
ANALOG TRIP
ACTUATOR
DRIVER
TRG
COMMON
CONTROL BLOCK
CREG
GND
Figure 74. Application Circuit—Single Coil, Signal and Power Share the Same CT
Rev. B | Page 35 of 40
GPIO2
REF
VREF
17088-073
RZCT
R1
ADP2450
Data Sheet
CT1
RECT BRIDGE
DIODE
DRV
R–COIL1
RINT
CT2
CINT
PGND1
RECT BRIDGE
R BOT_VP
R–COIL2
RINT
VPTH
COUT1
ADP2450
BOOST SHUNT
CONTROL
FB1
POWER
DETECTION
DET
RTOP_VP
CINT
VOUT1
BST
VOUT1
RECT BRIDGE
VIN
BUCK
REGULATOR
CIN2
RPOWER
R BOT1
SW
CT3
R TOP1
CBST
MCU
L
VOUT2
VCORE
COUT2
FB2
PGND2
R–COIL3
RINT
CT4
CINT
VOLTAGE
MONITORING
RECT BRIDGE
VOUT2
AVDD
EIN1
R–COIL4
RINT
CINT
EIN2
EIN3
VREF
EIN4
VCOM
RCOM
RINT
RSTO
RESET
GAIN0
GAIN SELECTION
PGA 1
PGA 2
PGA 3
PGA 4
GAIN1
GPIO1
RGAIN
EOUT1
ADC1
EOUT2
ADC2
EOUT3
ADC3
EOUT4
ADC4
DC OFFSET AND
COMPENSTION
R2
EIN5_N
R3
EIN5_P
R5
ZCT
R4
VTRP
R TRP
GATE
VREG
ACTUATOR
EOUT5
ADC5
AMPLIFIER 5
VREF
VOUT1
EA5
ANALOG TRIP
ACTUATOR
DRIVER
COMMON
CONTROL BLOCK
CREG
VTRPL
RTRPL
TRG
GPIO2
REF
VREF
GND
Figure 75. Application Circuit—Dual Coil, CT Provides Power and Rogowski Coils Provide Signal
Rev. B | Page 36 of 40
17088-074
RZCT
R1
Data Sheet
ADP2450
FACTORY-PROGRAMMABLE OPTIONS
The output voltage of the buck regulator, the reset rising delay time (tRST_DELAY_R), and the analog trip deglitch time (tTRP) can be preset to
one of the options listed in Table 15. To order a device with options other than the default options, contact a local Analog Devices, Inc.,
sales or distribution representative.
Table 15. Fuse Selectable Trim Options
Parameter
Buck Regulator Output Voltage
Reset Rising Delay Time (tRST_DELAY_R)
Analog Trip Deglitch Time (tTRP)
Options
Adjustable, 3.3 V, 5 V
0.5 ms (default), 1 ms, 2 ms, 5 ms
200 μs (default), 350 μs, 500 μs, 750 μs, 1 ms, 2 ms, 3 ms, 4 ms
Rev. B | Page 37 of 40
ADP2450
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00 SQ
4.90
PIN 1
INDICATOR
AREA
DETAIL A
(JEDEC 95)
0.30
0.25
0.18
25
P IN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)
32
24
1
0.50
BSC
3.25
3.10 SQ
2.95
EXPOSED
PAD
17
0.80
0.75
0.70
SIDE VIEW
0.20 MIN
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
PKG-003898
8
9
16
09-12-2018-A
0.50
0.40
0.30
TOP VIEW
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD
Figure 76. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-7)
Dimensions shown in millimeters
9.20
9.00 SQ
8.80
SIDE VIEW
1.60
MAX
0.75
0.60
0.45
TOP VIEW
48
37
1
1.00 REF
36
SEATING
PLANE
7.20
7.00 SQ
6.80
0.20
0.15
0.09
0.15
0.10
0.05
7°
0°
0.08 MAX
COPLANARITY
12
25
24
13
VIEW A
0.50
BSC
VIEW A
PKG-005430
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
Figure 77. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
Rev. B | Page 38 of 40
0.27
0.22
0.17
01-17-2018-A
1.45
1.40
1.35
Data Sheet
ADP2450
ORDERING GUIDE
Model1
ADP2450ACPZ-1-R7
ADP2450ACPZ-2-R7
ADP2450ACPZ-3-R7
ADP2450ACPZ-4-R7
ADP2450ACPZ-5-R7
ADP2450ASTZ-1-R7
ADP2450ASTZ-2-R7
ADP2450ASTZ-3-R7
ADP2450ASTZ-4-R7
ADP2450ASTZ-5-R7
ADP2450ACPZ-3-EVBZ
ADP2450ASTZ-3-EVBZ
1
Temperature
Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Buck Output
Voltage
3.3 V
5V
Adjustable
Adjustable
5V
3.3 V
5V
Adjustable
Adjustable
5V
Adjustable
Analog Trip
Deglitch Time
200 μs
200 μs
200 μs
200 μs
500 μs
500 μs
500 μs
500 μs
500 μs
500 μs
200 μs
Reset Rising
Delay Time
0.5 ms
0.5 ms
0.5 ms
2 ms
5 ms
0.5 ms
0.5 ms
0.5 ms
2 ms
2 ms
0.5 ms
Adjustable
500 μs
0.5 ms
Z = RoHS Compliant Part.
Rev. B | Page 39 of 40
Package
Description
32-Lead LFCSP
32-Lead LFCSP
32-Lead LFCSP
32-Lead LFCSP
32-Lead LFCSP
48-Lead LQFP
48-Lead LQFP
48-Lead LQFP
48-Lead LQFP
48-Lead LQFP
32-Lead LFCSP
Evaluation Board
48-Lead LQFP
Evaluation Board
Package
Option
CP-32-7
CP-32-7
CP-32-7
CP-32-7
CP-32-7
ST-48
ST-48
ST-48
ST-48
ST-48
ADP2450
Data Sheet
NOTES
©2018–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D17088-0-7/19(B)
Rev. B | Page 40 of 40
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