ADP3020ARU

a High-Efficiency Notebook Computer Power Supply Controller ADP3020 GENERAL DESCRIPTION FEATURES Wide Input Voltage Range: 4.5 V to 25 V High Conversion Efficiency > 96% Integrated Current Sense—No External Resistor Required Low Shutdown Current: 7 A (Typical) Dual Synchronous Buck Controllers with Selectable PWM/Power-Saving Mode Operation Built-In Gate Drive Boost Circuit for Driving External N-Channel MOSFETs Two Independently Programmable Output Voltages Fixed 3.3 V or Adjustable (1.25 V to VIN–0.5 V) Fixed 5 V or Adjustable (1.25 V to VIN–0.5 V) Programmable PWM Frequency Integrated Linear Regulator Controller Extensive Circuit Protection Functions 38-Lead TSSOP Package APPLICATIONS Notebook Computers and PDAs Portable Instruments General Purpose DC-DC Converters The ADP3020 is a highly efficient dual synchronous buck switching regulator controller optimized for converting the battery or adapter input into the system supply voltages required in notebook computers. The ADP3020 uses a dual-mode PWM/Power Saving Mode architecture to maintain efficiency over a wide load range. The oscillator frequency can be programmed for 200 kHz, 300 kHz, or 400 kHz operation, or it can be synchronized to an external clock signal of up to 600 kHz. The ADP3020 provides accurate and reliable short circuit protection using an internal current sense circuit, which reduces cost and increases overall efficiency. Other protection features include programmable soft-start, UVLO, and integrated output undervoltage/overvoltage protection. The ADP3020 contains a linear regulator controller that is designed to drive an external P-channel MOSFET or PNP transistor. The linear regulator output is adjustable, and can be used to generate the auxiliary voltages required in many laptop designs. FUNCTIONAL BLOCK DIAGRAM VIN 5.5V TO 25V ADP3020 1.20V PFO 5V LINEAR REF Q1 L1 3.3V 5V SMPS Q4 3.3V SMPS Q2 Q3 L2 5V SS5 SS3 Q5 LINEAR CONTROLLER POWER-ON RESET PWRGD 2.5V R EV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 C to ADP3020–SPECIFICATIONS (@ T = –40noted.)+85 C, VIN = 12 V, SS5 = SS3 = INTVCC, INTVCC Load = 0 mA, REF Load = 0 mA, MODE = 0 V, SYNC = 0 V, SD = 5 V, unless otherwise A Parameter INTERNAL 5 V REGULATOR Input Voltage Range 5 V Voltage Line Regulation Total Variation Switchover Voltage Switchover Hysteresis Undervoltage Lockout Threshold Voltage Undervoltage Lockout Hysteresis REFERENCE Output Voltage2 SUPPLY CURRENT Shutdown Current Standby Current Quiescent Current (PWM Mode) Symbol INTVCC Conditions Min 5.5 4.95 4.8 4.65 3.6 Typ Max 25 5.15 5.2 4.85 4.2 Unit V V mV/V V V mV V mV TA = 25°C 5.5 V ≤ VIN ≤ 25 V Line, Temp AUXVCC from Low to High AUXVCC from High to Low INTVCC Falling 5.025 0.3 4.75 100 3.8 120 REF IQ 5.5 V ≤ VIN ≤ 25 V SD = 0 V SS3 = SS5 = SD2 = 0 V SD = 5 V No Loads, MODE = 5 V SS3 = SS5 = SD2 = 5 V FB5 = FB3 = FB2 = 1.25 V, ADJ/FX5 = ADJ/FX3 = 5 V No Loads, MODE = 0 V SS3 = SS5 = SD2 = 5 V FB5 = FB3 = FB2 = 1.25 V, ADJ/FX5 = ADJ/FX3 = 5 V SYNC = AGND SYNC = REF SYNC = INTVCC tF ≤ 200 ns tR ≤ 200 ns SYNC = REF 1.185 1.197 7 250 0.95 1.209 15 400 1.8 V µA µA mA Quiescent Current (Power-Saving Mode) 650 µA OSCILLATOR Frequency fOSC 176 264 352 230 4.6 200 300 400 224 336 448 600 0.4 kHz kHz kHz kHz V V µA V V SYNC Input Frequency Range Input Low Voltage3 Input High Voltage3 Input Current POWER GOOD Output Voltage In Regulation Output Voltage Out of Regulation PWRGD 1.2 4.8 0.4 PWRGD Trip Threshold PWRGD Hysteresis CPOR Pull-Up Current ERROR AMPLIFIER DC Gain Gain-Bandwidth Product Input Leakage Current MAIN SMPS CONTROLLERS Fixed 5 V Output Voltage PWM Mode Power-Saving Mode Fixed 3.3 V Output Voltage PWM Mode Power-Saving Mode 10 kΩ Pull-Up to 5 V 10 kΩ Pull-Up to 5 V FB5 < 90% of Nominal Output Value FB5 Rising FB5 Falling CPOR = 1.2 V –8 –4 4 2.5 67 10 –2 % % µA dB MHz nA GBW IEAN FB5 ADJ/FX5 = ADJ/FX3 = 5 V 200 5.5 V ≤ VIN ≤ 25 V, ADJ/FX5 = 0 V 5.5 V ≤ VIN ≤ 25 V, ADJ/FX5 = 0 V FB3 5.5 V ≤ VIN ≤ 25 V, ADJ/FX3 = 0 V 5.5 V ≤ VIN ≤ 25 V, ADJ/FX3 = 0 V 4.90 4.925 3.234 3.250 5.0 5.025 3.3 3.316 5.10 5.125 3.366 3.382 V V V V – 2– REV. 0 ADP3020 Parameter Adjustable Output Voltage PWM Mode Power-Saving Mode Output Voltage Adjustment Range3 Current Limit Threshold (PWM Mode) CLSET5 = CLSET3 = Floating CLSET5 = CLSET3 = 0 V Current Limit Threshold (Power-Saving Mode) CLSET5 = CLSET3 = Floating CLSET5 = CLSET3 = 0 V Power-Saving Mode Trip Threshold Soft-Start Current Soft-Start Turn-On Threshold Feedback Input Leakage Current Maximum Duty Cycle3 Transition Time (DRVH/DRVL) Rise Fall Logic Input Low Voltage Logic Input High Voltage LINEAR REGULATOR CONTROLLER Feedback Threshold SD2 Pull-Up Current SD2 Threshold Current Sinking Capability FB2 Input Leakage Current POWER-FAIL COMPARATOR PFI Input Threshold PFI Input Hysteresis PFI Input Current PFO High Voltage PFO Low Voltage FAULT PROTECTION Output Overvoltage Trip Threshold Output Undervoltage Lockout Threshold Symbol EAN5, EAN3 FB5, FB3 FB5, FB3 Conditions 5.5 V ≤ VIN ≤ 25 V, ADJ/FX5 = ADJ/FX3 = 5 V 5.5 V ≤ VIN ≤ 25 V, ADJ/FX5 = ADJ/FX3 = 5 V ADJ/FX5 = ADJ/FX3 = 5 V 5.5 V ≤ VIN ≤ 25 V, TA = 25°C 5.5 V ≤ VIN ≤ 25 V, TA = 25°C 5.5 V ≤ VIN ≤ 25 V, TA = 25°C 5.5 V ≤ VIN ≤ 25 V, TA = 25°C CLSET5 = CLSET3 = 0 V, TA = 25°C SS3 = SS5 = 3 V SS5, SS3 IFB DMAX tR tF 0.7 ADJ/FX5 = ADJ/FX3 = 5 V, FB = 1.2 V VIN = 5.5 V, SYNC = AGND CLOAD = 3000 pF, 10%–90% CLOAD = 3000 pF, 90%–10% MODE, SD, ADJ/FX3, ADJ/FX5 MODE, SD, ADJ/FX3, ADJ/FX5 Min 1.173 1.179 1.25 54 115 72 144 Typ Max Unit V V 1.197 1.221 1.203 1.227 VIN–0.5 V 90 173 mV mV 16 35 28 4 1.2 1.8 200 mV mV mV µA V nA % 94 99 40 40 70 70 0.6 2.4 1.176 1.20 4 1.2 45 50 1.20 24 1.224 1.8 ns ns V V V µA V mA nA V mV nA V V % % FB2 SD2 DRV2 IFB SD2 = 1.2 V DRV2 = 2 V, FB2 = 1 V, SD2 = 5 V FB2 = 1.2 V PFO from High to Low 10 kΩ Pull-Up to 5 V 10 kΩ Pull-Up to 5 V With Respect to Nominal Output With Respect to Nominal Output 0.7 20 1.176 1.224 200 4.8 0.4 115 75 120 80 125 85 NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 The reference’s line-regulation error is insignificant. The reference cannot be used for external load. 3 Guaranteed by design, not tested in production. Specifications subject to change without notice. REV. 0 – 3– ADP3020 PIN FUNCTION DESCRIPTIONS Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 Mnemonic CS5 FB5 EAN5 EAO5 ADJ/FX5 SS5 CLSET5 REF AGND CLSET3 MODE SYNC Function Current Sense Input for top N-Channel MOSFET of the 5 V Buck Converter. Connect to the drain of the top N-channel MOSFET. Feedback Input for the 5 V Buck Converter. Connect to the output sense point in fixed output mode. Connect to an external resistor divider in adjustable output mode. Inverting Input of the Error Amplifier of the 5 V Buck Converter. Use for external loop compensation only in fixed output mode. In adjustable output mode, connect to an external resistor divider. Error Amplifier Output for the 5 V Buck Converter. TTL Logic Input. When ADJ/FX5 = 0 V, fixed output mode, connect FB5 to the output sense point. When ADJ/FX5 = 5 V, adjustable output mode, connect FB5 to the external resistor divider. Soft Start for the 5 V Buck Converter. Also used as an ON/OFF Pin. Current Limit Setting. A resistor can be connected from AGND to CLSET5. A minimum current limit is obtained by leaving it unconnected. A max current limit is obtained by connecting it to AGND. 1.2 V Bandgap Reference. Bypass it with a capacitor (1 nF typical) to AGND. REF cannot be used directly with an external load. Analog Signal Ground. Current Limit Setting. A resistor can be connected from AGND to CLSET3. A minimum current limit is obtained by leaving it unconnected. A max current limit is obtained by connecting it to AGND. TTL Logic Input. MODE = 5 V, always in constant frequency PWM mode; MODE = 0 V, PWM mode at moderate and heavy loads, and Power Saving (PSV) Mode at light load. Oscillator Synchronization and Frequency Select. fOSC = 200 kHz, when SYNC = 0 V; fOSC = 300 kHz, if SYNC is tied to the REF Pin; fOSC = 400 kHz, when SYNC = 5 V. Oscillator can be synchronized with an external source through the SYNC Pin. Soft Start for the 3.3 V Buck Converter. Also used as an ON/OFF Pin TTL Logic Input. When ADJ/FX3 = 0 V, fixed output mode, connect FB3 to the output sense point. When ADJ/FX3 = 5 V, adjustable output mode, connect FB3 to external resistor divider. Error Amplifier Output for the 3.3 V Buck Converter. Error Amplifier Inverting Input of the 3.3 V Buck Converter. Use for external loop compensation only in fixed output mode. In adjustable output mode, connect to an external resistor divider. Feedback Input for the 3.3 V Buck Converter. Connect to output sense point in fixed output mode. Connect to an external resistor divider in adjustable output mode. Current Sense Input for Top N-Channel MOSFET of the 3.3 V Buck Converter. It should be connected to the drain of the N-channel MOSFET. The (–) Input of a comparator that can be used as a power fail detector. The positive input is connected to the 1.20 V reference. There is a 24 mV hysteresis for this comparator. Open Drain Output. This pin will sink current when the PFI pin is lower than 1.20 V. Otherwise, PFO is floating. Power Good Output. PWRGD goes low with no delay, whenever the 5 V output drops 8% below its nominal value. When the 5 V output is within –4% of its nominal value, PWRGD will be released after a time delay determined by the timing capacitor on the CPOR pin. Connect a capacitor between CPOR and AGND to set the delay time for the PWRGD pin. A 2.5 µA pull-up current is used to charge the capacitor. A manual reset (MR) function can also be implemented by grounding this pin. Shutdown input for the Linear Regulator Controller. Feedback for the Linear Regulator Controller. Open Collector Output for the Linear Regulator Controller. Boost Capacitor Connection for High Side Gate Driver of the 3.3 V Buck Converter. High Side Gate Driver for 3.3 V Buck Converter. Switching Node (Inductor) Connection of the 3.3 V Buck Converter. Low Side Gate Driver of 3.3 V Buck Converter. Main Supply Input (4.5 V to 25 V). 13 14 15 16 17 18 19 20 21 SS3 ADJ/FX3 EAO3 EAN3 FB3 CS3 PFI PFO PWRGD 22 CPOR 23 24 25 26 27 28 29 30 SD2 FB2 DRV2 BST3 DRVH3 SW3 DRVL3 VIN –4– REV. 0 ADP3020 PIN FUNCTION DESCRIPTIONS (Continued) Pin No. 31 32 Mnemonic INTVCC AUXVCC Function Linear Regulator Bypass for the internal 5 V LDO. Bypass this pin with a 4.7 µF capacitor to AGND. Supply Switch Over. When AUXVCC > 4.75 V, and both of the switchers are in Power Saving mode, the internal 5 V LDO is turned off. The chip is powered by AUXVCC pin. There is a 2% hysteresis for this pin. Shutdown Control Input, Active Low. If SD = 0 V, the chip is in shutdown with very low quiescent current. For automatic start-up, connect SD to VIN directly. Power Ground. Low Side Driver for 5 V Buck Converter. Switching Node (Inductor) Connection for 5 V Buck Converter. High Side Gate Driver for 5 V Buck Converter. Boost Capacitor Connection for High Side Gate Driver of the 5 V Buck Converter. 33 34 35 36 37 38 SD PGND DRVL5 SW5 DRVH5 BST5 ABSOLUTE MAXIMUM RATINGS * PIN CONFIGURATION CS5 1 FB5 2 EAN5 3 EAO5 4 ADJ/FX5 5 SS5 6 CLSET5 7 REF 8 38 BST5 37 DRVH5 36 SW5 35 DRVL5 34 PGND 33 SD VIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +27 V AGND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 0.3 V INTVCC . . . . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to +6 V BST5, BST3 to PGND . . . . . . . . . . . . . . . . . –0.3 V to +32 V BST5 to SW5 . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V BST3 to SW3 . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V CS5, CS3 . . . . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to VIN SW3, SW5 to PGND . . . . . . . . . . . . . . –0.3 V to VIN + 0.3 V SD . . . . . . . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to +27 V DRVL5/3 to PGND . . . . . . . . . –0.3 V to (INTVCC + 0.3 V) DRVH5/3 to SW5/3 . . . . . . . . . –0.3 V to (INTVCC + 0.3 V) All Other Inputs and Outputs . . . . . . . . . . . . . . . . . . AGND – 0.3 V to INTVCC + 0.3 V θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98°C/W Operating Ambient Temperature Range . . . . –40°C to +85°C Junction Temperature Range . . . . . . . . . . . . –40°C to +150°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C *This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. ADP3020 32 AUXVCC 31 INTVCC TOP VIEW AGND 9 (Not to Scale) 30 VIN CLSET3 10 MODE 11 SYNC 12 SS3 13 ADJ/FX3 14 EAO3 15 EAN3 16 FB3 17 CS3 18 PFI 19 29 DRVL3 28 SW3 27 DRVH3 26 BST3 25 DRV2 24 FB2 23 SD2 22 CPOR 21 PWRGD 20 PFO ORDERING GUIDE Model ADP3020ARU Temperature Range –40°C to +85°C Package Description Thin Shrink Small Outline Package Option RU-38 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3020 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 –5– ADP3020 INPUT AUXVCC 32 – + SD 33 INTVCC 5V 31 +5V LINEAR REG 14mV –+ + – REF 1.2V AGND 8 1.2V REF 7 ULVO VIN 30 ADP3020 + 4.7V – 72mV –+ 1 CS5 CLSET5 9 38 – 1.20V + INTVCC 200kHz/ 300kHz/ 400kHz OSC POWER– ON RESET PFO 20 PFI 19 BST5 DRVH5 SW5 VOUT5 5V 37 36 MODE 11 SYNC 12 PWRGD 21 CONTROL LOGIC 35 34 DRVL5 PGND FB5 + – –3mV FB5 + +2% – 1.22V 2 3.3V CPOR 22 DRV2 25 2.5V FB2 1.2V 24 4A SD2 23 1.2V + – EA + – + –2% 1.18V – 3 1.2V EAO5 EAN5 – + 0% – 1.2V SHUTDOWN + +20% – + –20% – S Q R OC 2.5V – ON5 – DUPLICATE FOR SECOND CONTROLLER Figure 1. Block Diagram (All Switches and Components Are Shown for Fixed Output Operation) –6– + + + 4 1.44V 0.7 A 0.96V 5 ADJ/FX5 4A 6 SS5 1.2V REV. 0 Typical Performance Characteristics– ADP3020 100 VIN = 6V 100 90 VIN = 15V 90 VIN = 6V EFFICIENCY – % EFFICIENCY – % 80 80 VIN = 15V 70 70 60 60 50 0.01 0.1 1 OUTPUT CURRENT – A 10 50 0.01 0.1 1 OUTPUT CURRENT – A 10 Figure 2. Efficiency vs. 5 V Output Current Figure 5. Efficiency, 1.5 V Output Current 100 VIN = 6V 90 1200 +85 C VIN = 15V EFFICIENCY – % CURRENT – A 1000 +25 C –40 C 80 70 800 60 50 0.01 600 0.1 1 OUTPUT CURRENT – A 10 5 10 15 INPUT VOLTAGE – V 20 25 Figure 3. Efficiency vs. 3.3 V Output Current Figure 6. PWM Mode Input Current vs. Input Voltage 100 900 90 VIN = 6V 800 +85 C 700 +25 C –40 C 600 EFFICIENCY – % 80 70 VIN = 15V 60 CURRENT – A 10 500 50 0.01 0.1 1 OUTPUT CURRENT – A 400 5 10 15 INPUT VOLTAGE – V 20 25 Figure 4. Efficiency vs. 2.5 V Output Current Figure 7. PSV Mode Input Current vs. Input Voltage REV. 0 –7– ADP3020 300 +85 C CURRENT LIMIT THRESHOLD – mV CLSET = GND 200 250 +25 C 250 CURRENT – A –40 C 150 VIN = 5.5V TO 25V 100 200 150 50 100 5 10 15 INPUT VOLTAGE – V 20 25 0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 AMBIENT TEMPERATURE – C Figure 8. Input Standby Current vs. Input Voltage Figure 11. Current Limit Threshold vs. Temperature 10 9 8 7 1.210 1.205 REFERENCE OUTPUT – V +85 C CURRENT – A +25 C 6 5 –40 C 4 3 2 1 0 5 10 15 INPUT VOLTAGE – V 20 25 1.200 1.195 1.190 VIN = 5.5V TO 25V 1.185 1.180 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 AMBIENT TEMPERATURE – C Figure 9. Input Shutdown Current vs. Input Voltage Figure 12. Reference Output vs. Temperature 315 TEK STOP: SINGLE SEQ 250 S/s [T ] SYNC = REF 310 CH1 = 3.3V OUTPUT VIN = 25 305 VIN = 12 CH2 = 2.5V OUTPUT 300 VIN = 7.5 295 VIN = 5.5 FREQUENCY – kHz CH3 = SS3 VIN = 12V 290 –40 CH4 = SS5 –10 20 50 AMBIENT TEMPERATURE – C 80 CH1 CH3 2.00V 1.00V CH2 CH4 1.00V 1.00V M 200MS CH4 740mV Figure 10. PWM Mode Oscillator Frequency vs. Temperature Figure 13. Soft-Start Sequencing –8– REV. 0 ADP3020 STOP [ T ] STOP [ T ] CH1 = 5V OUTPUT CH1 = 5V OUTPUT CH2 = I OUT = 10mA TO 3A CH2 = I OUT = 10mA TO 3A CH1 200mV CH2 2.00V M 200 s CH2 1.88V CH1 200mV CH2 2.00V M 200 s CH2 1.88V Figure 14. Power-Saving Mode, Transient Response Figure 16. PWM Mode, Transient Response STOP [ T ] TEK STOP: SINGLE SEQ 250 S/s [T ] CH1 = 5V OUTPUT (IOUT = 20mA) CH1 CH2 CH2 = SW5 CH1 200mV CH2 5.00V M 400 s CH2 1.90V CH1 10.0V CH2 200mV M 5.00ms CH1 10.8V Figure 15. Power-Saving Mode, Waveforms Figure 17. VIN = 7.5 V to 22 V Transient, 2.5 V Output, CH1 – Input Voltage, CH2 – Output Voltage REV. 0 –9– ADP3020 THEORY OF OPERATION The ADP3020 is a dual-mode, step-down power supply controller for notebook computers or similar battery-powered applications. The device contains two synchronous step-down buck controllers and a linear regulator controller. The buck controllers in the ADP3020 have the ability to provide either fixed 3.3 V and 5 V outputs or independently adjustable (1.25 V to VIN–0.5 V) outputs. High efficiency over a broad load range is achieved by using a proprietary dual-mode PWM/power-saving (PSV) mode architecture. Efficiency is further improved by deleting the external current sense resistor, which is the main contributor to loss during high current, low output voltage conditions. CIRCUIT DESCRIPTION Dual-Mode Architecture MODE can be driven by an external TTL logic signal. When MODE is pulled HIGH, PSV mode operation is disabled, and the system is always in constant frequency PWM mode. In order to enable PSV mode at light loads, the MODE pin needs to be pulled LOW. Table I. PWM Mode and PSV Mode Mode High Low Low Low Load Current X Heavy Moderate Light Operating Mode PWM PWM PWM PSV Description Constant-Frequency PWM Constant-Frequency PWM Constant-Frequency PWM Variable-Frequency, Burst Mode The ADP3020 contains two independent dual-mode, synchronous buck controllers. Traditional constant frequency PWM buck converters suffer from relatively low efficiency under light load conditions. In order to maintain high efficiency over a wide load range, the ADP3020 uses a proprietary dual-mode architecture. At moderate to heavy loads, the buck converter operates in the traditional Pulsewidth Modulation (PWM) mode. At light loads, PSV mode is used to increase system efficiency. A proprietary detection scheme is used for transition from one mode to the other. Input current to the high-side MOSFET is detected when going from PWM mode to PSV mode, and output voltage information is used when changing from PSV mode to PWM mode. When the high-side N-channel MOSFET is turned on, the current going through the N-channel MOSFET is measured as a voltage between CS and SW. If the peak current through the MOSFET is less than 20% of the current limit value set by CLSET, an internal counter that is based on the oscillator frequency will be started. If the current stays below this threshold for 16 PWM cycles, the buck converter will enter power-saving mode. The counter will automatically reset if the peak current is higher than 20% of the current limit value any time prior to when the counter reaches 16. In PSV mode, the buck converter works like a window regulator. If the output voltage drops below the PWM mode nominal output voltage, the high-side MOSFET will be turned on. It will remain on until the output capacitors are charged up to 2% above the PWM mode nominal output voltage. The high-side MOSFET will then be latched off until the output capacitors are discharged to the lower threshold. The discharge rate is dependent on the output capacitor value and load current. It is important to note that the current limit threshold when in PSV mode is approximately 1/4 of the current limit threshold when in PWM mode. If a large load is applied to the converter when in PSV mode (for example, larger than the current limit in PSV mode), the output will continue to drop due to the lower current limit threshold of PSV mode. When the output voltage drops to 2% below the PWM mode nominal voltage, the converter will automatically return to PWM mode. Once in PWM mode, the current limit is quadrupled, and the output will be charged up to the nominal level, as long as the load does not exceed the higher PWM current limit. PWM/PSV Operation (MODE) X = Don’t Care. Forcing the ADP3020 to always remain in constant frequency PWM mode can be used to reduce interference, as this allows filtering of the fixed fundamental frequency and its harmonics. The operating frequency should be carefully chosen so that both the fundamental and harmonic frequencies are not within sensitive audio or IF bands. This is particularly important in noise-sensitive applications such as multimedia systems, cellular phones, computers with built-in RF communications, and PDAs. If two or more switching regulators are used in a system, it is best to synchronize all the switching regulators to a single master regulator or an external clock signal. Internal 5 V Supply (INTVCC) An internal low dropout regulator (LDO) generates a 5 V supply (INTVCC) that powers all of the functional blocks within the IC. The total current rating of this LDO is 50 mA. However, this current is used for supplying gate-drive power, and it is not recommended that current be drawn from this pin for other purposes. Bypass INTVCC to AGND with a 4.7 µF capacitor. A UVLO circuit is also included in the regulator. When INTVCC < 3.8 V, the two switching regulators and the linear regulator controller are shut down. The UVLO hysteresis voltage is about 120 mV. The internal LDO has a built-in fold-back current limit, so that it will be protected if a short circuit is applied to the 5 V output. If AUXVCC is higher than 4.75 V, and both the 5 V and 3.3 V switching regulators are in PSV mode, an internal switch will connect INTVCC to AUXVCC, while simultaneously turning off the internal LDO. AUXVCC can be tied to either the 5 V switching regulator output or a separate 5 V voltage source. By doing this, the power loss across the internal LDO is eliminated, and the total efficiency in PSV mode is improved. When AUXVCC = GND, this automatic power switchover feature will be disabled. Internal Reference (REF) The ADP3020 contains a precision 1.2 V bandgap reference. Bypass REF to AGND with a 1 nF ceramic capacitor. The reference is intended for internal use only. An external voltage buffer is needed if the reference is used for another purpose. Boost High Side Gate Drive Supply (BST) Table I shows the summary of the operating modes of the synchronous buck controllers. The MODE pin determines whether or not the controllers remain in PWM mode under all load conditions. The gate drive voltage for the high-side N-channel MOSFETs is generated by a flying-capacitor boost circuit. The boost capacitor connected between BST and SW is charged from the INTVCC supply. Use only small-signal diodes for the boost circuit. REV. 0 – 10 – ADP3020 Synchronous Rectifier (DRVL) Synchronous rectification is used to reduce conduction losses and to ensure proper start-up of the boost gate driver circuit. Antishoot-through protection has been included to prevent cross conduction during switch transitions. The low side driver must be turned off before the high side driver is turned on. For typical N-channel MOSFETs, the dead time is about 50 ns. On the other edge, a dead time of about 50 ns is achieved by an internal delay circuit. The synchronous rectifier is turned off when the current flowing through the low-side MOSFET falls to zero when in Discontinuous Conduction (DCM) PWM mode and PSV mode. In Continuous Conduction (CCM) PWM mode, the current flowing through the low-side MOSFET never reaches zero, so the synchronous rectifier is turned off by the next clock cycle. Oscillator Frequency and Synchronization (SYNC) coefficient of RDS(ON) of the N-channel MOSFET is canceled by the internal current limit circuitry, so that an accurate current limit value can be obtained over a wide temperature range. In PSV mode, the current limit value is reduced to about 1/4 of the value in PWM mode to reduce the interference noise to other components on the PC board. Output Undervoltage Protection Each switching controller has an undervoltage protection circuit. When the current flowing through the high-side MOSFET reaches the current limit continuously for eight clock cycles, and the output voltage is below 20% of the nominal output voltage, both controllers will be latched off and will not restart until SD or SS3/SS5 is toggled, or until VIN is cycled below 4 V. This feature is disabled during soft start. Output Overvoltage Protection The SYNC pin controls the oscillator frequency. When SYNC = 0 V, fOSC = 200 kHz ; when SYNC = REF, fOSC = 300 kHz; when SYNC = 5 V, fOSC = 400 kHz. 400 kHz operation will minimize external component size and cost while 200 kHz operation provides better efficiency and lower dropout. The SYNC pin can also be used to synchronize the oscillator with an external 5 V clock signal. A low-to-high transition on SYNC initiates a new cycle. Synchronization range is 230 kHz to 600 kHz. Shutdown (SD) Holding SD = GND low will put the ADP3020 into ultralow current shutdown mode. For automatic start-up, SD can be tied directly to VIN. Soft-Start and Power-Up Sequencing (SS) SS3 and SS5 are soft start pins for the two controllers. A 4 µA pull-up current is used to charge an external soft start capacitor. Power-up sequencing can be easily done by choosing different size external capacitors. When SS3/SS5 < 1.2 V, the two switching regulators are turned off. When 1.2 V < SS5/SS3 < 2.6 V, the regulators start working in soft start mode. When SS3/SS5 > 2.6 V, the regulators are in normal operating mode. The controllers are forced to stay in PWM mode during the soft-start period. The minimum soft-start time (~20 µs) is set by an internal capacitor. Table II shows the ADP3020 operating modes. Current Limiting (CLSET) Both converter outputs are continuously monitored for overvoltage. If either output voltage is higher than the nominal output voltage by more than 20%, both converter’s high-side gate drivers (DRVH5/3) will be latched off, and the low-side gate drivers will be latched on, and will not restart until SD or SS5/SS3 are toggled, or until VIN is cycled below 4 V. The low-side gate driver (DRVL) is kept high when the controller is in off-state and the output voltage is less than 93% of the nominal output voltage. Discharging the output capacitors through the main inductor and low-side N-channel MOSFET will cause the output to ring. This will make the output momentarily go below GND. To prevent damage to the circuit, use a reverse-biased 1 A Schottky diode across the output capacitors to clamp the negative surge. Power Good Output (PWRGD) The ADP3020 also provides a PWRGD signal for the microprocessor. During start-up, the PWRGD pin is held low until 5 V output is within –4% of its preset voltage. Then, after a time delay determined by an external timing capacitor connected from CPOR to GND, PWRGD will be actively pulled up to INTVCC by an external pull-up resistor. CPOR can also be used as a manual reset (MR) function. When the 5 V output is lower than the preset voltage by more than 8%, PWRGD is immediately pulled low. Linear Regulator Controller A cycle-by-cycle current limiting scheme is used by monitoring current through the top N-channel MOSFET when it is turned on. By measuring the voltage drop across the high-side MOSFET VDS(ON), the external sense resistor can be deleted. The current limit value can be set by CLSET. When CLSET = Floating, the maximum VDS(ON) = 72 mV at room temperature; when CLSET = 0 V, the maximum VDS(ON) = 144 mV at room temperature. An external resistor can be connected between CLSET and AGND to choose a value between 72 mV and 144 mV. The temperature The ADP3020 includes an onboard linear regulator controller. An external PNP transistor can be used for operation up to 1 A. For higher output current applications, a low threshold PMOS can be used as the pass transistor. The output voltage can be set by a resistor divider. The minimum output voltage of the LDO is 1.25 V, while the maximum output voltage depends on where the LDO input is connected and the dropout voltage of the external pass transistor. Table II. Operating Modes SD Low High High High High High SS5 X SS5 < 1.2 V 1.2 V < SS5 < 2.6 V 2.6 V < SS5 X X SS3 X SS3 < 1.2 V X X 1.2 V < SS3 < 2.6 V 2.6 V < SS3 Mode Shutdown Standby Run Run Run Run Description All Circuits Turned Off 5 V and 3.3 V Off; INTVCC = 5 V, REF = 1.2 V 5 V in Soft Start 5 V in Normal Operation 3.3 V in Soft Start 3.3 V in Normal Operation REV. 0 – 11 – ADP3020 Output Voltage Adjustment Input Voltage Range Fixed output voltages (5 V and 3.3 V) are selected when ADJ/FX5 = ADJ/FX3 = 0 V. The output voltage of each controller can also be set by an external feedback resistor network when ADJ/FX5 = ADJ/FX3 = 5 V as shown in Figure 18. There should be two external feedback resistor dividers for each controller, one for the voltage feedback loop, and one for output voltage monitor. Both resistor dividers need to be identical. The minimum output voltage is 1.25 V. The maximum output voltage is limited only by the minimum supply voltage. Remote output voltage sensing can be done for both fixed and adjustable output voltage modes. The output voltage can be calculated using the following formula:  R1 VOUT = REF × 1 +  R2  (1) The input voltage range of the ADP3020 is 5.5 V to 25 V when 5 V output is desired, and 4.5 V to 25 V when neither switcher output is >4.0 V. This converter design is optimized to deliver the best performance within a 7.5 V to 18 V range, which is the nominal voltage for three to four cell Li-Ion battery stacks. Voltages above 18 V may occur under light loads and when the system is powered from an ac adapter with no battery installed. Maximum Output Current and MOSFET Selection where REF = 1.2 V, and R1/R2 = R3/R4. VIN DRVH VOUT DRVL The maximum output current for each switching regulator is limited by sensing the voltage drop between the drain and source of the high-side MOSFET when it is turned on. A current sense comparator senses voltage drop between CS5 and SW5 for the 5 V converter and between CS3 and SW3 for the 3.3 V converter. The sense comparator threshold is 72 mV when the programming pin, CLSET, is floating, and is 144 mV when CLSET is connected to ground. Current-limiting is based on sensing the peak current. Peak current varies with input voltage and depends on the inductor value. The higher the ripple current or input voltage, the lower the converter maximum output current at the set current sense amplifier threshold. The relation between peak and dc output current is given by:  VIN( MAX ) – VOUT  I PEAK = IOUT + VOUT ×    2 × f × L × VIN( MAX )  (2) ADP3020 R3 FB R4 EAN 5V ADJ/FX R2 R1 At a given current comparator threshold VTH and MOSFET RDS(ON), the maximum inductor peak current is: I PEAK = VTH RDS(ON ) (3) Rearranging Equation 2 to solve for IOUT(MAX) gives: Figure 18. Adjustable Output Mode IOUT( MAX ) = If the loop is carefully compensated, R3 and R4 can be, removed, and FB and EAN can be tied together. APPLICATION INFORMATION  VIN( MAX ) – VOUT  VTH – VOUT ×   (4) RDS(ON )  2 × f × L × VIN( MAX )  A typical notebook PC application circuit using the ADP3020 is shown in Figure 19. Although the component values given in Figure 19 are based on a 5 V @ 4 A /3.3 V @ 4 A/2.5 V @ 1.5 A design, the ADP3020 output drivers are capable of handling output currents anywhere from