ADP3025JRU-REEL

High Efficiency Dual Output Power Supply Controller ADP3025 GENERAL DESCRIPTION Wide input voltage range: 5.5 V to 25 V High conversion efficiency > 96% Integrated current sense—no external resistor required Low shutdown current: 19 µA (typical) Voltage mode PWM with input feed-forward for fast line transient response Dual synchronous buck controllers Built-in gate drive boost circuit for driving external high-side N-channel MOSFET 2 independently programmable output voltages: Fixed 3.3 V or adjustable (800 mV to 6.0 V) Fixed 5 V or adjustable (800 mV to 6.0 V) Programmable PWM frequency Integrated linear regulator controller Extensive circuit protection functions The ADP3025 is a highly efficient, dual synchronous buck switching regulator controller optimized for converting a battery or adapter input into the supply voltage required in portable products and industrial systems. The oscillator frequency can be programmed for 200 kHz or 300 kHz operation, or can be synchronized to an external clock signal of up to 350 kHz. TE FEATURES LE The ADP3025 provides accurate and reliable short-circuit protection by using an internal current sense circuit that reduces cost and increases overall efficiency. Other protection features include programmable soft start, UVLO, and integrated output undervoltage/overvoltage protection. The ADP3025 contains a linear regulator controller designed to drive an external N-channel MOSFET. The linear regulator output is adjustable and can be used to generate auxiliary supply voltages. APPLICATIONS The ADP3025 is specified over the 0°C to 70°C commercial temperature range and is available in a 38-lead TSSOP package. Portable instruments General-purpose dc-to-dc converters B SO SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM VIN 5.5V TO 25V PFO 800mV 5V LINEAR REGULATOR REF Q1 Q3 L2 5V Q4 O L1 3.3V SWITCHING CONTROLLER 5V SWITCHING CONTROLLER 3.3V Q2 SS3 SS5 Q5 POWER-ON RESET ADP3025 2.5V 02699-0-001 PWRGD LINEAR CONTROLLER Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. ADP3025 TABLE OF CONTENTS Output Voltage Adjustment ...................................................... 13 Absolute Maximum Ratings............................................................ 5 Application Information ........................................................... 13 ESD Caution.................................................................................. 5 Input Voltage Range ................................................................... 13 Pin Configuration and Function Descriptions............................. 6 Maximum Output Current and MOSFET Selection ............. 14 Typical Performance Characteristics ............................................. 9 Nominal Inductor Value............................................................ 15 Theory of Operation ...................................................................... 11 Inductor Selection ...................................................................... 15 Internal 5 V Supply (INTVCC) ................................................ 11 CIN and COUT Selection ............................................................... 16 Reference (REF).......................................................................... 11 Power MOSFET Selection......................................................... 16 Boosted High-Side Gate Drive Supply (BST) ......................... 11 Soft Start ...................................................................................... 17 Synchronous Rectifier (DRVL) ................................................ 11 Fixed or Adjustable Output Voltage......................................... 17 Oscillator Frequency and Synchronization (SYNC).............. 11 Efficiency Enhancement............................................................ 17 LE TE Specifications..................................................................................... 3 Transient Response Considerations......................................... 18 Soft Start and Power-Up Sequencing (SS) .............................. 11 Feedback Loop Compensation................................................. 18 Current Limiting (CLSET) ........................................................ 12 Compensation Loop Design and Test Method ...................... 19 Output Undervoltage Protection.............................................. 12 Recommended Applications..................................................... 19 B SO Shutdown SD............................................................................... 11 Output Overvoltage and Reverse Voltage Protection............ 12 Layout Considerations............................................................... 19 Power Good Output (PWRGD) ............................................... 12 Outline Dimensions ....................................................................... 21 Linear Regulator Controller...................................................... 12 Ordering Guide .......................................................................... 21 REVISION HISTORY Revision A 4/04—Data Sheet changed from Rev. 0 to Rev. A Page O Change Changes to Features...................................................................... 1 Changes to Specifications ............................................................ 3 Changes to Figures 4 and 5.......................................................... 9 Changes to Theory of Operation section ................................ 11 Changes to Output Voltage Adjustment section .................... 13 Changes to Table 5...................................................................... 13 Changes to Table 6...................................................................... 15 Changes to Table 8...................................................................... 16 Changes to Table 9...................................................................... 17 1/04—Revision 0: Initial Version Rev. A | Page 2 of 24 ADP3025 SPECIFICATIONS1 Table 1. TA = 0°C to 70°C, VIN = 12 V, SS5 = SS3 = INTVCC, INTVCC Load = 0 mA, REF Load = 0 mA, SYNC = 0 V, SD = 5 V, unless otherwise noted OSCILLATOR Frequency Symbol INTVCC VUVLO Min TA = 25°C 5.5 V ≤ VIN ≤ 25 V Full VIN and temperature range INTVCC falling Typ 5.02 1.0 4.8 5.5 V ≤ VIN ≤ 25 V 784 5.5 V ≤ VIN ≤ 25 V, SD= 0 V SS3 = SS5 = COMP2/SD2 = 0 V, SD = 5 V No loads, SS3 = SS5 = COMP2/SD2 = 4 V, FB5 = 810 mV, FB3 = 810 mV, FB2 = 810 mV, ADJ/FX5 = ADJ/FX3 = 5 V SYNC = AGND, 5.5 V ≤ VIN ≤ 25 V SYNC = INTVCC, 5.5 V ≤ VIN ≤ 25 V tF ≤ 200 ns tR ≤ 200 ns SYNC = 5 V 175 250 Max Unit 25 5.15 V V mV/V V 5.2 4.25 270 4.5 V mV 800 816 mV 19 120 1.3 70 200 1.9 µA µA mA 210 300 245 350 kHz kHz 350 0.4 kHz V V µA TE REF IQ B SO O PWRGD Trip Threshold PWRGD Hysteresis CPOR Pull-Up Current ERROR AMPLIFIER DC Gain3 Gain-Bandwidth Product3 Input Leakage Current 5.5 4.95 4.05 fOSC SYNC Input Frequency Range Input Low Voltage3 Input High Voltage3 Input Current POWER GOOD Output Voltage in Regulation Output Voltage out of Regulation Conditions LE Parameter INTERNAL 5 V REGULATOR Input Voltage Range Output Voltage Line Regulation Total Variation VIN Undervoltage Lockout Threshold Voltage Hysteresis REFERENCE Output Voltage2 SUPPLY Shutdown Current Standby Current Quiescent Current 230 2.8 0.5 PWRGD 10 kΩ pull-up to 5 V 10 kΩ pull-up to 5 V, FB5 < 90% of nominal output value FB5 rising; with respect to nominal output FB5 falling; with respect to nominal output CPOR = 1.2 V GBW IEAN ADJ/FX5 = ADJ/FX3 = 5 V Rev. A | Page 3 of 24 4.8 0.4 –6.0 –3.0 –3.7 4 –1 –1.5 V V –0.3 % % µA 200 dB MHz nA 47 10 ADP3025 SPECIFICATIONS (continued) Conditions Min Typ Max Unit FB5 FB3 FB5, FB3 5.5 V ≤ VIN ≤ 25 V, ADJ/FX5 = 0 V 5.5 V ≤ VIN ≤ 25 V, ADJ/FX3 = 0 V 5.5 V ≤ VIN ≤ 25 V, ADJ/FX5 = ADJ/FX3 = 5 V ADJ/FX5 = ADJ/FX3 = 5 V 4.90 3.234 776 5.0 3.3 800 5.10 3.366 824 V V mV 6.0 V 5.5 V = VIN = 25 V, TA = 25°C 5.5 V ≤ VIN ≤ 25 V, TA = 25°C SS3 = SS5 = 3 V 54 240 0.7 0.4 72 300 2.1 0.6 90 360 3.8 0.8 600 94 99 mV mV µA V nA % 40 45 70 70 ns ns 50 50 100 100 ns ns 0.6 V V 824 mV µA V dB ms MHz nA ADJ/FX5 = ADJ/FX3 = 5 V, FB = 800 mV VIN = 5.5 V, SYNC = AGND tR(DRVL) tF(DRVL) CLOAD = 3000 pF, 10% to 90% CLOAD = 3000 pF, 90% to 10% tR(DRVH) tF(DRVH) VIL VIH O FAULT PROTECTION Output Overvoltage Trip Threshold Output Undervoltage Lockout Threshold 1 2 3 0.800 TE SS5, SS3 IFB DMAX CLOAD = 3000 pF, 10% to 90% CLOAD = 3000 pF, 90% to 10% B SO Output Voltage Adjustment Range3 Current Limit Threshold CLSET5 = CLSET3 = Floating CLSET5 = CLSET3 = 0 V Soft Start Current Soft Start Turn-On Threshold Feedback Input Leakage Current Maximum Duty Cycle3 Transition Time (DRVL) Rise Fall Transition Time (DRVH) Rise Fall Logic Input Voltage ADJ/FX3, ADJ/FX5, SD Logic Low Logic High LINEAR REGULATOR CONTROLLER Feedback Threshold COMP2/SD2 Pull-Up Current COMP2/SD2 Threshold DC Gain3 Transconductance gm 3 Gain-Bandwidth Product3 FB2 Input Leakage Current POWER-FAIL COMPARATOR PFI Input Threshold PFI Input Hysteresis PFI Input Current PFO High Voltage PFO Low Voltage Symbol LE Parameter MAIN SMPS CONTROLLERS Fixed 5 V Output Voltage Fixed 3.3 V Output Voltage Adjustable Output Voltage FB2 COMP2/SD2 2.9 776 COMP2/SD2 = 0 V 0.5 COMP2/SD2 = 3 V GBW IFB2 FB2 = 800 mV PFI PFO from high to low 776 IPFI PFOH PFOL 10 kΩ pull-up to 5 V 10 kΩ pull-up to 5 V 4.8 With respect to nominal output With respect to nominal output 115 70 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. The reference’s line regulation error is insignificant. The reference is not supposed to be loaded externally. Guaranteed by design, not tested in production. Rev. A | Page 4 of 24 800 2.8 0.85 62 0.3 20 20 800 14 1.1 824 0.4 mV mV nA V V 125 90 % % 500 120 80 ADP3025 ABSOLUTE MAXIMUM RATINGS 0°C to 70°C 0°C to 150°C –65°C to +150°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. B SO θJA Operating Ambient Temperature Range Junction Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 10 sec) Rating –0.3 V to +27 V ±0.3 V AGND – 0.3 V to +6 V –0.3 V to +32 V –0.3 V to +6 V –0.3 V to +6 V AGND – 0.3 V to VIN –2 V to VIN + 0.3 V AGND – 0.3 V to +27 V –0.3 V to INTVCC + 0.3 V –0.3 V to INTVCC + 0.3 V AGND – 0.3 V to INTVCC + 0.3 V 98°C/W LE Parameter VIN to AGND AGND to PGND INTVCC BST5, BST3 to PGND BST5 to SW5 BST3 to SW3 CS5, CS3 SW3, SW5 to PGND SD DRVL5/3 to PGND DRVH5/3 to SW5/3 All Other Inputs and Outputs TE Table 2. ADP3025 Stress Ratings ESD CAUTION O ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 5 of 24 ADP3025 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CS5 1 38 BST5 FB5 2 37 DRVH5 EAN5 3 36 SW5 EAO5 4 35 DRVL5 ADJ/FX5 5 34 PGND1 SS5 6 33 S D ADP3025 CLSET5 7 32 PGND2 TOP VIEW 31 INTVCC1 (Not to Scale) 30 VIN AGND 9 REF 8 SYNC 12 29 DRVL3 28 SW3 27 DRVH3 TE CLSET3 10 INTVCC2 11 SS3 13 26 BST3 ADJ/FX3 14 25 DRV2 EAO3 15 24 FB2 EAN3 16 23 COMP2/SD2 CS3 18 21 PWRGD 20 PFO LE PFI 19 22 CPOR 02699-0-002 FB3 17 Figure 2. 38-Lead TSSOP Pin Configuration Table 3. Pin Function Descriptions Mnemonic CS5 2 FB5 3 EAN5 4 5 EAO5 ADJ/FX5 6 7 SS5 CLSET5 8 9 10 REF AGND CLSET3 Function Current Sense Input for the Top N-Channel MOSFET of the 5 V Buck Converter. Connect to the drain of the top N-channel MOSFET. Feedback Input for the 5 V Buck Converter. Connect to the output sense point in fixed output mode. Connect to an external resistor divider in adjustable output mode. Inverting Input of the Error Amplifier of the 5 V Buck Converter. Use for external loop compensation only in fixed output mode. In adjustable output mode, connect to the external resistor divider. Error Amplifier Output for the 5 V Buck Converter. TTL Logic Input. When ADJ/FX5 = 0 V, fixed output mode, connect FB5 to the output sense point. When ADJ/FX5 = 5 V, adjustable output mode, connect FB5 to the external resistor divider. Soft Start for the 5 V Buck Converter. Also used as an ON/OFF pin. Current Limit Setting. A resistor can be connected from AGND to CLSET5. A minimum current limit is obtained by leaving it open. A maximum current limit is obtained by connecting it to AGND. 800 mV Reference. Bypass it with a capacitor (22 nF typical) to AGND. REF cannot be loaded externally. Analog Signal Ground. Current Limit Setting. A resistor can be connected from AGND to CLSET3. A minimum current limit is obtained by leaving it open. A maximum current limit is obtained by connecting it to AGND. Linear Regulator Bypass for the Internal 5 V LDO. Bypass this pin with a 4.7 µF capacitor to AGND. Pins 11 and 31 must be connected for proper operation. Oscillator Synchronization and Frequency Select. fOSC = 200 kHz when SYNC = 0 V; select fOSC = 300 kHz, when SYNC = 5 V. The oscillator can be synchronized with an external source through the SYNC pin. Soft Start for the 3.3 V Buck Converter. Also used as an ON/OFF pin. TTL Logic Input. When ADJ/FX3 = 0 V, fixed output mode, connect FB3 to the output sense point. When ADJ/FX3 = 5 V, adjustable output mode, connect FB3 to the external resistor divider. Error Amplifier Output for the 3.3 V Buck Converter. Error Amplifier Inverting Input of the 3.3 V Buck Converter. Use for external loop compensation only in fixed output mode. In adjustable output mode, connect to an external resistor divider. Feedback Input for the 3.3 V Buck Converter. Connect to output sense point in fixed output mode. Connect to an external resistor divider in adjustable output mode. Current Sense Input for the Top N-Channel MOSFET of the 3.3 V Buck Converter. CS3 should be connected to the drain of the N-channel MOSFET. O B SO Pin No. 1 11, 31 INTVCC2, 1 12 SYNC 13 14 SS3 ADJ/FX3 15 16 EAO3 EAN3 17 FB3 18 CS3 Rev. A | Page 6 of 24 ADP3025 PFO 21 PWRGD 22 CPOR 23 COMP2/SD2 24 25 26 27 28 29 30 32, 34 33 FB2 DRV2 BST3 DRVH3 SW3 DRVL3 VIN PGND2, 1 SD 35 36 37 38 DRVL5 SW5 DRVH5 BST5 TE 20 Function Negative Input of a Comparator that can be Used as a Power-Fail Detector. The positive input is connected to the 800 mV reference. There is a 14 mV hysteresis for this comparator. Power Failure Output, Open Drain Output. This pin sinks current when the PFI pin is lower than 800 mV. Otherwise, PFO is floating. Power Good Output. PWRGD goes low with no delay whenever the 5 V output drops 7% below its nominal value. When the 5 V output is within –3% of its nominal value, PWRGD is released after a time delay determined by the timing capacitor on the CPOR pin. Power-On Reset Capacitor. Connect a capacitor between CPOR and AGND to set the delay time for the PWRGD pin. A 1 µA pull-up current is used to charge the capacitor. A manual reset (MR) function can also be achieved by pulling this pin low. Compensation Input for the Linear Regulator Controller. Connect an RC network to GND for stable operation. This pin is also used as an ON/OFF pin of the linear regulator controller. Feedback for the Linear Regulator Controller. NMOS Gate Drive Output for the Linear Regulator Controller. Boost Capacitor Connection for High-Side Driver of the 3.3 V Buck Converter. High-Side Gate Drive for the 3.3 V Buck Converter. Switching Node (Inductor) Connection of the 3.3 V Buck Converter. Low-Side Gate Drive of the 3.3 V Buck Converter. Main Supply Input (5.5 V to 25 V). Power Ground. Pins 32 and 34 must be connected together for proper operation. Shutdown Control Input, Active Low. If SD = 0 V, the chip is in shutdown mode with very low quiescent current. For automatic startup, connect SD to VIN via a resistor. Low-Side Gate Drive for the 5 V Buck Converter. Switching Node (Inductor) Connection for the 5 V Buck Converter. High-Side Gate Drive for the 5 V Buck Converter. Boost Capacitor Connection for the High-Side Driver of the 5 V Buck Converter. LE Mnemonic PFI O B SO Pin No. 19 Rev. A | Page 7 of 24 ADP3025 INPUT PGND VIN 30 ADP3025 + OC 72mV – + CS5 1 – SD 33 INTVCC1 5V +5V LINEAR REG 31 + – 11 INTVCC2 REF AGND 8 CLSET5 7 800mV REF UVLO 9 PFO 20 38 – 19 37 + 0.8V BST5 TE PFI 14mV – + 36 DRVH5 SW5 INTVCC 200kHz/ 300kHz/ OSC SYNC 12 CONTROL LOGIC 35 3.3V CPOR POWERON RESET FB5 1µA 22 DRVL5 PGND1 PGND2 LE 34 PWRGD 21 VOUT5 5V 32 + – + –3mV 2 816mV FB5 – DRV2 25 + 2.5V 800mV B SO – – 24 0.8V – – COMP2/SD2 + ×1 gm + EA 23 + FB2 + SHUTDOWN 792mV 4 EAN5 EAO5 960mV – + 3 800mV 5 ADJ/FX5 0.7µA 640mV – OC – R 1.8V + 2.1µA SS5 6 + – 0.6V DUPLICATE FOR SECOND CONTROLLER Figure 3. Block Diagram (All Switches and Components Shown for Fixed Output Operation) Rev. A | Page 8 of 24 02699-0-003 O S Q ADP3025 TYPICAL PERFORMANCE CHARACTERISTICS 100 190 170 VIN = 15V 80 150 CURRENT (µA) EFFICIENCY (%) VIN = 6.5V 60 40 130 +70°C 110 +25°C 90 0°C 20 1 2 3 4 OUTPUT CURRENT (A) Figure 4. Efficiency vs. 5 V Output Current 5 15 25 20 INPUT VOLTAGE (V) LE 70 60 VIN = 15V 80 0 1 2 3 4 OUTPUT CURRENT (A) 30 20 10 0 02699-0-005 0 B SO 40 40 5 O 25 20 Figure 8. Input Shutdown Current vs. Input Voltage 310 VIN=25V 1600 FREQUENCY (kHz) 305 +70°C 1400 15 INPUT VOLTAGE (V) Figure 5. Efficiency vs. 3.3 V Output Current 1800 10 02699-0-008 60 CURRENT (µA) 50 VIN = 6.5V 20 +25°C 0°C 1200 VIN=12V 300 295 VIN=7.5V 1000 5 10 15 20 INPUT VOLTAGE (V) 25 Figure 6. Input Current vs. Input Voltage 290 0 10 20 30 40 50 60 AMBIENT TEMPERATURE (°C) Figure 9. Oscillator Frequency vs. Temperature Rev. A | Page 9 of 24 70 02699-0-009 VIN=5.5V 02699-0-006 CURRENT (µA) 10 Figure 7. Input Standby Current vs. Input Voltage 100 EFFICIENCY (%) 50 02699-0-007 0 TE 0 02699-0-004 70 ADP3025 CLSET = GND VIN = 5.5V TO 25V 350 300 250 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE (°C) TE 200 02699-0-010 CURRENT LIMIT THRESHOLD (mV) 400 Figure 10. Current Limit Threshold vs. Temperature Figure 13. Load Transient Response—1 A to 3 A 816 LE 808 804 800 788 784 0 10 20 30 40 50 60 AMBIENT TEMPERATURE (°C) 70 02699-0-011 792 B SO 796 Figure 11. Reference Output vs. Temperature Figure 14. Load Transient Response—3 A to 1 A O REFERENCE OUTPUT (mV) 812 Figure 12. Soft Start Sequencing Figure 15. VIN = 7.5 V to 22 V Transient, 2.5 V Output, CH1—Input Voltage, CH2—Output Voltage Rev. A | Page 10 of 24 ADP3025 THEORY OF OPERATION INTERNAL 5 V SUPPLY (INTVCC) REFERENCE (REF) B SO The ADP3025 contains a precision 800 mV reference. Bypass REF to AGND with a 22 nF ceramic capacitor. The reference is intended for internal use only. BOOSTED HIGH-SIDE GATE DRIVE SUPPLY (BST) The gate drive voltage for the high-side N-channel MOSFET is generated by a flying-capacitor boost circuit. The boost capacitor connected between BST and SW is charged from the INTVCC supply. Use only small-signal diodes for the boost circuit. SYNCHRONOUS RECTIFIER (DRVL) Synchronous rectification is used to reduce conduction losses and ensure proper startup of the boost gate driver circuit. Antishoot-through protection has been included to prevent O OSCILLATOR FREQUENCY AND SYNCHRONIZATION (SYNC) The SYNC pin controls the oscillator frequency. When SYNC = 0 V, fOSC = 200 kHz; when SYNC = 5 V, fOSC = 300 kHz. 300 kHz operation minimizes external component size and cost; 200 kHz operation provides better efficiency and lower dropout. The SYNC pin can also be used to synchronize the oscillator with an external 5 V clock signal. A low-to-high transition on SYNC initiates a new cycle. The synchronization range is 230 kHz to 350 kHz. LE An internal low dropout regulator (LDO) generates a 5 V supply (INTVCC) that powers all the functional blocks within the IC. The total current rating of this LDO is 50 mA. However, this current is used for supplying gate drive power; current should not be drawn from this pin for other purposes. Bypass INTVCC to AGND with a 4.7 µF capacitor. A UVLO circuit is also included in the regulator. When INTVCC < 4.05 V, the two switching regulators and the linear regulator controller are shut down. The UVLO hysteresis voltage is about 300 mV. The internal LDO has a built-in foldback current limit so that it is protected if a short circuit is applied to the 5 V output. cross-conduction during switch transitions. The low-side driver must be turned off before the high-side driver is turned on. For typical N-channel MOSFETs, the dead time is approximately 50 ns. On the other edge, a dead time of approximately 50 ns is achieved by an internal delay circuit. In discontinuous conduction mode (DCM), the synchronous rectifier is turned off when the current flowing through the low-side MOSFET falls to zero. In continuous conduction mode (CCM), the current flowing through the low-side MOSFET never reaches zero, so the synchronous rectifier is turned off by the next clock cycle. TE The ADP3025 contains two synchronous step-down buck controllers and a linear regulator controller. The buck controllers in the ADP3025 have the ability to provide either fixed 3.3 V and 5 V outputs or independently adjustable (800 mV to 6.0 V) outputs. Efficiency is improved by eliminating the external current sense resistor, which is the main contributor to loss during high current, low output voltage conditions. SHUTDOWN SD Holding SD low puts the ADP3025 into ultralow current shutdown mode. For automatic startup, SD can be tied to VIN via a resistor. SOFT START AND POWER-UP SEQUENCING (SS) SS3 and SS5 are soft start pins for the two controllers. A 2 µA pull-up current is used to charge an external soft start capacitor. Power-up sequencing can easily be done by choosing different capacitance. When SS3/SS5 < 0.6 V, the two switching regulators are turned off. When 0.6 V < SS5/SS3 < 1.8 V, the regulators start working in soft start mode. When SS3/SS5 > 1.8 V, the regulators are in normal operating mode. The minimum soft start time (~20 µs) is set by an internal capacitor. Table 4 shows the ADP3025 operating modes. Table 4. Operating Modes SD Low High High High High High SS5 SS3 SS5 < 0.6 V 0.6 V < SS5 < 1.8 V 1.8 V < SS5 SS3 < 0.6 V 0.6 V < SS3 < 1.8 V 1.8 V < SS3 Description All Circuits Turned Off 5 V and 3.3 V Off; INTVCC = 5 V, REF = 800 mV 5 V in Soft Start 5 V in Normal Operation 3.3 V in Soft Start 3.3 V in Normal Operation Rev. A | Page 11 of 24 ADP3025 CURRENT LIMITING (CLSET) POWER GOOD OUTPUT (PWRGD) A cycle-by-cycle current limiting scheme is used by monitoring current through the top N-channel MOSFET when it is turned on. By measuring the voltage drop across the high-side MOSFET, VDS(ON), the use of an external sense resistor can be omitted. The current limit value can be set by CLSET. When CLSET is floating, the maximum VDS(ON) = 72 mV at room temperature; when CLSET = 0 V, the maximum VDS(ON) = 300 mV at room temperature. An external resistor can be connected between CLSET and AGND to choose a value between 72 mV and 300 mV. The relationship between the external resistance and the maximum VDS(ON) is The ADP3025 also provides a PWRGD signal output. During startup, the PWRGD pin is held low until the 5 V output is within –3% of its preset voltage. Then, after a time delay determined by an external timing capacitor connected from CPOR to GND, PWRGD is actively pulled up to INTVCC by an external pull-up resistor. This delay can be calculated by (110 kΩ + REXT ) (26 kΩ + REXT ) (1) (2) CPOR can also be used as a manual reset (MR) input. When the 5 V output is lower than the preset voltage by more than 7%, PWRGD is immediately pulled low. LE The ADP3025 includes an on-board linear regulator controller. An external NMOS can be used as the pass transistor. The output voltage can be set by a resistor divider. The minimum output voltage of the LDO is 800 mV, while the maximum output voltage cannot exceed a voltage level determined by the IC’s INTVCC voltage minus the threshold voltage of the external N-type MOSFET device. Assuming a INTVCC of 5 V, the recom-mended maximum output voltage is around 2.5 V. To ensure loop stability, a compensation network can be attached to the COMP2/SD2 pin, as shown in Figure 17. B SO Each switching controller has an undervoltage protection circuit. When the current flowing through the high-side MOSFET reaches the current limit continuously for eight clock cycles and the output voltage stays below 20% of the nominal output voltage, both controllers are latched off and do not restart until SD or SS3/SS5 is toggled, or until VIN is cycled below 4.05 V. This feature is disabled during soft start. OUTPUT OVERVOLTAGE AND REVERSE VOLTAGE PROTECTION Both converter outputs are continuously monitored for overvoltage. If either output voltage is higher than the nominal output voltage by more than 20%, both converters’ high-side gate drivers (DRVH5/3) are latched off, and the low-side gate drivers are latched on. The chip will not restart until SD or SS5/SS3 is toggled, or until VIN is cycled below 4.05 V. The lowside gate driver (DRVL) is kept high when the controller is in the off-state and the output voltage is less than 93% of the nominal output voltage. Discharging the output capacitors through the main inductor and low-side N-channel MOSFET causes the output to ring. This makes the output go below GND momentarily. To prevent damage to the circuit, use a 1 A Schottky diode in parallel with the output capacitors to clamp the negative surge. O 1 μA LINEAR REGULATOR CONTROLLER The temperature coefficient of RDS(ON) of the N-channel MOSFET is canceled by the internal current limit circuitry, so an accurate current limit value can be obtained over a wide temperature range. OUTPUT UNDERVOLTAGE PROTECTION 1.2 V × CCPOR TE VDS (ON ) MAX = 72 mV tD = Large signal response limits the maximum/minimum load ratio. When the linear regulator is loaded, the MOSFET’s gate source voltage is at its threshold level and changes only slightly. The loop response speed depends on the loop transfer function, which is fast enough for most applications. However, when the load is extremely light, the gate source voltage of the MOSFET is much lower than its nominal value. If at this moment the load increases suddenly, the MOSFET’s gate source capacitance needs to be charged up, which takes time. To optimize large signal response, not exceeding a maximum-to-minimum load ratio of 100 to 1 is recommended. Rev. A | Page 12 of 24 ADP3025 OUTPUT VOLTAGE ADJUSTMENT APPLICATION INFORMATION Fixed output voltages (5 V/3.3 V) are selected when ADJ/FX5 = ADJ/FX3 = 0 V. The output voltage of each controller can also be set by an external feedback resistor network when ADJ/FX5 = ADJ/FX3 = 5 V, as shown in Figure 16. There should be two external feedback resistor dividers for each controller, one for the voltage feedback loop and one for the output voltage monitor. Both resistor dividers must be identical. The minimum output voltage is 800 mV, and the maximum output voltage is 6.0 V. A typical application circuit using the ADP3025 is shown in Figure 17. Although the component values given in Figure 17 are based on a 5 V @ 4 A/3.3 V @ 4 A/2.5 V @ 1.5 A design, the ADP3025 output drivers are capable of handling output currents anywhere from