PRELIMINARY TECHNICAL DATA
a
High-Efficiency Notebook Computer Power Supply Controller Preliminary Technical Data ADP3026
GENERAL DESCRIPTION
FEATURES Wide Input Voltage Range: 6.5 V to 25 V High Conversion Efficiency > 96% Integrated Integrated Current Sense—No External Resistor Required Low Shutdown Current: 14 A (Typical) ( Typical) Voltage Mode PWM with Input Feed Forward for Fast Line Transient Response Dual Synchronous Buck Controllers with PWM/ Power-Saving Mode Operation Built-In Gate Drive Boost Circuit for Driving External N-Channel MOSFETs Two Fixed Output Voltages: 3.3 V, 5 V PWM Frequency: 300 kHz Extensive Circuit Protection Functions 28-Lead TSSOP Package APPLICATIONS Notebook Computers and PDAs Portable Instruments General Purpose DC-DC Converters
The ADP3026 is a highly efficient dual synchronous buck switching regulator controller optimized for converting the battery or adapter input into the system supply voltages required in notebook computers. The ADP3026 uses a dual-mode PWM/Power Saving Mode architecture to maintain efficiency over a wide load range. The ADP3026 provides accurate and reliable short circuit protection using an internal current sense circuit, which reduces cost and increases overall efficiency. Other protection features include programmable soft-start, UVLO, and integrated output undervoltage/overvoltage protection.
FUNCTIONAL BLOCK DIAGRAM
V IN 6.5V TO 25V
ADP3026
5V LINEAR
REF Q1 L1 5V SMPS 3.3V SMPS Q2 3.3V
Q3 L2 5V Q4
SS5
SS3
PWRGD
POWER-ON RESET
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3/12/02
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
PRELIMINARY TECHNICAL DATA
ADP3026–SPECIFICATIONS (@ T = –40 C to +85 C, VIN = 12 V, SS5 = SS3 = INTVCC, INTVCC Load = 0 mA, REF Load = 0 mA, SD = 5 V, unless otherwise noted.)
A
Parameter INTERNAL 5 V REGULATOR Input Voltage Range 5 V Voltage Line Regulation Total Variation Undervoltage Lockout Threshold Voltage Undervoltage Lockout Hysteresis REFERENCE Output Voltage2 SUPPLY CURRENT Shutdown Current Standby Current Quiescent Current (Power-Saving Mode) OSCILLATOR Frequency POWER GOOD Output Voltage In Regulation Output Voltage Out of Regulation
Symbol INTVCC
Conditions
Min 6.5 4.95 4.8 4.2
Typ
Max 25 5.15 5.2 4.5
Unit V V mV/V V V mV
TA = 25°C 6.5 V ≤ VIN ≤ 25 V Line, Temp INTVCC Falling
5.025 0.3 4.4 300
REF IQ
6.5 V ≤ VIN ≤ 25 V SD = 0 V SS3 = SS5 = 0 V SD = 5 V No Loads SS3 = SS5 = 5 V FB5 = 5.05 V, FB3 = 3.33 V 6.5 V ≤ VIN ≤ 25 V 10 kΩ Pull-Up to 5 V 10 kΩ Pull-Up to 5 V FB5 < 90% of Nominal Output Value FB5 Rising FB5 Falling CPOR = 1.2 V
792
800 14 100 400
808 20 200
V µA µA µA
fOSC PWRGD
264 4.8
300
336
kHz V V
0.4
PWRGD Trip Threshold PWRGD Hysteresis CPOR Pull-Up Current ERROR AMPLIFIER DC Gain Gain-Bandwidth Product MAIN SMPS CONTROLLERS Fixed 5 V Output Voltage PWM Mode Power-Saving Mode Fixed 3.3 V Output Voltage PWM Mode Power-Saving Mode Current Limit Threshold (PWM Mode) CLSET5 = CLSET3 = Floating CLSET5 = CLSET3 = 0 V Current Limit Threshold (Power-Saving Mode) CLSET5 = CLSET3 = Floating CLSET5 = CLSET3 = 0 V
–7
–3 4 1 67 10
–2
% % µA dB MHz
GBW FB5 6.5 V ≤ VIN ≤ 25 V 6.5 V ≤ VIN ≤ 25 V FB3 6.5 V ≤ VIN ≤ 25 V 6.5 V ≤ VIN ≤ 25 V 6.5 V ≤ VIN ≤ 25 V, TA = 25°C 6.5 V ≤ VIN ≤ 25 V, TA = 25°C 6.5 V ≤ VIN ≤ 25 V, TA = 25°C 6.5 V ≤ VIN ≤ 25 V, TA = 25°C 3.234 3.250 54 240 4.90 4.925
5.0 5.025 3.3 3.316 72 300
5.10 5.125 3.366 3.382 90 360
V V V V mV mV
16 70
mV mV
– 2–
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PRELIMINARY TECHNICAL DATA ADP3026
Parameter Power-Saving Mode Trip Threshold Soft-Start Current Soft-Start Turn-On Threshold Transition Time (DRVL) Rise Fall Transition Time (DRVH) Rise Fall Logic Input Low Voltage Logic Input High Voltage FAULT PROTECTION Output Overvoltage Trip Threshold Output Undervoltage Lockout Threshold Symbol Conditions CLSET5 = CLSET3 = 0 V, TA = 25°C SS3 = SS5 = 3 V SS5, SS3 tR(DRVL) tF(DRVL) CLOAD = 3000 pF, 10%–90% CLOAD = 3000 pF, 90%–10% 0.4 Min Typ 60 2.5 0.6 40 40 50 50 2.4 115 75 120 80 125 85 Max Unit mV µA V ns ns ns ns V V % %
0.8 70 70 100 100 0.6
tR(DRVH) CLOAD = 3000 pF, 10%–90% tF(DRVH) CLOAD = 3000 pF, 90%–10% SD SD With Respect to Nominal Output With Respect to Nominal Output
NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 The reference’s line-regulation error is insignificant. The reference cannot be used for external load. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA ADP3026
PIN FUNCTION DESCRIPTIONS
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Mnemonic CS5 FB5 EAN5 EAO5 SS5 CLSET5 REF AGND CLSET3 SS3 EAO3 EAN3 FB3 CS3 PWRGD
Function Current Sense Input for top N-Channel MOSFET of the 5 V Buck Converter. Connect to the drain of the top N-channel MOSFET. Feedback Input for the 5 V Buck Converter. Connect to the output sense point in fixed output mode. Inverting Input of the Error Amplifier of the 5 V Buck Converter. Use for external loop compensation . Error Amplifier Output for the 5 V Buck Converter. Soft Start for the 5 V Buck Converter. Also used as an ON/OFF Pin. Current Limit Setting. A resistor can be connected from AGND to CLSET5. A minimum current limit is obtained by leaving it unconnected. A max current limit is obtained by connecting it to AGND. 800 mV Bandgap Reference. Bypass it with a capacitor (22 nF typical) to AGND. REF cannot be used directly with an external load. Analog Signal Ground. Current Limit Setting. A resistor can be connected from AGND to CLSET3. A minimum current limit is obtained by leaving it unconnected. A max current limit is obtained by connecting it to AGND. Soft Start for the 3.3 V Buck Converter. Also used as an ON/OFF Pin Error Amplifier Output for the 3.3 V Buck Converter. Error Amplifier Inverting Input of the 3.3 V Buck Converter. Use for external loop compensation. Feedback Input for the 3.3 V Buck Converter. Connect to output sense point. Current Sense Input for Top N-Channel MOSFET of the 3.3 V Buck Converter. It should be connected to the drain of the N-channel MOSFET. Power Good Output. PWRGD goes low with no delay, whenever the 5 V output drops 7% below its nominal value. When the 5 V output is within –3% of its nominal value, PWRGD will be released after a time delay determined by the timing capacitor on the CPOR pin. Connect a capacitor between CPOR and AGND to set the delay time for the PWRGD pin. A 1 µA pull-up current is used to charge the capacitor. A manual reset (MR) function can also be implemented by grounding this pin. Boost Capacitor Connection for High-Side Gate Driver of the 3.3 V Buck Converter. High-Side Gate Driver for 3.3 V Buck Converter. Switching Node (Inductor) Connection of the 3.3 V Buck Converter. Low-Side Gate Driver of 3.3 V Buck Converter. Main Supply Input (6.5 V to 25 V). Linear Regulator Bypass for the internal 5 V LDO. Bypass this pin with a 4.7 µF capacitor to AGND. Shutdown Control Input, Active Low. If SD = 0 V, the chip is in shutdown with very low quiescent current. For automatic start-up, connect SD to VIN directly. Power Ground. Low-Side Driver for 5 V Buck Converter. Switching Node (Inductor) Connection for 5 V Buck Converter. High-Side Gate Driver for 5 V Buck Converter. Boost Capacitor Connection for High-Side Gate Driver of the 5 V Buck Converter.
16
CPOR
17 18 19 20 21 22 23 24 25 26 27 28
BST3 DRVH3 SW3 DRVL3 VIN INTVCC SD PGND DRVL5 SW5 DRVH5 BST5
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PRELIMINARY TECHNICAL DATA ADP3026
ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION
CS5 1 FB5 2 EAN5 EAO5 3 4 28 BST5 27 DRVH5
VIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +27 V AGND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V INTVCC . . . . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to +6 V BST5, BST3 to PGND . . . . . . . . . . . . . . . . . –0.3 V to +32 V BST5 to SW5 . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V BST3 to SW3 . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V CS5, CS3 . . . . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to VIN SW3, SW5 to PGND . . . . . . . . . . . . . . . . –2 V to VIN + 2 V SD . . . . . . . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to +27 V DRVL5/3 to PGND . . . . . . . . –0.3 V to (INTVCC + 0.3 V) DRVH5/3 to SW5/3 . . . . . . . . –0.3 V to (INTVCC + 0.3 V) All Other Inputs and Outputs . . . . . . . . . . . . . . . . . . AGND – 0.3 V to INTVCC + 0.3 V θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98°C/W Operating Ambient Temperature Range . . . . –40°C to +85°C Junction Temperature Range . . . . . . . . . . . . –40°C to +150°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
*This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged.
ADP3026
TOP VIEW (Not to Scale)
26 SW5 25 24 23 22 DRVL5 PGND SD INTVCC
SS5 5 CLSET5 REF 6 7
AGND 8 CLSET3 9 SS3 10 EAO3 11 EAN3 12
21 VIN 20 19 18 DRVL3 SW3 DRVH3
17 BST3 16 CPOR 15 PWRGD
FB3 13 CS3 14
ORDERING GUIDE
Model ADP3026ARU
Temperature Range –40°C to +85°C
Package Description Thin Shrink Small Outline
Package Option RU-28
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this device features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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–5–
PRELIMINARY TECHNICAL DATA ADP3026
INPUT
ADP3026
VIN 72mV +
+
1
CS5
SD INTVCC 5V +5V LINEAR REG 14mV + + CLSET5 REF 800mV AGND BST5 DRVH5 SW5 INTVCC 300kHz OSC PWRGD CONTROL LOGIC FB5 ›3mV CPOR 1A + +2% 816mV FB5 DRVL5 PGND VOUT5 5V 800mV REF
ULVO
POWER› ON RESET
+ 800mV 0%
+ ›2% 784mV EAN5 + + + ON5 0.6V EA 800mV EAO5 SHUTDOWN + +20% 960mV
+ ›20% S Q R OC
640mV
1.8V 2.5 A
SS5
DUPLICATE FOR SECOND CONTROLLER
Figure 1. Block Diagram
–6–
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PRELIMINARY TECHNICAL DATA Typical Performance Characteristics– ADP3026
300 100 VIN = 7V +25 C 90 250 VIN = 15V
CURRENT – A
+85 C
–40 C
EFFICIENCY › %
80
200
70 150 60 100 5 50 0.01 0.1 1 OUTPUT CURRENT › A 10 10 15 INPUT VOLTAGE – V 20 25
TPC 4. Input Standby Current vs. Input Voltage
TPC 1. Efficiency vs. 5 V Output Current
10
100 VIN = 7V 90 VIN = 15V
9 8 +85 C 7
CURRENT – A
+25 C 6 5 –40 C 4 3 2
EFFICIENCY › %
80
70
60
1 0 5
0.1 1 OUTPUT CURRENT › A 10
50 0.01
10
15 INPUT VOLTAGE – V
20
25
TPC 5. Input Shutdown Current vs. Input Voltage
TPC 2. Efficiency vs. 3.3 V Output Current
900
315
800 +85 C 700 +25 C –40 C 600
SYNC = REF 310
FREQUENCY › kHz
CURRENT – A
VIN = 25 305 VIN = 12
300 VIN = 7.5
500
295
VIN = 5.5
400
5
10
15 INPUT VOLTAGE – V
20
25
290 ›40
›10 20 50 AMBIENT TEMPERATURE › C
80
TPC 3. PSV Mode Input Current vs. Input Voltage
TPC 6. PWM Mode Oscillator Frequency vs. Temperature
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PRELIMINARY TECHNICAL DATA ADP3026
250
STOP
CURRENT LIMIT THRESHOLD › mV CLSET = GND 200
[
T
]
CH1 = 5V OUTPUT
150 VIN = 6.5V TO 25V
100
50
0 ›40 ›30 ›20 ›10
CH2 = I OUT = 10mA TO 3A
0 10 20 30 40 50 AMBIENT TEMPERATURE › C 60 70 80
CH1 200mV
CH2
2.00V
M 200 s
CH2
1.88V
TPC 7.Current Limit Threshold vs. Temperature
TPC 10. Power-Saving Mode, Transient Response
1.210
STOP
1.205 REFERENCE OUTPUT › V
[
T
]
1.200
CH1 = 5V OUTPUT (IOUT = 20mA)
1.195
1.190 VIN = 6.5V TO 25V 1.185
CH2 = SW5
1.180 ›40 ›30 ›20 ›10
0 10 20 30 40 50 AMBIENT TEMPERATURE › C
60
70
80
CH1 200mV
CH2
5.00V
M 400 s
CH2
1.90V
TPC 8. Reference Output vs. Temperature
TPC 11. Power-Saving Mode, Waveforms
TEK STOP: SINGLE SEQ 250 S/s [T
]
STOP
[
T
]
CH1 = 3.3V OUTPUT
CH1 = 5V OUTPUT
CH2 = 2.5V OUTPUT
CH3 = SS3
CH2 = I OUT = 10mA TO 3A
VIN = 12V CH4 = SS5 CH1 CH3 2.00V 1.00V CH2 CH4 1.00V 1.00V M 200MS CH4 740mV
CH1 200mV
CH2
2.00V
M 200 s
CH2
1.88V
TPC 12. PWM Mode, Transient Response TPC 9. Soft-Start Sequencing
–8–
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PRELIMINARY TECHNICAL DATA ADP3026
TEK STOP: SINGLE SEQ 250 S/s [T ]
CH1
CH2
CH1
10.0V
CH2
200mV
M 5.00ms CH1
10.8V
TPC 13. VIN = 7.5 V to 22 V Transient, 5 V Output, CH1 – Input Voltage, CH2 – Output Voltage
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–9–
PRELIMINARY TECHNICAL DATA ADP3026
THEORY OF OPERATION
The ADP3026 is a dual-mode, step-down power supply controller for notebook computers or similar battery-powered applications. The device contains two synchronous stepdown buck controllers and a linear regulator controller. The buck controllers in the ADP3026 have the ability to provide fixed 3.3 V and 5 V outputs. High efficiency over a broad load range is achieved by using a proprietary dual-mode PWM/power-saving (PSV) mode architecture. Efficiency is further improved by deleting the external current sense resistor, which is the main contributor to loss during high current, low output voltage conditions.
CIRCUIT DESCRIPTION Dual-Mode Architecture
level, as long as the load does not exceed the higher PWM current limit.
PWM/PSV Operation
Table I shows the summary of the operating modes of the synchronous buck controllers.
Table I. PWM Mode and PSV Mode
Load Current Heavy Moderate Light
Operating Mode PWM PWM PSV
Description Constant-Frequency PWM Constant-Frequency PWM Variable-Frequency, Burst Mode
The ADP3026 contains two independent dual-mode, synchronous buck controllers. Traditional constant frequency PWM buck converters suffer from relatively low efficiency under light load conditions. In order to maintain high efficiency over a wide load range, the ADP3026 use a proprietary dual-mode architecture. At moderate to heavy loads, the buck converter operates in the traditional Pulsewidth Modulation (PWM) mode. At light loads, PSV mode is used to increase system efficiency. A proprietary detection scheme is used for transition from one mode to the other. Input current to the high-side MOSFET is detected when going from PWM mode to PSV mode, and output voltage information is used when changing from PSV mode to PWM mode. When the high-side N-channel MOSFET is turned on, the current going through the N-channel MOSFET is measured as a voltage between CS and SW. If the peak current through the MOSFET is less than 20% of the current limit value set by CLSET, an internal counter that is based on the oscillator frequency will be started. If the current stays below this threshold for 16 PWM cycles, the buck converter will enter power-saving mode. The counter will automatically reset if the peak current is higher than 20% of the current limit value any time prior to when the counter reaches 16. In PSV mode, the buck converter works like a window regulator. If the output voltage drops below the PWM mode nominal output voltage, the high-side MOSFET will be turned on. It will remain on until the output capacitors are charged up to 2% above the PWM mode nominal output voltage. The high-side MOSFET will then be latched off until the output capacitors are discharged to the lower threshold. The discharge rate is dependent on the output capacitor value and load current. It is important to note that the current limit threshold when in PSV mode is approximately 1/4 of the current limit threshold when in PWM mode. If a large load is applied to the converter when in PSV mode (for example, larger than the current limit in PSV mode), the output will continue to drop due to the lower current limit threshold of PSV mode. When the output voltage drops to 2% below the PWM mode nominal voltage, the converter will automatically return to PWM mode. Once in PWM mode, the current limit is quadrupled, and the output will be charged up to the nominal
Internal 5 V Supply (INTVCC) An internal low dropout regulator (LDO) generates a 5 V supply (INTVCC) that powers all of the functional blocks within the IC. The total current rating of this LDO is 50 mA. However, this current is used for supplying gate-drive power, and it is not recommended that current be drawn from this pin for other purposes. Bypass INTVCC to AGND with a 4.7 µF capacitor. A UVLO circuit is also included in the regulator. When INTVCC < 3.8 V, the two switching regulators, and the linear regulator controller are shut down. The UVLO hysteresis voltage is about 120 mV. The internal LDO has a built-in fold-back current limit, so that it will be protected if a short circuit is applied to the 5 V output.
Reference (REF)
The ADP3026 contains a precision 800 mV bandgap reference. Bypass REF to AGND with a 22 nF ceramic capacitor. The reference is intended for internal use only.
Boost High-Side Gate Drive Supply (BST)
The gate drive voltage for the high-side N-channel MOSFET is generated by a flying-capacitor boost circuit. The boost capacitor connected between BST and SW is charged from the INTVCC supply. Use only small-signal diodes for the boost circuit.
Synchronous Rectifier (DRVL)
Synchronous rectification is used to reduce conduction losses and to ensure proper start-up of the boost gate driver circuit. Antishoot-through protection has been included to prevent cross conduction during switch transitions. The low-side driver must be turned off before the high-side driver is turned on. For typical N-channel MOSFETs, the dead time is about 50 ns. On the other edge, a dead time of about 50 ns is achieved by an internal delay circuit. The synchronous rectifier is turned off when the current flowing through the low-side MOSFET falls to zero when in Discontinuous Conduction (DCM) PWM mode and PSV mode. In Continuous Conduction (CCM) PWM mode, the current flowing through the low-side MOSFET never reaches zero, so the synchronous rectifier is turned off by the next clock cycle.
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PRELIMINARY TECHNICAL DATA ADP3026
Shutdown (SD)
Holding SD = GND low will put the ADP3026 into ultralow current shutdown mode. For automatic start-up, SD can be tied directly to VIN.
Soft-Start and Power-Up Sequencing (SS)
clock cycles, and the output voltage is below 20% of the nominal output voltage, both controllers will be latched off and will not restart until SD or SS3/SS5 is toggled, or until VIN is cycled below 4 V. This feature is disabled during soft start.
Output Overvoltage Protection
SS3 and SS5 are soft-start pins for the two controllers. A 2.5 µA pull-up current is used to charge an external softstart capacitor. Power-up sequencing can easily be done by choosing different capacitance. When SS3/SS5 < 0.6 V, the two switching regulators are turned off. When 0.6 V < SS5/ SS3 < 1.8 V, the regulators start working in soft-start mode. When SS3/SS5 > 1.8 V, the regulators are in normal operating mode. The controllers are forced to stay in PWM mode during the soft-start period. The minimum soft-start time (~20 µs) is set by an internal capacitor. Table II shows the ADP3026 operating modes.
Current Limiting (CLSET)
A cycle-by-cycle current limiting scheme is used by monitoring current through the top N-channel MOSFET when it is turned on. By measuring the voltage drop across the high-side MOSFET VDS(ON), the external sense resistor can be deleted. The current limit value can be set by CLSET. When CLSET = Floating, the maximum VDS(ON) = 72 mV at room temperature; when CLSET = 0 V, the maximum VDS(ON) = 300 mV at room temperature. An external resistor can be connected between CLSET and AGND to choose a value between 72 mV and 300 mV. The relationship between the external resistance and the maximum VDS(ON) is:
Both converter outputs are continuously monitored for overvoltage. If either output voltage is higher than the nominal output voltage by more than 20%, both converter’s high-side gate drivers (DRVH5/3) will be latched off, and the lowside gate drivers will be latched on, and will not restart until SD or SS5/SS3 are toggled, or until VIN is cycled below 4 V. The low-side gate driver (DRVL) is kept high when the controller is in off-state and the output voltage is less than 93% of the nominal output voltage. Discharging the output capacitors through the main inductor and low-side N-channel MOSFET will cause the output to ring. This will make the output momentarily go below GND. To prevent damage to the circuit, use a reverse-biased 1 A Schottky diode across the output capacitors to clamp the negative surge.
Power Good Output (PWRGD)
VDS(ON )MAX = 72 mV
(110K + REXT ) (26K + REXT )
The ADP3026 also provides a PWRGD signal for the microprocessor. During start-up, the PWRGD pin is held low until 5 V output is within –3% of its preset voltage. Then, after a time delay determined by an external timing capacitor connected from CPOR to GND, PWRGD will be actively pulled up to INTVCC by an external pull-up resistor. This delay can be calcualated by:
(1)
Td =
1.2V × CCPOR 1µA
(2)
The temperature coefficient of RDS(ON) of the N-channel MOSFET is canceled by the internal current limit circuitry, so that an accurate current limit value can be obtained over a wide temperature range. In PSV mode, the current limit value is reduced to about 1/4 of the value in PWM mode to reduce the interference noise to other components on the PC board.
Output Undervoltage Protection
CPOR can also be used as a manual reset (MR) function. When the 5 V output is lower than the preset voltage by more than 7%, PWRGD is immediately pulled low.
APPLICATION INFORMATION
Each switching controller has an undervoltage protection circuit. When the current flowing through the high-side MOSFET reaches the current limit continuously for eight
A typical notebook PC application circuit using the ADP3026 is shown in Figure 2. Although the component values given in Figure 3 are based on a 5 V @ 4 A /3.3 V @ 4 A design, the ADP3026 output drivers are capable of
Table II. Operating Modes
SD Low High High High High High
SS5 X SS5 < 0.6 V 0.6 V < SS5 < 1.8 V 1.8 V < SS5 X X
SS3 X SS3 < 0.6 V X X 0.6 V < SS3 < 1.8 V 1.8 V < SS3
Mode Shutdown Standby Run Run Run Run
Description All Circuits Turned Off 5 V and 3.3 V Off; INTVCC = 5 V, REF = 0.8 V 5 V in Soft Start 5 V in Normal Operation 3.3 V in Soft Start 3.3 V in Normal Operation
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PRELIMINARY TECHNICAL DATA ADP3026
handling output currents anywhere from
