ADP3118JRZ-RL

Dual Bootstrapped 12 V MOSFET Driver with Output Disable ADP3118 FEATURES GENERAL DESCRIPTION Optimized for low gate charge MOSFETs All-in-one synchronous buck driver Bootstrapped high-side drive One PWM signal generates both drives Anticross-conduction protection circuitry Output disable control turns off both MOSFETs to float output per Intel VRM 10 Meets CPU VR requirement when used with Analog Devices, Inc. Flex-Mode1 controller The ADP3118 is a dual, high voltage MOSFET driver optimized for driving two N-channel MOSFETs, which are the two switches in a nonisolated synchronous buck power converter. Each of the drivers is capable of driving a 3000 pF load with a 25 ns propagation delay and a 25 ns transition time. One of the drivers can be bootstrapped and is designed to handle the high voltage slew rate associated with floating high-side gate drivers. The ADP3118 includes overlapping drive protection to prevent shoot-through current in the external MOSFETs. The OD pin shuts off both the high-side and the low-side MOSFETs to prevent rapid output capacitor discharge during system shutdown. APPLICATIONS Multiphase desktop CPU supplies Single-supply synchronous buck converters The ADP3118 is specified over the commercial temperature range of 0°C to 85°C and is available in 8-lead SOIC and 8-lead LFCSP packages. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM VIN 12V D1 VCC 4 ADP3118 BST 1 CBST2 CBST1 IN 2 DRVH RG 8 Q1 DELAY RBST TO INDUCTOR SW 7 CMP VCC 6 CMP CONTROL LOGIC DRVL Q2 5 PGND DELAY 6 OD 3 05452-001 1V Figure 1. 1 Flex-Mode™ is protected by U.S. Patent 6683441. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved. ADP3118 TABLE OF CONTENTS Features .............................................................................................. 1  Low-Side Driver ............................................................................9  Applications ....................................................................................... 1  High-Side Driver ...........................................................................9  General Description ......................................................................... 1  Overlap Protection Circuit...........................................................9  Simplified Functional Block Diagram ........................................... 1  Application Information ................................................................ 10  Revision History ............................................................................... 2  Supply Capacitor Selection ....................................................... 10  Specifications..................................................................................... 3  Bootstrap Circuit ........................................................................ 10  Absolute Maximum Ratings............................................................ 4  MOSFET Selection ..................................................................... 10  ESD Caution .................................................................................. 4  High-Side (Control) MOSFETs ................................................ 10  Pin Configuration and Function Descriptions ............................. 5  Low-Side (Synchronous) MOSFETs ........................................ 11  Timing Characteristics..................................................................... 6  PC Board Layout Considerations............................................. 11  Typical Performance Characteristics ............................................. 7  Outline Dimensions ....................................................................... 13  Theory of Operation ........................................................................ 9  Ordering Guide .......................................................................... 13  REVISION HISTORY 9/07—Rev. 0 to Rev. A Added LFCSP ...................................................................... Universal Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 13 4/05—Revision 0: Initial Version Rev. A | Page 2 of 16 ADP3118 SPECIFICATIONS VCC = 12 V, BST = 4 V to 26 V, TA = 0°C to 85°C, unless otherwise noted. 1 Table 1. Parameter PWM INPUT Input Voltage High Input Voltage Low Input Current Hysteresis OD INPUT Input Voltage High Input Voltage Low Input Current Hysteresis Propagation Delay Times 2 HIGH-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Output Resistance, Unbiased Transition Times Propagation Delay Times2 SW Pull-Down Resistance LOW-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Output Resistance, Unbiased Transition Times Propagation Delay Times2 Symbol 1 2 Min Typ Max Unit 0.8 +1 V V μA mV 2.0 −1 90 250 2.0 tpdlOD See Figure 3 250 20 35 V V μA mV ns tpdhOD See Figure 3 40 55 ns BST − SW = 12 V BST − SW = 12 V BST − SW = 0 V BST − SW = 12 V, CLOAD = 3 nF, see Figure 4 BST − SW = 12 V, CLOAD = 3 nF, see Figure 4 BST − SW = 12 V, CLOAD = 3 nF, see Figure 4 BST − SW = 12 V, CLOAD = 3 nF, see Figure 4 SW to PGND 2.2 1.0 10 25 20 25 25 10 3.5 2.5 Ω Ω kΩ ns ns ns ns kΩ VCC = PGND CLOAD = 3 nF, see Figure 4 CLOAD = 3 nF, see Figure 4 CLOAD = 3 nF, see Figure 4 CLOAD = 3 nF, see Figure 4 SW = 5 V SW = PGND 2.0 1.0 10 20 16 12 30 190 150 −1 90 trDRVH tfDRVH tpdhDRVH tpdlDRVH trDRVL tfDRVL tpdhDRVL tpdlDRVL Timeout Delay SUPPLY Supply Voltage Range Supply Current UVLO Voltage Hysteresis Conditions VCC ISYS 110 95 0.8 +1 4.15 BST = 12 V, IN = 0 V VCC rising 2 1.5 350 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to the signal going low. Rev. A | Page 3 of 16 40 30 40 35 3.2 2.5 35 30 35 45 13.2 5 3.0 Ω Ω kΩ ns ns ns ns ns ns V mA V mV ADP3118 ABSOLUTE MAXIMUM RATINGS Unless otherwise specified, all voltages are referenced to PGND. Table 2. Parameter VCC BST BST to SW SW DC