ADP3120

Dual Bootstrapped 12 V MOSFET Driver with Output Disable ADP3120 FEATURES All-in-one synchronous buck driver Bootstrapped high-side drive One PWM signal generates both drives Anticross-conduction protection circuitry Output disable control turns off both MOSFETs to float output per Intel® VRM 10 specification GENERAL DESCRIPTION The ADP3120 is a dual, high voltage MOSFET driver optimized for driving two N-channel MOSFETs, the two switches in a nonisolated synchronous buck power converter. Each of the drivers is capable of driving a 3000 pF load with a 45 ns propagation delay and a 25 ns transition time. One of the drivers can be bootstrapped and is designed to handle the high voltage slew rate associated with floating high-side gate drivers. The ADP3120 includes overlapping drive protection to prevent shoot-through current in the external MOSFETs. The OD pin shuts off both the high-side and the low-side MOSFETs to prevent rapid output capacitor discharge during system shutdown. The ADP3120 is specified over the commercial temperature range of 0°C to 85°C and is available in 8-lead SOIC and 8-lead LFCSP packages. APPLICATIONS Multiphase desktop CPU supplies Single-supply synchronous buck converters SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM 12V VCC 4 D1 ADP3120 BST 1 CBST2 CBST1 IN 2 8 DRVH RG Q1 RBST DELAY TO INDUCTOR SW 7 CMP VCC 6 CMP 1V CONTROL LOGIC DRVL 5 Q2 DELAY OD 3 PGND 05591-001 6 Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. ADP3120 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 ESD Caution.................................................................................. 4 Pin Configurations and Function Descriptions ........................... 5 Timing Characteristics..................................................................... 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ........................................................................ 9 Low-Side Driver............................................................................ 9 High-Side Driver .......................................................................... 9 Overlap Protection Circuit.......................................................... 9 Application Information................................................................ 10 Supply Capacitor Selection ....................................................... 10 Bootstrap Circuit........................................................................ 10 MOSFET Selection..................................................................... 10 High-Side (Control) MOSFETs................................................ 10 Low-Side (Synchronous) MOSFETs ........................................ 11 PC Board Layout Considerations............................................. 11 Outline Dimensions ....................................................................... 13 Ordering Guide .......................................................................... 13 REVISION HISTORY 7/05—Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADP3120 SPECIFICATIONS 1 VCC = 12 V, BST = 4 V to 26 V, TA = 0°C to 85°C, unless otherwise noted. Table 1. Parameter PWM INPUT Input Voltage High Input Voltage Low Input Current Hysteresis OD INPUT Input Voltage High Input Voltage Low Input Current Hysteresis Propagation Delay Times 2 HIGH-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Output Resistance, Unbiased Transition Times Propagation Delay Times2 Symbol Conditions Min 2.0 −1 90 2.0 −1 90 tpdhl OD tpdhl OD See Figure 4 See Figure 4 BST − SW = 12 V BST – SW = 12 V BST – SW = 0 V BST – SW = 12 V, CLOAD = 3 nF, see Figure 5 BST – SW = 12 V, CLOAD = 3 nF, see Figure 5 BST – SW = 12 V, CLOAD = 3 nF, 25°C ≤ TA ≤ 85°C, see Figure 5 BST – SW = 12 V, CLOAD = 3 nF, see Figure 5 SW to PGND 0.8 +1 250 20 40 2.2 1.0 10 25 20 45 25 10 2.0 1.0 10 20 16 12 30 190 150 35 55 3.5 2.5 40 30 70 35 0.8 +1 250 Typ Max Unit V V μA mV V V μA mV ns ns Ω Ω kΩ ns ns ns ns kΩ Ω Ω kΩ ns ns ns ns ns ns V mA V mV trDRVH tfDRVH tpdhDRVH tpdlDRVH 32 SW Pull-Down Resistance LOW-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Output Resistance, Unbiased Transition Times Propagation Delay Times2 Timeout Delay SUPPLY Supply Voltage Range Supply Current UVLO Voltage Hysteresis 1 2 3.2 2.5 35 30 35 45 trDRVL tfDRVL tpdhDRVL tpdlDRVL VCC = PGND CLOAD = 3 nF, Figure 5 CLOAD = 3 nF, Figure 5 CLOAD = 3 nF, Figure 5 CLOAD = 3 nF, Figure 5 SW = 5 V SW = PGND 110 95 4.15 VCC ISYS BST = 12 V, IN = 0 V VCC rising 2 1.5 350 13.2 5 3.0 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to it going low. Rev. 0 | Page 3 of 16 ADP3120 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC BST BST to SW SW DC