ADP3309ART-36

a FEATURES 1 .2% Accuracy Over Line and Load Regulations @ +25 C Ultralow Dropout Voltage: 120 mV Typical @ 100 mA Requires Only CO = 0.47 F for Stability anyCAP = Stable with All Types of Capacitors (Including MLCC) Current and Thermal Limiting Low Noise Low Shutdown Current: 1 A 3.0 V to 12 V Supply Range –20 C to +85 C Ambient Temperature Range Several Fixed Voltage Options Ultrasmall SOT-23-5 Package Excellent Line and Load Regulations APPLICATIONS Cellular Telephones Notebook, Palmtop Computers Battery Powered Systems PCMCIA Regulator Bar Code Scanners Camcorders, Cameras anyCAP™ 100 mA Low Dropout Linear Regulator ADP3309 FUNCTIONAL BLOCK DIAGRAM ADP3309 OUT CC R1 IN ERR/NC Q2 SD BANDGAP REF THERMAL PROTECTION DRIVER Q1 GM R2 GND GENERAL DESCRIPTION The ADP3309 is a member of the ADP330x family of precision low dropout anyCAP voltage regulators. It is pin-for-pin and functionally compatible with National’s LP2981, but offers performance advantages. The ADP3309 stands out from conventional LDOs with a novel architecture and an enhanced process. Its patented design requires only a 0.47 µF output capacitor for stability. This device is stable with any type of capacitor regardless of its ESR (Equivalent Series Resistance) value, including ceramic types for space restricted applications. The ADP3309 achieves ± 1.2% accuracy at room temperature and ± 2.2% overall accuracy over temperature, line and load regulations. The dropout voltage of the ADP3309 is only 120 mV (typical) at 100 mA. This device also includes a current limit and a shutdown feature. In shutdown mode, the ground current is reduced to ~1 µA. The ADP3309 operates with a wide input voltage range from 3.0 V to 12 V and delivers a load current in excess of 100 mA. The ADP3309 anyCAP LDO offers a wide range of output voltages. For a 50 mA version, refer to the ADP3308 data sheet. ERR/NC ADP3309-3.3 VIN C1 + 0.47 F – ON OFF SD GND IN OUT + – VOUT = +3.3V C2 0.47 F Figure 1. Typical Application Circuit anyCAP is a trademark of Analog Devices, Inc. R EV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 ADP3309-xx–SPECIFICATIONS otherwise noted.) The following specifications apply to all voltage options. 1 (@TA = –20 C to +85 C, VIN = 7 V, CIN = 0.47 F, COUT = 0.47 F, unless Min Typ Max Parameter OUTPUT VOLTAGE ACCURACY Symbol VOUT Conditions VIN = VOUTNOM + 0.3 V to 12 V IL = 0.1 mA to 100 mA TA = +25°C VIN = VOUTNOM + 0.3 V to 12 V IL = 0.1 mA to 100 mA VIN = VOUTNOM + 0.3 V to 12 V TA = +25°C IL = 0.1 mA to 100 mA TA = +25°C IL = 100 mA IL = 0.1 mA VIN = 2.4 V IL = 0.1 mA VOUT = 98% of VOUTNOM IL = 100 mA IL = 10 mA IL = 1 m A ON OFF 0 < VSD ≤ 5 V 5 < VSD ≤ 12 V @ VIN = 12 V VSD = 0 V, VIN = 12 V TA = +25°C VSD = 0 V, VIN = 12 V TA = +85°C TA = +25°C @ VIN = 12 V TA = +85°C @ VIN = 12 V VEO = 5 V ISINK = 400 µA VIN = VOUTNOM + 1 V, TA = +25°C f = 10 Hz–100 kHz Units –1.2 –2.2 0.02 0.06 0.8 0.19 0.9 0.12 0.025 0.004 2.0 0.75 0.75 +1.2 +2.2 % % mV/V mV/mA LINE REGULATION LOAD REGULATION GROUND CURRENT GROUND CURRENT IN DROPOUT DROPOUT VOLTAGE ∆V O ∆V IN ∆V O ∆ IL IGND IGND VDROP 2.0 0.3 1.7 0.25 0.07 0.015 0.3 1 9 mA mA mA V V V V V µA µA µA µA µA µA µA V mA µV rms SHUTDOWN THRESHOLD SHUTDOWN PIN INPUT CURRENT VTHSD ISDIN GROUND CURRENT IN SHUTDOWN IQ MODE 0.005 0.01 1 3 2 4 13 OUTPUT CURRENT IN SHUTDOWN MODE ERROR PIN OUTPUT LEAKAGE ERROR PIN OUTPUT “LOW” VOLTAGE PEAK LOAD CURRENT OUTPUT NOISE @ 5 V OUTPUT IOSD IEL VEOL ILDPK VNOISE 0.12 150 100 0.3 NOTES 1 Ambient temperature of +85 °C corresponds to a junction temperature of 125 °C under typical full load test conditions. Specifications subject to change without notice. – 2– REV. 0 ADP3309 ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS Input Supply Voltage . . . . . . . . . . . . . . . . . . . –0.3 V to +16 V Shutdown Input Voltage . . . . . . . . . . . . . . . . –0.3 V to +16 V Power Dissipation . . . . . . . . . . . . . . . . . . . . Internally Limited Operating Ambient Temperature Range . . . –55°C to +125°C Operating Junction Temperature Range . . . –55°C to +125°C θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190°C/W θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C *This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. Pin Name 1 2 3 IN GND SD Function Regulator Input. Ground Pin. Active Low Shutdown Pin. Connect to ground to disable the regulator output. When shutdown is not used, this pin should be connected to the input pin. Open Collector. Output that goes low to indicate the output is about to go out of regulation. This pin can be left open. (NC = No Connect). Output of the Regulator, fixed 2.7, 2.85, 2.9, 3.0, 3.3 or 3.6 volts output voltage. Bypass to ground with a 0.47 µF or larger capacitor. PIN CONFIGURATION 4 ERR/NC 5 ORDERING GUIDE OUT Model ADP3309ART-2.7 ADP3309ART-2.85 ADP3309ART-2.9 ADP3309ART-3 ADP3309ART-3.3 ADP3309ART-3.6 Voltage Output 2.7 V 2.85 V 2.9 V 3.0 V 3.3 V 3.6 V Package Option* SOT-23 SOT-23 SOT-23 SOT-23 SOT-23 SOT-23 Marking Code DNC DVC DWC DPC DRC DSC IN GND SD ADP3309 TOP VIEW (Not to Scale) NC = NO CONNECT OUT ERR/NC *SOT = Surface Mount. Contact the factory for the availability of other output voltage options. Other Member of anyCAP Family 1 Model ADP3308 Output Current 50 mA Package Option2 SOT-23-5 Lead NOTES 1 See individual data sheet for detailed ordering information. 2 SOT = Surface Mount. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3309 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 –3– ADP3309–Typical Performance Characteristics 3.302 3.301 I L = 0mA 3.302 1150 VOUT = +3.3V VIN = +7V VOUT = +3.3V 3.301 OUTPUT VOLTAGE – Volts VOUT = +3.3V I L = 0mA OUTPUT VOLTAGE – Volts IL = 10mA 3.300 3.299 3.298 3.297 3.296 IL = 100mA 3.295 3.3 IL = 50mA 3.300 3.299 3.298 3.297 3.296 3.295 GROUND CURRENT – A 900 650 400 160 0 0 10 20 30 40 50 60 70 80 OUTPUT LOAD – mA 90 100 4 5 6 7 8 9 10 11 12 13 14 INPUT VOLTAGE – Volts 0 1.2 2.4 3.6 4.8 6.0 7.2 8.4 9.6 10.8 12.0 INPUT VOLTAGE – Volts Figure 2. Line Regulation: Output Voltage vs. Supply Voltage Figure 3. Output Voltage vs. Load Current Figure 4. Quiescent Current vs. Supply Voltage 900 0.2 1250 VIN = +7V GROUND CURRENT – A IL = 0mA 0.0 IL = 50mA GROUND CURRENT – A OUTPUT VOLTAGE – % 750 0.1 1000 IL = 100mA 600 750 –0.1 450 IL = 0 TO 100mA 300 500 –0.2 IL = 100mA –0.3 –0.4 –45 –25 250 IL = 0mA 150 0 25 50 75 OUTPUT LOAD – mA 100 –5 15 35 55 75 95 115 135 TEMPERATURE – C 0 –25 –5 15 35 55 75 95 TEMPERATURE – C 115 135 Figure 5. Quiescent Current vs. Load Current Figure 6. Output Voltage Variation % vs. Temperature Figure 7. Quiescent Current vs. Temperature 120 INPUT/OUTPUT VOLTAGE – Volts 5 INPUT/OUTPUT VOLTAGE – Volts 8.0 INPUT-OUTPUT VOLTAGE – mV VOUT = +3.3V RL = 33 4 VIN 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 VSD = VIN CL = 0.47 F RL = 33 VOUT = +3.3V 0 20 40 60 80 100 120 140 160 180 200 TIME – s VOUT 96 72 3 48 2 24 1 0 0 25 50 75 OUTPUT LOAD – mA 100 0 0 1 2 3 4 3 2 INPUT VOLTAGE – Volts 1 0 Figure 8. Dropout Voltage vs. Output Current Figure 9. Power-Up/Power-Down Figure 10. Power-Up Overshoot –4– REV. 0 ADP3309 3.320 VOUT = +3.3V 3.310 3.300 3.290 Volts 3.310 3.300 3.290 Volts 3.320 VOUT = +3.3V 3.320 3.310 3.300 3.290 3.280 IOUT 100 VOUT = +3.3V CL = 0.47 F 3.280 RL = 33 CL = 0.47 F Volts 3.280 RL = 3.3k CL = 0.47 F VIN mA VIN 7.5 7.0 7.5 7.0 10 0 40 80 120 160 200 240 280 320 360 400 TIME – s 0 20 40 60 80 100 120 140 160 180 200 TIME – s 0 100 200 300 TIME – s 400 500 Figure 11. Line Transient Response Figure 12. Line Transient Response Figure 13. Load Transient 3.320 3.310 Volts 4 VOUT = +3.3V CL = 4.7 F mA CL = 0.47 F VOUT 300 200 100 Volts 3 3.300 3.290 IOUT 2 CL = 4.7 F 1 +3.3V 0 3.280 IOUT mA µ 4 Volts 100 10 VOUT = +3.3V VOUT 2 0 0 3 0 VOUT = +3.3V RL = 33 VSD +3V 0 100 200 300 TIME – s 400 500 0 0.5 1 1.5 2 2.5 3 3.5 TIME – sec 4 4.5 5 0 20 40 60 TIME – s 80 100 Figure 14. Load Transient Figure 15. Short Circuit Current Figure 16. Turn On VOLTAGE NOISE SPECTRAL DENSITY – V Hz 4 +3.3V 3 2 1 0 3 0 VSD VOUT = +3.3V RL = 33 CL = 0.47 F 0 –10 a. 0.47 F, RL = 33k b. 0.47 F, RL = 33 c. 10 F, RL = 33k d. 10 F, RL = 33 VOUT = +3.3V b 10 RIPPLE REJECTION – dB –20 –30 –40 –50 1 Volts a –60 –70 b d –80 –90 ac 10 100 100k 1k 10k FREQUENCY – Hz c d VOUT = +3.3V, CL = 0.47 F IL = 1mA 0.1 0 10 20 30 TIME – s 40 50 –100 1M 10M 0.01 100 1k 10k FREQUENCY – Hz 100k Figure 17. Turn Off Figure 18. Power Supply Ripple Rejection Figure 19. Output Noise Density REV. 0 –5– ADP3309 THEORY OF OPERATION The ADP3309 anyCAP LDO uses a single control loop for regulation and reference functions. The output voltage is sensed by a resistive voltage divider consisting of R1 and R2, which is varied to provide the available output voltage option. Feedback is taken from this network by way of a series diode (D1) and a second resistor divider (R3 and R4) to the input of an amplifier. INPUT Q1 OUTPUT COMPENSATION ATTENUATION CAPACITOR (VBANDGAP/VOUT) NONINVERTING WIDEBAND DRIVER GM PTAT VOS R4 R3 D1 (a) R2 R1 RLOAD Additional features of the circuit include current limit and thermal shutdown. Compared to the standard solutions that give warning after the output has lost regulation, the ADP3309 provides improved system performance by enabling the ERR pin to give warning before the device loses regulation. As the chip’s temperature rises above 165°C, the circuit activates a soft thermal shutdown, indicated by a signal low on the ERR pin, to reduce the current to a safe level. APPLICATION INFORMATION Capacitor Selection: anyCAP PTAT CURRENT ADP3309 CLOAD GND Figure 20. Functional Block Diagram Output Capacitors: As with any micropower device, output transient response is a function of the output capacitance. The ADP3309 is stable with a wide range of capacitor values, types and ESR (anyCAP). A capacitor as low as 0.47 µF is all that is needed for stability. However, larger capacitors can be used if high output current surges are anticipated. The ADP3309 is stable with extremely low ESR capacitors (ESR ≈ 0), such as multilayer ceramic capacitors (MLCC) or OSCON. Input Bypass Capacitor: An input bypass capacitor is not required. However, for applications where the input source is high impedance or far from the input pin, a bypass capacitor is recommended. Connecting a 0.47 µF capacitor from the input pin (Pin 1) to ground reduces the circuit’s sensitivity to PC board layout. If a bigger output capacitor is used, the input capacitor must be 1 µF minimum. Thermal Overload Protection A very high gain error amplifier is used to control this loop. The amplifier is constructed in such a way that at equilibrium it produces a large, temperature proportional input “offset voltage” that is repeatable and very well controlled. The temperature proportional offset voltage is combined with the complementary diode voltage to form a “virtual bandgap” voltage, implicit in the network, although it never appears explicitly in the circuit. Ultimately, this patented design makes it possible to control the loop with only one amplifier. This technique also improves the noise characteristics of the amplifier by providing more flexibility on the trade-off of noise sources that leads to a low noise design. The R1, R2 divider is chosen in the same ratio as the bandgap voltage to the output voltage. Although the R1, R2 resistor divider is loaded by the diode D1, and a second divider consisting of R3 and R4, the values can be chosen to produce a temperature stable output. The patented amplifier controls a new and unique noninverting driver that drives the pass transistor, Q1. The use of this special noninverting driver enables the frequency compensation to include the load capacitor in a pole splitting arrangement to achieve reduced sensitivity to the value, type and ESR of the load capacitance. Most LDOs place very strict requirements on the range of ESR values for the output capacitor because they are difficult to stabilize due to the uncertainty of load capacitance and resistance. Moreover, the ESR value, required to keep conventional LDOs stable, changes depending on load and temperature. These ESR limitations make designing with LDOs more difficult because of their unclear specifications and extreme variations over temperature. This is no longer true with the ADP3309 anyCAP LDO. It can be used with virtually any capacitor, with no constraint on the minimum ESR. This innovative design allows the circuit to be stable with just a small 0.47 µF capacitor on the output. Additional advantages of the design scheme include superior line noise rejection and very high regulator gain which leads to excellent line and load regulation. An impressive ± 2.2% accuracy is guaranteed over line, load and temperature. The ADP3309 is protected against damage due to excessive power dissipation by its thermal overload protection circuit, which limits the die temperature to a maximum of 165°C. Under extreme conditions (i.e., high ambient temperature and power dissipation) where die temperature starts to rise above 165°C, the output current is reduced until the die temperature has dropped to a safe level. The output current is restored when the die temperature is reduced. Current and thermal limit protections are intended to protect the device against accidental overload conditions. For normal operation, device power dissipation should be externally limited so that junction temperatures will not exceed 125°C. Calculating Junction Temperature Device power dissipation is calculated as follows: PD = (VIN – VOUT) ILOAD + (VIN) IGND Where ILOAD and IGND are load current and ground current, VIN and VOUT are input and output voltages respectively. Assuming ILOAD = 100 mA, IGND = 2 mA, VIN = 5.0 V and VOUT = 3.3 V, device power dissipation is: PD = (5.0 – 3.3) 100 mA + 5.0 × 2 mA = 180 mW ∆T = TJ – TA = PD × θJA = 0.18 × 190 = 34.2°C With a maximum junction temperature of 125°C, this yields a maximum ambient temperature of ~90°C. Printed Circuit Board Layout Consideration Surface mount components rely on the conductive traces or pads to transfer heat away from the device. Appropriate PC board layout techniques should be used to remove heat from the immediate vicinity of the package. –6– REV. 0 ADP3309 The following general guidelines will be helpful when designing a board layout: 1. PC board traces with larger cross section areas will remove more heat. For optimum results, use PC boards with thicker copper and or wider traces. 2. Increase the surface area exposed to open air so heat can be removed by convection or forced air flow. 3. Do not use solder mask or silk screen on the heat dissipating traces because it will increase the junction to ambient thermal resistance of the package. Shutdown Mode VIN = 4V TO 12V OUTPUT SELECT 4V 0V IN OUT VOUT = 2.7V/3.3V ADP3309-2.7 SD GND C1 1.0 F + IN OUT + C2 0.47 F ADP3309-3.3 SD GND Figure 21. Crossover Switch Higher Output Current Applying a TTL high signal to the shutdown pin or tying it to the input pin will turn the output ON. Pulling the shutdown pin down to a TTL low signal or tying it to ground will turn the output OFF. In shutdown mode, quiescent current is reduced to less than 1 µA. Error Flag Dropout Detector The ADP3309 can source up to 100 mA without any heatsink or pass transistor. If higher current is needed, an appropriate pass transistor can be used, as in Figure 22, to increase the output current to 1 A. VIN = 4V TO 8V C1 47 F MJE253* R1 50 VOUT = 3.3V@1A The ADP3309 will maintain its output voltage over a wide range of load, input voltage and temperature conditions. If the output is about to lose regulation, for example, by reducing the supply voltage below the combined regulated output and dropout voltages, the ERR pin will be activated. The ERR output is an open collector that will be driven low. Once set, the ERRor flag’s hysteresis will keep the output low until a small margin of operating range is restored either by raising the supply voltage or reducing the load. APPLICATION CIRCUITS Crossover Switch IN OUT + ADP3309-3.3 SD GND ERR C2 10 F *AAVID531002 HEATSINK IS USED Figure 22. Higher Output Current Linear Regulator Constant Dropout Post Regulator The circuit in Figure 21 shows that two ADP3309s can be used to form a mixed supply voltage system. The output switches between two different levels selected by an external digital input. Output voltages can be any combination of voltages from the Ordering Guide of the data sheet. The circuit in Figure 23 provides high precision with low dropout for any regulated output voltage. It significantly reduces the ripple from a switching regulator while providing a constant dropout voltage, which limits the power dissipation of the LDO to 30 mW. The ADP3000 used in this circuit is a switching regulator in the step-up configuration. L1 6.8 H VIN = 2.5V TO 3.5V C1 100 F 10V D1 1N5817 ADP3309-3.3 IN OUT GND + Q2 2N3906 R3 124k 1% R4 274k 3.3V@100mA SD R1 120 I LIM VIN SW1 FB GND SW2 C2 100 F 10V Q1 2N3906 R2 30.1k 1% C3 2.2 F ADP3000-ADJ Figure 23. Constant Dropout Post Regulator REV. 0 –7– ADP3309 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 5-Lead Surface Mount Package (SOT-23) C3250–2.5–7/98 0.0079 (0.20) 0.0031 (0.08) 10° 0° 0.0217 (0.55) 0.0138 (0.35) 0.1181 (3.00) 0.1102 (2.80) 0.0669 (1.70) 0.0590 (1.50) PIN 1 5 1 2 4 3 0.1181 (3.00) 0.1024 (2.60) 0.0374 (0.95) BSC 0.0748 (1.90) BSC 0.0512 (1.30) 0.0354 (0.90) 0.0059 (0.15) 0.0019 (0.05) 0.0197 (0.50) 0.0138 (0.35) 0.0571 (1.45) 0.0374 (0.95) SEATING PLANE –8– REV. 0 PRINTED IN U.S.A.