a
Adjustable Output Ultralow IQ, 200 mA,
SOT-23, anyCAP Low Dropout Regulator
ADP3331
FEATURES
High Accuracy over Line and Load: ⴞ0.7% @ 25ⴗC,
1.4% over Temperature
Ultralow Dropout Voltage: 140 mV (Typ) @ 200 mA
Can Be Used as a High Current (>1 A) LDO
Controller
Requires Only CO = 0.47 F for Stability
anyCAP = Stable with Any Type of Capacitor
(Including MLCC)
Current and Thermal Limiting
Low Noise
Low Shutdown Current: 10 nA Typical
2.6 V to 12 V Supply Range
1.5 V to 11.75 V Output Range
–40ⴗC to +85ⴗC Ambient Temperature Range
Ultrasmall Thermally Enhanced Chip-on-Lead™
SOT-23-6 Lead Package
®
FUNCTIONAL BLOCK DIAGRAM
Q1
IN
THERMAL
PROTECTION
CC
ERR
FB
gm
DRIVER
Q2
SD
BAND GAP
REF
GND
ERR
ADP3331
APPLICATIONS
Cellular Telephones
Notebook, Palmtop Computers
Battery-Powered Systems
PCMCIA Regulators
Bar Code Scanners
Camcorders, Cameras
OUT
ADP3331
EOUT
R3
330k⍀
OUT
VIN
IN
C1 +
0.47F
VOUT
R1
SD
FB
GND
6
4
+
C2
0.47F
R2
ON
OFF
Figure 1. Typical Application Circuit
GENERAL DESCRIPTION
The ADP3331 is a member of the ADP330x family of precision
low dropout anyCAP voltage regulators. The ADP3331 operates
with an input voltage range of 2.6 V to 12 V and delivers a load
current up to 200 mA. The ADP3331 stands out from the
conventional LDOs with a novel architecture and an enhanced
process that enables it to offer performance advantages and higher
output current than its competition. Its patented design requires
only a 0.47 mF output capacitor for stability. This device is insensitive to capacitor equivalent series resistance (ESR), and is stable
with any good quality capacitor, including ceramic (MLCC) types
for space restricted applications. The ADP3331 achieves exceptional accuracy of ± 0.7% at room temperature and ± 1.4% overall
accuracy over temperature, line, and load variations. The dropout voltage of the ADP3331 is only 140 mV (typical) at 200 mA.
This device also includes a safety current limit, thermal overload protection, and a shutdown feature. In shutdown mode, the
ground current is reduced to less than 2 mA. The ADP3331 has
ultralow quiescent current 34 mA (typical) in light load situations.
The SOT-23-6 package has been thermally enhanced using
Analog Device’s proprietary Chip-on-Lead feature to maximize power dissipation.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/461-3113
© 2014 Analog Devices, Inc. All rights reserved.
(TA = –40ⴗC to +85ⴗC, VIN = 7 V, CIN = 0.47 F, COUT = 0.47 F, unless otherwise
ADP3331–SPECIFICATIONS noted.)
Parameter
Symbol
3
OUTPUT VOLTAGE ACCURACY
HIGH OUTPUT VOLTAGE RANGE
1, 2
Conditions
VIN = VOUTNOM + 0.25 V to 12 V,
VOUTNOM ≥ 2.35 V,
IL = 0.1 mA to 200 mA,
TA = 25∞C
VIN = VOUTNOM + 0.25 V to 12 V,
VOUTNOM ≥ 2.35 V,
IL = 0.1 mA to 150 mA,
TA = –40∞C to +85∞C
VIN = VOUTNOM + 0.25 V to 12 V,
VOUTNOM ≥ 2.35 V,
IL = 0.1 mA to 200 mA,
TA = –20∞C to +85∞C
3
VIN = 2.6 V to 12 V,
VOUTNOM = 1.5 V to 2.35 V,
IL = 0.1 mA to 200 mA,
TA = 25∞C
VIN = 2.6 V to 12 V,
VOUTNOM = 1.5 V to 2.35 V,
IL = 0.1 mA to 150 mA,
TA = –40∞C to +85∞C
VIN = 2.6 V to 12 V,
VOUTNOM = 1.5 V to 2.35 V,
IL = 0.1 mA to 200 mA,
TA = –20∞C to +85∞C
OUTPUT VOLTAGE ACCURACY
LOW OUTPUT VOLTAGE RANGE
Min
Typ
Max
Unit
–0.7
+0.7
%
–1.4
+1.4
%
–1.4
+1.4
%
–0.7
+0.7
%
–1.4
+1.4
%
–1.4
+1.4
%
DVO
DVIN
VIN = VOUTNOM + 0.25 V to 12 V
TA = 25∞C
0.06
mV/V
DVO
DIL
IL= 0.1 mA to 200 mA
TA = 25∞C
0.04
mV/mA
GROUND CURRENT
IGND
IL = 200 mA, TA = –20∞C to +85∞C
IL = 150 mA
IL = 50 mA
IL = 0.1 mA
1.6
1.2
0.4
34
4.0
3.1
1.1
50
mA
mA
mA
mA
GROUND CURRENT
IN DROPOUT
IGND
VIN = VOUTNOM – 100 mV
IL = 0.1 mA
37
55
mA
VOUT = 98% of VOUTNOM
IL = 200 mA, TA = –20∞C to +85∞C
IL = 150 mA
IL = 10 mA
IL = 1 mA
0.14
0.11
0.042
0.025
0.23
0.17
0.06
0.05
V
V
V
V
LINE REGULATION
LOAD REGULATION
2
DROPOUT VOLTAGE
VDROP
PEAK LOAD CURRENT
ILDPK
VIN = VOUTNOM + 1 V
300
mA
OUTPUT NOISE
VNOISE
f = 10 Hz–100 kHz, CL = 10 mF
IL = 200 mA, CNR = 10 nF, VOUT = 3 V
f = 10 Hz–100 kHz, CL = 10 mF
IL = 200 mA, CNR = 0 nF, VOUT = 3 V
47
mV rms
95
mV rms
SHUTDOWN THRESHOLD
VTHSD
ON
OFF
2.0
0.4
V
V
SHUTDOWN PIN INPUT CURRENT
ISD
0 < SD £ 12 V
0 < SD £ 5 V
1.9
1.4
9
6
mA
mA
GROUND CURRENT IN
SHUTDOWN MODE
IGNDSD
SD = 0 V, VIN = 12 V
0.01
2
mA
–2–
REV. B
ADP3331
Parameter
Symbol
Conditions
OUTPUT CURRENT IN
SHUTDOWN MODE
IOSD
ERROR PIN OUTPUT LEAKAGE
ERROR PIN OUTPUT
LOW VOLTAGE
Min
Typ
Max
Unit
TA = 25∞C @ VIN = 12 V
TA = 85∞C @ VIN = 12 V
1
2
mA
mA
IEL
VEO = 5 V
1
mA
VEOL
ISINK = 400 mA
0.40
V
0.19
NOTES
1
Ambient temperature of 85∞C corresponds to a junction temperature of 125∞C under typical full load test conditions.
2
Application stable with no load.
3
Assumes the use of ideal resistors. Overall accuracy also depends on the tolerance of the external resistors used to set the output voltage.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
Input Supply Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to +16 V
Shutdown Input Voltage . . . . . . . . . . . . . . . . . –0.3 V to +16 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . Internally Limited
Operating Ambient Temperature Range . . . . –40∞C to +85∞C
Operating Junction Temperature Range . . . –40∞C to +125∞C
qJA (4-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . . 165∞C/W
qJA (2-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . . 190∞C/W
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300∞C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215∞C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C
OUT
ADP3331
6
SD
5 FB
TOP VIEW
ERR 3 (Not to Scale) 4 GND
IN
2
PIN FUNCTION DESCRIPTIONS
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Pin
Name
Function
1
OUT
2
3
IN
ERR
4
5
GND
FB
6
SD
Output of the Regulator. Bypass to ground
with a 0.47 mF or larger capacitor.
Regulator Input.
Open Collector Output that goes low to
indicate that the output is about to go out
of regulation.
Ground.
Feedback Input. Connect to an external
resistor divider, which sets the output
voltage.
Active Low Shutdown Pin. Connect to
ground to disable the regulator output.
When shutdown is not used, this pin
should be connected to the input pin.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3331 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. B
1
–3–
WARNING!
ESD SENSITIVE DEVICE
ADP3331–Typical Performance Characteristics
3.010
3.005
VOUT = 3.0V
3.008
OUTPUT VOLTAGE (V)
IL = 0mA
3.004
IL = 10mA
3.002
3.000
IL = 50mA
2.998
IL = 100mA
2.996
2.994
IL = 200mA
2.992
2.990
3.25 4
5
IL = 150mA
6
7
8
9
10
INPUT VOLTAGE (V)
VOUT = 3V
40
GROUND CURRENT (A)
3.003
3.006
3.002
3.001
3.000
2.999
2.998
2.997
2.996
11
12
25
IL = 0mA
1.0
0.8
0.6
0.4
IL = 50mA
0.2
IL = 150mA
0.1
IL = 200mA
0.0
0.2
100
150
50
OUTPUT LOAD (mA)
200
TPC 4. Ground Current vs. Load
Current
–0.1
–45 –25
–5 15 35 55 75 95 115 135
JUNCTION TEMPERATURE (ⴗC)
TPC 5. Output Voltage Variation % vs.
Junction Temperature
GROUND CURRENT (mA)
0.3
OUTPUT VOLTAGE (%)
GROUND CURRENT (mA)
10
0
2
4
6
8
INPUT VOLTAGE (V)
10
12
TPC 3. Ground Current vs. Supply
Voltage
1.4
3.0
VIN = 7V
2.8
IL = 200mA
2.6
2.4
2.2
IL = 150mA
2.0
1.8
IL = 100mA
1.6
1.4
1.2
1.0
0.8
0.6
0.4 IL = 50mA
0.2
IL = 0mA
0
–45 –25 –5 15 35 55 75 95 115 135
JUNCTION TEMPERATURE (ⴗC)
TPC 6. Ground Current vs. Junction
Temperature
3.5
VOUT = 3V
SD = VIN
RL = 15⍀
200
150
100
50
CL = 0.47F
3
2.5
1
1.5
0
1.0
10
0.5
0
0
25
50
75 100 125 150 175 200
OUTPUT LOAD (mA)
TPC 7. Dropout Voltage vs.
Output Current
2
2.0
VIN (V)
INPUT/OUTPUT VOLTAGE (V)
3.0
VOUT (V)
250
0
15
50 75 100 125 150 175 200
OUTPUT LOAD (mA)
0.4
0
20
0
0
TPC 2. Output Voltage vs. Load
Current
1.2
IL = 0A
25
5
VIN = 7V
0
30
2.994
1.6
IL = 100A
35
2.995
TPC 1. Line Regulation Output
Voltage vs. Supply Voltage
INPUT/OUTPUT VOLTAGE (mV)
OUTPUT VOLTAGE (V)
45
VOUT = 3.0V
VIN = 7V
3.004
CL = 10F
VIN = 7V
VOUT = 3V
SD = VIN
RL = 15⍀
5
0
0
1.0
2.0
3.0
TIME (sec)
4.0
5.0
TPC 8. Power-Up/Power-Down
–4–
0
100
200
300
TIME (s)
400
500
TPC 9. Power-Up Response
REV. B
ADP3331
3.100
3.040
3.000
VOUT = 3V
RL = 15⍀
CL = 0.47F
2.960
3.050
V
VOUT (V)
VOUT (V)
3.040
3.000
VOUT = 3V
RL = 15⍀
CL = 10F
2.960
VIN = 7V
VOUT = 3V
CL = 0.47F
2.950
2.920
2.920
3.000
2.900
7.5
VIN (V)
7.0
0
100
200
300
TIME (s)
400
0
V
200
300
TIME (s)
400
500
0
3
0
VIN = 7V
VOUT = 3V
CL = 10F
2.950
2
VOUT
mA
0
VERR 3
0
100
2
VIN = 7V
20mA
VSD
0
0
0
200
400
600
800
0
0
1000
TIME (s)
TPC 13. Load Transient Response
CL = 0.47F
IL = 0.1mA
400
600
TIME (s)
RMS NOISE (V)
CL = 0.47F
IL = 200mA
–50
CL = 0.47F
CNR = 0
–60
CL = 10F
IL = 200mA
–70
100
1k
10k
100k
FREQUENCY (Hz)
IL = 0mA
IL = 200mA
WITH NOISE REDUCTION
40
CL = 10F
IL = 0.1mA
–80
100
60
20
1M
TPC 16. Power Supply Ripple
Rejection
10M
0
0
1000
1
IL = 200mA
80
800
TPC 15. Turn On–Turn Off Response
120
–30
REV. B
200
140
–20
–90
10
0
160
VOUT = 3.0V
–10
–40
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
TIME (Sec)
TPC 14. Short Circuit Current
0
1000
1
IOUT
200
100
800
VIN = 7V
VOUT = 3V
CL = 10F
RL = 15⍀
3
300
200
600
VOUT
400
2.900
400
TPC 12. Load Transient Response
500
3.000
200
TIME (s)
V
V
3.050
mA
100
TPC 11. Line Transient Response
3.100
RIPPLE REJECTION (dB)
20mA
0
7.0
500
TPC 10. Line Transient Response
100
VOLTAGE NOISE SPECTRAL
DENSITY (V/ Hz)
VIN (V)
7.5
mA
200
CL = 10F
CNR = 0
CL = 0.47F
CNR = 10nF
0.1
CL = 10F
CNR = 10nF
VOUT = 3.0V
IL = 200mA
IL = 0mA WITH NOISE REDUCTION
10
20
30
CL (F)
40
TPC 17. RMS Noise vs. CL
(10 Hz to 100 kHz)
–5–
50
0.01
10
100
1k
10k
FREQUENCY (Hz)
100k
TPC 18. Output Noise Density
1M
ADP3331
innovative design allows the circuit to be stable with just a small
0.47 mF capacitor on the output. Additional advantages of the
pole-splitting scheme include superior line noise rejection and
very high regulator gain. The high gain leads to excellent regulation, and ± 1.4% accuracy is guaranteed over line, load, and
temperature.
THEORY OF OPERATION
The ADP3331 anyCAP LDO uses a single control loop for both
regulation and reference functions, as shown in Figure 2. The
output voltage is sensed by an external resistive voltage divider
consisting of R1 and R2. Feedback is taken from this network
by way of a series diode (D1) and a second resistor divider (R3
and R4) to the input of an amplifier.
INPUT
Additional features of the circuit include current limit, thermal
shutdown, and an error flag. Compared to standard solutions that
give a warning after the output has lost regulation, the ADP3331
provides improved system performance by enabling the ERR pin
to give a warning just before the device loses regulation.
OUTPUT
COMPENSATION
CAPACITOR
Q1
NONINVERTING
WIDEBAND
DRIVER
gm
ATTENUATION
(VBANDGAP/VOUT)
R3
PTAT
VOS
R1
D1
(a)
R4
PTAT
CURRENT
CLOAD
As the chip’s temperature rises above +165∞C, the circuit activates a soft thermal shutdown to reduce the current to a safe
level. The thermal shutdown condition is indicated by the ERR
signal going low.
RLOAD
R2
ADP3331
APPLICATION INFORMATION
Capacitor Selection
GND
Output Capacitor: The stability and transient response of the
LDO is a function of the output capacitor. The ADP3331 is stable
with a wide range of capacitor values, types, and ESR (anyCAP).
A capacitor as low as 0.47 mF is all that is needed for stability;
larger capacitors can be used if high current surges on the output
are anticipated. The ADP3331 is stable with extremely low ESR
capacitors (ESR ª 0), such as multilayer ceramic capacitors
(MLCC) or OSCON. Note that the effective capacitance of some
capacitor types falls below the minimum over temperature or
with dc voltage.
Figure 2. Functional Block Diagram
A very high gain error amplifier is used to control this loop.
The amplifier is constructed in such a way that at equilibrium it
produces a large, temperature-proportional input offset voltage
that is repeatable and very well controlled. The temperatureproportional offset voltage is combined with the complementary
diode voltage to form a virtual band gap voltage, implicit in the
network, although it never appears explicitly in the circuit. Ultimately, this patented design makes it possible to control the loop
with only one amplifier. This technique also improves the noise
characteristics of the amplifier by providing more flexibility on
the trade-off of noise sources, which leads to a low noise design.
Input Capacitor: An input bypass capacitor is not strictly required
but is recommended in any application involving long input
wires or high source impedance. Connecting a 0.47 mF capacitor
from the input to ground reduces the circuit’s sensitivity to
PC board layout and input transients. If a larger output capacitor
is necessary, a larger value input capacitor is also recommended.
The R1, R2 divider is chosen in the same ratio as the band gap
voltage to output voltage. Although the R1, R2 resistor divider
is loaded by the diode D1 and a second divider consisting of R3
and R4, the values are chosen to produce a temperature stable
output. This unique arrangement specifically corrects for the
loading of the divider so that the error resulting from the base
current loading in conventional circuits is avoided.
Noise Reduction Capacitor: A noise reduction capacitor can be
used to reduce the output noise by 6 dB to 10 dB. This capacitor limits the noise gain when connected between the feedback
pin (FB) and the output pin (OUT), as shown in Figure 3. Low
leakage capacitors in the 10 pF to 500 pF range provide the best
performance. Since FB is internally connected to a high impedance node, any connection to this node should be carefully done
to avoid noise pickup from external sources. The pad connected
to this pin should be as small as possible; long PC board traces
are not recommended. When adding a noise reduction capacitor,
use the following guidelines:
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole-splitting arrangement to
achieve reduced sensitivity to the value, type, and ESR of the
load capacitor.
Most LDOs place strict requirements on the range of ESR values
for the output capacitor because they are difficult to stabilize due
to the uncertainty of the load capacitance and resistance. Moreover, the ESR value required to keep conventional LDOs stable
changes, depending on load and temperature. These ESR limitations make designing with LDOs more difficult because of their
unclear specifications and extreme variations over temperature.
∑ Maintain a minimum load current of 1 mA when not in
shutdown.
∑ For CNR values greater than 500 pF, add a 100 kW series
resistor (RNR).
It is important to note that as CNR increases, the turn-on time
will be delayed. With CNR values greater than 1 nF, this delay
may be on the order of several milliseconds.
The ADP3331 solves this problem. It can be used with any good
quality capacitor, with no constraint on the minimum ESR. The
–6–
REV. B
ADP3331
ERR
R4
ADP3331
OUT
VIN
IN
C1 +
0.47F
SD
R1
FB
GND
Note that at output voltages above 5.2 V and below 1.6 V, nonstandard resistor values or the addition of a resistor to the divider
network is required to achieve the best performance. For output
voltages below 1.6 V, select a standard resistance value for R2 and
then calculate the value of R1:
EOUT
RNR
CNR
VOUT
+C2
0.47F
R3
ÊV
ˆ
R1 = Á OUT - 1˜ ¥ R2
Ë VFB
¯
R2
ON
OFF
For output voltages above 5.2 V, select a standard resistance for
R1, and calculate the value of R2:
Figure 3. Noise Reduction Circuit
Output Voltage
The ADP3331 has an adjustable output voltage that can be set by
an external resistor divider. The output voltage will be divided by
R1 and R2, and then fed back to the FB pin. Refer to Figure 3.
For the output voltage to have the lowest possible sensitivity to
temperature variations, it is important that the parallel resistance
of R1 and R2 be as close as possible to 230 kW:
R1 ¥ R2
= 230 kW
R1 + R2
(1)
Also, for the best accuracy over temperature, the feedback voltage
should set for 1.204 V:
VOUT
(5)
Ê R2 ˆ
Á
˜ = VFB
Ë R1 + R2 ¯
(2)
Where VOUT is the desired output voltage and VFB is the virtual
band gap voltage. Note that VFB does not actually appear at the
FB pin due to loading by the internal PTAT current.
Ê
ˆ
VFB
R2 = R1 ¥ Á
˜
V
V
Ë OUT
FB ¯
(6)
After selecting values for R1 and R2, calculate the value of R3
needed to maintain the 230 k impedance:
Ê R1 ¥ R2 ˆ
R3 = 230 kW - Á
˜
Ë R1 + R2 ¯
(7)
Using standard values, as shown in Table I, will sacrifice some
output voltage accuracy.
Output Current Limit
The ADP3331 is short-circuit protected by limiting the pass
transistor’s base drive current. The maximum output current is
limited to about 300 mA.
Thermal Overload Protection
ÊV
ˆ
R1 = 230 Á OUT ˜ kW
Ë VFB ¯
(3)
The ADP3331 is protected by its thermal overload protection
circuit against damage due to excessive power dissipation.
Thermal protection limits the die temperature to a maximum of
165∞C. Under extreme conditions (i.e., high ambient temperature and power dissipation) where the die temperature starts to
rise above 165∞C, the output current will be reduced until the
die temperature has dropped to a safe level.
230
R2 =
kW
Ê
VFB ˆ
1
Á V
˜
Ë
OUT ¯
(4)
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, the device’s power dissipation should be externally
limited so that the junction temperature will not exceed 125∞C.
Combining the above equations and solving for R1 and R2
results in the following formulas:
Chip-on-Lead
The output voltage can be adjusted to any voltage from 1.5 V to
11.75 V. For example, Table I shows some representative feedback resistor values for output voltages in the specified range.
Table I. Feedback Resistor Selection
VOUT (V)
R1 (1%)
R2 (1%)
R3 (1%)
1.5
1.8
2.2
2.7
3.3
5
9
243 kW
340 kW
422 kW
511 kW
634 kW
953 kW
1.00 MW
1.00 MW
698 kW
511 kW
412 kW
365 kW
301 kW
154 kW
34.8 kW
REV. B
The ADP3331 uses a patented Chip-on-Lead package design to
ensure the best thermal performance in a SOT-23 footprint. In a
standard SOT-23, most of the heat flows out of the ground pin.
The Chip-on-Lead package uses an electrically isolated die
attach, which allows all the pins to contribute to heat conduction.
This technique reduces the thermal resistance to 190∞C/W on a
2-layer board compared to >230∞C/W for a standard SOT-23
lead frame. Figure 4 shows the difference between the standard
SOT-23 and the Chip-on-Lead lead frames.
97.6 kW
–7–
ADP3331
degree of overshoot is determined by several factors: the output
voltage setting, the output load, the noise reduction capacitor,
and the output capacitor.
SILICON DIE
WITH
ELECTRICALLY
ISOLATED
DIE ATTACH
SILICON
DIE
NORMAL SOT-23-6 PACKAGE
The output voltage setting is determined by the application and
cannot be tailored for minimum overshoot. In general, for output
voltages of 2.2 V or less, the overshoot becomes larger as the
output voltage decreases.
THERMALLY ENHANCED
CHIP-ON-LEAD PACKAGE
The output load is also determined by the system requirements.
However, if the ADP3331 has no load on the output during
startup, a small amount of preload can be added to minimize
overshoot. A preload of 2 mA to 20 mA is recommended.
Figure 4. Chip-on-Lead Package
Calculating Junction Temperature
Device power dissipation is calculated as follows:
PD = (VIN - VOUT )I LOAD + (VIN )IGND
A noise reduction capacitor, if not already being used, is suggested to reduce the overshoot. Values in the range of 10 pF to
100 pF work best, along with the preload suggested previously.
(8)
Where ILOAD and IGND are load current and ground current and
VIN and VOUT are the input and output voltages, respectively.
The output capacitor can be adjusted to minimize the overshoot. Values in the 0.47 mF to 1.0 mF range should be used in
conjunction with the preload and noise reduction capacitor.
Further increases in the output capacitance may be acceptable if
the output already has a sizable load during startup.
Assuming that the worst case operating conditions are ILOAD =
200 mA, IGND = 4 mA, VIN = 4.2 V, and VOUT = 3.0 V, the
device power dissipation is
PD = (4.2 V - 3.0 V ) 200 mA + (4.2 V ) 4 mA = 257 mW (9)
Higher Output Current
The ADP3331 can source up to 200 mA without any heat sink
or pass transistor. If higher current is needed, an appropriate pass
transistor can be used, as in Figure 5, to increase the output
current to 1 A.
The proprietary package used on the ADP3331 has a thermal
resistance of 165∞C/W when placed on a 4-layer board and
190∞C/W when placed on a 2-layer board. This allows the ambient
temperature to be significantly higher for a given power dissipation than with a standard package. Assuming a 4-layer board, the
junction temperature rise above ambient will be approximately
equal to
D TJA = 0.257 W ¥ 165oC/W = 42.4oC
VIN = 3.3V
C1
47F
(10)
IN
To limit the junction temperature to 125∞C, the maximum
allowable ambient temperature is
TA( MAX ) = + 125oC - 42.4oC = 82.6oC
MJE253*
VOUT = 1.8V @ 1A
R1
50⍀
OUT
C2
10F
ADP3331
SD
(11)
340k⍀
FB
GND
ERR
698k⍀
*REQUIRES HEAT SINK
Shutdown Mode
Applying a TTL level high signal to the shutdown (SD) pin, or
tying it to the input pin, will turn the output ON. Pulling the
SD to 0.4 V or below, or tying it to ground, will turn the output
OFF. In shutdown mode, the quiescent current is reduced to
less than 1 mA.
Figure 5. High Output Current Linear Regulator
Printed Circuit Board Layout Considerations
Use the following general guidelines when designing printed
circuit boards:
Error Flag Dropout Detector
1. PC board traces with larger cross sectional areas will remove
more heat from the ADP3331. For optimum heat transfer,
specify thick copper and use wide traces.
The ADP3331 will maintain its output voltage over a wide
range of load, input voltage, and temperature conditions. If the
output is about to lose regulation due to the input voltage
approaching the dropout level, the error flag will be activated.
The ERR output is an open collector, which will be driven low.
2. The thermal resistance can be decreased by approximately
10% by adding a few square centimeters of copper area to
the lands connected to the pins of the LDO.
Once set, the ERR flag’s hysteresis will keep the output low until
a small margin of operating range is restored either by raising
the supply voltage or reducing the load.
3. The feedback pin is a high impedance input, and care should
be taken when making a connection to this pin. The voltage
setting resistors and noise reduction network must be located
as close as possible. Long PC board traces are not recommended. Avoid routing traces near possible noise sources.
Low Voltage Applications
In applications where the output voltage is 2.2 V or less, the
ADP3331 may begin to exhibit some turn-on overshoot. The
–8–
REV. B
ADP3331
OUTLINE DIMENSIONS
3.00
2.90
2.80
1.70
1.60
1.50
6
5
4
1
2
3
3.00
2.80
2.60
PIN 1
INDICATOR
0.95 BSC
1.90
BSC
1.45 MAX
0.95 MIN
0.15 MAX
0.05 MIN
0.20 MAX
0.08 MIN
10°
4°
0°
SEATING
PLANE
0.50 MAX
0.30 MIN
0.60
BSC
COMPLIANT TO JEDEC STANDARDS MO-178-AB
0.55
0.45
0.35
12-16-2008-A
1.30
1.15
0.90
Figure 6. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADP3331ARTZ-REEL7
1
Temperature Range
–40°C to +85°C
Output Voltage (V)
Adjustable
Package Option
RJ-6
Z = RoHS Compliant Part.
REVISION HISTORY
2/14—Rev. A to Rev. B
Updated Outline Dimensions .......................................................... 9
Changes to Ordering Guide ............................................................. 9
5/03— Rev. 0 to Rev. A
Renumbered figures and TPCs ........................................ Universal
Changes to Features .......................................................................... 1
Changes to Figure 3 .......................................................................... 7
Changes to Output Voltage Section ................................................ 7
Changes to Table I ............................................................................. 7
Updated Outline Dimensions .......................................................... 9
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00146-0-2/14(B)
Rev. B | Page 9
Package Description
6-Lead SOT-23
Branding Code
L9B
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