Ultralow, IQ, anyCAP®
Low Dropout Regulator
ADP3342
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Q1
IN
OUT
VCC
THERMAL
PROTECTION
CC
gm
DRIVER
PWRGD
SD
BAND GAP +
ADP3342
REF –
02712-001
Accuracy over line and load: ±4.0% @ 25°C,
±5% over temperature
Ultralow dropout voltage: 190 mV (typ) @ 300 mA
Requires only CO = 1.0 µF for stability
anyCAP architecture stable with any type of capacitor
(including MLCC)
Current and thermal limiting
Low shutdown current: < 2 µA
1.7 V ≤ VIN ≤ 6 V
2.8 V ≤ VCC ≤ 6 V
VOUT = 1.2 V ±5%
0°C to +100°C ambient temperature range
Ultrasmall thermally enhanced 8-lead MSOP package
GND
Figure 1.
APPLICATIONS
Notebook PCs
Desktop PCs
3.3V
GENERAL DESCRIPTION
The ADP3342 stands out from the conventional LDOs because
it has the lowest thermal resistance of any MSOP-8 package and
an enhanced process that enables it to offer performance
advantages beyond its competition. Its patented design requires
only a 1.0 µF output capacitor for stability. This device is
insensitive to output capacitor equivalent series resistance (ESR)
and is stable with any good quality capacitor, including ceramic
(MLCC) types for space-restricted applications. The dropout
voltage of the ADP3342 is only 190 mV (typical) at 300 mA.
This device also includes a safety current limit, thermal
overload protection, and a shutdown control pin.
ADP3342
VIN
1.8V
1µF
7
+
6
ON
OFF
IN
OUT 2
+
VOUT
1.2V
1µF
SD PWRGD 5
GND
4
02712-002
The ADP3342 is a unique member of the ADP33xx family
of precision low dropout anyCAP voltage regulators. The
ADP3342 operates with an input voltage range of 1.7 V to 6 V
and delivers a continuous load current up to 300 mA. In order
to support the ability to regulate from such a low input voltage,
the power rail to the IC, VCC, has been split off from the main
power rail, IN, from which the output is powered.
3
VCC
Figure 2. Typical Application Circuit
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
www.analog.com
Tel: 781.329.4700
Fax: 781.326.8703
© 2005 Analog Devices, Inc. All rights reserved.
ADP3342
TABLE OF CONTENTS
Specifications..................................................................................... 3
Capacitor Selection .................................................................... 12
Absolute Maximum Ratings............................................................ 4
Input Bypass Capacitor.............................................................. 12
ESD Caution.................................................................................. 4
Power Good Monitoring Function .......................................... 12
Pin Configuration and Function Descriptions............................. 5
Shutdown Mode ......................................................................... 12
Typical Performance Characteristics ............................................. 6
Thermal Overload Protection .................................................. 12
Theory of Operation ...................................................................... 11
Calculating Junction Temperature........................................... 12
Application Information................................................................ 12
Outline Dimensions ....................................................................... 13
PC Application—VCCVID ....................................................... 12
Ordering Guide .......................................................................... 13
REVISION HISTORY
2/05— Rev. C to Rev. D
Format Updated..................................................................Universal
Change to Features ........................................................................... 1
Change to Specifications.................................................................. 3
Changes to Table 3............................................................................ 5
11/04—Rev. B to Rev. C
Changes to ORDERING GUIDE ................................................... 3
3/03—Rev. A to Rev. B
Changes to FEATURES .....................................................................1
Changes to Figure 1............................................................................1
Changes to SPECIFICATIONS.........................................................2
Changes to ABSOLUTE MAXIMUM RATINGS ..........................3
Changes to PIN FUNCTION DESCRIPTIONS ............................3
Changes to PC Application—VCCVID section .............................7
Deleted Paddle under Lead Package section...................................7
Changes to Calculating Junction Temperature section .................8
Updated OUTLINE DIMENSIONS ................................................8
10/02—Rev. 0 to Rev. A
Changes to PIN CONFIGURATION ..............................................3
Changes to PIN FUNCTION DESCRIPTION.............................. 3
Updated OUTLINE DIMENSIONS ................................................8
Rev. D | Page 2 of 16
ADP3342
SPECIFICATIONS
VCC = 3.0 V, VIN = 1.8 V, CIN = COUT = 1 µF, TA = 0°C to 100°C, unless otherwise noted.1, 2
Table 1.
Parameter
OUTPUT
Voltage Accuracy
Symbol
Conditions
Min
VOUT
VCC = 2.8 V to 6 V, VIN = 1.7 V to 6 V
IL = 0.1 mA to 300 mA
TA = 25°C
VCC = 2.8 V to 6 V, VIN = 1.7 V to 6 V
IL = 0.1 mA to 300 mA
TA = −40°C to +100°C
VCC = 2.8 V to 6 V, VIN = 1.7 V to 6 V
TA = 25°C
IL = 0.1 mA to 300 mA
TA = 25°C
VOUT = 98% of VOUTNOM
IL = 300 mA
IL = 200 mA
IL = 100 mA
VCC = 3 V, VIN = 1.8 V
f = 10 Hz to 100 kHz, CL = 1 µF
IL = 300 mA
Line Regulation
Load Regulation
Dropout Voltage
Current Limiting
Output Noise
OPERATING CURRENTS
Ground Current in Regulation
VCC Current in Regulation
Ground Current in Shutdown
SHUTDOWN
Threshold Voltage
VDROP
ILIM
VNOISE
IGND
IVCC
IGNDSD
VTHSD
−4.0
+4.0
%
−5.0
+5.0
%
VCC − 0.9
IPWRGDL
VPWRGDL3
VPWRGDH3
TD14
TD25
TD36
VPWRGD = 1.2 V, VCC = 3.0 V
IPWRGD = 300 µA
IPWRGD = 300 µA
IL = 3 mA to 300 mA, COUT = 1 µF to 10 µF
IL = 3 mA to 300 mA, COUT = 1 µF to 10 µF
IL = 3 mA to 300 mA, COUT = 1 µF to 10 µF
0.85
THPROT
IL = 100 mA
ISD
Output Current in Shutdown
IOSD
Off-Time Delay
THERMAL PROTECTION
Shutdown Temperature
Unit
On
Off
0 ≤ SD ≤ 6 V
TA = 25°C, VCC = 6 V, VIN = 6 V
TA = 100°C, VCC = 6 V, VIN = 6 V
SD Input Current
PWRGD
Output Current
Output Low Voltage
Output High Voltage
On-Time Delay
Max
IL = 300 mA, TA = −40°C to +100°C
IL = 300 mA, TA = 0°C to 100°C
IL = 300 mA, TA = 25°C
IL = 200 mA
IL = 0.1 mA
IL = 300 mA
SD = 0 V, VCC = 6 V, VIN = 1.8 V
1
3
Rev. D | Page 3 of 16
0.04
mV/V
0.12
mV/mA
190
125
70
450
60
450
mV
mV
mV
mA
µV rms
3.0
3.0
3.0
2.0
100
100
0.01
8.5
6.0
4.0
175
170
2
mA
mA
mA
mA
µA
µA
µA
1.4
0.6
7
V
V
µA
0.01
0.01
1
2
µA
µA
1.5
0.4
VCC − 0.4
5
50
0.05
All limits at temperature extremes are guaranteed via a correlation using standard statistical quality control (SQC) methods.
Ambient temperature of 100°C corresponds to a junction temperature of 125°C under typical full load test conditions.
VPWRGDL, VPWRGDH: Power good output voltages. Guaranteed by design and characterization.
4
TD1: Delay time from VOUT crossing 1 V to PWRGD high. Guaranteed by design.
5
TD2: Delay time from SD high to PWRGD high. Guaranteed by design.
6
TD3: Delay time between SD low and PWRGD low. Guaranteed by design.
2
Typ
300
300
1
165
mA
V
V
µs
µs
µs
°C
ADP3342
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Input Supply Voltage
Shutdown Input Voltage
Power Dissipation
Operating Ambient Temperature Range
Operating Junction Temperature Range
θJA (2-Layer Board)
θJA (4-Layer Board)
θJC
Storage Temperature Range
Lead Temperature Range (Soldering, 10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
Rating
−0.3 V to +13 V
−0.3 V to +13 V
Internally Limited
−40°C to +100°C
−40°C to +150°C
205°C/W
142°C/W
56°C/W
−65°C to +150°C
300°C
215°C
220°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Absolute maximum ratings apply individually
only, not in combination. Unless otherwise specified, all other
voltages are referenced to GND.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. D | Page 4 of 16
ADP3342
NC 1
OUT 2
ADP3342
VCC 3
TOP VIEW
(Not to Scale)
GND 4
8
NC
7
IN
6
SD
5
PWRGD
NC = NO CONNECT
02712-003
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1, 8
2
3
4
5
6
Mnemonic
NC
OUT
VCC
GND
PWRGD
SD
7
IN
Function
No Connection.
Output of the Regulator. Bypass to ground with a 1.0 µF or larger capacitor.
Supply Voltage.
Ground Pin.
Power Good. Used to indicate that output is in regulation.
Active Low Shutdown Pin. Connect to ground to disable the regulator output. When shutdown is not used,
this pin should be connected to the VCC pin.
Regulator Input.
Rev. D | Page 5 of 16
ADP3342
TYPICAL PERFORMANCE CHARACTERISTICS
3.5
1.25
VOUT = 1.2V
VCC = 3V
VIN = 1.8V
VCC = 3.0V
3.0
1.23
GROUND CURRENT (mA)
IL = 0mA
1.22
1.21
IL = 100mA
1.20
IL = 200mA
1.19
IL = 300mA
1.17
1.7
2.7
3.7
4.7
INPUT VOLTAGE (V)
2.0
1.5
1.0
0.5
02712-004
1.18
2.5
02712-007
OUTPUT VOLTAGE (V)
1.24
0
0
5.7
50
250
300
Figure 7. Ground Current vs. Load Current
Figure 4. Line Regulation Output Voltage vs. Supply Voltage
1.0
1.23
VIN = 1.8V
VCC = 3.0V
0
0.9
0.8
1.22
OUTPUT CHANNEL (%)
0.7
OUTPUT VOLTAGE (V)
100
150
200
OUTPUT LOAD (mA)
1.21
1.20
1.19
200mA
0.6
0.5
0.4
0.3
0.2
300mA
0.1
0
–0.1
1.18
1.17
0
50
100
150
200
OUTPUT LOAD (mA)
250
02712-008
02712-005
–0.2
–0.3
–0.4
–50
300
Figure 5. Output Voltage vs. Load Current
–25
0
25
50
75
100
JUNCTION TEMPERATURE (°C)
125
150
Figure 8. Output Voltage Variation vs. Junction Temperature
120
5.50
VOUT = 1.2V
VCC = 3V
VCC = 3.0V
VIN = 1.8V
5.00
110
GROUND CURRENT (mA)
100
90
80
70
4.00
IL = 300mA
3.50
3.00
2.50
IL = 200mA
2.00
1.50
IL = 100mA
50
1.2
1.6
2.0
2.4
2.8 3.2 3.6 4.0 4.4
INPUT VOLTAGE (V)
4.8
5.2
5.6
0.50
IL = 0mA
0
–40
6.0
Figure 6. Ground Current vs. Supply Voltage
02712-009
1.00
60
02712-006
GROUND CURRENT (mA)
4.50
IL = 0µA
–20
0
20
40
60
JUNCTION TEMPERATURE (°C)
80
Figure 9. Ground Current vs. Junction Temperature
Rev. D | Page 6 of 16
100
ADP3342
VOUT (V)
0.20
VCC = 3V
CL = 1µF
RL = 4Ω
1.32
1.22
0.15
1.12
0.10
VIN (V)
3.00
1.80
02712-013
0.05
02712-010
INPUT–OUTPUT VOLTAGE (V)
0.25
0
0
50
100
150
200
OUTPUT LOAD (mA)
250
0
300
40
80
120
TIME (µs)
7.0
VCC = 3V
CL = 10µF
RL = 4Ω
VCC = 3.0V
VIN = 1.8V
VOUT (V)
6.0
5.5
5.0
1.32
1.22
4.5
MAX
1.12
4.0
3.5
3.00
VIN (V)
TYP
3.0
2.5
1.80
2.0
1.5
1.0
–40
02712-014
MIN
02712-011
GROUND CURRENT @ 300mA LOAD (mA)
200
Figure 13. Line Transient Response
Figure 10. Dropout Voltage vs. Output Current
6.5
160
–25
–10
5
20
35
50
TEMPERATURE (°C)
65
80
0
95
Figure 11. Ground Current @ 300 mA Load vs. Ambient Temperature
40
80
120
TIME (µs)
160
200
Figure 14. Line Transient Response
6
VOUT = 1.2V
SD = VIN
RL = 4Ω
VOUT (V)
1.3
4
1.2
VCC = 3V
VIN = 1.8V
CL = 1µF
1.1
3
2
400
IOUT (mA)
1
0
–2
0
200
400
600
TIME (µs)
800
200
5
02712-015
–1
02712-012
INPUT–OUTPUT VOLTAGE (V)
5
0
1000
400
800
1200
TIME (µs)
Figure 15. Load Transient Response
Figure 12. Power-Up/Power-Down
Rev. D | Page 7 of 16
1600
2000
ADP3342
2.0
OUTPUT (V)
1.2
VCC = 3V
VIN = 1.8V
CL = 10µF
PWRGD (V)
1.1
200
VCC = 3V
VIN = 1.8V
RL = 4Ω
0
3.0
0
1.8
02712-016
5
SD (V)
IOUT (mA)
400
1.0
0
400
800
1200
TIME (µs)
1600
0
2000
02712-019
VOUT (V)
1.3
0
100
Figure 16. Load Transient Response
OUTPUT (V)
PWRGD (V)
0.5
1.0
0
VCC = 3V
VIN = 1.8V
RL = 4Ω
3.0
0
1.8
02712-017
0
SD (V)
IOUT (A)
500
0
200
400
600
TIME (µs)
800
0
1000
02712-020
VOUT (V)
0
1.0
2
Figure 17. Short-Circuit Current
OUTPUT (V)
VCC = 3V
RL = 4Ω
VIN = 1.8V
2.0
6
10
TIME (µs)
14
18
Figure 20. Turn-Off Delay
1.0
0
VOUT = 1.8V
SD = 3.0V
RL = 4Ω
2.0
1.0
0
3.0
0
VCC (V)
1.8
–200
200
600
1000
TIME (µs)
1400
3.0
0
02712-018
0
02712-021
OUTPUT (V)
400
2.0
VIN = 1.8V
PWRGD (V)
300
TIME (µs)
Figure 19. Turn-On Delay
1.2
SD (V)
200
200
1800
Figure 18. Power-On/Power-Off Response from Shutdown
600
1000
TIME (µs)
1400
1800
Figure 21. Power-On/Power-Off Response from VCC
Rev. D | Page 8 of 16
ADP3342
60
1.2
50
RMS NOISE (µV)
3.0
0
40
300mA
30
0mA
1.8
20
0
10
200
400
600
TIME (µs)
800
0
1000
0
40
50
100
VOUT = 1.2V
VOUT = 1.2V
IL = 1mA
CL = 10µF
IL = 300mA
–30
VOLTAGE NOISE SPECTRAL
DENSITY (µV/√Hz)
CL = 1µF
IL = 300mA
–40
CL = 1µF
IL = 50µA
–60
–70
CL = 10µF
IL = 50µA
–80
100
1k
10k
100k
FREQUENCY (Hz)
1M
10
CL = 10µF
1
CL = 1µF
0.1
0.01
02712-023
RIPPLE REJECTION (dB)
30
Figure 24. RMS Noise vs. CL (10 Hz to 100 Hz)
–20
–90
10
20
CL (µF)
Figure 22. Power-On/Power-Off Response from VIN
–50
10
0.001
10
10M
Figure 23. Power Supply Ripple Rejection
02712-025
0
02712-024
VIN = 1.8V
SD = 3.0V
RL = 4Ω
0
02712-022
VIN (V)
PWRGD (V)
OUTPUT (V)
70
100
1k
10k
FREQUENCY (Hz)
Figure 25. Output Noise Density
Rev. D | Page 9 of 16
100k
1M
ADP3342
1.25
VCC (V)
3.6
1.23
3.0
VIN = 1.8V
SD = 3V
1.21
100mA
200mA
400
300mA
1.15
35
55
75
95
115
135
AMBIENT TEMPERATURE (°C)
155
0
175
650
ICL (mA)
600
02712-027
550
1.6
1.7
1.8
15
25
TIME (ms)
35
Figure 28. Current Limit vs. VCC
Figure 26. Thermal Protection
500
1.5
200
0
02712-026
1.17
02712-028
1.19
ICL (mA)
OUTPUT VOLTAGE (V)
0mA
50mA
1.9
2.0
VIN (V)
Figure 27. Current Limit vs. VIN
Rev. D | Page 10 of 16
45
ADP3342
THEORY OF OPERATION
The anyCAP LDO ADP3342 uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider consisting of R1 and R2. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
VCC
OUTPUT
COMPENSATION
ATTENUATION
CAPACITOR
(VBAND GAP/VOUT)
Q1
NONINVERTING
WIDEBAND
DRIVER
gm
R3
PTAT
VOS
R4
ADP3342
R1
CLOAD
D1
(a)
PTAT
CURRENT
RLOAD
R2
GND
02712-029
INPUT
Figure 29. Control Loop Functional Block Diagram
A very high gain error amplifier is used to control this loop.
The amplifier is constructed in such a way that, at equilibrium,
it produces a large, temperature proportional input offset voltage that is repeatable and very well controlled. The temperature
proportional offset voltage is combined with the complementary
diode voltage to form a virtual band gap voltage, implicit in the
network, although it never appears explicitly in the circuit.
Ultimately, this patented design makes it possible to control the
loop with only one amplifier. This technique also improves the
noise characteristics of the amplifier by providing more flexibility on the trade-off of noise sources that lead to a low noise
design.
The R1, R2 divider is chosen in the same ratio as the band gap
voltage to the output voltage. Although the R1, R2 resistor divider
is loaded by Diode D1 and a second divider consisting of R3
and R4, the values can be chosen to produce a temperature stable
output. This unique arrangement specifically corrects for the
loading of the divider so that the error resulting from base current loading in conventional circuits is avoided.
The patented amplifier controls a unique noninverting driver
that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole splitting arrangement to
achieve reduced sensitivity to the value, type, and ESR of the
load capacitance.
Most LDOs place very strict requirements on the range of ESR
values for the output capacitor because they are difficult to
stabilize due to the uncertainty of load capacitance and resistance.
Moreover, the ESR value required to keep conventional LDOs
stable, changes depending on load and temperature. These ESR
limitations make designing with LDOs more difficult because of
their unclear specifications and extreme variations over
temperature.
With the ADP3342 anyCAP LDO, this is no longer true. It can
be used with virtually any good quality capacitor, with no constraint on the minimum ESR. This innovative design allows the
circuit to be stable with just a small 1 µF capacitor on the output.
Additional advantages of the pole splitting scheme include
superior line noise rejection and very high regulator gain,
resulting in excellent line and load regulation. Additional features
of the circuit include current limit, thermal shutdown, and noise
reduction.
Rev. D | Page 11 of 16
ADP3342
APPLICATION INFORMATION
PC APPLICATION—VCCVID
SHUTDOWN MODE
The ADP3342 has been optimized for PC applications that
require a 1.2 V output for powering the voltage identification
rail, VCCVID. The rail from which the output draws current, the
IN pin, is separated from the rail that powers the IC, the VCC
pin. This allows a higher efficiency design when, as recommended for IMVP-3/5 applications, the VCC pin is connected
to a 3.3 V supply to power the IC adequately, and the IN pin is
connected to a 1.8 V supply. The efficiency is nearly 60% in this
case.
Applying a TTL high signal to the shutdown (SD) pin, or tying
it to the VCC input pin, turns on the output. Pulling SD down
to 0.4 V or below, or tying it to ground, turns off the output. In
shutdown mode, quiescent current is reduced.
CAPACITOR SELECTION
As with any voltage regulator, output transient response is a
function of the output capacitance. The ADP3342 is stable with
a wide range of capacitor values, types, and ESR (anyCAP). A
capacitor as low as 1 µF is all that is needed for stability; larger
capacitors can be used if high output current surges are anticipated. The ADP3342 is stable with extremely low ESR capacitors
(ESR ≈ 0), such as multilayer ceramic capacitors (MLCC) or
OSCON. The effective capacitance of some capacitor types may
fall below the minimum at cold temperature. Ensure that the
capacitor provides more than 1 µF at minimum temperature.
INPUT BYPASS CAPACITOR
THERMAL OVERLOAD PROTECTION
The ADP3342 is protected against damage due to excessive
power dissipation by its thermal overload protection circuit,
which limits the die temperature to a maximum of 165°C.
Under extreme conditions, that is, high ambient temperature
and power dissipation where die temperature starts to rise
above 165°C, the output current is reduced until the die temperature drops to a safe level. The output current is restored when
the die temperature is reduced.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, device power dissipation should be limited by operating conditions so that the junction temperature does not
exceed 150°C.
CALCULATING JUNCTION TEMPERATURE
Device power dissipation is calculated as follows:
An input bypass capacitor is not strictly required but is advisable
in any application involving long input wires or high source
impedance. Connecting a 1 µF capacitor from IN to ground
reduces the circuit’s sensitivity to PC board layout. If a larger
value output capacitor is used, a larger value input capacitor is
also recommended.
PD = (VIN − VOUT) × ILOAD + VIN × IGND
where ILOAD and IGND are load current and ground current, and
VIN and VOUT are input and output voltages, respectively.
Assuming that ILOAD = 300 mA, IGND = 4 mA, VIN = 1.8 V, and
VOUT = 1.2 V, device power dissipation is
POWER GOOD MONITORING FUNCTION
The PWRGD pin does not monitor the output voltage directly
but rather detects whether the internal PNP pass transistor is
being modulated by the regulation loop. This method of
detecting PWRGD, rather than using a voltage threshold
detection, provides an inherent and desirable delay in asserting
the PWRGD signal. During startup or overload, the regulation
loop is not in control, so the PWRGD pin is low.
PD = (1.8 V − 1.2 V) × 300 mA + (1.8 V) × 4 mA = 187 mW
The ADP3342 is capable of supplying 300 mA @ VIN = 1.8 V in
a typical notebook PC application. If a higher input voltage,
such as 3.3 V, is used, the power dissipation of the ADP3342 is
limited by the thermal overload protection. Assuming a 4-layer
board, the junction temperature rise above ambient
temperature is approximately equal to
ΔTJA = 193 mW × 142°C/W = 27.4°C
Rev. D | Page 12 of 16
ADP3342
OUTLINE DIMENSIONS
3.00
BSC
8
3.00
BSC
1
5
4.90
BSC
4
PIN 1
0.65 BSC
1.10 MAX
0.15
0.00
0.38
0.22
COPLANARITY
0.10
0.23
0.08
8°
0°
0.80
0.60
0.40
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 30. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADP3342JRM-REEL
ADP3342JRM-REEL7
ADP3342JRMZ-REEL71
1
Output
Voltage
1.2 V
1.2 V
1.2 V
Temperature
Range
0°C to 100°C
0°C to 100°C
0°C to 100°C
Package Description
8-Lead Mini Small Outline Package (MSOP)
8-Lead Mini Small Outline Package (MSOP)
8-Lead Mini Small Outline Package (MSOP)
Z = Pb-free part.
Rev. D | Page 13 of 16
Package
Option
RM-8
RM-8
RM-8
Branding
LJA
LJA
LJA
ADP3342
NOTES
Rev. D | Page 14 of 16
ADP3342
NOTES
Rev. D | Page 15 of 16
ADP3342
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02712–0–2/05(D)
Rev. D | Page 16 of 16
