ADP3408ARU-25

a FEATURES Handles all GSM Baseband Power Management Six LDOs Optimized for Specific GSM Subsystems Li-Ion and NiMH Battery Charge Function Optimized for the AD20msp430 Baseband Chipset APPLICATIONS GSM/DCS/PCS/CDMA Handsets GSM Power Management System ADP3408 FUNCTIONAL BLOCK DIAGRAM VBAT VBAT2 VRTCIN SIM LDO DIGITAL CORE LDO ANALOG LDO POWER-UP SEQUENCING AND PROTECTION LOGIC TCXO LDO MEMORY LDO RTC LDO REF BUFFER VSIM VCORE PWRONKEY ROWX PWRONIN VAN VTCXO TCXOEN SIMEN VMEM VRTC GENERAL DESCRIPTION RESCAP 26 REFOUT The ADP3408 is a multifunction power system chip optimized for GSM handsets, especially those based on the Analog Devices AD20msp430 system solution. It contains six LDOs, one to power each of the critical GSM sub-blocks. Sophisticated controls are available for power-up during battery charging, keypad interface, and RTC alarm. The charge circuit maintains low current charging during the initial charge phase and provides an end-of-charge signal when a Li-Ion battery is being charged. The ADP3408 is specified over the temperature range of –20°C to +85°C and is available in narrow body TSSOP-28 pin package. RESET CHRDET EOC CHGEN GATEIN BATSNS ISENSE GATEDR CHRIN BATTERY CHARGE CONTROLLER BATTERY CHARGE DIVIDER MVBAT DGND ADP3408 27 AGND R EV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 ≤ +85 , VBAT = VBAT2 3 CVCORE = CVAN ADP3408–SPECIFICATIONS1 (–2010C ≤F,TminimumCloads applied on=all V–5.5 V, CVSIM =otherwise noted.) = CVMEM = 2.2 F, VTCXO = 0.22 F, CVRTC = 0.1 F, CVBAT = outputs, unless A Parameter SHUTDOWN SUPPLY CURRENT VBAT ≤ 2.5 V (Deep Discharged Lockout Active) 2.5 V < VBAT ≤ 3.2 V (UVLO Active) VBAT > 3.2 V OPERATING GROUND CURRENT VSIM, VCORE, VMEM, VRTC On All LDOs On Symbol ICC Condition VBAT = VBAT2 = 2.3 V VBAT = VBAT2 = 3.0 V VBAT = VBAT2 = 4.0 V Min Typ 7 30 45 225 345 1.0 Max 20 55 80 300 450 3.0 Unit µA µA µA µA µA % of max load current V mV IGND VBAT = 3.6 V Minimum Loads Minimum Loads Maximum Loads UVLO ON THRESHOLD UVLO HYSTERESIS DEEP DISCHARGED LOCKOUT ON THRESHOLD DEEP DISCHARGED LOCKOUT HYSTERESIS INPUT HIGH VOLTAGE (PWRONIN, TCXOEN, SIMEN, CHGEN, GATEIN) INPUT LOW VOLTAGE (PWRONIN, TCXOEN, SIMEN, CHGEN, GATEIN) INPUT HIGH BIAS CURRENT (PWRONIN, TCXOEN, SIMEN, CHGEN, GATEIN) INPUT LOW BIAS CURRENT (PWRONIN, TCXOEN, SIMEN, CHGEN, GATEIN) PWRONKEY INPUT HIGH VOLTAGE PWRONKEY INPUT LOW VOLTAGE PWRONKEY INPUT PULL-UP RESISTANCE TO VBAT THERMAL SHUTDOWN THRESHOLD2 THERMAL SHUTDOWN HYSTERESIS ROWX CHARACTERISTICS ROWX Output Low Voltage ROWX Output High Leakage Current SIM CARD LDO (VSIM) Output Voltage Line Regulation Load Regulation Output Capacitor Required for Stability Dropout Voltage DIGITAL CORE LDO (VCORE) Output Voltage ADP3408ARU-2.5 ADP3408ARU-1.8 Line Regulation Load Regulation Output Capacitor Required for Stability VBAT VBAT VBAT VBAT VIH 2.0 3.2 200 2.4 100 3.3 2.75 V mV V VIL 0.4 V IIH 1.0 µA IIL –1.0 µA VIH VIL 0.7 × VBAT 0.3 × VBAT 70 100 160 45 130 V V kΩ ºC ºC VOL IIH PWRONKEY = Low IOL = 200 µA PWRONKEY = High V(ROWX) = 5 V Line, Load, Temp Min Load 50 µA ≤ ILOAD ≤ 20 mA, VBAT = 3.6 V VO = VINITIAL – 100 mV, ILOAD = 20 mA 2.80 2.85 2 1 0.4 1 2.92 V µA V mV mV µF VSIM ∆VSIM ∆VSIM CO VDO 2.2 35 100 mV VCORE VCORE ∆VCORE ∆VCORE CO Line, Load, Temp Line, Load, Temp Min Load 50 µA ≤ ILOAD ≤ 100 mA, VBAT = 3.6 V 2.40 1.75 2.45 1.80 2 7 2.50 1.85 V V mV mV µF 2.2 –2– REV. 0 ADP3408 Parameter RTC LDO REAL-TIME CLOCK LDO/ COIN CELL CHARGER (VRTC) Maximum Output Voltage ADP3408ARU-2.5 ADP3408ARU-1.8 Off Reverse Input Current Output Capacitor Required for Stability ANALOG LDO (VAN) Output Voltage Line Regulation Load Regulation Output Capacitor Required for Stability Ripple Rejection Output Noise Voltage Symbol Condition Min Typ Max Unit VRTC VRTC IL CO VAN ∆VAN ∆VAN CO ∆VBAT/ ∆VAN3 VNOISE 1 µA ≤ ILOAD ≤ 10 µA 1 µA ≤ ILOAD ≤ 10 µA VBAT = 2.15 V, TA = 25°C 2.39 1.80 0.1 2.45 1.95 2.51 2.1 0.5 V V µA µF V mV mV µF dB Line, Load, Temp Min Load 50 µA ≤ ILOAD ≤ 130 mA, VBAT = 3.6 V f = 217 Hz VBAT = 3.6 V f = 10 Hz to 100 kHz ILOAD = 130 mA VBAT = 3.6 V Line, Load, Temp Min Load 50 µA ≤ ILOAD ≤ 20 mA, VBAT = 3.6 V VO = VINITIAL – 100 mV ILOAD = 20 mA f = 217 Hz VBAT = 3.6 V f = 10 Hz to 100 kHz ILOAD = 20 mA, VBAT = 3.6 V Line, Load, Temp Min Load 50 µA < ILOAD < 60 mA, VBAT = 3.6 V 2.40 2.45 2 8 2.50 2.2 65 80 µV rms TCXO LDO (VTCXO) Output Voltage Line Regulation Load Regulation Output Capacitor Required for Stability Dropout Voltage Ripple Rejection Output Noise Voltage VTCXO ∆VTCXO ∆VTCXO CO VDO ∆VBAT/ ∆VTCXO VNOISE 2.66 2.715 2 1 2.77 V mV mV µF mV dB 0.22 160 65 80 310 µV rms MEMORY LDO (VMEM) Output Voltage Line Regulation Load Regulation Output Capacitor Required for Stability Dropout Voltage REFOUT Output Voltage Line Regulation Load Regulation Ripple Rejection Maximum Capacitive Load Output Noise Voltage RESET GENERATOR (RESET) Output High Voltage Output Low Voltage Output Current Delay Time per Unit Capacitance Applied to RESCAP Pin BATTERY VOLTAGE DIVIDER Divider Ratio Divider Impedance at MVBAT Divider Leakage Current Divider Resistance VMEM ∆VMEM ∆VMEM CO 2.744 2.80 2 3 2.856 2.2 80 180 1.23 V mV mV mV µF mV V mV mV dB pF µV rms VREFOUT ∆VREFOUT ∆VREFOUT ∆VBAT/ ∆VREFOUT CO VNOISE Line, Load, Temp Min Load 0 µA < ILOAD < 50 µA VBAT = 3.6 V f = 217 Hz VBAT = 3.6 V, ILOAD = 50 µA f = 10 Hz to 100 kHz, VBAT = 3.6 V IOH = 500 µA IOL = –500 µA VOL = 0.25 V, VOH = VMEM – 0.25 V 1.19 1.210 0.2 0.5 75 65 100 40 VOH VOL IOL/IOH TD VMEM – 0.25 0.25 1 0.6 1.2 2.4 V V mA ms/nF BATSNS/MVBAT ZO TCXOEN = High TCXOEN = Low TCXOEN = High 2.32 59.5 215 2.35 85 300 2.37 110 1 385 kΩ kΩ µA kΩ REV. 0 –3– ADP3408 Parameter BATTERY CHARGER Charger Output Voltage Load Regulation Symbol BATSNS ∆BATSNS Condition 4.35 V ≤ CHRIN ≤ 10 V3 CHGEN = Low, No Load CHRIN = 5 V 0 ≤ CHRIN – ISENSE < Current Limit Threshold CHGEN = Low Min 4.150 Typ 4.200 Max 4.250 15 Unit V mV CHRDET On Threshold CHRDET Off Threshold CHRDET Off Delay4 CHRIN Supply Current BATTERY CHARGER Current Limit Threshold High Current Limit (UVLO Not Active) Low Current Limit (UVLO Active) ISENSE Bias Current End-of-Charge Signal Threshold CHRIN – BATSNS CHRIN – BATSNS CHRIN < VBAT CHRIN = 5 V CHRIN – ISENSE CHRIN = 5 V dc VBAT = 3.6 V CHGEN = Low VBAT = 2 V CHGEN = Low CHRIN = 5 V 30 15 90 45 6 0.6 150 100 mV mV ms/nF mA 142 160 190 mV 20 35 mV µA 200 CHRIN – ISENSE CHRIN = 5 V VBAT > 4.0 V CHGEN = Low CHGEN = Low CHRIN = 5 V VBAT > 3.6 V CHGEN = High, CL = 2 nF CHRIN = 5 V VBAT = 3.6 V CHGEN = High, GATEIN = High IOH = –1 mA CHRIN = 5 V VBAT = 3.6 V CHGEN = High GATEIN = Low IOL = 1 mA IOH = –250 µA IOL = +250 µA CHRIN = 7.5 V CHGEN = High GATEIN = Low CHRIN = 7.5 V CHGEN = High GATEIN = Low 5.30 5.50 3.82 0.1 14 35 mV EOC Reset Threshold GATEDR Transition Time VBAT tR, tF 3.96 4.10 1 V µs GATEDR High Voltage VOH 4.5 V GATEDR Low Voltage VOL 0.5 V Output High Voltage (EOC, CHRDET) Output Low Voltage (EOC, CHRDET) Battery Overvoltage Protection Threshold (GATEDR → High) Battery Overvoltage Protection Hysteresis VOH VOL BATSNS 2.4 0.25 5.70 V V V BATSNS 200 mV NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 This feature is intended to protect against catastophic failure of the device. Maximum allowed operating junction temperature is 125ºC. Operation beyond 125ºC could cause permanent damage to the device. 3 No isolation diode present between charger input and battery. 4 Delay set by external capacitor on the RESCAP pin. Specifications subject to change without notice. –4– REV. 0 ADP3408 ABSOLUTE MAXIMUM RATINGS * PIN FUNCTION DESCRIPTIONS Voltage on any pin with respect to any GND Pin . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +10 V Voltage on any pin may not exceed VBAT, with the following exceptions: CHRIN, GATEDR, ISENSE Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Operating Ambient Temperature Range . . . . . –20°C to +85°C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125°C θJA, Thermal Impedance (TSSOP-28) 4-Layer PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W 1-Layer PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98°C/W Lead Temperature Range (Soldering, 60 sec.) . . . . . . . . 300°C *This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Mnemonic PWRONIN PWRONKEY ROWX SIMEN VRTCIN VRTC BATSNS MVBAT CHRDET CHRIN GATEIN GATEDR DGND ISENSE EOC CHGEN RESCAP RESET VSIM VBAT2 VMEM VCORE VBAT VAN VTCXO REFOUT AGND TCXOEN Function Power On/Off Signal from Microprocessor Power-On/-Off Key Power Key Interface Output SIM LDO Enable RTC LDO Input Voltage Real-Time Clock Supply/ Coin Cell Battery Charger Battery Voltage Sense Input Divided Battery Voltage Output Charge Detect Output Charger Input Voltage Microprocessor Gate Input Signal Gate Drive Output Digital Ground Charge Current Sense Input End of Charge Signal Charger Enable for GATEIN, NiMH Pulse Charging Reset Delay Time Main Reset SIM LDO Output Battery Input Voltage 2 Memory LDO Output Digital Core LDO Output Battery Input Voltage Analog LDO Output TCXO LDO Output Output Reference Analog Ground TCXO LDO Enable and MVBAT Enable ORDERING GUIDE Model Core LDO Output Temperature Voltage Range –20°C to +85°C –20°C to +85°C Package Option* RU-28 RU-28 ADP3408ARU-2.5 2.5 V ADP3408ARU-1.8 1.8 V *RU = Thin Shrink Small Outline PIN CONFIGURATION PWRONIN 1 PWRONKEY 2 ROWX 3 SIMEN 4 VRTCIN 5 VRTC 6 BATSNS 7 28 TCXOEN 27 AGND 26 REFOUT 25 VTCXO 24 VAN ADP3408 23 VBAT TOP VIEW 22 VCORE (Not to Scale) 21 VMEM MVBAT 8 20 VBAT2 19 VSIM 18 RESET 17 RESCAP 16 CHGEN 15 EOC CHRDET 9 CHRIN 10 GATEIN 11 GATEDR 12 DGND 13 ISENSE 14 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3408 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 –5– ADP3408 Table I. LDO Control Logic VAN and REFOUT PWRONKEY PWRONIN CHRDET TCXOEN PHONE STATUS State #1 Battery Deep Discharged State #2 Phone Off State #3 Phone Off, Turn-On Allowed State #4 Charger Applied State #5 Phone Turned On by User Key State #6 Phone Turned On by BB State #7 Enable SIM Card State #8 Phone and TCXO LDO Kept On by BB L H X L X X X X X X L L X X OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON OFF H H H H L H H X L X L L X L OFF OFF OFF OFF OFF OFF ON ON ON ON ON ON OFF OFF H H H H H H X L L L H H X H H L L L L L H OFF OFF ON ON ON ON ON ON ON ON ON ON ON ON OFF OFF OFF OFF OFF OFF OFF H H L H H H H ON ON ON ON ON ON ON *UVLO is active only when phone is turned off. UVLO is ignored once the phone is turned on. –6– MVBAT VTCXO VCORE UVLO* SIMEN VMEM DDLO VRTC VSIM REV. 0 Typical Performance Characteristics– ADP3408 450 400 350 1000 10000 1.8 REVERSE LEAKAGE CURRENT – A ALL LDO, MVBAT, REFOUT, ON_MIN_LOAD (SIMEN = H, TCXOEN = H) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 25 30 35 40 45 50 55 60 65 70 75 80 85 TEMPERATURE – C RTC REVERSE LEAKAGE (VBAT = 2.3V) RTC REVERSE LEAKAGE (VBAT = FLOAT) –20 C +85 C 300 250 200 150 100 3.0 IGND – VSIM, VCORE, VMEM, VRTC, ON_MIN_LOAD (SIMEN = H, TCXOEN = L) I VRTC – A A +25 C 100 VCORE, VMEM, VRTC, ON_MIN_LOAD (SIMEN = L, TCXOEN = L) 10 3.5 4.0 4.5 VBAT – V 5.0 5.5 0 0.5 1.0 1.5 VRTC – V 2.0 2.5 TPC 1. Ground Current vs. Battery Voltage TPC 2. RTC I/V Characteristic TPC 3. VRTC Reverse Leakage Current vs. Temperature 180 160 DROPOUT VOLTAGE – mA 3.2 VTCXO 3.2 140 120 100 80 60 40 20 0 0 20 40 60 LOAD CURRENT – mA 80 VSIM VMEM VBAT 3.0 3.0 VBAT VTCXO VMEM 10mV/DIV 10mV/DIV VTCXO VMEM 10mV/DIV 10mV/DIV TIME – 100 s/DIV TIME – 100 s/DIV TPC 4. Dropout Voltage vs. Load Current TPC 5. Line Transient Response, Minimum Loads TPC 6. Line Transient Response, Maximum Loads 3.2 3.2 20mA VBAT 3.0 VAN VCORE VSIM 10mV/DIV 10mV/DIV 10mV/DIV 3.0 VBAT LOAD 3mA VTCXO VMEM 10mV/DIV 10mV/DIV VTCXO 10mV/DIV TIME – 100 s/DIV TIME – 100 s/DIV TIME – 200 s/DIV TPC 7. Line Transient Response, Minimum Loads TPC 8. Line Transient Response, Maximum Loads TPC 9. VTCXO Load Step REV. 0 –7– ADP3408 100mA 20mA LOAD 3mA LOAD 60mA 5mA LOAD 10mA VSIM 5mV/DIV VMEM 10mV/DIV VCORE 10mV/DIV TIME – 200 s/DIV TIME – 200 s/DIV TIME – 200 s/DIV TPC 10. VSIM Load Step TPC 11. VMEM Load Step TPC 12. VCORE Load Step 130mA PWRONIN (2V/DIV) VAN (100mV/DIV) PWRONIN (2V/DIV) REFOUT (100mV/DIV) LOAD 10mA VSIM (100mV/DIV) VAN 10mV/DIV VCORE (100mV/DIV) VTCXO (100mV/DIV) VMEM (100mV/DIV) TIME – 200 s/DIV TIME – 400 s/DIV TIME – 100 s/DIV TPC 13. VAN Load Step TPC 14. Turn On Transient by PWRONIN, Minimum Load (Part 1) TPC 15. Turn On Transient by PWRONIN, Minimum Load (Part 2) 80 PWRONIN (2V/DIV) PWRONIN (2V/DIV) RIPPLE REJECTION – dB 70 VAN 60 VTCXO REFOUT (100mV/DIV) VAN (100mV/DIV) VCORE 50 40 30 20 10 0 MLCC OUTPUT CAPS VBAT = 3.2V, FULL LOADS REFOUT VSIM (100mV/DIV) VMEM (100mV/DIV) VCORE (100mV/DIV) TIME – 20 s/DIV VTCXO (100mV/DIV) TIME – 20 s/DIV 4 10 100 1k 10k FREQUENCY – Hz 100k TPC 16. Turn On Transient by PWRONIN, Maximum Load (Part 1) TPC 17. Turn On Transient by PWRONIN, Maximum Load (Part 2) TPC 18. Ripple Rejection vs. Frequency –8– REV. 0 ADP3408 VOLTAGE SPECTRAL NOISE DENSITY – nV/ Hz 80 70 RIPPLE REJECTION – dB REFOUT 600 FULL LOAD MLCC CAPS VAN CHARGER VOUT – V 4.25 4.24 4.23 4.22 4.21 4.20 4.19 4.18 4.17 4.16 500 60 50 40 VTCXO 30 20 10 0 2.5 FREQUENCY = 217Hz MAX LOADS 2.6 2.7 2.8 2.9 3.0 VBAT – V 3.1 3.2 3.3 VMEM VCORE VAN VSIM 400 TCXO 300 200 REF 100 0 10 100 1k 10k FREQUENCY – Hz 100k 4.15 –40 –20 0 20 40 60 80 100 120 TEMPERATURE – C TPC 19. Ripple Rejection vs. Battery Voltage 4.24 VIN = 5.0V RSENSE = 250m TPC 20. Output Noise Density TPC 21. Charger V OUT vs. Temperature, VIN = 5.0 V, ILOAD = 10 mA 4.24 RSENSE = 250m OUTPUT VOLTAGE – V OUTPUT VOLTAGE – V 4.23 4.23 4.22 4.22 ILOAD = 500mA 4.21 ILOAD = 10mA 4.21 4.20 0 200 400 ILOAD – mA 600 800 4.20 5 6 7 8 INPUT VOLTAGE – V 9 10 TPC 22. Charger V OUT vs. I LOAD (VIN = 5.0 V) TPC 23. Charger VOUT vs. VIN REV. 0 –9– ADP3408 VBAT VRTCIN VBAT2 SIM LDO VBAT 100k Q PWRONKEY ROWX S UVLO DEEP DISCHARGED UVLO VREF EN DGND OUT VSIM R OVER- TEMP SHUTDOWN DIGITAL CORE LDO VBAT VREF EN DGND OUT PG VCORE PWRONIN ANALOG LDO VBAT SIMEN CHARGER DETECT TCXOEN RESCAP CHRDET VBAT VREF EN EOC CHGEN GATEIN BATSNS ISENSE GATEDR CHRIN LI-ION BATTERY CHARGE CONTROLLER AND PROCESSOR CHARGE INTERFACE MEMORY LDO VBAT VREF EN DGND OUT VMEM AGND OUT VTCXO RESET GENERATOR RESET TCXO LDO VREF EN AGND OUT VAN RTC LDO VBAT VREF EN DGND OUT VRTC MVBAT EN REF BUFFER REFOUT ADP3408 1.21V AGND + – AGND DGND Figure 1. Functional Block Diagram EOC CHGEN GATEIN D1 BATSNS Q1 SI3441DY GATEDR ISENSE R1 0.2 C1 10nF CHRIN (10V MAX) CHRDET ADP3408 BATTERY CHARGE CONTROLLER Figure 2. Battery Charger Typical Application –10– REV. 0 ADP3408 PWRON PWRONKEY KEYPADROW GPIO PWRONIN PWRONKEY ROWX SIMEN VRTCIN VRTC CAPACITOR TYPE BACKUP COIN CELL AUXADC GPIO CHARGER IN GPIO R1 0.33 Q1 SI3441DY D1 LI OR NIMH BATTERY C2, 10nF GATEDR DGND ISENSE RESCAP CHGEN EOC C4 0.1 F C1 0.1 F VRTC TCXOEN AGND REFOUT VTCXO R2 10 REF VTCXO C3, 10 F VAN C8 2.2 F C9 0.22 F C10 0.1 F VCORE VMEM C6 2.2 F VSIM RESET C5 2.2 F C7 2.2 F GPIO GPIO CLKON U1 VAN VBAT VCORE VMEM VBAT2 VSIM RESET ADP3408 BATSNS MVBAT CHRDET CHRIN GATEIN Figure 3. Typical Application Circuit THEORY OF OPERATION The ADP3408 is a power management chip optimized for use with GSM baseband chipsets in handset applications. Figure 1 shows a block diagram of the ADP3408. The ADP3408 contains several blocks: • Six Low Dropout Regulators (SIM, Core, Analog, Crystal Oscillator, Memory, Real-Time Clock) • • • • • • Reset Generator Buffered Precision Reference Lithium Ion Charge Controller and Processor Interface Power-On/-Off Logic Undervoltage Lockout Deep Discharge Lockout However, high battery voltages normally occur only when the battery is being charged and the handset is not in conversation mode. In this mode there is a relatively light load on the LDOs. A fully charged Li-Ion battery is 4.25 V, where the ADP3408 can deliver the maximum power (0.56W) up to 85°C ambient temperature. 1.2 1.0 POWER DISSIPATION – W 0.8 0.6 These functions have traditionally been done either as a discrete implementation or as a custom ASIC design. The ADP3408 combines the benefits of both worlds by providing an integrated standard product where every block is optimized to operate in a GSM environment while maintaining a cost competitive solution. Figure 3 shows the external circuitry associated with the ADP3408. Only a minimal number of support components are required. Input Voltage 0.4 0.2 0.0 –20 0 20 40 60 AMBIENT TEMPERATURE – C 80 100 The input voltage range of the ADP3408 is 3 V to 5.5 V and is optimized for a single Li-Ion cell or three NiMH cells. The thermal impedance of the ADP3408 is 68°C/W for four-layer boards. The end-of-charge voltage for high capacity NiMH cells can be as high as 5.5 V. Power dissipation should be calculated at maximum ambient temperatures and battery voltage in order not to exceed the 125°C maximum allowable junction temperature. Figure 4 shows the maximum power dissipation as a function of ambient temperature. Figure 4. Power Dissipation vs. Temperature Low Dropout Regulators (LDOs) The ADP3408 high-performance LDOs are optimized for their given functions by balancing quiescent current, dropout voltage, regulation, ripple rejection, and output noise. 2.2 µF tantalum or MLCC ceramic capacitors are recommended for use with the core, memory, SIM, and analog LDOs. A 0.22 µF capacitor is recommended for the TCXO LDO. REV. 0 –11– ADP3408 NON-CHARGING MODE ripple coming from the RF power amplifier. VAN is rated to 130 mA load, which is sufficient to supply the complete analog section of the baseband converter such as the AD652l. TCXO LDO (VTCXO) NO CHARGER DETECTER CHRIN > BATSNS YES The TCXO LDO is intended as a supply for a temperaturecompensated crystal oscillator, which needs its own ultralow noise supply. VTCXO is rated for 5 mA of output current and is turned on along with the analog LDO when TCXOEN is asserted. RTC LDO (VRTC) YES VBAT > UVLO NO LOW CURRENT CHARGE MODE VSENSE = 20mV NIMH BATTERY TYPE The RTC LDO charges up a capacitor-type backup coin cell to run the real-time clock module. It has been designed to charge electric double layer capacitors such as the PAS621 from Kanebo. The PAS621 has a small physical size (6.8 mm diameter) and a nominal capacity of 0.3 F, giving many hours of backup time. The ADP3408 supplies current both for charging the coin cell and for the RTC module when the digital supply is off. The nominal charging voltage is 2.45 V, which ensures long cell life while obtaining in excess of 90% of the nominal capacity. In addition, it features a very low quiescent current since this LDO is running all the time, even when the handset is switched off. It also has reverse current protection with low leakage, which is needed when the main battery is removed and the coin cell supplies the RTC module. SIM LDO (VSIM) LI+ CHGEN = LOW CHGEN = HIGH HIGH CURRENT CHARGE MODE VSENSE = 160mV NIMH CHARGING MODE GATEIN = PULSED NO VBAT > 4.2V The SIM LDO generates the voltage needed for 3 V SIMs. It is rated for 20 mA of supply current and can be controlled completely independently of the other LDOs. Reference Output (REFOUT) NO VBAT > 5.5V YES YES NIMH CHARGER OFF GATEIN = HIGH CONSTANT VOLTAGE MODE NO ICHARGE < I END OF CHARGE The reference output is a low noise, high precision reference with a guaranteed accuracy of 1.5% over temperature. The reference can be used with the baseband converter, if the converter’s own reference is not accurate. This will significantly reduce calibration time needed for the baseband converter during production. Note that the reference in the AD6521 has an initial accuracy of 10%, but can be calibrated to within 1%. Power ON/OFF VBAT < 5.5V NO YES EOC = HIGH YES TERMINATE CHARGE CHREN = HIGH GATEIN = HIGH The ADP3408 handles all issues regarding the powering ON and OFF of the handset. It is possible to turn on the ADP3408 in three different ways: • Pulling the PWRONKEY Low • Pulling PWRONIN High • CHRIN exceeds CHRDET Threshold Pulling the PWRONKEY low is the normal way of turning on the handset. This will turn all the LDOs on, except the SIM LDO, as long as the PWRONKEY is held low. When the VCORE LDO comes into regulation the RESET timer is started. After timing out, the RESET pin goes high, allowing the baseband processor to start up. With the baseband processor running, it can poll the ROWX pin of the ADP3408 to determine if the PWRONKEY has been depressed and pull PWRONIN high. Once the PWRONIN is taken high, the PWRONKEY can be released. Note that by monitoring the ROWX pin, the baseband processor can detect a second PWRONKEY press and turn the LDOs off in an orderly manner. In this way, the PWRONKEY can be used for ON/ OFF control. Pulling the PWRONIN pin high is how the alarm in the Real-Time Clock module will turn the handset on. Asserting PWRONIN will turn the core and memory LDOs on, starting up the baseband processor. REV. 0 Figure 5. Battery Charger Flow Chart Digital Core LDO (VCORE) The digital core LDO supplies the baseband circuitry in the handset (baseband processor and baseband converter). The LDO has been optimized for very low quiescent current at light loads as this LDO is on at all times. Memory LDO (VMEM) The memory LDO supplies the peripheral subsystems of the baseband processor including GPIO, display, and SIM interfaces as well as memory. The LDO has also been optimized for low quiescent current and will power up at the same time as the core LDO. Analog LDO (VAN) This LDO has the same features as the core LDO. It has furthermore been optimized for good low frequency ripple rejection for use with the baseband converter sections in order to reject the –12– ADP3408 Applying an external charger can also turn the handset on. This will turn on all the LDOs, except the SIM LDO, again starting up the baseband processor. Note that if the battery voltage is below the undervoltage lockout threshold, applying the adapter will not start up the LDOs. Deep Discharge Lockout (DDLO) This ensures that the handset will always power-off before the ADP3408 exceeds its absolute maximum thermal ratings. Battery Charging The DDLO block in the ADP3408 has two functions: • To shut off the VRTC LDO in the event that the main battery discharges to below the RTC LDO’s output voltage. This will force the real-time clock to run off the backup coin cell or double layer capacitor. • To shut down the handset in the event that the software fails to turn off the phone when the battery drops below 2.9 V to 3.0 V. The DDLO will shut down the handset when the battery falls below 2.4 V to prevent further discharge and damage to the cells. Undervoltage Lockout (UVLO) The ADP3408 battery charger can be used with Lithium Ion (Li+) and Nickel Metal Hydride (NiMH) batteries. The charger initialization, trickle charging, and Li+ charging are implemented in hardware. Battery type determination and NiMH charging must be implemented in software. The charger block works in three different modes: • Low Current (Trickle) Charging • Lithium Ion Charging • Nickel Metal Hydride Charging Charge Detection The UVLO function in the ADP3408 prevents startup when the initial voltage of the battery is below the 3.2 V threshold. If the battery voltage is this low with no load, there is insufficient capacity left to run the handset. When the battery is greater than 3.2 V, such as inserting a fresh battery, the UVLO comparator trips, and the threshold is reduced to 3.0 V. This allows the handset to start normally until the battery decays to below 3.0 V. Note that the DDLO has enabled the RTC LDO under this condition. Once the system is started, and the core and memory LDOs are up and running, the UVLO function is disabled. The ADP3408 is then allowed to run until the battery voltage reaches the DDLO threshold, typically 2.4 V. Normally, the battery voltage is monitored by the baseband processor and usually shuts off the phone at around 3.0 V. If the handset is off, and the battery voltage drops below 3.0 V, the UVLO circuit disables startup and puts the ADP3408 into UVLO shutdown mode. In this mode the ADP3408 draws very low quiescent current, typically 30 µA. The RTC LDO is still running until the DDLO disables it. In this mode the ADP3408 draws 5 µA of quiescent current. NiMH batteries can reverse polarity if the three-cell battery voltage drops below 3.0 V which will degrade the batteries’ performance. Lithium ion batteries will lose their capacity if repeatedly overdischarged, so minimizing the quiescent currents helps prevent battery damage. RESET The ADP3408 contains a reset circuit that is active at both power-up and power-down. The RESET pin is held low at initial power-up. An internal power good signal is generated by the core LDO when its output is up, which starts the reset delay timer. The delay is set by an external capacitor on RESCAP: t RESET = 1.2 ms × CRESCAP nF (1) The ADP3408 charger block has a detection circuit that determines if an adapter has been applied to the CHRIN pin. If the adapter voltage exceeds the battery voltage by 90 mV, the CHRDET output will go high. If the adapter is then removed and the voltage at the CHRIN pin drops to only 45 mV above the BATSNS pin, CHRDET goes low. Trickle Charging When the battery voltage is below the UVLO threshold, the charge current is set to the Low Current Limit, or about 10% of the full charge current. The low current limit is determined by the voltage developed across the current sense resistor. Therefore, the trickle charge current can be calculated by: I CHR (TRICKLE ) = 20 mV RSENSE (2) Trickle charging is performed for deeply discharged batteries to prevent undue stress on either the battery or the charger. Trickle charging will continue until the battery voltage exceeds the UVLO threshold. Once the UVLO threshold has been exceeded the charger will switch to the high current limit, the LDOs will start up, and the baseband processor will start to run. The processor must then poll the battery to determine which chemistry is present and set the charger to the proper mode. Lithium Ion Charging For lithium ion charging, the CHGEN input must be low. This allows the ADP3408 to continue charging the battery at the full current. The full charge current can be calculated by using: I CHR ( FULL ) = 160 mV RSENSE (3) At power-off, RESET will be kept low to prevent any baseband processor starts. Over-Temperature Protection If the voltage at BATSNS is below the charger’s output voltage of 4.2 V, the battery will continue to charge in the constant current mode. If the battery has reached the final charge voltage, a constant voltage is applied to the battery until the charge current has reduced to the charge termination threshold. The charge termination threshold is determined by the voltage across the sense resistor. If the battery voltage is above 4.0 V and the voltage across the sense resistor has dropped to 14 mV, an Endof-Charge signal is generated and the EOC output goes high. See Figure 6. The maximum die temperature for the ADP3408 is 125°C. If the die temperature exceeds 160°C, the ADP3408 will disable all the LDOs except the RTC LDO. The LDOs will not be REV. 0 –13– ADP3408 VBAT ICHG Separate inputs for the SIM LDO and the RTC LDO are supplied for additional bypassing or filtering. The SIM LDO has VBAT2 as its input and the RTC LDO has VRTCIN. LDO Capacitor Selection EOC The performance of any LDO is a function of the output capacitor. The core, memory, SIM, and analog LDOs require a 2.2 µF capacitor and the TCXO LDO requires a 0.22 µF capacitor. Larger values may be used, but the overshoot at startup will increase slightly. If a larger output capacitor is desired, be sure to check that the overshoot and settling time are acceptable for the application. All the LDOs are stable with a wide range of capacitor types and ESR (anyCAP® technology). The ADP3408 is stable with extremely low ESR capacitors (ESR ~ 0), such as Multilayer Ceramic Capacitors (MLCC), but care should be taken in their selection. Note that the capacitance of some capacitor types show wide variations over temperature or with dc voltage. A good quality dielectric, X7R or better, capacitor is recommended. The RTC LDO can have a rechargeable coin cell or an electric double-layer capacitor as a load, but an additional 0.1 µF ceramic capacitor is recommended for stability and best performance. RESET Capacitor Selection TIME Figure 6. End of Charge The baseband processor can either let the charger continue to charge the battery for an additional amount of time or terminate the charging. To terminate the charging, the processor must pull the GATEIN and CHGEN pins high. NiMH Charging For NiMH charging, the processor must pull the CHGEN pin high. This disables the internal Li+ mode control of the gate drive pin. The gate drive must now be controlled by the baseband processor. By pulling GATEIN high, the GATEDR pin is driven high, turning the PMOS off. By pulling the GATEIN pin low, the GATEDR pin is driven low, and the PMOS is turned on. So, by pulsing the GATEIN input, the processor can charge a NiMH battery. Note that when charging NiMH cells, a current-limited adapter is required. During the PMOS off periods, the battery voltage needs to be monitored through the MVBAT pin. The battery voltage is continually polled until the final battery voltage is reached, at which time the charge can either be terminated or the frequency of the pulsing reduced. An alternative method of determining the end of charge is to monitor the temperature of the cells and terminate the charging when a rapid rise in temperature is detected. Battery Voltage Monitoring RESET is held low at power-up. An internal power-good signal starts the reset delay when the core LDO is up. The delay is set by an external capacitor on RESCAP: ms × CRESCAP (4) nF A 100 nF capacitor will produce a 120 ms reset delay. The current capability of RESET is minimal (a few hundred nA) when VCORE is off to minimize power consumption. When VCORE is on, RESET is capable of driving 500 µA. t RESET = 1.2 Setting the Charge Current The ADP3408 is capable of charging both Lithium Ion and NiMH batteries. For NiMH batteries, the charge current is limited by the adapter. For Lithium Ion batteries, the charge current is programmed by selecting the sense resistor, R1. The Lithium Ion charge current is calculated using: I CHR = VSENSE 160 mV = R1 R1 (5) The battery voltage can be monitored at MVBAT during charging and discharging to determine the condition of the battery. An internal resistor divider can be connected to BATSNS when both the digital and analog baseband sections are powered up. To enable MVBAT both PWRONIN and TCXOEN must be high. The ratio of the voltage divider is selected so that the 2.4 V maximum input of the AD6521’s auxiliary ADC will correspond with the maximum battery voltage of 5.5 V. The divider will be disconnected from the battery when the baseband sections are powered down. APPLICATION INFORMATION Input Capacitor Selection Where VSENSE is the high current limit threshold voltage. Or if the charge current is known, R1 can be found. R1 = VSENSE 160 mV = I CHR I CHR (6) Similarly the trickle charge current and the end of charge current can be calculated: ITRICKLE = I EOC = VSENSE 20 mV = R1 R1 (7) For the input (VBAT, VBAT2, and VRTCIN) of the ADP3408, a local bypass capacitor is recommended. Use a 10 µF, low ESR capacitor. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size but may not be cost effective. A lower cost alternative may be to use a 10 µF tantalum capacitor with a small (1 µF to 2 µF) ceramic in parallel. anyCAP is a registered trademark of Analog Devices Inc. Example: Assume an 800mA-H capacity Lithium Ion battery and an 1C charge rate. R1 = 200 mΩ, ITRICKLE = 100 mA, and IEOC = 100 mA. –14– REV. 0 ADP3408 Appropriate sense resistors are available from the following vendors: Vishay Dale IRC Panasonic Charger FET Selection VDS = VADAPT ( MIN ) – VDIODE – VSENSE – VBAT = 5 V – 0.5 V – 0.160 V – 4.2 V = 140 mV RDS (ON ) = VDS 140 mV = = 175 mΩ I CHR( MAX ) 800 mA PDISS = VADAPT ( MAX ) – VDIODE – VSENSE – UVLO × I CHR PDISS The type and size of the pass transistor is determined by the threshold voltage, input-output voltage differential, and the charge current. The selected PMOS must satisfy the physical, electrical and thermal design requirements. To ensure proper operation, the minimum VGS the ADP3408 can provide must be enough to turn on the FET. The available gate drive voltage can be estimated using the following: ( ) = (6.5 V – 0.5 V – 0.160 V – 3.2) × 0.8 A = 2.11W Appropriate PMOS FETs are available from the following vendors: Siliconix IR Fairchild Charger Diode Selection VGS = VADAPTER ( MIN ) − VGATEDR − VSENSE where: (8) VADAPTER(MIN) is the minimum adapter voltage, VGATEDR is the gate drive “low” voltage, 0.5 V, and VSENSE is the maximum high current limit threshold voltage. The difference between the adapter voltage (VADPTER) and the final battery voltage (VBAT) must exceed the voltage drop due to the blocking diode, the sense resistor, and the ON resistance of the FET at maximum charge current, where: The diode, D1, shown in Figure 2, is used to prevent the battery from discharging through the PMOS’ body diode into the charger’s internal bias circuits. Choose a diode with a current rating high enough to handle the battery charging current and a voltage rating greater than VBAT. The blocking diode is required for both lithium and nickel battery types. Printed Circuit Board Layout Considerations VDS = VADAPTER( MIN ) − VDIODE − VSENSE − VBAT The RDS(ON) of the FET can then be calculated. RDS (ON ) = VDS I CHR ( MAX ) Use the following general guidelines when designing printed circuit boards: 1. Connect the battery to the VBAT, VBAT2, and VRTCIN pins of the ADP3408. Locate the input capacitor as close to the pins as possible. 2. VAN and VTCXO capacitors should be returned to AGND. 3. VCORE, VMEM and VSIM capacitors should be returned to DGND. (9) (10) The thermal characteristics of the FET must be considered next. The worst-case dissipation can be determined using: PDISS = VADAPTER (MAX ) − VDIODE − VSENSE − UVLO × I CHR ( ) (11) 4. Split the ground connections. Use separate traces or planes for the analog, digital, and power grounds and tie them together at a single point, preferably close to the battery return. 5. Run a separate trace from the BATSNS pin to the battery to prevent voltage drop error in the MVBAT measurement. 6. Kelvin-connect the charger’s sense resistor by running separate traces to the CHRIN and ISENSE pins. Make sure that the traces are terminated as close to the resistor’s body as possible. 7. Use the best industry practice for thermal considerations during the layout of the ADP3408 and charger components. Careful use of copper area, weight, and multilayer construction all contribute to improved thermal performance. It should be noted that the adapter voltage can be either preregulated or nonregulated. In the preregulated case the difference between the maximum and minimum adapter voltage is probably not significant. In the unregulated case, the adapter voltage can have a wide range specified. However, the maximum voltage specified is usually with no load applied. So, the worst-case power dissipation calculation will often lead to an over-specified pass device. In either case, it is best to determine the load characteristics of the adapter to optimize the charger design. For example: VADAPTER(MIN) = 5.0 V VADAPTER(MAX) = 6.5 V VDIODE = 0.5 V at 800 mA VSENSE = 160 mV VGATEDR = 0.5 V VGS = 5 V – 0.5 V – 160 V = 4.34 V Therefore, choose a low threshold voltage FET. REV. 0 –15– ADP3408 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Thin Shrink Small Outline (TSSOP) (RU-28) C02623–1–9/01(0) 0.028 (0.70) 0.020 (0.50) 0.386 (9.80) 0.378 (9.60) ß PIN 1 28 15 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 14 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX SEATING PLANE 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 8 0 –16– REV. 0 PRINTED IN U.S.A.