ADP3412JR-REEL7

a Dual MOSFET Driver with Bootstrapping ADP3412 FUNCTIONAL BLOCK DIAGRAM FEATURES All-In-One Synchronous Buck Driver Bootstrapped High Side Drive One PWM Signal Generates Both Drives Programmable Transition Delay Anticross-Conduction Protection Circuitry BST VCC ADP3412 APPLICATIONS Multiphase Desktop CPU Supplies Mobile Computing CPU Core Power Converters Single-Supply Synchronous Buck Converters Standard-to-Synchronous Converter Adaptations IN DLY DRVH OVERLAP PROTECTION CIRCUIT SW DRVL PGND GENERAL DESCRIPTION The ADP3412 is a dual MOSFET driver optimized for driving two N-channel MOSFETs which are the two switches in a nonisolated synchronous buck power converter. Each of the drivers is capable of driving a 3000 pF load with a 20 ns propagation delay and a 30 ns transition time. One of the drivers can be bootstrapped and is designed to handle the high voltage slew rate associated with “floating” high side gate drivers. The ADP3412 includes overlapping drive protection (ODP) to prevent shoot-through current in the external MOSFETs. 5V 12V D1 VCC BST ADP3412 CBST DRVH IN Q1 SW DLY CDLY DELAY 1V DRVL Q2 1V PGND Figure 1. General Application Circuit REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 ADP3412–SPECIFICATIONS1 (T = 0ⴗC to 70ⴗC, VCC = 5 V, BST = 4 V to 26 V, unless otherwise noted.) A Parameter Symbol SUPPLY Supply Voltage Range Quiescent Current VCC ICCQ Conditions PWM INPUT Input Voltage High2 Input Voltage Low2 HIGH SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times3 (See Figure 2) Propagation Delay3, 4 (See Figure 2) LOW SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times3 (See Figure 2) Propagation Delay3, 4 (See Figure 2) Min Typ Max Unit 4.15 5.0 1 7.5 2 V mA 0.8 V V 2.5 2.5 20 20 5 5 35 Note 5 25 Ω Ω ns ns ns 2.5 2.5 20 5 5 35 30 25 Ω Ω ns ns ns 2.0 trDRVH, tfDRVH tpdhDRVH tpdlDRVH VBST – VSW = 4.6 V VBST – VSW = 4.6 V VBST – VSW = 4.6 V, CLOAD = 3 nF VBST – VSW = 4.6 V VBST – VSW = 4.6 V trDRVL, tfDRVL tpdhDRVL tpdlDRVL VCC = 4.6 V VCC = 4.6 V VCC = 4.6 V, CLOAD = 3 nF VCC = 4.6 V VCC = 4.6 V 10 NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 µA). 3 AC specifications are guaranteed by characterization but not production tested. 4 For propagation delays, “tpdh” refers to the specified signal going high; “tpdl” refers to it going low. 5 Maximum propagation delay = 40 ns + (1 ns/pF
CDLY). Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +8 V BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +8 V SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5.0 V to +25 V IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V Operating Ambient Temperature Range . . . . . . . 0°C to 70°C Operating Junction Temperature Range . . . . . . 0°C to 125°C θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C *This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. Unless otherwise specified, all voltages are referenced to PGND. –2– REV. A ADP3412 PIN FUNCTION DESCRIPTIONS Pin Mnemonic Function 1 BST 2 3 IN DLY 4 5 6 7 VCC DRVL PGND SW 8 DRVH Floating Bootstrap Supply for the Upper MOSFET. A capacitor connected between BST and SW Pins holds this bootstrapped voltage for the high side MOSFET as it is switched. The capacitor should be chosen between 100 nF and 1 F. TTL-level input signal that has primary control of the drive outputs. Low High Transition Delay. A capacitor from this pin to ground programs the propagation delay from turn-off of the lower FET to turn-on of the upper FET. The formula for the low high transition delay is DLY = CDLY × (1 ns/pF) + 20 ns. The rise time for turn-on of the upper FET is not included in the formula. Input Supply. This pin should be bypassed to PGND with ~1 µF ceramic capacitor. Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET. Power Ground. Should be closely connected to the source of the lower MOSFET. This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turnon of the lower MOSFET until the voltage is below ~1 V. Thus, according to operating conditions, the high low transition delay is determined at this pin. Buck Drive. Output drive for the upper (buck) MOSFET. PIN CONFIGURATION BST 1 IN 2 8 DRVH ADP3412 7 SW TOP VIEW DLY 3 (Not to Scale) 6 PGND VCC 4 5 DRVL ORDERING GUIDE Model Temperature Range Package Description Package Option ADP3412JR 0°C to 70°C 8-Lead Standard Small Outline Package (SOIC) SOIC-8 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3412 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. A –3– WARNING! ESD SENSITIVE DEVICE ADP3412 IN tpdlDRVL tfDRVL trDRVL tpdlDRVH DRVL tpdhDRVH DRVH-SW tfDRVH trDRVH VTH VTH tpdhDRVL SW 1V Figure 2. Nonoverlap Timing Diagram (Timing Is Referenced to the 90% and 10% Points Unless Otherwise Noted) –4– REV. A Typical Performance Characteristics–ADP3412 30 2V/DIV 2V/DIV VCC = 5V CLOAD = 3nF DRVL DRVH 25 DRVL TIME – ns VOLTAGE VOLTAGE RISE TIME 20 DRVH IN IN VCC = 5V CLOAD = 3nF VSW = 0V VCC = 5V CLOAD = 3nF CDLY = 20pF 20ns/DIV 5 TIME – ns TIME – ns TPC 1. DRVH Fall and DRVL Rise Times 0 TPC 2. DRVL Fall and DRVH Rise Times 0 25 50 75 JUNCTION TEMPERATURE – ⴗC 85 TPC 3. DRVH Rise and Fall Times vs. Temperature 40 35 VCC = 5V CLOAD = 3nF 30 FALL TIME 10 20ns/DIV 35 15 VCC = 5V TA = 25ⴗC VCC = 5V TA = 25ⴗC 30 30 25 20 FALL TIME 15 10 TIME – ns RISE TIME TIME – ns TIME – ns 25 20 DRVH DRVL 10 DRVL 15 10 5 5 0 0 0 50 75 25 AMBIENT TEMPERATURE – ⴗC 0 85 TPC 4. DRVL Rise and Fall Times vs. Temperature 1 2 3 4 CAPACITANCE – nF 5 0 6 TPC 5. DRVH and DRVL Rise Times vs. Load Capacitance 0 VCC = 5V CLOAD = 3nF SUPPLY CURRENT – mA tpdlDRVH 20 15 tpdlDRVL 10 5 5 6 VCC = 5V fIN = 250kHz CLOAD = 3nF SUPPLY CURRENT – mA 25 2 3 4 CAPACITANCE – nF 11.0 VCC = 5V TA = 25ⴗC CLOAD = 3nF 35 1 TPC 6. DRVH and DRVL Fall Times vs. Load Capacitance 40 30 TIME – ns DRVH 20 30 25 20 15 10 10.5 10.0 9.5 5 0 0 0 25 50 75 100 JUNCTION TEMPERATURE – ⴗC TPC 7. Propagation Delay vs. Temperature REV. A 125 0 9.0 200 400 600 800 1000 IN FREQUENCY – kHz TPC 8. Supply Current vs. Frequency –5– 1200 0 25 50 75 100 JUNCTION TEMPERATURE – ⴗC TPC 9. Supply Current vs. Temperature 125 ADP3412 THEORY OF OPERATION To prevent the overlap of the gate drives during Q2’s turn OFF and Q1’s turn ON, the overlap circuit provides a programmable delay that is set by a capacitor on the DLY Pin. When the PWM input signal goes high, Q2 will begin to turn OFF (after a propagation delay), but before Q1 can turn ON, the overlap protection circuit waits for the voltage at DRVL to drop to around 10% of VCC. Once the voltage at DRVL has reached the 10% point, the overlap protection circuit will wait for a 20 ns typical propagation delay plus an additional delay based on the external capacitor, CDLY. The delay capacitor adds an additional 1 ns/pF of delay. Once the programmable delay period has expired, Q1 will begin turn ON. The delay allows time for current to commutate from the body diode of Q2 to an external Schottky diode, which allows turnoff losses to be reduced. Although not as foolproof as the adaptive delay, the programmable delay adds a safety margin to account for variations in size, gate charge, and internal delay of the external power MOSFETs. The ADP3412 is a dual MOSFET driver optimized for driving two N-channel MOSFETs in a synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high side and the low side FETs. Each driver is capable of driving a 3 nF load with only a 20 ns transition time. A more detailed description of the ADP3412 and its features follows. Refer to the General Application Circuit in Figure 1. Low Side Driver The low side driver is designed to drive low RDS(ON) N-channel MOSFETs. The maximum output resistance for the driver is 5 Ω for both sourcing and sinking gate current. The low output resistance allows the driver to have 20 ns rise and fall times into a 3 nF load. The bias to the low side driver is internally connected to the VCC supply and PGND. The driver’s output is 180 degrees out of phase with the PWM input. APPLICATION INFORMATION Supply Capacitor Selection High Side Driver The high side driver is designed to drive a floating low RDS(ON) N-channel MOSFET. The maximum output resistance for the driver is 5 Ω for both sourcing and sinking gate current. The low output resistance allows the driver to have 20 ns rise and fall times into a 3 nF load. The bias voltage for the high side driver is developed by an external bootstrap supply circuit, which is connected between the BST and SW Pins. For the supply input (VCC) of the ADP3412, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents drawn. Use a 1 µF, low ESR capacitor. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size and can be obtained from the following vendors: Murata The bootstrap circuit comprises a diode, D1, and bootstrap capacitor, CBST. When the ADP3412 is starting up, the SW Pin is at ground, so the bootstrap capacitor will charge up to VCC through D1. When the PWM input goes high, the high side driver will begin to turn ON the high side MOSFET, Q1, by pulling charge out of CBST. As Q1 turns ON, the SW Pin will rise up to VIN, forcing the BST Pin to VIN + VC(BST), which is enough gate-to-source voltage to hold Q1 ON. To complete the cycle, Q1 is switched OFF by pulling the gate down to the voltage at the SW Pin. When the low side MOSFET, Q2, turns ON, the SW Pin is pulled to ground. This allows the bootstrap capacitor to charge up to VCC again. The high side driver’s output is in phase with the PWM input. GRM235Y5V106Z16 www.murata.com TaiyoYuden EMK325F106ZF www.t-yuden.com Tokin C23Y5V1C106ZP www.tokin.com Keep the ceramic capacitor as close as possible to the ADP3412. Bootstrap Circuit The bootstrap circuit uses a charge storage capacitor (CBST) and a Schottky diode, as shown in Figure 1. Selection of these components can be done after the high side MOSFET has been chosen. The bootstrap capacitor must have a voltage rating that is able to handle the maximum battery voltage plus 5 V. A minimum 50 V rating is recommended. The capacitance is determined using the following equation: Overlap Protection Circuit The overlap protection circuit (OPC) prevents both of the main power switches, Q1 and Q2, from being ON at the same time. This is done to prevent shoot-through currents from flowing through both power switches and the associated losses that can occur during their ON-OFF transitions. The overlap protection circuit accomplishes this by adaptively controlling the delay from Q1’s turn OFF to Q2’s turn ON and by externally setting the delay from Q2’s turn OFF to Q1’s turn ON. C BST = QGATE ∆VBST where, QGATE is the total gate charge of the high side MOSFET, and ∆VBST is the voltage droop allowed on the high side MOSFET drive. For example, the IRF7811 has a total gate charge of about 20 nC. For an allowed droop of 200 mV, the required bootstrap capacitance is 100 nF. A good quality ceramic capacitor should be used. To prevent the overlap of the gate drives during Q1’s turn OFF and Q2’s turn ON, the overlap circuit monitors the voltage at the SW Pin. When the PWM input signal goes low, Q1 will begin to turn OFF (after a propagation delay), but before Q2 can turn ON, the overlap protection circuit waits for the voltage at the SW Pin to fall from VIN to 1 V. Once the voltage on the SW Pin has fallen to 1 V, Q2 will begin turn ON. By waiting for the voltage on the SW Pin to reach 1 V, the overlap protection circuit ensures that Q1 is OFF before Q2 turns on, regardless of variations in temperature, supply voltage, gate charge, and drive current. A Schottky diode is recommended for the bootstrap diode due to its low forward drop, which maximizes the drive available for the high side MOSFET. The bootstrap diode must have a minimum 40 V rating to withstand the maximum battery voltage plus 5 V. The average forward current can be estimated by: IF(AVG) ≈ QGATE × f MAX –6– REV. A ADP3412 where fMAX is the maximum switching frequency of the controller. The peak surge current rating should be checked in-circuit, since this is dependent on the source impedance of the 5 V supply and the ESR of CBST. Printed Circuit Board Layout Considerations Use the following general guidelines when designing printed circuit boards: 1. Trace out the high current paths and use short, wide traces to make these connections. 2. Connect the PGND Pin of the ADP3412 as close as possible to the source of the lower MOSFET. 3. The VCC bypass capacitor should be located as close as possible to VCC and PGND Pins. Delay Capacitor Selection The delay capacitor, CDLY, is used to add an additional delay when the low side FET drive turns off and when the high side drive starts to turn on. The delay capacitor adds 1 ns/pF of additional time to the 20 ns of fixed delay. If a delay capacitor is required, look for a good quality ceramic capacitor with an NPO or COG dielectric, or for a good quality mica capacitor. Both types of capacitors are available in the 1 pF to 100 pF range and have excellent temperature and leakage characteristics. VIN 12V 270␮F ⴛ 4 OS-CON 16V C12 C13 C14 C15 R4 4m⍀ C26 4.7␮F R6 10⍀ C4 4.7␮F U1 ADP3160 RA 60.4k⍀ COC 1.4nF RZ 1.1k⍀ 1 VID4 VCC 16 2 VID3 REF 15 3 VID2 CS– 14 4 VID1 PWM1 13 5 VID0 PWM2 12 6 COMP RB 10k⍀ The circuit in Figure 3 shows how two drivers can be combined with the ADP3160 to form a total power conversion solution for VCC(CORE) generation in a high current GOA computer. Figure 4 gives a CPU a similar application circuit for a 35 A processor. R7 20⍀ VIN RTN FROM CPU Typical Application Circuits C21 15nF R8 330⍀ D1 MBR052LTI Z1 ZMM5236BCT PWRGND 10 8 CT GND 9 U2 ADP3412 Q5 2N3904 1 BST C23 330pF C5 1␮F C22 1nF SW 7 3 DLY PGND 6 4 VCC DRVL 5 L1 600nH Q2 FDB8030L 1200␮F ⴛ 8 OS-CON 2.5V 11m⍀ ESR (EACH) + + + + + + VCC(CORE) 1.1V – 1.85V 53.4A + + C10 1␮F D2 MBR052LTI C11 C16 C17 C18 C19 C20 C21 C22 U3 ADP3412 1 BST 2 IN R1 1k⍀ C6 1␮F DRVH 8 3 DLY PGND 6 4 VCC DRVL 5 C8 15pF –7– Q3 FDB7030L SW 7 Figure 3. 53.4 A Intel CPU Supply Circuit REV. A Q1 FDB7030L C7 15pF C1 150pF C2 100pF DRVH 8 2 IN CS+ 11 7 FB C9 1␮F R5 2.4k⍀ Q4 FDB8030L L2 600nH VCC(CORE) RTN ADP3412 1000␮F ⴛ 6 RUBYCON ZA SERIES VIN 5V C12 C13 C14 C15 C24 C25 R7 20⍀ VIN RTN R4 5m⍀ 12V VCC C26 4.7␮F 12V VCC RTN R6 10⍀ C4 4.7␮F U1 ADP3160 FROM CPU RA 14.7k⍀ COC 1nF RZ 10k⍀ 1 VID4 VCC 16 2 VID3 REF 15 3 VID2 CS– 14 4 VID1 PWM1 13 5 VID0 PWM2 12 6 COMP RB 22.1k⍀ C21 15nF D1 MBR052LTI R5 2.4k⍀ Z1 ZMM5236BCT 1 BST DRVH 8 2 IN C23 330pF PWRGND 10 8 CT GND 9 Q1 FDB6035AL SW 7 L1 600nH 3 DLY PGND 6 4 VCC DRVL 5 C5 1␮F C22 1nF Q2 FDB7030L C7 15pF 1000␮F ⴛ 8 RUBYCON ZA SERIES 24m⍀ ESR (EACH) C10 1␮F D2 MBR052LTI + + + + + + VCC(CORE) 1.1V – 1.85V 35A + + VCC(CORE) CS+ 11 7 FB U2 ADP3412 Q5 2N3904 R8 330⍀ C9 1␮F U3 ADP3412 1 BST DRVH 8 C1 150pF 2 IN C11 C16 C17 C18 C19 C20 C27 C28 Q3 FDB6035AL SW 7 RTN L2 600nH 3 DLY PGND 6 R1 1k⍀ C2 100pF 4 VCC DRVL 5 C8 15pF C6 1␮F Q4 FDB7030L Figure 4. 35 A Athlon CPU Supply Circuit –8– REV. A ADP3412 OUTLINE DIMENSIONS 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 8 5 1 4 6.20 (0.2440) 5.80 (0.2284) PIN 1 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 0.50 (0.0196) ⴛ 45ⴗ 0.25 (0.0099) 8ⴗ 0.25 (0.0098) 0ⴗ 1.27 (0.0500) 0.41 (0.0160) 0.19 (0.0075) 0.51 (0.0201) 0.33 (0.0130) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS-012AA REV. A –9– ADP3412 Revision History Location Page 08/02—Data Sheet changed from REV. 0 to REV. A. Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 –10– REV. A –11– –12– PRINTED IN U.S.A. C01023–0–8/02 (A)