ADP3417JR-REEL7

a Dual Bootstrapped MOSFET Driver ADP3417 FEATURES All-In-One Synchronous Buck Driver Bootstrapped High Side Drive One PWM Signal Generates Both Drives Anticross-Conduction Protection Circuitry FUNCTIONAL BLOCK DIAGRAM VCC APPLICATIONS Multiphase Desktop CPU Supplies Single-Supply Synchronous Buck Converters Standard-to-Synchronous Converter Adaptations BST DRVH IN OVERLAP PROTECTION CIRCUIT SW DRVL ADP3417 PGND 12V GENERAL DESCRIPTION The ADP3417 is a dual MOSFET driver optimized for driving two N-channel MOSFETs which are the two switches in a nonisolated synchronous buck power converter. Each of the drivers is capable of driving a 3000 pF load with a 20 ns propagation delay and a 30 ns transition time. One of the drivers can be bootstrapped and is designed to handle the high voltage slew rate associated with “floating” high side gate drivers. The ADP3417 includes overlapping drive protection (ODP) to prevent shoot-through current in the external MOSFETs. VCC D1 BST ADP3417 CBST DRVH IN Q1 SW The ADP3417 is specified over the commercial temperature range of 0°C to 70°C and is available in an 8-lead SOIC package. DELAY TO INDUCTOR 1V DRVL Q2 PGND 1V Figure 1. General Application Circuit REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 ADP3417–SPECIFICATIONS1(VCC = 12 V, BST = 4 V to 26 V, T = 0
C to 70
C, unless otherwise noted.) A Parameter Symbol Conditions SUPPLY Supply Voltage Range Quiescent Current VCC ISYS VCC = BST = 12 V, IN = 0 V trDRVH tfDRVH Propagation Delay3, 4 tpdhDRVH tpdlDRVH trDRVL tfDRVL Propagation Delay3, 4 (See Figure 2) Max Unit 5 13.2 7 V mA 0.8 V V 1.75 1.0 45 3.0 2.5 55 Ω Ω ns 20 30 ns 45 15 65 35 ns ns 1.75 1.0 25 3.0 2.5 35 Ω Ω ns 21 30 ns 30 10 60 20 ns ns 2.5 Transition Times3 LOW SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times3 Typ 4.15 PWM INPUT Input Voltage High2 Input Voltage Low2 HIGH SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times3 Min tpdhDRVL tpdlDRVL VBST – VSW = 12 V VBST – VSW = 12 V See Figure 2, VBST – VSW = 12 V, CLOAD = 3 nF See Figure 2, VBST – VSW = 12 V, CLOAD = 3 nF See Figure 2, VBST – VSW = 12 V, VBST – VSW = 12 V VCC = 12 V VCC = 12 V See Figure 2, VCC = 12 V, CLOAD = 3 nF See Figure 2, VCC = 12 V, CLOAD = 3 nF See Figure 2, VCC = 12 V See Figure 2, VCC = 12 V NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 µA). 3 AC specifications are guaranteed by characterization but not production tested. 4 For propagation delays, “TPDH” refers to the specified signal going high; “TPDL” refers to it going low. Specifications subject to change without notice. –2– REV. A ADP3417 ORDERING GUIDE ABSOLUTE MAXIMUM RATINGS * VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5.0 V to +25 V IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V Operating Ambient Temperature Range . . . . . . . 0°C to 70°C Operating Junction Temperature Range . . . . . . 0°C to 125°C θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C Model Temperature Package Range Description ADP3417JR 0°C to 70°C Package Option 8-Lead Standard Small Outline (SOIC) SOIC-8 PIN CONFIGURATION *This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. Unless otherwise specified, all voltages are referenced to PGND. BST 1 8 DRVH IN 7 SW 6 PGND 5 DRVL 2 ADP3417 TOP VIEW (Not To Scale) NC 3 VCC 4 NC = NO CONNECT PIN FUNCTION DESCRIPTIONS Pin Mnemonic Function 1 BST 2 3 4 5 6 7 IN NC VCC DRVL PGND SW 8 DRVH Floating Bootstrap Supply for the Upper MOSFET. A capacitor connected between BST and SW Pins holds this bootstrapped voltage for the high side MOSFET as it is switched. The capacitor should be chosen between 100 nF and 1 ␮F. Logic-level input signal that has primary control of the drive outputs. No Connection Input Supply. This pin should be bypassed to PGND with ~1 µF ceramic capacitor. Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET. Power Ground. Should be closely connected to the source of the lower MOSFET. This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turnon of the lower MOSFET until the voltage is below ~1 V. Thus, according to operating conditions, the high low transition delay is determined at this pin. Buck Drive. Output drive for the upper (buck) MOSFET. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3417 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. A –3– WARNING! ESD SENSITIVE DEVICE ADP3417 IN tpdl DRVL tfDRVL tpdl DRVH trDRVL DRVL tfDRVH tpdhDRVH DRVH-SW trDRVH VTH VTH tpdh DRVL SW 1V Figure 2. Nonoverlap Timing Diagram (Timing Is Referenced to the 90% and 10% Points Unless Otherwise Noted) –4– REV. A Typical Performance Characteristics– ADP3417 60 VCC = 12V CLOAD = 3nF T T IN 50 IN DRVH 1 RISE TIME – ns 3 3 DRVH 1 DRVL DRVL DRVH 40 30 DRVL 2 2 20 TPC 1. DRVH Fall and DRVL Rise Times TA = 25
C VCC = 12V 26 FALL TIME – ns RISE TIME – ns FALL TIME – ns 26 DRVH 50 40 DRVL 30 20 0 25 50 75 100 JUNCTION TEMPERATURE –
C 10 125 TPC 4. DRVH and DRVL Fall Times vs. Temperature 2 3 4 LOAD CAPACITANCE – nF 5 VCC = 12V CLOAD = 3nF fIN = 250kHz SUPPLY CURRENT – mA SUPPLY CURRENT – mA 50 40 30 20 15 14 13 10 0 0 200 400 600 800 1000 IN FREQUENCY – kHz TPC 7. Supply Current vs. Frequency REV. A 1200 12 DRVH 20 14 1 16 TA = 25
C VCC = 12V CLOAD = 3nF DRVL 22 16 TPC 5. DRVH and DRVL Rise Times vs. Load Capacitance 60 24 18 22 20 TA = 25
C VCC = 12V DRVH 60 24 125 28 70 VCC = 12V CLOAD = 3nF DRVL 25 50 75 100 JUNCTION TEMPERATURE –
C TPC 3. DRVH and DRVL Rise Times vs. Temperature TPC 2. DRVL Fall and DRVH Rise Times 28 0 0 25 50 75 100 JUNCTION TEMPERATURE –
C TPC 8. Supply Current vs. Temperature –5– 125 1 2 3 4 LOAD CAPACITANCE – nF 5 TPC 6. DRVH and DRVL Fall Times vs. Load Capacitance ADP3417 To prevent the overlap of the gate drives during Q2’s turn OFF and Q1’s turn ON, the overlap circuit provides a internal delay that is set to 50 ns. When the PWM input signal goes high, Q2 will begin to turn OFF (after a propagation delay), but before Q1 can turn ON, the overlap protection circuit waits for the voltage at DRVL to drop to around 10% of VCC. Once the voltage at DRVL has reached the 10% point, the overlap protection circuit will wait for a 50 ns typical propagation delay. Once the delay period has expired, Q1 will begin turn ON. THEORY OF OPERATION The ADP3417 is a dual MOSFET driver optimized for driving two N-channel MOSFETs in a synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high side and the low side FETs. Each driver is capable of driving a 3 nF load. A more detailed description of the ADP3417 and its features follows. Refer to the Functional Block Diagram. Low Side Driver The low side driver is designed to drive low RDS(ON) N-channel MOSFETs. The maximum output resistance for the driver is 3 Ω for sourcing and 2.5 Ω for sinking gate current. The low output resistance allows the driver to have 25 ns rise times and 20 ns fall times into a 3 nF load. The bias to the low side driver is internally connected to the VCC supply and PGND. APPLICATION INFORMATION Supply Capacitor Selection For the supply input (VCC) of the ADP3417, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents drawn. Use a 1 µF, low ESR capacitor. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size. Keep the ceramic capacitor as close as possible to the ADP3417. When the driver is enabled, the driver’s output is 180 degrees out of phase with the PWM input. When the ADP3417 is disabled, the low side gate is held low. Bootstrap Circuit The bootstrap circuit uses a charge storage capacitor (CBST) and a diode, as shown in Figure 1. Selection of these components can be done after the high side MOSFET has been chosen. High Side Driver The high side driver is designed to drive a floating low RDS(ON) N-channel MOSFET. The maximum output resistance for the driver is 3 Ω for sourcing and 2.5 Ω for sinking gate current. The low output resistance allows the driver to have 45 ns rise times and 20 ns fall times into a 3 nF load. The bias voltage for the high side driver is developed by an external bootstrap supply circuit, which is connected between the BST and SW Pins. The bootstrap capacitor must have a voltage rating that is able to handle the maximum supply voltage. A minimum 25 V rating is recommended. The capacitance is determined using the following equation: The bootstrap circuit comprises a diode, D1, and bootstrap capacitor, CBST. When the ADP3417 is starting up, the SW Pin is at ground, so the bootstrap capacitor will charge up to VCC through D1. When the PWM input goes high, the high side driver will begin to turn the high side MOSFET, Q1, ON by pulling charge out of CBST. As Q1 turns ON, the SW Pin will rise up to VIN, forcing the BST Pin to VIN + VC(BST), which is enough gate to source voltage to hold Q1 ON. To complete the cycle, Q1 is switched OFF by pulling the gate down to the voltage at the SW Pin. When the low side MOSFET, Q2, turns ON, the SW Pin is pulled to ground. This allows the bootstrap capacitor to charge up to VCC again. The high side driver’s output is in phase with the PWM input. CBST = QGATE ∆VBST (1) where, QGATE is the total gate charge of the high side MOSFET, and ∆VBST is the voltage droop allowed on the high side MOSFET drive. For example, the IRF7811 has a total gate charge of about 20 nC. For an allowed droop of 200 mV, the required bootstrap capacitance is 100 nF. A good quality ceramic capacitor should be used. A small-signal diode can be used for the bootstrap diode due to the ample gate drive available for the high side MOSFET. The bootstrap diode must have a minimum 15 V rating to withstand the maximum boosted supply voltage. The average forward current can be estimated by: Overlap Protection Circuit IF(AVG) ≈ QGATE × f MAX The overlap protection circuit (OPC) prevents both of the main power switches, Q1 and Q2, from being ON at the same time. This is done to prevent shoot-through currents from flowing through both power switches and the associated losses that can occur during their ON-OFF transitions. The overlap protection circuit accomplishes this by adaptively controlling the delay from Q1’s turn OFF to Q2’s turn ON and by internally setting the delay from Q2’s turn OFF to Q1’s turn ON. (2) where fMAX is the maximum switching frequency of the controller. The peak surge current rating should be checked in-circuit, since this is dependent on the source impedance of the 12 V supply and the ESR of CBST. Printed Circuit Board Layout Considerations Use the following general guidelines when designing printed circuit boards: To prevent the overlap of the gate drives during Q1’s turn OFF and Q2’s turn ON, the overlap circuit monitors the voltage at the SW Pin. When the PWM input signal goes low, Q1 will begin to turn OFF (after a propagation delay), but before Q2 can turn ON, the overlap protection circuit waits for the voltage at the SW Pin to fall from VIN to 1 V. Once the voltage on the SW Pin has fallen to 1 V, Q2 will begin turn ON. By waiting for the voltage on the SW Pin to reach 1 V, the overlap protection circuit ensures that Q1 is OFF before Q2 turns on, regardless of variations in temperature, supply voltage, gate charge, and drive current. 1. Trace out the high current paths and use short, wide traces to make these connections. 2. Connect the PGND Pin of the ADP3417 as close as possible to the source of the lower MOSFET. 3. The VCC bypass capacitor should be located as close as possible to VCC and PGND Pins. –6– REV. A REV. A –7– R2 U5 10k 1/6 7404 OUTEN COC 1.2nF C10 100pF RA 32.4k Q1 2N7000 FROM CPU RB 10.0k VINRTN VIN12V + C3 C4 4.7F CS– 13 CS+ 12 PWRGD 11 9 FB 10 CT PGND 14 PC 15 PWM3 16 8 GND 7 COMP 6 SHARE 5 VID0 PWM2 17 4 VID1 REF 19 PWM1 18 3 VID2 VCC 20 2 VID3 U1 ADP3163 C2 + 1 VID4 C1 + 270F/16V x 3 OS-CON SP SERIES 18m ESR(EACH) R3 1k C9 150pF L1 1H R4 10 C7 1nF C6 15nF R5 20 D1 1N4148 C18 1F D4 1N4148 C15 1F D3 1N4148 D2 1N4148 C12 1F DRVL 5 DRVL 4 VCC 3 NC 2 IN 1 BST Figure 3. 65 A Intel Pentium 4 CPU Supply Circuit, VR Down Guideline Design Q9 FDB8030L DRVL 5 DRVL PGND 6 SW 7 SW DRVH 8 DRVH C17 U4 100nF ADP3417 Q8 FDB8030L PGND 6 4 VCC SW 7 SW DRVH 8 DRVH 3 NC 2 IN 1 BST U3 ADP3417 C14 100nF Q7 FDB8030L DRVL 5 PGND 6 3 NC 4 VCC SW 7 2 IN DRVH 8 C11 U2 100nF ADP3417 1 BST 10F  2 MLCC R7 5m R10 2 C19 15nF L4 600nH Q5 FDB7030L R9 2 C16 15nF L3 600nH Q4 FDB7030L R8 2 C13 15nF + C29 NC = NO CONNECT 10F  27 MLCC C20 + 2200F/6.3V  9 L2 RUBYCON MBZ SERIES 600nH 13m ESR (EACH) Q3 FDB7030L 65A VCC(CORE)RTN VCC(CORE) 1.1V – 1.85V ADP3417 Typical Application Circuits The circuit in Figure 3 shows how three ADP3417 drivers can be combined with the ADP3163 to form a total power conversion solution for VCC(CORE) generation for an Intel Pentium®4 CPU. ADP3417 OUTLINE DIMENSIONS 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) C02713–0–8/02(A) Dimensions shown in millimeters and (inches) 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 8 5 1 4 6.20 (0.2440) 5.80 (0.2284) PIN 1 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 0.50 (0.0196)  45
0.25 (0.0099) 8
0.25 (0.0098) 0
1.27 (0.0500) 0.41 (0.0160) 0.19 (0.0075) 0.51 (0.0201) 0.33 (0.0130) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS-012AA Revision History Location Page 08/02—Data Sheet changed from REV. 0 to REV. A. PRINTED IN U.S.A. Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 –8– REV. A