ADP3418KRZ1

Dual Bootstrapped 12 V MOSFET Driver with Output Disable ADP3418 FEATURES All-in-one synchronous buck driver Bootstrapped high-side drive 1 PWM signal generates both drives Anticross-conduction protection circuitry Output disable control turns off both MOSFETs to float the output per Intel® VRM 10 and AMD Opteron specifications GENERAL DESCRIPTION The ADP3418 is a dual, high voltage MOSFET driver optimized for driving two N-channel MOSFETs, the two switches in a nonisolated, synchronous, buck power converter. Each of the drivers is capable of driving a 3000 pF load with a 30 ns transition time. One of the drivers can be bootstrapped, and is designed to handle the high voltage slew rate associated with floating highside gate drivers. The ADP3418 includes overlapping drive protection to prevent shoot-through current in the external MOSFETs. The OD pin shuts off both the high-side and the low-side MOSFETs to prevent rapid output capacitor discharge during system shutdowns. The ADP3418 is specified over the commercial temperature range of 0°C to 85°C, and is available in an 8-lead SOIC package. APPLICATIONS Multiphase desktop CPU supplies Single-supply synchronous buck converters FUNCTIONAL BLOCK DIAGRAM 12V CVCC VCC 4 D1 CBST2 CBST1 Q1 RG RBST1 7 ADP3418 1 BST DRVH IN 2 8 DELAY SW TO INDUCTOR CMP S R Q Q DELAY VCC 6 5 DRVL PGND Q2 CMP 1V 6 3 OD Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. 03229-B-001 ADP3418 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 ESD Caution .................................................................................. 4 Pin Configuration and Function Descriptions ............................. 5 Timing Characteristics..................................................................... 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ........................................................................ 9 Low-Side Driver............................................................................ 9 High-Side Driver .......................................................................... 9 Overlap Protection Circuit...........................................................9 Application Information ................................................................ 10 Supply Capacitor Selection ....................................................... 10 Bootstrap Circuit ........................................................................ 10 MOSFET Selection ..................................................................... 10 PC Board Layout Considerations ................................................. 12 Outline Dimensions ....................................................................... 14 Ordering Guide .......................................................................... 14 REVISION HISTORY 8/04—Data Sheet Changed from Rev. A to Rev. B Updated Figure 1; Deleted Figure 2.....................................................1 Updated Specifications Table ...............................................................3 Updated Pin Description......................................................................5 Updated Theory of Operation .............................................................9 Updated Applications Section............................................................10 Change to Ordering Guide.................................................................14 4/04—Data Sheet Changed from Rev. 0 to Rev. A Updated Format...................................................................... Universal Change to General Description ...........................................................1 Change to Figure 13 ..............................................................................8 Change to Ordering Guide.................................................................12 3/03—Revision 0: Initial Version Rev. B | Page 2 of 16 ADP3418 SPECIFICATIONS1 VCC = 12 V, BST = 4 V to 26 V, TA = 0°C to 85°C, unless otherwise noted. Table 1. Parameter SUPPLY Supply Voltage Range Supply Current OD INPUT Input Voltage High Input Voltage Low Input Current Propagation Delay Time PWM INPUT Input Voltage High Input Voltage Low Input Current HIGH-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times Symbol VCC ISYS Conditions Min 4.15 BST = 12 V, IN = 0 V 2.6 –1 tpdhOD tpdlOD See Figure 3 See Figure 3 3.0 –1 VBST − VSW = 12 V VBST − VSW = 12 V See Figure 4, VBST − VSW = 12 V, CLOAD = 3 nF See Figure 4, VBST − VSW = 12 V, CLOAD = 3 nF See Figure 4, VBST − VSW = 12 V VBST − VSW = 12 V 1.8 1.0 35 20 40 20 1.8 1.0 25 21 30 10 240 120 0.8 +1 3.0 2.5 45 30 65 35 3.0 2.5 35 30 60 20 25 20 0.8 +1 40 40 3 Typ Max 13.2 6 Unit V mA V V µA ns ns V V µA Ω Ω ns ns ns ns Ω Ω ns ns ns ns ns ns trDRVH tfDRVH Propagation Delay2 LOW-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times Propagation Delay Timeout Delay 2 tpdhDRVH tpdlDRVH trDRVL tfDRVL tpdhDRVL tpdlDRVL See Figure 4, CLOAD = 3 nF See Figure 4, CLOAD = 3 nF See Figure 4 See Figure 4 SW = 5 V SW = PGND 90 1 2 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to it going low. Rev. B | Page 3 of 16 ADP3418 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC BST DC 20 mil) traces to make these connections. Connect the PGND pin of the ADP3418 as closely as possible to the source of the lower MOSFET. The VCC bypass capacitor should be located as close as possible to the VCC and PGND pins. Use vias to other layers when possible to maximize thermal conduction away from the IC. CBST1 CBST2 D1 RBST The circuit in Figure 15 shows how four drivers can be combined with the ADP3188 to form a total power conversion solution for generating VCC(CORE) for an Intel CPU that is VRD 10.x compliant. Figure 14 shows an example of the typical land patterns based on the guidelines given previously. For more detailed layout guidelines for a complete CPU voltage regulator subsystem, refer to the ADP3188 data sheet. 03229-B-014 CVCC Figure 14. External Component Placement Example for the ADP3418 Driver Rev. B | Page 12 of 16 LI 370nH 18A VIN 12V 2700MF/16V/3.3A × 2 SANYO MV-WX SERIES R3 2.2Ω C8 12nF + C1 + C2 C7 4.7µF C6 6.8nF VIN RTN D2 1N4148 1 BST 2 IN 3 OD U2 ADP3418 DRVH 8 SW 7 PGND 6 DRVL 5 + C24 C31 Q1 NTD60N02 560µF/4V × 8 L4 320nH/1.4mΩ SANYO SEPC SERIES 5mΩ EACH VCC (CORE) 0.8375 V – 1.6V 95A TDC, 119A PK 4 VCC + VCC (CORE) RTN C5 4.7µF R4 2.2Ω C12 12nF Q3 NTD110N02 Q4 NTD110N02 D1 1N4148 D3 1N4148 1 BST 2 IN 3 OD U3 ADP3418 C10 6.8nF DRVH 8 SW 7 PGND 6 DRVL 5 C11 4.7µF Q5 NTD60N02 10µF × 18 MLCC IN SOCKET L3 320nH/1.4mΩ 4 VCC C9 4.7µF C3 + 100µF C4 1µF R2 137kΩ 1% 1 VID4 2 VID3 3 VID2 4 VID1 5 VID0 6 VID5 7 FBRTN 8 FB 9 COMP 10 PWRGD 11 EN 12 DELAY U1 ADP3188 VCC 28 PWM1 27 PWM2 26 PWM3 25 PWM4 24 SW1 23 SW2 22 SW3 21 SW4 20 GND 19 CSCOMP 18 CSSUM 17 560pF CCS1 R5 2.2Ω C16 12nF Q7 NTD110N02 Q8 NTD110N02 D4 1N4148 2 IN U4 ADP3418 1 BST C14 6.8nF DRVH 8 SW 7 Figure 15. VRD 10.x Compliant Intel CPU Supply Circuit Rev. B | Page 13 of 16 3 OD 4 VCC C15 4.7µF Q9 NTD60N02 PGND 6 DRVL 5 FROM CPU L4 320nH/1.4mΩ CB C21 1nF 470pF C13 4.7µF POWER GOOD CA RB RA 1.21kΩ 470pF 12.1kΩ CFB 22pF RPH4 158kΩ, 1% CCS2 RCS1 35.7kΩ 84.5kΩ RCS2 1.5nF R6 2.2Ω C20 12nF Q11 NTD110N02 Q12 NTD110N02 ENABLE 13 RT 14 RAMPADJ ILIMIT 15 RPH2 RPH3 158kΩ, RPH1 1% 158kΩ, 158kΩ, 1% 1% C19 4.7µF D5 1N4148 CSREF 16 C22 1nF CLDY 39nF RLDY 470kΩ U5 ADP3418 1 BST 2 IN 3 OD 4 VCC C16 6.8nF DRVH 8 SW 7 PGND 6 DRVL 5 RT 137kΩ 1% Q13 NTD60N02 L5 320nH/1.4mΩ RTH1 100kΩ, 5% NTC C23 1nF RLIM 150kΩ 1% C17 4.7µF Q15 NTD110N02 Q16 NTD110N02 ADP3418 03229-B-015 ADP3418 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 5 4 4.00 (0.1574) 3.80 (0.1497) 1 6.20 (0.2440) 5.80 (0.2284) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 1.75 (0.0688) 1.35 (0.0532) 0.50 (0.0196) × 45° 0.25 (0.0099) 0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE 8° 0.25 (0.0098) 0° 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 16. 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model ADP3418KRZ1 ADP3418KRZ–REEL1 Temperature Range 0°C to 85°C 0°C to 85°C Package Description SOIC SOIC Package Option RN-8 RN-8 1 Z = Pb-free part. Rev. B | Page 14 of 16 ADP3418 NOTES Rev. B | Page 15 of 16 ADP3418 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03229–0–8/04(B) Rev. B | Page 16 of 16