ADP3421

a Geyserville-Enabled DC-DC Converter Controller for Mobile CPUs ADP3421 FUNCTIONAL BLOCK DIAGRAM ADP3421 DACOUT VID4 VID3 VID2 VID1 VID0 VID DAC CURRENT LIMIT COMPARATOR EN LTO LTB LTI CORE CONTROLLER CLKDRV CLKFB IODRV CLOCK LDO CONTROLLER LEVEL TRANSLATOR CORE COMPARATOR CS+ CS– VHYS REG RAMP OUT FEATURES Meets Intel® Mobile Voltage Positioning Requirements Lowest Processor Dissipation for Longest Battery Life Best Transient Containment Minimum Number of Output Capacitors System Power Management Compliant Fast, Smooth Output Transition During VID Code Change Programmable Current Limit Power Good Integrated LDO Controllers for Clock and I/O Supplies Programmable UVLO Soft Start with Restart Lock-In APPLICATIONS Geyserville-Enabled Core DC-DC Converters Fixed Voltage Mobile CPU Core DC-DC Converters Notebook/Laptop Power Supplies Programmable Output Power Supplies CLSET SSC SOFT START TIMER AND POWER GOOD GENERATOR SSL CORE GENERAL DESCRIPTION The ADP3421 is a hysteretic dc-dc buck converter controller with two auxiliary linear regulator controllers. The ADP3421 provides a total power conversion control solution for a microprocessor by delivering the core, I/O, and clock voltages. The optimized low-voltage design is powered from the 3.3 V system supply and draws only 10 µA maximum in shutdown. The main output voltage is set by a 5-bit VID code. To accommodate the transition time required by the newest processors for on-thefly VID changes, the ADP3421 features high-speed operation to allow a minimized inductor size that results in the fastest change of current to the output. To further allow for the minimum number of output capacitors to be used, the ADP3421 features active voltage positioning that can be optimally compensated to ensure a superior load transient response. The main output signal interfaces with the ADP3410 dual MOSFET driver, which is optimized for high speed and high efficiency for driving both the upper and lower (synchronous) MOSFETs of the buck converter. IOFB I/O LDO CONTROLLER BIAS AND REFERENCE BIAS EN UVLO VCC VIN/VCC MONITOR AND UVLO BIAS REFERENCE CONTROLLER PWRGD GND SD REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 ADP3421–SPECIFICATIONS1 (0 C, C T = 10100 CC, VCC =.83.3 V,CV k pF, = 1 nF, A OUT SSC V, VCORE = VDAC, ROUT = 100 = 1.3 nF, CLTB = 1.5 nF, unless otherwise noted.) SSL Min Typ 7 Max 15 350 10 2.9 Unit mA µA µA V V mV V µA µA V V V V V V V V µA mA mV V V µA V % µs mV µA SD = VCC, VULVO = 2.0 Parameter SUPPLY-UVLO-POWER GOOD Supply Current Symbol ICC(ON) ICC(UVLO) VCCH ICCH VCCL VCCHYS VUVLOTH IUVLO VSDTH VCOREH(UP)1 VCOREH(DN)2 VCOREL(UP)1 VCOREL(DN)2 VPWRGD3 Conditions VUVLO = 0.2 V VSD = 0 V, 3.0 V ≤ VCC ≤ 3.6 V 2.7 20 1.175 1.225 –0.3 0.6 1.0 0.8 1.10 × VDAC 1.08 × VDAC 0.90 × VDAC 0.88 × VDAC 0.95 × VCC 0 0 –0.6 0.3 1.53 0.8 10 0.925 –0.85 –1.0 1.0 150 1.70 VCC UVLO Threshold VCC UVLO Hysteresis Battery UVLO Threshold Battery UVLO Hysteresis Shutdown Input Threshold Core Power Good Threshold VUVLO = 1.275 V VUVLO = 1.175 V 3.0 V < VCC < 5.0 V 0.925 V < VDAC < 2.000 V PWRGD Output Voltage VCORE = VDAC VCORE = 0.8 VDAC VUVLO = 0.2 V VSSC = 0 V VSSC = 1.7 V, VUVLO = 1.1 V 1.275 +0.3 1.4 0.7 × VCC 1.12 × VDAC 1.10 × VDAC 0.92 × VDAC 0.90 × VDAC VCC 0.8 0.4 –1.4 400 1.87 0.7 × VCC 40 2.000 0.85 35 +3 +2 CORE CONVERTER SOFT-START TIMER Timing Charge Current ISSC(UP) Discharge Current ISSC(DN) Enable Threshold VSSCEN4 Termination Threshold VSSCTH VID DAC VID Input Threshold VID Input Pull-Up Current Nominal Output Voltage Output Voltage Accuracy Output Voltage Settling Time CORE COMPARATOR Input Offset Voltage Input Bias Current Hysteresis Current VVID0..4 IVID0..4 VDAC ∆VDAC/VDAC tDACS5 VCOREOS IREG IRAMP See VID Code Table I VREG = 1.3 V VREG = VRAMP = 1.3 V VCORE = VRAMP = 1.3 V VCS– = 1.30 V, VCS+ = 1.28 V VREG = 1.28 V RVHYS Open RVHYS = 170 kΩ RVHYS = 17 kΩ VREG = 1.32 V RVHYS Open RVHYS = 170 kΩ RVHYS = 17 kΩ VCC = 3.0 V VCC = 3.6 V TA = 25°C 0°C ≤ TA ≤ 100°C –3 –2 –2 –7 –82 –2 7 82 1.53 2.5 0 –10 –97 +2 –13 –113 +2 13 113 1.87 3.0 0.4 20 30 10 µA µA µA µA µA µA V V V ns ns ns Hysteresis Setting Reference Voltage VVHYS Output Voltage VOUTH VOUTL tCOREPD7 Propagation Delay Time6 Rise and Fall Time6 tCORER8, tCOREF8 10 97 1.70 7 –2– REV. A ADP3421 Parameter CURRENT LIMIT COMPARATOR Input Offset Voltage Input Bias Current Hysteresis Current Symbol VCLOS ICL+ ICL– Conditions VCS– = 1.3 V VCS+ = 1.3 V VCORE = VRAMP = 1.3 V VREG = 1.28 V, VCS– = 1.3 V VCS+ = 1.28 V RIHYS Open RIHYS = 170 kΩ RIHYS = 17 kΩ VCS+ = 1.32 V RIHYS Open RIHYS = 170 kΩ RIHYS = 17 kΩ TA = 25°C 0°C ≤ TA ≤ 100°C VSSC = 0 V VSSC = 1.7 V, VUVLO = 1.1 V –0.6 0.3 1.53 VCLKFB = 2.5 V VCLKDRV = 2.55 V VCLKDRV = 2.45 V ∆ICLKDRV = 1 mA VIOFB = 1.5 V VIODRV = 1.53 V VIODRV = 1.47 V ∆ICLKDRV = 1 mA ILTI = –10 µA ILTI = –10 µA9 VLTI = 0.175 V9 Min –6 –5 Typ Max +6 +5 Unit mV µA –22 –265 –30 –300 –5 –38 –335 –5 –27 –225 1.87 60 100 –1.4 400 1.87 25 1 20 µA µA µA µA µA µA V ns ns µA mA mV V µA µA mA mA/V µA µA mA mA/V V V mV ns Hysteresis Setting Reference Voltage VVHYS Propagation Delay Time6 tCLPD7 LINEAR REGULATOR SOFT-START TIMER Charge Current ISSC(UP) Discharge Current ISSC(DN) Enable Threshold VSSCEN4 Termination Threshold VSSCTH 2.5 V CLK LDO CONTROLLER Feedback Bias Current Output Drive Current DC Transconductance 1.5 V I/O LDO CONTROLLER Feedback Bias Current Output Drive Current DC Transconductance LEVEL TRANSLATOR Input Clamping Threshold Output Voltage Propagation Delay Time6 ICLKFB ICLKDRV GCLK IIOFB IIODRV GIO VLTIH VLTOH VLTOL tLTPD –13 –175 1.53 –20 –200 1.70 30 50 –1.0 1.0 150 1.70 12.5 3 500 7.5 10 650 0.95 0.9 × VCCLT 15 1 60 1.5 VCCLT 375 10 NOTES 1 VCORE ramps up monotonically. 2 VCORE ramps down monotonically. 3 During latency time of VID code change, the Power Good output signal should not be considered valid. 4 Internal bias and soft start are not enabled unless the soft-start pin voltage first drops below the enable threshold. 5 Measured from 50% of VID code transient amplitude to the point where V DAC settles within ± 1% of its steady state value. 6 Guaranteed by characterization. 7 40 mV p-p amplitude impulse with 20 mV overdrive. Measure from the input threshold intercept point to 50% of the output voltage swing. 8 Measured between the 30% and 70% points of the output voltage swing. 9 The LTO output tied to V CCLT = 2.5 V rail through an R LTO = 150 Ω pull-up resistor. Specifications subject to change without notice. REV. A –3– ADP3421 ABSOLUTE MAXIMUM RATINGS * PIN CONFIGURATION VHYS 1 CLSET 2 LTO 3 LTI 4 LTB 5 VID4 6 VID3 7 28 27 26 25 24 Input Supply Voltage (VCC) . . . . . . . . . . . . . . –0.3 V to +7 V UVLO Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V All Other Inputs/Outputs . . . . . . . . . . . . . . . . . . VCC + 0.3 V Operating Ambient Temperature Range . . . . . . 0°C to 100°C Junction Temperature Range . . . . . . . . . . . . . . . 0°C to 150°C θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98°C/W Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . 300°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CS– CS+ REG RAMP VCC OUT ADP3421 23 TOP VIEW 22 GND VID2 8 (Not to Scale) 21 DACOUT VID1 9 VID0 10 CLKDRV 11 CLKFB 12 IODRV 13 20 19 18 17 16 15 CORE SSC SSL UVLO PWRGD SD ORDERING GUIDE Model Temperature Range Package Description Package Option IOFB 14 ADP3421JRU 0°C to 100°C Thin Shrink Small RU-28 Outline (TSSOP) CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3421 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN FUNCTION DESCRIPTIONS WARNING! ESD SENSITIVE DEVICE Pin 1 2 Mnemonic VHYS CLSET Function Core Comparator Hysteresis Setting. The voltage at this pin is held at a 1.7 V reference level. A resistor to ground programs at a 1:1 ratio the current that is alternately switched into and out of the RAMP pin. Current Limit Setting. The voltage at this pin is held at a 1.7 V reference level. A resistor to ground programs a current that is gained up by 3:1 flowing out of the CS– pin, assuming the current limit comparator is not triggered. Level Translator Output. This pin must be tied through a pull-up resistor to the voltage level desired for the output high level. That voltage cannot be less than 1.5 V. Level Translator Input. This pin should be driven from an open drain/collector signal. The pull-up current is provided by the pull-up resistor on the LTO pin. However, the pull-up current will be terminated when the LTI pin reaches 1.5 V. Level Translator Bypass. For operation of the level translator with high-speed signals, this pin should be bypassed to ground with a large value capacitor. VID Input. Most significant bit. VID Input VID Input VID Input VID Input. Least significant bit. 2.5 V Linear Regulator Driver Output. This pin sinks current from the base of a PNP transistor as needed to keep the CLKFB node regulated at 2.5 V. 2.5 V Linear Regulator Output Feedback. This pin is connected to the collector of a PNP transistor whose base is driven by the CLKDRV pin. 1.5 V Linear Regulator Driver Output. This pin sinks current from the base of a PNP transistor as needed to keep the IOFB node regulated at 1.5 V. 1.5 V Linear Regulator Output Feedback. This pin is connected to the collector of a PNP transistor whose base is driven by the IODRV pin. 3 4 LTO LTI 5 6 7 8 9 10 11 12 13 14 LTB VID4 VID3 VID2 VID1 VID0 CLKDRV CLKFB IODRV IOFB –4– REV. A ADP3421 Pin 15 16 Mnemonic SD PWRGD Function Shutdown Input. When this pin is pulled low, the IC shuts down and all regulation functions will be disabled. Power Good Output. This signal will go high only when the SD pin is high to allow IC operation, the UVLO and VCC pins are above their respective start-up thresholds, the SSC and SSL pins are above a voltage where soft start is completed, and the voltage at the CORE pin is within the specified limits of the programmed VID voltage. By choosing the soft-start capacitor for the core larger than that for the linear regulators, at start-up the core and linear outputs should all be in regulation before PWRGD is asserted. Undervoltage Lockout Input. This pin monitors the input voltage through a resistor divider. When the pin voltage is below a specified threshold, the IC enters into UVLO mode regardless of the status of SD. When in UVLO mode, a current source is switched on at this pin, which sinks current from the external resistor divider. The generated UVLO hysteresis is equal to the current sink value times the upper divider resistor. Linear Regulator Soft Start. During power-up, an external soft-start capacitor is charged by a current source to control the ramp-up rates of the linear regulators. Core Voltage Soft Start. During power-up, an external soft-start capacitor is charged by a current source to control the ramp-up rate of the core voltage. Core Converter Voltage Monitor. This pin is used to monitor the core voltage for power good verification. VID-Programmed Digital-to-Analog Converter Output. This voltage is the reference voltage for output voltage regulation. Ground Logic-Level Drive Signal Output of Core Controller. This pin provides the drive command signal to the IN pin of the ADP3410 driver. This pin is not capable of directly driving a power MOSFET. Power Supply Current Ramp Input. This pin provides the negative feedback for the core output voltage. The switched sink/ source current from this pin, which is set up at the VHYS pin, works against the terminating resistance at this pin to set the hysteresis for the hysteretic control. Regulation Voltage Summing Input. In the recommended configuration, the DACOUT voltage and the core voltage are summed at this pin to establish regulation with output voltage positioning. Current Limit Positive Sense. This pin senses the positive node of the current sense resistor. Current Limit Negative Sense. This pin connects through a resistor to the negative node of the current sense resistor. A current flows out of the pin, as programmed at the CLSET pin. When this pin is more negative than the CS+ pin, the current limit comparator is triggered and the current flowing out of the pin is reduced to two-thirds of its previous value, producing a current limit hysteresis. 17 UVLO 18 19 20 21 22 23 24 25 SSL SSC CORE DACOUT GND OUT VCC RAMP 26 27 28 REG CS+ CS– REV. A –5– ADP3421–Typical Performance Characteristics 100m HIGH NORMAL OPERATING MODE 10m 1000 SUPPLY CURRENT – A SOFT-START TIME – ms 100 CORE FULL-SCALE 1m UVLO MODE 100 POWER GOOD 10 10 SHUTDOWN MODE LOW 1 CORE ZERO-SCALE AND LDOS 1 0 20 40 60 80 TEMPERATURE – C 100 –0.15 –0.1 –0.05 0 0.05 0.1 0.15 RELATIVE CORE VOLTAGE – VCORE / VCORE 0.1 0.1 1 10 TIMING CAPACITANCE – nF 100 TPC 1. Supply Current vs. Temperature TPC 2. Power Good vs. Relative Core Voltage Variation TPC 3. Soft-Start Time vs. Timing Capacitance 2.010 +0.85% A 100 OUT = HIGH, RHYS = 17k HYSTERESIS CURRENT – A 0 OUT = LOW, RCLSET = 170k OUT = HIGH, RCLSET = 170k DAC OUTPUT – V 2.000 1.990 0.9375 –0.85% FULL-SCALE CURRENT LIMIT THRESHOLD CURRENT – –100 OUT = HIGH, RHYS = 170k 0 +0.85% OUT = LOW, RHYS = 170k –200 OUT = LOW, RCLSET = 17k 0.925 –0.85% 0.9125 0 ZERO-SCALE OUT = LOW, RHYS = 17k –100 100 0 20 40 60 80 AMBIENT TEMPERATURE – C 100 –300 0 OUT = HIGH, RCLSET = 17k 20 40 60 80 AMBIENT TEMPERATURE – C 100 20 40 60 80 AMBIENT TEMPERATURE – C TPC 4. DAC Output Voltage vs. Temperature TPC 5. Core Hysteresis Current vs. Temperature TPC 6. Current Limit Threshold Current vs. Temperature IO LDO REGULATOR OUTPUT VOLTAGE – V 30 VIOFB = 1.47V 20 IO LDO 1.52 EXT = 100 CLK LDO REGULATOR OUTPUT VOLTAGE – V 40 OUTPUT DRIVE CURRENT – mA 1.55 2.60 2.55 EXT = 100 2.50 1.50 10 CLK LDO VCLKFB = 2.45V 0 0 20 40 60 80 AMBIENT TEMPERATURE – C 100 1.48 2.45 1.45 100 1m 0.01 0.1 LOAD CURRENT – A 1 10 2.40 100 0.01 1m 0.1 LOAD CURRENT – A 1 TPC 7. LDO Drive Current vs. Temperature TPC 8. IO LDO DC Load Regulation TPC 9. CLK LDO DC Load Regulation –6– REV. A ADP3421 THEORY OF OPERATION Supply Voltages The ADP3421 is optimized for use with, and specified at a 3.3 V supply, but can operate at up to 6 V at the expense of increased quiescent current and minor tolerance degradation. The ADP3410 MOSFET driver can accommodate up to 30 V for driving the upper power MOSFET to 5 V above a 25 V rail. Undervoltage Lockout applied to the DAC input. The VID code corresponds to that recommended in guidelines for the mobile Pentium® III published by Intel (see Table I). Table I. VID Code VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VOUT 2.000 1.950 1.900 1.850 1.800 1.750 1.700 1.650 1.600 1.550 1.500 1.450 1.400 1.350 1.300 Off* 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.00 0.975 0.950 0.925 Off* The undervoltage lockout (UVLO) circuit comprises the low V IN and low VCC detection comparators. UVLO for VIN provides a system UVLO that monitors the battery voltage and allows the converter operation to be disabled if the battery falls below a preset threshold. A resistor divider to the UVLO pin sets the UVLO-off level for the system comparing to a specified reference. When VIN goes low enough to activate UVLO, this triggers a specified current sink into the pin to be switched on. This raises the UVLO-on threshold above the UVLO-off threshold by the current sink values times the upper resistor of the divider. So the resistor divider ratio at the UVLO pin is used to set the UVLO threshold and the hysteresis. Hysteresis for the system UVLO is recommended to prevent oscillation due to nonzero battery impedance. If UVLO is triggered during a condition where the battery is loaded by the converter operation, the converter will turn off and the battery voltage will then rise to a slightly higher level. A good design will ensure that the hysteresis is sufficient to prevent the converter from turning on again. UVLO for VCC provides an internally specified UVLO threshold for the ADP3421 to ensure that it only operates when the applied VCC is sufficient to ensure that it can operate properly. Activation of either UVLO circuit disables the reference and bias circuits in the IC except for that which is needed for UVLO detection. Power Good If the IC is enabled and is not in the UVLO mode and has finished its soft-start period, and if the core voltage is within ± 10% of the VID programmed value, then a high-level signal appears at the PWRGD pin. Power Good During VID Change *No CPU shutdown When a VID change occurs, the DAC output responds faster than the output voltage, which is slew rate limited by the output filter. In this case, PWRGD may momentarily go low. To avoid system interruption, the PC power management system should not respond to this glitch. The PWRGD signal corresponds to V_GATE as specified in Intel’s Geyserville Voltage Regulator specification. The glitch can be masked from the system by using the appropriate system programming settings or by using a functionally equivalent OR gate, which provides a blanking signal for the specified latency period where the core voltage is allowed to settle at its new value. Because of the minimal output capacitor requirement, the response time of the core voltage is well within the specified latency period and, when the power converter is properly compensated, it does not exhibit any overshoot. VID-Programmed DAC Reference Core Comparator The core comparator is an ultrafast hysteretic comparator with a typical propagation delay to the OUT pin of 15 ns at a 20 mV overdrive. This comparator is used with a switched hysteresis current for controlling the main feedback loop, as described in the Main Feedback Loop Operation section. This comparator has no relation to the CORE pin, which is used only for core voltage monitoring for the PWRGD function. Current Limit Comparator This 5-bit digital-to-analog converter (DAC) serves as the programmable reference source of the dc-dc converter. Programming is accomplished by CMOS logic-level VID code Pentium is a registered trademark of Intel Corp. The current limit comparator monitors the voltage across the current-sense resistor RCS and it overrides the core comparator and forces the OUT pin to low when the current exceeds the peak current limit threshold. The current control is hysteretic, with a valley current threshold equal to two-thirds of the peak current limit threshold. When the sensed current signal falls to two-thirds of the peak threshold, the OUT pin is allowed to go high again, and the control of the main loop reverts back to the core comparator. REV. A –7– ADP3421 A resistor (RCLS) connected between the CLSET and ground sets a current that is internally multiplied by a factor of three and flows out of the CS– pin. The resistor RCL connected in series with the CS– pin to the negative current sense point (i.e., the output voltage) sets the voltage that must be developed across RCS to trip the current limit comparator. Once it is tripped, the CS– current is scaled down by two-thirds, so the inductor current must ramp down accordingly to reset the comparator. Core Converter Soft-Start Timer time of the linear regulator output voltages. For maximum flexibility in controlling the start-up sequence, the soft-start function of the linear regulators was separated from that of the core converter. Level Translator The soft-start function limits the ramp-up time of the core voltage in order to reduce the initial in-rush current on the core input voltage (battery) rail. The soft-start circuit consists of an internal current source, an external soft-start timing capacitor, an internal switch across the capacitor, and a comparator monitoring the capacitor voltage. The soft-start capacitor is held discharged when either the SD signal is low or the device is in UVLO mode. As soon as SD is set to high, and VCC and VIN rise above their respective UVLO thresholds, the short across the external timing capacitor is removed, and the internal soft-start current source begins to charge the timing capacitor. During the charge of the soft-start capacitor, the Power Good signal is set to low. When the timing capacitor voltage reaches an internally set soft-start termination threshold, the core monitor window comparator output is enabled, allowing the Power Good status to be determined. If the core voltage has already settled within the specified limits the Power Good signal goes high, otherwise it stays low. The soft-start capacitor remains charged until either SD goes low, or VCC or VIN drop below their respective UVLO thresholds. When this occurs, an internal switch quickly discharges the soft-start timing capacitor to prepare the IC for a new start-up sequence. Soft-Start Restart Lock In The level translator converts any digital input signal to a userprogrammable voltage level. This can be used to translate an IO-level signal (i.e., 1.5 V) into a CLK-level or VCC-level or even 5 V-level signal. For example, the 1.5 V FERR# signal can be converted to a 3.3 V level for the PII-X4 chipset. The output signal is in phase with the input, and it is not necessary to have a pull-up on the input signal. The ADP3421 provides pull-up for the input signal to 1.5 V. The only practical restriction on the input signal is that it must not prevent pull-up to 1.5 V. An external pull-up resistor sets the output signal level. Throughput time for the signal using a 150 Ω pull-up resistor is 5 ns (typ). APPLICATION INFORMATION Overview—Combined ADP3421 and ADP3410 Power Controller for PC Systems The ADP3421 is a power controller that can provide a regulation solution for all three power rails of an Intel Pentium II or III processor. Together with the ADP3410 driver IC, these ICs form an integral part of a PC system, featuring a high-speed ( ~1 µF) input bypass MLC capacitor close to the MOSFETs so that the physical area of the loop enclosed in the electrical path through the bypass capacitor and around through the top and bottom MOSFETs (drain-source) is small. This is the switching power path loop. 5. Make provisions for thermal management of all the MOSFETs. Heavy copper and wide traces to ground and power planes will help to pull out the heat. Heat sinking by a metal tap soldered in the power plane near the MOSFETs will help. Even just small airflow can help tremendously. Paralleled MOSFETs will help spread the heat, even if the on resistance is higher. 6. An external “antiparallel” Schottky diode (across the bottom MOSFET) may help efficiency a small amount (< ~1 %); a MOSFET with a built-in antiparallel Schottky is more effective. For an external Schottky, it should be placed next to the bottom MOSFET or it may not be effective at all. Also, a higher current rating (bigger device with lower voltage drop) is more effective. 7. Both ground pins of the ADP3410 should be connected into the same ground plane with the power switching circuitry, and the VCC bypass capacitor should be close to the VCC pin and connected into the same ground plane. Output Filter Output Inductor and Capacitors, Current-Sense Resistor 12. If the placement overview cannot be followed, the ground pin of the ADP3421 should be Kelvin-connected into the ground plane near the output capacitors to avoid introducing ground noise from the power switching stage into the control circuitry. All other control components should be grounded on that same signal ground. 13. If critical signal lines (i.e., signals from the current-sense resistor leading back to the ADP3421) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. 14. Absolutely avoid crossing any signal lines over the switching power path loop, as previously described. 15. Accurate voltage positioning depends on accurate current sensing, so the control signals that differentially monitor the voltage across the current-sense resistor should be Kelvin-connected. 16. The RC filter used for the current-sense signal should be located near the control components. LDOs PNP Transistors 17. The maximum steady-state power dissipation expected for the design should be calculated so that an acceptable package type PNP for each output is selected and properly mounted to be able to dissipate the power with acceptable temperature rise. 18. Each PNP transistor should be located close to the load that it sources. 19. The supply voltage to the PNP emitters should be low impedance to avoid loop instability. It is good design practice to have at least one MLC capacitor near each of the PNP emitters to help ensure the impedance is sufficiently low. 8. Locate the current-sense resistor very near to the output capacitors. 9. PCB trace resistances from the current-sense resistor to the output capacitors, and from the output capacitors to the load, should be minimized, known (calculated or measured), and compensated for as part of the design if it is significant. (Remote sensing is not sufficient for relieving this requirement.) A square section of 1 ounce copper trace has a resistance of ~500 mΩ. Using 2~3 squares of copper can make a noticeable impact on a 15 A design. 10. Whenever high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. 11. The ground connection of the output capacitors should be close to the ground connection of the lower MOSFET and it should be a ground plane. Current may pulsate in this path if the power source ground is closer to the output capacitors than the power switching circuitry, so a close connection will minimize the voltage drop. REV. A –11– ADP3421 TYPICAL APPLICATION–GEYSERVILLE-ENABLED MOBILE VRM CONVERTER 5V 3.3V VIN U1 R1 51.1k ADP3421 1 VHYS CS– 28 CS+ 27 REG 26 RAMP 25 VCC 24 OUT 23 GND 22 DACOUT 21 CORE 20 SSC 19 SSL 18 UVLO 17 PWRGD 16 SD 15 C22 1nF R11 220k R16 3.3k R15 332 R22 100k U2 C25 22nF R19 2k C10 10 F D2 10BQ040 C15 10 F C16 10 F R10 10k R2 160k 2 CLSET 3 LTO 4 LTI 5 LTB 6 VID4 7 VID3 C31 1pF ADP3410 1 2 OVPSET SD R21,10k BST 14 DRVH 13 SW 12 SRMON 11 PGND 10 DRVL VCC 9 8 C28 10 F C17 100nF C2 100nF C1 100nF C41 1pF C29 100pF R17 75k M1 IRF7811 C32 15nF R20 10 3 4 GND IN DRVLSD L1 1H D1 10BQ040 RCS 5m VCC CPU CORE R18 576 5 6 C18 10pF R5 10k M2 IRF7811 R8 2.2 M3 IRF7811 R9 2.2 FROM CPU 8 VID2 9 VID1 10 VID0 C23 1nF C21 1.5nF R6 7.5k DLY VCCGD C4–C6, C11, C12, C26, C27 220 F 7 GND 7 Q2 2N3906 Q1 MJD210 C3 68 F C14 100 F 11 CLKDRV 12 CLKFB 13 IODRV 14 IOFB R12 470k C20 10 F VCC ON CORE SENSE V GATE VCC CPU IO VCC CPU CLK VRON Figure 1. Mobile VRM Schematic OUTLINE DIMENSIONS Dimensions shown in mm and (inches). 28-Lead Thin Shrink Small Outline Package (TSSOP) (RU-28) 9.80 (0.386) 9.60 (0.378) 28 15 4.50 (0.177) 4.30 (0.169) 6.50 (0.256) 6.25 (0.246) 1 14 PIN 1 0.15 (0.006) 0.05 (0.002) 1.10 (0.043) MAX SEATING PLANE 0.65 (0.026) BSC 0.30 (0.012) 0.19 (0.008) 0.20 (0.008) 0.09 (0.004) 8 0 0.70 (0.028) 0.50 (0.020) Revision History Location 5/02—Data Sheet changed from REV. 0 to REV. A. Page Changed Figures to TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Renumbered Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 –12– REV. A PRINTED IN U.S.A. CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN C00152–0–5/02(A)