ADP3625

High Speed, Dual, 4 A MOSFET Driver with Thermal Protection ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 FEATURES Industry-standard-compatible pinout High current drive capability Precise threshold shutdown comparator UVLO with hysteresis Overtemperature warning signal Overtemperature shutdown 3.3 V-compatible inputs 10 ns typical rise time and fall time @ 2.2 nF load Matched propagation delays between channels Fast propagation delay 9.5 V to 18 V supply voltage (ADP3633/ADP3634/ADP3635) 4.5 V to 18 V supply voltage (ADP3623/ADP3624/ADP3625) Parallelable dual outputs Rated from −40°C to +85°C ambient temperature Thermally enhanced packages, 8-lead SOIC_N_EP and 8-lead MINI_SO_EP GENERAL DESCRIPTION The ADP362x/ADP363x is a family of high current and dual high speed drivers, capable of driving two independent N-channel power MOSFETs. The family uses the industry-standard footprint but adds high speed switching performance and improved system reliability. The family has an internal temperature sensor and provides two levels of overtemperature protection, an overtemperature warning, and an overtemperature shutdown at extreme junction temperatures. The SD function, generated from a precise internal comparator, provides fast system enable or shutdown. This feature allows redundant overvoltage protection, complementing the protection inside the main controller device, or provides safe system shutdown in the event of an overtemperature warning. The wide input voltage range allows the driver to be compatible with both analog and digital PWM controllers. Digital power controllers are supplied from a low voltage supply, and the driver is supplied from a higher voltage supply. The ADP362x/ADP363x family adds UVLO and hysteresis functions, allowing safe startup and shutdown of the higher voltage supply when used with low voltage digital controllers. The device family is available in thermally enhanced SOIC_N_EP and MINI_SO_EP packaging to maximize high frequency and current switching in a small printed circuit board (PCB) area. APPLICATIONS AC-to-dc switch mode power supplies DC-to-dc power supplies Synchronous rectification Motor drives FUNCTIONAL BLOCK DIAGRAM VDD ADP3623/ADP3624/ADP3625 ADP3633/ADP3634/ADP3635 8 SD 1 OVERTEMPERATURE PROTECTION VEN NONINVERTING INA, 2 INA INVERTING PGND 3 UVLO NONINVERTING INB, 4 INB INVERTING VDD OTW 7 OUTA 6 VDD 5 OUTB 08132-101 Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing ....................................................... .... ..... 4 Absolute Maximum Ratings ............................................................ 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 9 Test Circuit ...................................................................................... 11 Theory of Operation ...................................................................... 12 Input Drive Requirements (INA, INA, INB, INB, and SD) .. 12 Low-Side Drivers (OUTA, OUTB) .......................................... 12 Shutdown (SD) Function .......................................................... 12 Overtemperature Protections ................................................... 12 Supply Capacitor Selection ....................................................... 13 PCB Layout Considerations ...................................................... 13 Parallel Operation ...................................................................... 13 Thermal Considerations............................................................ 14 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 16 REVISION HISTORY 7/09—Rev. 0 to Rev. A Added ADP3623, ADP3625, ADP3633, and ADP3635 .............................................................................. Universal Changes to Features Section, General Description Section, and Figure 1 ....................................................................................... 1 Changes to Table 1 ............................................................................ 3 Added Figure 4; Renumbered Sequentially .................................. 4 Added Figure 7.................................................................................. 7 Added Table 3; Renumbered Sequentially .................................... 7 Added Figure 9 and Table 5............................................................. 8 Changes to Figure 10 ........................................................................ 9 Changes to Figure 16 to Figure 19 Captions ............................... 10 Changes to Figure 20...................................................................... 11 Changes to Figure 21, Input Drive Requirements (INA, INA, INB, INB, and SD) Section, and Figure 22 ........................ 12 Changes to Figure 23 and Parallel Operation Section ............... 13 Changes to Design Example Section ........................................... 14 Changes to Ordering Guide .......................................................... 16 5/09—Revision 0: Initial Version Rev. A | Page 2 of 16 ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 SPECIFICATIONS VDD = 12 V, TJ = −40°C to +125°C, unless otherwise noted. 1 Table 1. Parameter SUPPLY Supply Voltage Range Supply Current Standby Current UVLO Turn-On Threshold Voltage Turn-Off Threshold Voltage Hysteresis DIGITAL INPUTS (INA, INA, INB, INB, SD) Input Voltage High Input Voltage Low Input Current SD Threshold High SD Threshold Low SD Hysteresis Internal Pull-Up/Pull-Down Current OUTPUTS (OUTA, OUTB) Output Resistance, Unbiased Peak Source Current Peak Sink Current SWITCHING TIME OUTA, OUTB Rise Time OUTA, OUTB Fall Time OUTA, OUTB Rising Propagation Delay OUTA, OUTB Falling Propagation Delay SD Propagation Delay Low SD Propagation Delay High Delay Matching Between Channels OVERTEMPERATURE PROTECTION Overtemperature Warning Threshold Overtemperature Shutdown Threshold Temperature Hysteresis for Shutdown Temperature Hysteresis for Warning Overtemperature Warning Low 1 Symbol VDD VDD IDD ISBY VUVLO_ON VUVLO_ON VUVLO_OFF VUVLO_OFF Test Conditions/Comments ADP3633/ADP3634/ADP3635 ADP3623/ADP3624/ADP3625 No switching, INA, INA, INB, and INB disabled SD = 5 V VDD rising, TA = 25°C, ADP3633/ADP3634/ADP3635 VDD rising, TA = 25°C, ADP3623/ADP3624/ADP3625 VDD falling, TA = 25°C, ADP3633/ADP3634/ADP3635 VDD falling, TA = 25°C, ADP3623/ADP3624/ADP3625 ADP3633/ADP3634/ADP3635 ADP3623/ADP3624/ADP3625 Min 9.5 4.5 Typ Max 18 18 3 3 9.5 4.5 8.5 4.3 Unit V V mA mA V V V V V V V V µA V V V mV µA kΩ A A 1.2 1.2 8.0 3.8 7.0 3.5 8.7 4.2 7.7 3.9 1.0 0.3 VIH VIL IIN VSD_H VSD_H VSD_L VSD_HYST 2.0 0 V < VIN < VDD TA = 25°C TA = 25°C TA = 25°C −20 1.19 1.21 0.95 240 0.8 +20 1.38 1.35 1.05 320 1.28 1.28 1.0 280 6 80 4 −4 10 10 14 22 32 48 2 VDD = PGND See Figure 20 See Figure 20 tRISE tFALL tD1 tD2 tdL_SD tdH_SD CLOAD = 2.2 nF, see Figure 3 and Figure 4 CLOAD = 2.2 nF, see Figure 3 and Figure 4 CLOAD = 2.2 nF, see Figure 3 and Figure 4 CLOAD = 2.2 nF, see Figure 3 and Figure 4 See Figure 2 See Figure 2 25 25 30 35 45 75 ns ns ns ns ns ns ns °C °C °C °C V TW TSD THYS_SD THYS_W VOTW_OL See Figure 6 See Figure 6 See Figure 6 See Figure 6 Open drain, −500 µA 120 150 135 165 30 10 150 180 0.4 All limits at temperature extremes guaranteed via correlation using standard statistical quality control (SQC) methods. Rev. A | Page 3 of 16 ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 TIMING SD tdL_SD tdH_SD 90% 10% 08132-002 OUTA, OUTB Figure 2. Shutdown Timing Diagram INA, INB VIH VIL tD1 tRISE tD2 tFALL 90% OUTA, OUTB 10% 90% 10% 08132-003 Figure 3. Output Timing Diagram (Noninverting) INA, INB VIL VIH tD1 tRISE tD2 tFALL 90% OUTA, OUTB 10% 90% 10% 08132-003 Figure 4. Output Timing Diagram (Inverting) VUVLO_ON VUVLO_OFF VDD UVLO MODE OUTPUTS DISABLED NORMAL OPERATION UVLO MODE OUTPUTS DISABLED Figure 5. UVLO Function Rev. A | Page 4 of 16 08132-005 ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 TSD TSD – THYS_SD TW TW – THYS_W TJ NORMAL OPERATION OT WARNING OUTPUTS ENABLED OTW OT SHUTDOWN OUTPUTS DISABLED OT WARNING OUTPUTS ENABLED 08132-006 NORMAL OPERATION Figure 6. Overtemperature Warning and Shutdown Rev. A | Page 5 of 16 ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VDD OUTA, OUTB DC 40 mil) traces to make these connections. Minimize trace inductance between the OUTA and OUTB outputs and MOSFET gates. Connect the PGND pin of the ADP362x/ADP363x device as closely as possible to the source of the MOSFETs. Rev. A | Page 13 of 16 4 B 5 08132-027 Figure 25. Parallel Operation 08132-021 ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 THERMAL CONSIDERATIONS When designing a power MOSFET gate drive, the maximum power dissipation in the driver must be considered to avoid exceeding maximum junction temperature. Data on package thermal resistance is provided in Table 2 to help the designer in this task. There are several equally important aspects that must be considered. • • • • • • Gate charge of the power MOSFET being driven Bias voltage value used to power the driver Maximum switching frequency of operation Value of external gate resistance Maximum ambient (and PCB) temperature Type of package In all practical applications where the external resistor is in the order of a few ohms, the contribution of the external resistor can be neglected, and the extra loss is assumed in the driver, providing a good guard band to the power loss calculations. In addition to the gate charge losses, there are also dc bias losses, due to the bias current of the driver. This current is present regardless of the switching. PDC = VDD × IDD The total estimated loss is the sum of PDC and PGATE. PLOSS = PDC + (n × PGATE) where n is the number of gates driven. When the total power loss is calculated, the temperature increase can be calculated as ΔTJ = PLOSS × θJA All of these factors influence and limit the maximum allowable power dissipated in the driver. The gate of a power MOSFET has a nonlinear capacitance characteristic. For this reason, although the input capacitance is usually reported in the MOSFET data sheet as CISS, it is not useful to calculate power losses. The total gate charge necessary to turn on a power MOSFET device is usually reported on the device data sheet under QG. This parameter varies from a few nanocoulombs (nC) to several hundreds of nC, and is specified at a specific VGS value (10 V or 4.5 V). The power necessary to charge and then discharge the gate of a power MOSFET can be calculated as: PGATE = VGS × QG × fSW where: VGS is the bias voltage powering the driver (VDD). QG is the total gate charge. fSW is the maximum switching frequency. The power dissipated for each gate (PGATE) still needs to be multiplied by the number of drivers (in this case, 1 or 2) being used in each package, and it represents the total power dissipated in charging and discharging the gates of the power MOSFETs. Not all of this power is dissipated in the gate driver because part of it is actually dissipated in the external gate resistor, RG. The larger the external gate resistor is, the smaller the amount of power that is dissipated in the gate driver. In modern switching power applications, the value of the gate resistor is kept at a minimum to increase switching speed and minimize switching losses. Design Example For example, consider driving two IRFS4310Z MOSFETs with a VDD of 12 V at a switching frequency of 300 kHz, using an ADP3624 in the SOIC_N_EP package. The maximum PCB temperature considered for this design is 85°C. From the MOSFET data sheet, the total gate charge is QG = 120 nC. PGATE = 12 V × 120 nC × 300 kHz = 432 mW PDC = 12 V × 1.2 mA = 14.4 mW PLOSS = 14.4 mW + (2 × 432 mW) = 878.4 mW From the MOSFET data sheet, the SOIC_N_EP thermal resistance is 59°C/W. ΔTJ = 878.4 mW × 59°C/W = 51.8°C TJ = TA + ΔTJ = 136.8°C ≤ TJMAX This estimated junction temperature does not factor in the power dissipated in the external gate resistor and, therefore, provides a certain guard band. If a lower junction temperature is required by the design, the MINI_SO_EP package can be used, which provides a thermal resistance of 43°C/W, so that the maximum junction temperature is ΔTJ = 878.4 mW × 43°C/W = 37.7°C TJ = TA + ΔTJ = 122.7°C ≤ TJMAX Other options to reduce power dissipation in the driver include reducing the value of the VDD bias voltage, reducing switching frequency, and choosing a power MOSFET with smaller gate charge. Rev. A | Page 14 of 16 ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 OUTLINE DIMENSIONS 4.00 (0.157) 3.90 (0.154) 3.80 (0.150) 5.00 (0.197) 4.90 (0.193) 4.80 (0.189) 8 1 5 4 2.29 (0.090) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 2.29 (0.090) TOP VIEW 6.20 (0.244) 6.00 (0.236) 5.80 (0.228) BOTTOM VIEW 1.27 (0.05) BSC 1.75 (0.069) 1.35 (0.053) 0.10 (0.004) MAX COPLANARITY 0.10 1.65 (0.065) 1.25 (0.049) SEATING PLANE 0.51 (0.020) 0.31 (0.012) (PINS UP) 0.50 (0.020) 0.25 (0.010) 45° 0.25 (0.0098) 0.17 (0.0067) 8° 0° 1.27 (0.050) 0.40 (0.016) COMPLIANT TO JEDEC STANDARDS MS-012-A A 072808A 071008-A CONTROLLING DIMENSIONS ARE IN MILLIMETER; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 26. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP] Narrow Body (RD-8-1) Dimensions shown in millimeters and (inches) 3.10 3.00 2.90 8 5 2.26 2.16 2.06 5.05 4.90 4.75 1.83 1.73 1.63 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 3.10 3.00 2.90 PIN 1 INDICATOR TOP VIEW 1 4 EXPOSED PAD 0.65 BSC 0.94 0.86 0.78 0.15 0.10 0.05 COPLANARITY 0.10 0.40 0.33 0.25 0.525 BSC BOTTOM VIEW 0.23 0.18 0.13 8° 0° 1.10 MAX SEATING PLANE 0.70 0.55 0.40 COMPLIANT TO JEDEC STANDARDS MO-187-AA-T Figure 27. 8-Lead Mini Small Outline Package with Exposed Pad [MINI_SO_EP] (RH-8-1) Dimensions shown in millimeters Rev. A | Page 15 of 16 ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 ORDERING GUIDE Model ADP3623ARDZ-RL1 ADP3623ARHZ-RL1 ADP3624ARDZ1 ADP3624ARDZ-RL1 ADP3624ARHZ1 ADP3624ARHZ-RL1 ADP3625ARDZ-RL1 ADP3625ARHZ-RL1 ADP3633ARDZ-RL1 ADP3633ARHZ-RL1 ADP3634ARDZ1 ADP3634ARDZ-RL1 ADP3634ARHZ1 ADP3634ARHZ-RL1 ADP3635ARDZ-RL1 ADP3635ARHZ-RL1 1 UVLO Option 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 9.5 V 9.5 V 9.5 V 9.5 V 9.5 V 9.5 V 9.5 V 9.5 V Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead Standard Small Outline Package (SOIC_N_EP), 13“ Tape and Reel 8-Lead Mini Small Outline Package (MINI_SO_EP), 13” Tape and Reel 8-Lead Standard Small Outline Package (SOIC_N_EP) 8-Lead Standard Small Outline Package (SOIC_N_EP), Tape Reel 8-Lead Mini Small Outline Package (MINI_SO_EP) 8-Lead Mini Small Outline Package (MINI_SO_EP), Tape Reel 8-Lead Standard Small Outline Package (SOIC_N_EP), 13” Tape and Reel 8-Lead Mini Small Outline Package (MINI_SO_EP), 13” Tape and Reel 8-Lead Standard Small Outline Package (SOIC_N_EP), 13” Tape and Reel 8-Lead Mini Small Outline Package (MINI_SO_EP), 13” Tape and Reel 8-Lead Standard Small Outline Package (SOIC_N_EP) 8-Lead Standard Small Outline Package (SOIC_N_EP), 13” Tape and Reel 8-Lead Mini Small Outline Package (MINI_SO_EP) 8-Lead Mini Small Outline Package (MINI_SO_EP), 13” Tape and Reel 8-Lead Standard Small Outline Package (SOIC_N_EP), 13” Tape and Reel 8-Lead Mini Small Outline Package (MINI_SO_EP), 13” Tape and Reel Package Option RD-8-1 RH-8-1 RD-8-1 RD-8-1 RH-8-1 RH-8-1 RD-8-1 RH-8-1 RD-8-1 RH-8-1 RD-8-1 RD-8-1 RH-8-1 RH-8-1 RD-8-1 RH-8-1 Ordering Quantity 2,500 3,000 Branding P3 2,500 P4 P4 3,000 2,500 3,000 2,500 3,000 P5 L3 2,500 L4 L4 3,000 2,500 3,000 L5 Z = RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08132-0-7/09(A) Rev. A | Page 16 of 16