ADP3629

High Speed, Dual, 2 A MOSFET Driver ADP3629/ADP3630/ADP3631 FEATURES Industry-standard-compatible pinout High current drive capability Precise threshold shutdown comparator UVLO with hysteresis Overtemperature warning signal Overtemperature shutdown 3.3 V-compatible inputs Rise time and fall time: 10 ns typical at 2.2 nF load Fast propagation delay Matched propagation delays between channels Supply voltage: 9.5 V to 18 V Dual outputs can be operated in parallel (ADP3629/ADP3630) Rated from −40°C to +85°C ambient temperature 8-lead SOIC_N and 8-lead MSOP GENERAL DESCRIPTION The ADP3629/ADP3630/ADP3631 are dual, high current, high speed drivers, capable of driving two independent N-channel power MOSFETs. The ADP3629/ADP3630/ADP3631 use the industry-standard footprint but add high speed switching performance and improved system reliability. The ADP3629/ADP3630/ADP3631 have an internal temperature sensor and provide two levels of overtemperature protection: an overtemperature warning and an overtemperature shutdown at extreme junction temperatures. The SD function, generated from a precise internal comparator, provides fast system enable or shutdown. This feature allows redundant overvoltage protection, complementing the protection inside the main controller device, or provides safe system shutdown in the event of an overtemperature warning. The wide input voltage range allows the driver to be compatible with both analog and digital PWM controllers. Digital power controllers are supplied from a low voltage supply, and the driver is supplied from a higher voltage supply. The ADP3629/ADP3630/ADP3631 add UVLO and hysteresis functions, allowing safe startup and shutdown of the higher voltage supply when used with low voltage digital controllers. APPLICATIONS AC-to-DC switch mode power supplies DC-to-DC power supplies Synchronous rectification Motor drives FUNCTIONAL BLOCK DIAGRAM VDD ADP3629/ADP3630/ADP3631 8 SD 1 OVERTEMPERATURE PROTECTION VEN NONINVERTING INA, 2 INA INVERTING PGND 3 UVLO NONINVERTING INB, 4 INB INVERTING VDD OTW 7 OUTA 6 VDD 5 OUTB 08401-101 Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADP3629/ADP3630/ADP3631 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  General Description ......................................................................... 1  Functional Block Diagram .............................................................. 1  Revision History ............................................................................... 2  Specifications..................................................................................... 3  Timing Diagrams.......................................................................... 4  Absolute Maximum Ratings............................................................ 6  Thermal Resistance ...................................................................... 6  ESD Caution .................................................................................. 6  Pin Configurations and Function Descriptions ........................... 7  Typical Performance Characteristics ............................................. 8  Test Circuit ...................................................................................... 10  Theory of Operation ...................................................................... 11  Input Drive Requirements (INA, INA, INB, INB, and SD) .. 11  Low-Side Drivers (OUTA, OUTB) .......................................... 11  Shutdown (SD) Function .......................................................... 11  Overtemperature Protections ................................................... 12  Supply Capacitor Selection ....................................................... 12  PCB Layout Considerations ...................................................... 12  Parallel Operation ...................................................................... 12  Thermal Considerations............................................................ 13  Outline Dimensions ....................................................................... 14  Ordering Guide .......................................................................... 14  REVISION HISTORY 9/09—Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADP3629/ADP3630/ADP3631 SPECIFICATIONS VDD = 12 V, TJ = −40°C to +125°C, unless otherwise noted. 1 Table 1. Parameter SUPPLY Supply Voltage Range Supply Current Standby Current UVLO Turn-On Threshold Voltage Turn-Off Threshold Voltage Hysteresis DIGITAL INPUTS (INA, INA, INB, INB, SD) Input Voltage High Input Voltage Low Input Current SD Threshold High SD Threshold Low SD Hysteresis Internal Pull-Up/Pull-Down Current OUTPUTS (OUTA, OUTB) Output Resistance, Unbiased Peak Source Current Peak Sink Current SWITCHING TIME OUTA, OUTB Rise Time OUTA, OUTB Fall Time OUTA, OUTB Rising Propagation Delay OUTA, OUTB Falling Propagation Delay SD Propagation Delay Low SD Propagation Delay High Delay Matching Between Channels OVERTEMPERATURE PROTECTION Overtemperature Warning Threshold Overtemperature Shutdown Threshold Temperature Hysteresis for Shutdown Temperature Hysteresis for Warning Overtemperature Warning Low 1 Symbol VDD IDD ISBY VUVLO_ON VUVLO_OFF Test Conditions/Comments Min 9.5 Typ Max 18 3 3 9.5 8.5 Unit V mA mA V V V V V μA V V V mV μA kΩ A A No switching, INA, INA, INB, and INB disabled SD = 5 V VDD rising, TA = 25°C VDD falling, TA = 25°C 8.0 7.0 1.2 1.2 8.7 7.7 1.0 VIH VIL IIN VSD_H VSD_L VSD_HYST 2.0 0 V < VIN < VDD TA = 25°C TA = 25°C TA = 25°C −20 1.19 1.21 0.95 240 0.8 +20 1.38 1.35 1.05 320 1.28 1.28 1.0 280 6 80 2 −2 10 10 14 22 32 48 2 VDD = PGND See Figure 20 See Figure 20 tRISE tFALL tD1 tD2 tdL_SD tdH_SD CLOAD = 2.2 nF, see Figure 3 and Figure 4 CLOAD = 2.2 nF, see Figure 3 and Figure 4 CLOAD = 2.2 nF, see Figure 3 and Figure 4 CLOAD = 2.2 nF, see Figure 3 and Figure 4 See Figure 2 See Figure 2 25 25 30 35 45 75 ns ns ns ns ns ns ns °C °C °C °C V TW TSD THYS_SD THYS_W VOTW_OL See Figure 6 See Figure 6 See Figure 6 See Figure 6 Open drain, −500 μA 120 150 135 165 30 10 150 180 0.4 All limits at temperature extremes guaranteed via correlation using standard statistical quality control (SQC) methods. Rev. 0 | Page 3 of 16 ADP3629/ADP3630/ADP3631 TIMING DIAGRAMS SD tdL_SD tdH_SD 90% 10% 08401-002 OUTA, OUTB Figure 2. Shutdown Timing Diagram INA, INB VIH VIL tD1 tRISE tD2 tFALL 90% OUTA, OUTB 10% 90% 10% 08401-003 Figure 3. Output Timing Diagram (Noninverting) INA, INB VIL VIH tD1 tRISE tD2 tFALL 90% OUTA, OUTB 10% 90% 10% 08401-103 Figure 4. Output Timing Diagram (Inverting) VUVLO_ON VUVLO_OFF VDD UVLO MODE OUTPUTS DISABLED NORMAL OPERATION UVLO MODE OUTPUTS DISABLED Figure 5. UVLO Function Rev. 0 | Page 4 of 16 08401-005 ADP3629/ADP3630/ADP3631 TSD TSD – THYS_SD TW TW – THYS_W TJ NORMAL OPERATION OT WARNING OUTPUTS ENABLED OTW OT SHUTDOWN OUTPUTS DISABLED OT WARNING OUTPUTS ENABLED 08401-006 NORMAL OPERATION Figure 6. Overtemperature Warning and Shutdown Rev. 0 | Page 5 of 16 ADP3629/ADP3630/ADP3631 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VDD OUTA, OUTB DC 40 mil) traces to make these connections. Minimize trace inductance between the OUTA and OUTB outputs and the MOSFET gates. Connect the PGND pin as close as possible to the source of the MOSFETs. Place the VDD bypass capacitor as close as possible to the VDD and PGND pins. When possible, use vias to other layers to maximize thermal conduction away from the IC. The overtemperature warning is an open-drain logic signal and is active low. In normal operation, when no thermal warning is present, the signal is high, whereas when the warning threshold is crossed, the signal is pulled low. 3.3V VDD OTW FLAGIN Figure 24 shows an example of the typical layout based on the preceding guidelines. ADP3629/ADP3630/ADP3631 PGND VDD OTW ADP1043 PGND The OTW open-drain configuration allows the connection of multiple devices to the same warning bus in a wire-OR’ed configuration, as shown in Figure 23. The overtemperature shutdown turns off the device to protect it in the event that the die temperature exceeds the absolute maximum limit of 150°C (see Table 2). Figure 24. External Component Placement Example PARALLEL OPERATION The two driver channels in the ADP3629 and ADP3630 devices can be combined to operate in parallel to increase drive capability and minimize power dissipation in the driver. The connection scheme for the ADP3630 is shown in Figure 25. In this configuration, INA and INB are connected together, and OUTA and OUTB are connected together. Particular attention must be paid to the layout in this case to optimize load sharing between the two drivers. 1 SD OTW 8 SUPPLY CAPACITOR SELECTION A local bypass capacitor for the supply input (VDD) of the ADP3629/ADP3630/ADP3631 is recommended to reduce the noise and to supply some of the peak currents that are drawn. An improper decoupling can dramatically increase the rise times, cause excessive resonance on the OUTA and OUTB pins, and, in some extreme cases, even damage the device due to inductive overvoltage on the VDD or OUTA/OUTB pins. The minimum capacitance required is determined by the size of the gate capacitances being driven, but as a general rule, a 4.7 μF, low ESR capacitor should be used. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size. To further reduce noise, use a smaller ceramic capacitor (100 nF) with a better high frequency characteristic in parallel with the main capacitor. Place the ceramic capacitor as close as possible to the ADP3629/ ADP3630/ADP3631 device and minimize the length of the traces going from the capacitor to the power pins of the device. ADP3630 2 INA A OUTA 7 VDD 3 PGND VDD 6 VDS INB OUTB 4 B 5 08401-027 Figure 23. OTW Signaling Scheme Example 08401-019 ADP3629/ADP3630/ADP3631 Figure 25. Parallel Operation Rev. 0 | Page 12 of 16 08401-021 ADP3629/ADP3630/ADP3631 THERMAL CONSIDERATIONS When designing a power MOSFET gate drive, the maximum power dissipation in the driver must be considered to avoid exceeding the maximum junction temperature. Data on package thermal resistance is provided in Table 3 to help the designer in this task. Several equally important aspects must also be considered. • • • • • • Gate charge of the power MOSFET being driven Bias voltage value used to power the driver Maximum switching frequency of operation Value of external gate resistance Maximum ambient (and PCB) temperature Type of package In all practical applications where the external resistor is in the order of a few ohms, the contribution of the external resistor can be ignored, and the extra loss is assumed to be in the driver, providing a good guard band for the power loss calculations. In addition to the gate charge losses, there are also dc bias losses (PDC) due to the bias current of the driver. This current is present regardless of the switching frequency. PDC = VDD × IDD The total estimated loss is the sum of PDC and PGATE. PLOSS = PDC + (n × PGATE) where n is the number of gates driven. When the total power loss is calculated, the temperature increase can be calculated as follows: ΔTJ = PLOSS × θJA All of these factors influence and limit the maximum allowable power dissipated in the driver. The gate of a power MOSFET has a nonlinear capacitance characteristic. For this reason, although the input capacitance is usually reported in the MOSFET data sheet as CISS, it is not useful to calculate power losses. The total gate charge necessary to turn on a power MOSFET device is usually reported on the device data sheet under QG. This parameter varies from a few nanocoulombs (nC) to several hundreds of nC and is specified at a specific VGS value (10 V or 4.5 V). The power necessary to charge and then discharge the gate of a power MOSFET can be calculated as follows: PGATE = VGS × QG × fSW where: VGS is the bias voltage powering the driver (VDD). QG is the total gate charge. fSW is the maximum switching frequency. The power dissipated for each gate (PGATE) must be multiplied by the number of drivers (in this case, 1 or 2) being used in each package; this PGATE value represents the total power dissipated in charging and discharging the gates of the power MOSFETs. Not all of this power is dissipated in the gate driver because part of it is actually dissipated in the external gate resistor, RG. The larger the external gate resistor, the smaller the amount of power that is dissipated in the gate driver. In modern switching power applications, the value of the gate resistor is kept at a minimum to increase switching speed and to minimize switching losses. Design Example For example, consider driving two IRFS4310Z MOSFETs with a VDD of 12 V at a switching frequency of 100 kHz, using an ADP3630 in the MSOP package. The maximum PCB temperature considered for this design is 85°C. From the MOSFET data sheet, the total gate charge is QG = 120 nC. PGATE = 12 V × 120 nC × 100 kHz = 144 mW PDC = 12 V × 1.2 mA = 14.4 mW PLOSS = 14.4 mW + (2 × 144 mW) = 302.4 mW The MSOP thermal resistance is 162.2°C/W (see Table 3). ΔTJ = 302.4 mW × 162.2°C/W = 49.0°C TJ = TA + ΔTJ = 134.0°C ≤ TJ_MAX This estimated junction temperature does not factor in the power dissipated in the external gate resistor and, therefore, provides a certain guard band. If a lower junction temperature is required by the design, the SOIC_N package, which provides a thermal resistance of 110.6°C/W, can be used. Using the SOIC_N package, the maximum junction temperature is ΔTJ = 302.4 mW × 110.6°C/W = 33.4°C TJ = TA + ΔTJ = 118.4°C ≤ TJ_MAX Other options to reduce power dissipation in the driver include reducing the value of the VDD bias voltage, reducing the switching frequency, and choosing a power MOSFET with a smaller gate charge. Rev. 0 | Page 13 of 16 ADP3629/ADP3630/ADP3631 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 5 4 4.00 (0.1574) 3.80 (0.1497) 1 6.20 (0.2441) 5.80 (0.2284) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 0.50 (0.0196) 0.25 (0.0099) 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 45° 0.51 (0.0201) 0.31 (0.0122) COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 26. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 3.20 3.00 2.80 8 5 3.20 3.00 2.80 PIN 1 IDENTIFIER 1 5.15 4.90 4.65 4 0.65 BSC 0.95 0.85 0.75 0.15 0.05 COPLANARITY 0.10 0.40 0.25 15° MAX 1.10 MAX 0.70 0.55 0.40 091709-A 6° 0° 0.23 0.13 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 27. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE Model ADP3629ARZ-R7 1 ADP3629ARMZ-R71 ADP3630ARZ-R71 ADP3630ARMZ-R71 ADP3631ARZ-R71 ADP3631ARMZ-R71 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Mini Small Outline Package [MSOP] Package Option R-8 RM-8 R-8 RM-8 R-8 RM-8 012407-A Ordering Quantity 2,500 3,000 2,500 3,000 2,500 3,000 Branding L8Q L8R L8S Z = RoHS Compliant Part. Rev. 0 | Page 14 of 16 ADP3629/ADP3630/ADP3631 NOTES Rev. 0 | Page 15 of 16 ADP3629/ADP3630/ADP3631 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08401-0-9/09(0) Rev. 0 | Page 16 of 16