ADP3650JCPZ-RL

Dual, Bootstrapped, 12 V MOSFET Driver with Output Disable ADP3650 Data Sheet FEATURES GENERAL DESCRIPTION All-in-one synchronous buck driver Bootstrapped high-side drive One PWM signal generates both drives Anti-crossconduction protection circuitry OD for disabling the driver outputs The ADP3650 is a dual, high voltage MOSFET driver optimized for driving two N-channel MOSFETs, the two switches in a nonisolated synchronous buck power converter. Each driver is capable of driving a 3000 pF load with a 45 ns propagation delay and a 25 ns transition time. One of the drivers can be bootstrapped and is designed to handle the high voltage slew rate associated with floating high-side gate drivers. The ADP3650 includes overlapping drive protection to prevent shoot-through current in the external MOSFETs. APPLICATIONS Telecom and datacom networking Industrial and medical systems Point of load conversion: memory, DSP, FPGA, ASIC The OD pin shuts off both the high-side and the low-side MOSFETs to prevent rapid output capacitor discharge during system shutdown. The ADP3650 is specified over the temperature range of −40°C to +85°C and is available in 8-lead SOIC_N and 8-lead LFCSP packages. FUNCTIONAL BLOCK DIAGRAM 12V D1 VCC 4 BST ADP3650 1 LATCH R1 R2 Q S IN 2 CBST2 CBST1 DRVH RG 8 Q1 DELAY RBST TO INDUCTOR SW 7 CMP VCC 6 CMP CONTROL LOGIC DRVL Q2 5 PGND DELAY 6 OD 3 07826-001 1V Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2008–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADP3650 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Low-Side Driver ............................................................................9 Applications ....................................................................................... 1 High-Side Driver ...........................................................................9 General Description ......................................................................... 1 Overlap Protection Circuit...........................................................9 Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 10 Revision History ............................................................................... 2 Supply Capacitor Selection ....................................................... 10 Specifications..................................................................................... 3 Bootstrap Circuit ........................................................................ 10 Timing Characteristics ................................................................ 4 MOSFET Selection ..................................................................... 10 Absolute Maximum Ratings ............................................................ 5 High-Side (Control) MOSFETs ................................................ 10 Thermal Resistance ...................................................................... 5 Low-Side (Synchronous) MOSFETs ........................................ 11 ESD Caution .................................................................................. 5 PCB Layout Considerations ...................................................... 11 Pin Configurations and Function Descriptions ........................... 6 Outline Dimensions ....................................................................... 12 Typical Performance Characteristics ............................................. 7 Ordering Guide .......................................................................... 12 Theory of Operation ........................................................................ 9 REVISION HISTORY 9/2017—Rev. A to Rev. B Changed CP-8-2 to CP-8-13 ........................................ Throughout Updated Outline Dimensions ....................................................... 12 Changes to Ordering Guide .......................................................... 12 7/2010—Rev. 0 to Rev. A Changes to General Description Section ...................................... 1 Changes to Table 1 ............................................................................ 3 Changes to Operating Ambient Temperature Range Parameter, Table 2 ................................................................................................ 5 Changes to Figure 8 and Figure 9 ................................................... 7 Changes to Ordering Guide .......................................................... 12 10/2008—Revision 0: Initial Version Rev. B | Page 2 of 12 Data Sheet ADP3650 SPECIFICATIONS VCC = 12 V, BST = 4 V to 26 V, TA = −40°C to +85°C, unless otherwise noted. 1 Table 1. Parameter DIGITAL INPUTS (IN, OD) Input Voltage High Input Voltage Low Input Current Hysteresis HIGH-SIDE DRIVER Output Resistance, Sourcing Current Symbol Propagation Delay Times −1 40 trDRVH tfDRVH tpdhDRVH tpdlDRVH t pdl OD tpdh OD SW Pull-Down Resistance LOW-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Output Resistance, Unbiased Transition Times Propagation Delay Times trDRVL tfDRVL tpdhDRVL tpdlDRVL t pdl OD tpdh Timeout Delay SUPPLY Supply Voltage Range Supply Current UVLO Voltage Hysteresis 1 Min Typ Max Unit 250 0.8 +1 350 V V µA mV 2.0 Output Resistance, Sinking Current Output Resistance, Unbiased Transition Times Test Conditions/Comments VCC ISYS OD BST − SW = 12 V; TA = 25°C BST − SW = 12 V; TA = −40°C to +85°C BST − SW = 12 V; TA = 25°C BST − SW = 12 V; TA = −40°C to +85°C BST − SW = 0 V BST − SW = 12 V, CLOAD = 3 nF, see Figure 3 BST − SW = 12 V, CLOAD = 3 nF, see Figure 3 BST − SW = 12 V, CLOAD = 3 nF, 25°C ≤ TA ≤ 85°C, see Figure 3 BST − SW = 12 V, CLOAD = 3 nF, see Figure 3 See Figure 2 1.4 10 25 20 45 40 30 70 Ω Ω Ω Ω kΩ ns ns ns 25 20 35 35 ns ns See Figure 2 40 55 ns SW to PGND 10 2.5 32 TA = 25°C TA = −40°C to +85°C TA = 25°C TA = −40°C to +85°C VCC = PGND CLOAD = 3 nF, see Figure 3 CLOAD = 3 nF, see Figure 3 CLOAD = 3 nF, see Figure 3 CLOAD = 3 nF, see Figure 3 See Figure 2 2.4 1.4 10 20 16 12 30 20 3.3 3.9 1.8 2.6 kΩ 3.3 3.9 1.8 2.6 35 30 35 45 35 Ω Ω Ω Ω kΩ ns ns ns ns ns See Figure 2 110 190 ns SW = 5 V SW = PGND 110 95 190 150 ns ns 4.15 BST = 12 V, IN = 0 V VCC rising 2 1.5 350 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. Rev. B | Page 3 of 12 13.2 5 3.0 V mA V mV ADP3650 Data Sheet TIMING CHARACTERISTICS Timing is referenced to the 90% and 10% points, unless otherwise noted. OD tpdlOD tpdhOD 07826-004 90% DRVH OR DRVL 10% Figure 2. Output Disable Timing Diagram IN tpdlDRVL tfDRVL tpdlDRVH trDRVL DRVL tfDRVH tpdhDRVH DRVH TO SW trDRVH VTH VTH 1V Figure 3. Timing Diagram Rev. B | Page 4 of 12 07826-005 tpdhDRVL SW Data Sheet ADP3650 ABSOLUTE MAXIMUM RATINGS All voltages are referenced to PGND, unless otherwise noted. Table 2. Parameter VCC BST DC