ADP3654ARDZ-RL

High Speed, Dual, 4 A MOSFET Driver ADP3654 Data Sheet FEATURES GENERAL DESCRIPTION Industry-standard-compatible pinout High current drive capability Precise UVLO comparator with hysteresis 3.3 V-compatible inputs 10 ns typical rise time and fall time at 2.2 nF load Matched propagation delays between channels Fast propagation delay 4.5 V to 18 V supply voltage Parallelable dual outputs Rated from −40°C to +125°C junction temperature Thermally enhanced packages, 8-lead SOIC_N_EP and 8-lead MINI_SO_EP The ADP3654 high current and dual high speed driver is capable of driving two independent N-channel power MOSFETs. The driver uses the industry-standard footprint but adds high speed switching performance. APPLICATIONS The driver is available in thermally enhanced SOIC_N_EP and MINI_SO_EP packaging to maximize high frequency and current switching in a small printed circuit board (PCB) area. The wide input voltage range allows the driver to be compatible with both analog and digital PWM controllers. Digital power controllers are powered from a low voltage supply, and the driver is powered from a higher voltage supply. The ADP3654 driver adds UVLO and hysteresis functions, allowing safe startup and shutdown of the higher voltage supply when used with low voltage digital controllers. AC-to-dc switch mode power supplies DC-to-dc power supplies Synchronous rectification Motor drives FUNCTIONAL BLOCK DIAGRAM NC 1 ADP3654 INA 2 PGND 3 UVLO NC 7 OUTA 6 VDD 4 5 OUTB 09054-001 INB 8 VDD Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2010–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADP3654 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Test Circuit .........................................................................................8 Applications ....................................................................................... 1 Theory of Operation .........................................................................9 General Description ......................................................................... 1 Input Drive Requirements (INA and INB) ................................9 Functional Block Diagram .............................................................. 1 Low-Side Drivers (OUTA, OUTB) .............................................9 Revision History ............................................................................... 2 Supply Capacitor Selection ..........................................................9 Specifications..................................................................................... 3 PCB Layout Considerations .........................................................9 Timing Diagrams.......................................................................... 3 Parallel Operation ...................................................................... 10 Absolute Maximum Ratings ............................................................ 4 Thermal Considerations............................................................ 10 ESD Caution .................................................................................. 4 Outline Dimensions ....................................................................... 12 Pin Configuration and Function Descriptions ............................. 5 Ordering Guide .......................................................................... 13 Typical Performance Characteristics ............................................. 6 REVISION HISTORY 8/15—Rev. 0 to Rev. A Changes to Figure 5 .......................................................................... 6 Updated Outline Dimensions ....................................................... 12 Changes to Ordering Guide .......................................................... 13 8/10—Revision 0: Initial Version Rev. A | Page 2 of 13 ADP3654 Data Sheet SPECIFICATIONS VDD = 12 V, TJ = −40°C to +125°C, unless otherwise noted.1 Table 1. Parameter SUPPLY Supply Voltage Range Supply Current UVLO Turn-On Threshold Voltage Turn-Off Threshold Voltage Hysteresis DIGITAL INPUTS (INA, INB) Input Voltage High Input Voltage Low Input Current Internal Pull-Up/Pull-Down Current OUTPUTS (OUTA, OUTB) Output Resistance, Unbiased Peak Source Current Peak Sink Current SWITCHING TIME OUTA and OUTB Rise Time OUTA and OUTB Fall Time OUTA and OUTB Rising Propagation Delay OUTA and OUTB Falling Propagation Delay Delay Matching Between Channels 1 Symbol Test Conditions/Comments VDD IDD No switching VUVLO_ON VUVLO_OFF VDD rising, TJ = 25°C, see Figure 3 VDD falling, TJ = 25°C, see Figure 3 3.8 3.5 VIH VIL IIN See Figure 2 See Figure 2 0 V < VIN < VDD 2.0 tRISE tFALL tD1 tD2 Min 18 3 V mA 4.5 4.3 V V V 6 VDD = PGND See Figure 14 See Figure 14 80 4 −4 kΩ A A CLOAD = 2.2 nF, see Figure 2 CLOAD = 2.2 nF, see Figure 2 CLOAD = 2.2 nF, see Figure 2 CLOAD = 2.2 nF, see Figure 2 10 10 14 22 2 0.8 +20 −20 VIL tRISE tD2 tFALL 90% 90% 09054-002 10% 10% Figure 2. Output Timing Diagram VUVLO_ON VUVLO_OFF NORMAL OPERATION UVLO MODE OUTPUTS DISABLED OUTPUTS DISABLED Figure 3. UVLO Function Rev. A | Page 3 of 13 09054-003 VDD UVLO MODE 1.2 V V µA µA VIH OUTA, OUTB Unit 4.2 3.9 0.3 TIMING DIAGRAMS tD1 Max 4.5 All limits at temperature extremes guaranteed via correlation using standard statistical quality control (SQC) methods. INA, INB Typ 25 25 30 35 ns ns ns ns ns ADP3654 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VDD OUTA, OUTB DC 40 mil) traces to make these connections. Minimize trace inductance between the OUTA and OUTB outputs and MOSFET gates. Connect the PGND pin of the ADP3654 device as closely as possible to the source of the MOSFETs. Place the VDD bypass capacitor as close as possible to the VDD and PGND pins. Use vias to other layers, when possible, to maximize thermal conduction away from the IC. ADP3654 Data Sheet Figure 16 shows an example of the typical layout based on the preceding guidelines. THERMAL CONSIDERATIONS When designing a power MOSFET gate drive, the maximum power dissipation in the driver must be considered to avoid exceeding maximum junction temperature. Data on package thermal resistance is provided in Table 2 to help the designer with this task. 09054-016 There are several equally important aspects that must be considered, such as the following: Figure 16. External Component Placement Example Note that the exposed pad of the package is not directly connected to any pin of the package, but it is electrically and thermally connected to the die substrate, which is the ground of the device. PARALLEL OPERATION The two driver channels present in the ADP3654 device can be combined to operate in parallel to increase drive capability and minimize power dissipation in the driver. The connection scheme is shown in Figure 17. In this configuration, INA and INB are connected together, and OUTA and OUTB are connected together. Particular attention must be paid to the layout in this case to optimize load sharing between the two drivers. 1 NC NC • • • • • • All of these factors influence and limit the maximum allowable power dissipated in the driver. The gate of a power MOSFET has a nonlinear capacitance characteristic. For this reason, although the input capacitance is usually reported in the MOSFET data sheet as CISS, it is not useful to calculate power losses. The total gate charge necessary to turn on a power MOSFET device is usually reported on the device data sheet under QG. This parameter varies from a few nanocoulombs (nC) to several hundred nC, and is specified at a specific VGS value (10 V or 4.5 V). The power necessary to charge and then discharge the gate of a power MOSFET can be calculated as: 8 PGATE = VGS × QG × fSW ADP3654 2 INA A OUTA where: VGS is the bias voltage powering the driver (VDD). QG is the total gate charge. fSW is the maximum switching frequency. 7 VDD 3 PGND VDD 6 VDS INB B OUTB 5 09054-017 4 Figure 17. Parallel Operation Gate charge of the power MOSFET being driven Bias voltage value used to power the driver Maximum switching frequency of operation Value of external gate resistance Maximum ambient (and PCB) temperature Type of package The power dissipated for each gate (PGATE) still needs to be multiplied by the number of drivers (in this case, 1 or 2) being used in each package, and it represents the total power dissipated in charging and discharging the gates of the power MOSFETs. Not all of this power is dissipated in the gate driver because part of it is actually dissipated in the external gate resistor, RG. The larger the external gate resistor is, the smaller the amount of power that is dissipated in the gate driver. In modern switching power applications, the value of the gate resistor is kept at a minimum to increase switching speed and minimize switching losses. In all practical applications where the external resistor is in the order of a few ohms, the contribution of the external resistor can be neglected, and the extra loss is assumed in the driver, providing a good guard band to the power loss calculations. Rev. A | Page 10 of 13 ADP3654 Data Sheet The SOIC_N_EP thermal resistance is 59°C/W. In addition to the gate charge losses, there are also dc bias losses, due to the bias current of the driver. This current is present regardless of the switching. ΔTJ = 878.4 mW × 59°C/W = 51.8°C TJ = TA + ΔTJ = 136.8°C ≤ TJMAX PDC = VDD × IDD This estimated junction temperature does not factor in the power dissipated in the external gate resistor and, therefore, provides a certain guard band. The total estimated loss is the sum of PDC and PGATE. PLOSS = PDC + (n × PGATE) where n is the number of gates driven. If a lower junction temperature is required by the design, the MINI_SO_EP package can be used, which provides a thermal resistance of 43°C/W, so that the maximum junction temperature is When the total power loss is calculated, the temperature increase can be calculated as ΔTJ = PLOSS × θJA ΔTJ = 878.4 mW × 43°C/W = 37.7°C Design Example For example, consider driving two IRFS4310Z MOSFETs with a VDD of 12 V at a switching frequency of 300 kHz, using an ADP3654 in the SOIC_N_EP package. The maximum PCB temperature considered for this design is 85°C. TJ = TA + ΔTJ = 122.7°C ≤ TJMAX Other options to reduce power dissipation in the driver include reducing the value of the VDD bias voltage, reducing switching frequency, and choosing a power MOSFET with smaller gate charge. From the MOSFET data sheet, the total gate charge is QG = 120 nC. PGATE = 12 V × 120 nC × 300 kHz = 432 mW PDC = 12 V × 1.2 mA = 14.4 mW PLOSS = 14.4 mW + (2 × 432 mW) = 878.4 mW Rev. A | Page 11 of 13 ADP3654 Data Sheet OUTLINE DIMENSIONS 5.00 4.90 4.80 2.29 0.356 5 1 4 6.20 6.00 5.80 4.00 3.90 3.80 2.29 0.457 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. BOTTOM VIEW 1.27 BSC 3.81 REF TOP VIEW 1.65 1.25 1.75 1.35 0.10 MAX 0.05 NOM COPLANARITY 0.10 0.51 0.31 8° 0° 45° 0.25 0.17 1.04 REF 1.27 0.40 COMPLIANT TO JEDEC STANDARDS MS-012-A A Figure 18. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP] Narrow Body (RD-8-1) Dimensions shown in millimeters 3.10 3.00 2.90 3.10 3.00 2.90 2.26 2.16 2.06 5 8 TOP VIEW 1 EXPOSED PAD 4 PIN 1 INDICATOR 0.65 BSC 0.94 0.86 0.78 0.15 0.10 0.05 COPLANARITY 0.10 5.05 4.90 4.75 0.525 BSC 1.10 MAX 0.40 0.33 0.25 SEATING PLANE BOTTOM VIEW 1.83 1.73 1.63 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.23 0.18 0.13 8° 0° 0.70 0.55 0.40 COMPLIANT TO JEDEC STANDARDS MO-187-AA-T Figure 19. 8-Lead Mini Small Outline Package with Exposed Pad [MINI_SO_EP] (RH-8-1) Dimensions shown in millimeters Rev. A | Page 12 of 13 071008-A SEATING PLANE 0.50 0.25 06-02-2011-B 8 ADP3654 Data Sheet ORDERING GUIDE Model1 ADP3654ARDZ UVLO Option 4.5 V Temperature Range −40°C to +125°C ADP3654ARDZ-R7 4.5 V −40°C to +125°C ADP3654ARDZ-RL 4.5 V −40°C to +125°C ADP3654ARHZ 4.5 V −40°C to +125°C ADP3654ARHZ-R7 4.5 V −40°C to +125°C ADP3654ARHZ-RL 4.5 V −40°C to +125°C 1 Package Description 8-Lead Standard Small Outline Package (SOIC_N_EP), Tube 8-Lead Standard Small Outline Package (SOIC_N_EP), 7“ Tape and Reel 8-Lead Standard Small Outline Package (SOIC_N_EP), 13“ Tape and Reel 8-Lead Mini Small Outline Package (MINI_SO_EP), Tube 8-Lead Mini Small Outline Package (MINI_SO_EP), 7“ Tape and Reel) 8-Lead Mini Small Outline Package (MINI_SO_EP), 13” Tape and Reel Z = RoHS Compliant Part. ©2010–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09054-0-8/15(A) Rev. A | Page 13 of 13 Package Option RD-8-1 Ordering Quantity 98 RD-8-1 1,000 RD-8-1 2,500 RH-8-1 50 78 RH-8-1 1,000 78 RH-8-1 3,000 78 Branding