Low Noise Micro PMU,
3 A Buck Regulator with 3 A LDO
ADP5003
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
EN1
VPVIN1 :
4.2V TO 15V
PVIN1
CPVIN1
VOUT1
COMP1
RC
CC
RBOT1
BUCK
REGULATOR
3A
VSET1
SW1
SW1
SW1
L1
VPVOUT1 :
0.6V TO 5.0V
CPVOUT1
PGND1
PGND1
PGND1
RTOP1
VREG
VPVINSYS :
4.2V TO 15V
RT
CVREG
PVINSYS
RRT
PWRGD
SYSTEM
CPVINSYS
SYNC
REFOUT
CREFOUT
PVIN2
PVIN2
VSET2
CPVIN2
PVIN2
VBUF
CVBUF
VREG_LDO
LOW NOISE
LDO ACTIVE
FILTER
3A
CVREG_LDO
PVOUT2
PVOUT2
PVOUT2
VPVOUT2 :
0.6V TO 3.3V
CPVOUT2
LOAD
VFB2P
EN2
VFB2N
AGND1
Low noise power for high speed analog-to-digital converter
(ADC) and digital-to-analog converter (DAC) designs
Powering RF transceivers and clocking ICs
PVIN1
AGND2
15021-001
Low noise, dc power supply system
High efficiency buck for first stage conversion
High PSRR, low noise LDO regulator to remove switching
ripple
Adaptive LDO regulator headroom control option for
optimal efficiency and PSRR across full load range
3 A, low noise, buck regulator
Wide input voltage range: 4.2 V to 15 V
Programmable output voltage range: 0.6 V to 5.0 V
0.3 MHz to 2.5 MHz internal oscillator
0.3 MHz to 2.5 MHz SYNC frequency range
3 A, low noise, NFET LDO regulator (active filter)
Wide input voltage range: 0.65 V to 5 V
Programmable output voltage range: 0.6 V to 3.3 V
Differential point of load remote sensing
3 µV rms output noise (independent of output voltage)
PSRR > 50 dB (to 100 kHz) with 400 mV headroom at 3 A
Ultrafast transient response
Power-good output
Precision enable inputs for both the buck regulator and LDO
−40°C to +125°C operating junction temperature range
32-lead, 5 mm × 5 mm, LFCSP
Figure 1.
GENERAL DESCRIPTION
The ADP5003 integrates a high voltage buck regulator and an
ultralow noise low dropout (LDO) regulator in a small, 5 mm ×
5 mm, 32-lead LFCSP package to provide highly efficient and
quiet regulated supplies.
The buck regulator is optimized to operate at high output
currents up to 3 A. The LDO is capable of a maximum output
current of 3 A and operates efficiently with low headroom
voltage while maintaining high power supply rejection.
The ADP5003 can operate in one of two modes. Adaptive mode
allows the LDO to operate with an optimized headroom by
adjusting the buck output voltage internally in response to the
LDO load current. Alternatively, the ADP5003 can operate in
independent mode, where both regulators operate separately
from each other, and where the output voltages are
Rev. A
programmed using resistor dividers.
The LDO regulator output can be accurately controlled at the
point of load (POL) using remote sensing that compensates for the
printed circuit board (PCB) trace impedance while delivering
high output currents.
Each regulator is activated via a dedicated precision enable
input. The buck switching frequency can be synchronized to
an external signal, or programmed with an external resistor.
Safety features in the ADP5003 include thermal shutdown (TSD),
input undervoltage lockout (UVLO) and independent current
limits for each regulator. The ADP5003 is rated for a −40°C to
+125°C operating junction temperature range.
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ADP5003
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Setting the Switching Frequency for the Buck Regulator ....... 22
Applications ....................................................................................... 1
Setting the Output Voltage for the Buck Regulator ................. 22
Functional Block Diagram .............................................................. 1
Selecting the Inductor for the Buck Regulator ......................... 22
General Description ......................................................................... 1
Selecting the Output Capacitor for the Buck Regulator.......... 22
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Designing the Compensation Network for the Buck Regulator
....................................................................................................... 23
Buck Regulator Specifications .................................................... 5
Selecting the Input Capacitor for the Buck Regulator............. 23
LDO Specifications ...................................................................... 6
Adaptive Headroom Control Design Example .......................... 24
Adaptive Headroom Controller Specifications ........................ 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 15
Power Management Unit ........................................................... 15
Buck Regulator ............................................................................ 15
LDO Regulator............................................................................ 17
Power-Good ................................................................................ 18
Setting the Switching Frequency for the Buck Regulator Using
Adaptive Headroom Control .................................................... 24
Setting the Output Voltage for the LDO Regulator Using
Adaptive Headroom Control .................................................... 24
Selecting the Inductor for the Buck Regulator Using Adaptive
Headroom Control ..................................................................... 24
Selecting the Output Capacitors for the Buck Regulator Using
Adaptive Headroom Control .................................................... 24
Designing the Compensation Network for the Buck
Regulator Using Adaptive Headroom Control ....................... 25
Selecting the Input Capacitor for the Buck Regulator Using
Adaptive Headroom Control .................................................... 25
Output Voltage of the Buck Regulator ..................................... 18
Recommended External Components for the Buck Regulator
....................................................................................................... 26
Output Voltage of the LDO Regulator ..................................... 18
Buck Configurations ...................................................................... 28
Voltage Conversion Limitations ............................................... 18
Independent ................................................................................ 28
Component Selection................................................................. 19
Adaptive Headroom ................................................................... 29
Compensation Components Design........................................ 21
Layout Considerations ................................................................... 30
Junction Temperature ................................................................ 21
Outline Dimensions ....................................................................... 31
Buck Regulator Design Example .................................................. 22
Ordering Guide .......................................................................... 31
Rev. A | Page 2 of 31
Data Sheet
ADP5003
REVISION HISTORY
3/2019—Rev. 0 to Rev. A
Changes to Applications Section, General Description, and
Figure 1 ............................................................................................... 1
Changes to Table 1 ............................................................................ 4
Changes to Table 2 ............................................................................ 5
Changes to Table 3 ............................................................................ 6
Changes to Table 5 ............................................................................ 7
Changes to Table 7 ............................................................................ 8
Updated Typical Performance Characteristics Section;
Renumbered Sequentially ................................................................ 9
Changes to Adaptive Headroom Control Section, Active Pull
Down Section, and Power-Good Section ....................................15
Changes to Oscillator Frequency Control Section .....................16
Add Figure 38 and Figure 39 .........................................................16
Changes to Current-Limit and Short-Circuit Protection
Section and Current Limit Section ...............................................17
Changes to Output Voltage of the Buck Regulator Section,
Figure 44, Output Voltage of the LDO Regulator Section,
Figure 45, and Voltage Conversion Limitations Section ............18
Changes to Input Capacitor Section, Inductor Section, and
Table 9 ...............................................................................................20
Changes to Compensation Components Design Section,
Figure 46 and Junction Temperature Section .............................. 21
Changes to Table 10, Setting the Switching Frequency for the
Buck Regulator Section, Setting the Output Voltage for the
Buck Regulator Section, Selecting the Inductor for the Buck
Regulator Section, and Selecting the Output Capacitor for the
Buck Regulator Section .................................................................. 22
Deleted Figure 44; Renumbered Sequentially ............................. 22
Changes Figure 47 ........................................................................... 23
Changes to Table 11, Setting the Output Voltage for the LDO
Regulator Using Adaptive Headroom Control Section, and
Selecting the Inductor for the Buck Regulator Using Adaptive
Headroom Control Section ........................................................... 24
Changes Figure 48 ........................................................................... 25
Changes to Recommended External Components for the Buck
Regulator Section and Table 12 Title ............................................ 26
Changes to Figure 49 Caption and Figure 50 .............................. 28
Changes to Adaptive Headroom Section and Figure 52 ............ 29
Changes to Layout Considerations Section and Figure 53 ........ 30
Updated Outline Dimensions........................................................ 31
11/2017—Revision 0: Initial Version
Rev. A | Page 3 of 31
ADP5003
Data Sheet
SPECIFICATIONS
VPVIN1 = VPVINSYS = 4.2 V to 15 V, VPVIN2 = 0.65 V to 5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for
typical specifications, unless otherwise noted.
Table 1.
Parameter
INPUT VOLTAGE RANGE
THERMAL SHUTDOWN
Threshold
Hysteresis
SYNC INPUT
Input Logic
High
Low
Input Leakage Current
ADAPTIVE MODE INPUT (VSET1)
Input Rising Threshold
Input Hysteresis
PRECISION ENABLING
High Level Threshold
Low Level Threshold
Shutdown Mode
EN1, EN2 Pull-Down Resistance
INPUT CURRENT
Both Channels Enabled
Both Channels Disabled
REFOUT CHARACTERISTICS
Output Voltage
Accuracy
VREG AND VREG_LDO CHARACTERISTICS
Output Voltage
Accuracy
Current Limit 1
POWER-GOOD PIN (PWRGD)
Power Good Threshold
Hysteresis
Output Voltage Level
Deglitch Time
PVINSYS UNDERVOLTAGE LOCKOUT (UVLO)
Input Voltage
Rising
Falling
1
Symbol
VPVIN1, VPVINSYS
VPVIN2
Min
4.2
0.65
TSD
TSD-HYS
VIH
VIL
VI-LEAKAGE
Typ Max Unit Test Conditions/Comments
15
V
5
V
155
15
°C
°C
1.1
0.4
1
V
V
µA
VADPR
VADPH
2.5
16
V
mV
VTH_H
VTH_L
VTH_S
RENPD
1.125 1.15 1.175
1.025 1.05 1.075
0.4
1.5
V
V
V
MΩ
ISTBY-NOSW
ISHUTDOWN
0.5
5
1
10
mA
µA
VREFOUT
2.0
V
+0.5 %
−0.5
VREG, VREG_LDO
5
−2
10
PWRGDF
PWRGDFH
VOL
tPWRGDD
80
UVLOPVINSYSRISE
UVLOPVINSYSFALL 3.9
+2
85
2.5
25
60
90
50
4.2
TJ rising
No load, not switching
TJ = −40°C to +125°C
V
%
mA
%
%
mV
µs
Applies to VOUT1 and VFB2P to VFB2N
PWRGD pin sink current = 1 mA
V
V
Do not use VREG and VREG_LDO to supply the external loads. This current limit protects against a pin short to ground.
Rev. A | Page 4 of 31
Data Sheet
ADP5003
BUCK REGULATOR SPECIFICATIONS
VPVIN1 = VPVINSYS = 4.2 V to 15 V, VPVIN2 = 0.65 V to 5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical
specifications, unless otherwise noted.
Table 2.
Parameter
OUTPUT CHARACTERISTICS
Programmable Output Voltage Range 1
Buck Regulator Gain
Error Amplifier Transconductance
Buck Output Voltage Accuracy 2
Regulation
Line
Load
Total Output Voltage Accuracy
OPERATING SUPPLY CURRENT
SW1 CHARACTERISTICS
SW1 On Resistance
Current Limit Threshold
Slew Rate
Minimum On Time 3
Minimum Off Time
BUCK REGULATOR ACTIVE PULL DOWN
BUCK REGULATOR SOFT START (SS)
HICCUP TIME
VSETx ADJUSTABLE INPUT BIAS CURRENT
OSCILLATOR
Internal Switching Frequency 1
Internal Switching Frequency 2
SYNC
Frequency Range
Minimum Pulse Width
Positive
Negative
Symbol
Min
VPVOUT1
ABUCK
gm1
0.6
509
−1
(ΔVPVOUT1/VPVOUT1)/ΔVPVIN1
(ΔVPVOUT1/VPVOUT1)/ΔILOAD1
2.5
600
Max
Unit
5.0
V
661
+1
µS
%
130
60
1.6
35
100
90
2
33
10
fSW1
fSW2
2.25
0.26
fSYNC
0.3
20
10
2.5
0.3
VOUT1 load current (ILOAD1) = 10 mA
%/V
%/A
%
mA
ILOAD1 = 10 mA
0 mA ≤ ILOAD1 ≤ 3 A, VPVIN1 = 12 V
4.2 V ≤ VPVIN1 ≤ 15 V, 1 mA ≤ ILOAD1 ≤ 3 A
ILOAD1 = 0 mA, LDO disabled, buck
switching
200
100
mΩ
mΩ
A
−1
150
A
V/ns
ns
ns
Ω
ms
ms
nA
VPVIN1 = 15 V (PVIN1 to SW1)
VPVIN1 = 15 V (SW1 to PGND1)
Negative channel field effect
transistor (NFET) switch valley
current limit
Negative current limit
VPVIN1 = 15 V, ILOAD1 = 1 A
2.75
0.34
MHz
MHz
2.5
MHz
3.5
SLEWSW1
tMIN_ON
tMIN_OFF
RPDWN-B
tSSBUCK
tHICCUP
IVSET1, IVSET2
Test Conditions/Comments
VPVOUT1/VVSET1
0.004
0.04
±1.5
3.8
IIN
RPFET
RNFET
ILIMIT1
Typ
128
Channel disabled
RRT ≤ 71.2 kΩ
RRT = 600 kΩ
ns
ns
The switching frequency, minimum on time, and minimum off time may limit the output voltage range.
The buck output voltage accuracy is relative to the nominal output voltage and accounts for reference voltage, gain, and offset error.
3
The minimum on time indicates the minimum high-side turn on time to ensure fixed frequency switching.
1
2
Rev. A | Page 5 of 31
ADP5003
Data Sheet
LDO SPECIFICATIONS
VPVIN1 = VPVINSYS = 4.2 V to 15 V, VPVIN2 = 0.65 V to 5 V, LDO headroom voltage (VHR) = 300 mV, TJ = −40°C to +125°C for
minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 3.
Parameter
OUTPUT CHARACTERISTICS
Programmable Output Voltage Range 1
LDO Gain
Output Voltage Accuracy 2
Regulation
Line
Symbol
Min
VLDO
ALDO
0.6
Typ
Max
Unit
Test Conditions/Comments
3.3
V
+1
%
VVFB2P-VFB2N
VLDO/VVSET2
VOUT2 load current (ILOAD2) =
150 mA
1.65
−1
(ΔVLDO/VLDO)/ΔVPVIN2
0.007
%/V
(ΔVLDO/VLDO)/ΔILOAD2
0.08
±1.5
%/A
%
OPERATING SUPPLY CURRENT
IGND
1.8
2.3
MINIMUM VOLTAGE REQUIREMENTS
PVINSYS to PVOUT2 3
VREG_LDO to PVOUT2 4
Dropout 5
CURRENT-LIMIT THRESHOLD 6
LDO SOFT START (SS) TIME
LDO ACTIVE PULL-DOWN
OUTPUT NOISE
LDO POWER SUPPLY REJECTION RATIO
VPVOUT2 = 1.3 V
VPVINSYS-PVOUT2
VVREG_LDO-PVOUT2
VDROPOUT
ILIMIT2
tSSLDO
RPDWNLDO
NPVOUT2
PSRRLDO
1.5
1.35
100
Load
Total Output Voltage Accuracy
mA
mA
400
300
3
V
V
mV
A
µs
Ω
µV rms
87
82
61
38
89
83
61
37
dB
dB
dB
dB
dB
dB
dB
dB
3.1
VPVOUT2 = 3.3 V
2.5
4.5
(VPVOUT2 + VHR) ≤ VPVIN2 ≤ 6 V,
ILOAD2 = 100 mA
10 mA ≤ ILOAD2 ≤ 3 A
(VPVOUT2 + VHR) ≤ VPVIN2 ≤ 6 V,
10 mA ≤ ILOAD2 ≤ 3 A
ILOAD2 = 0 μA
ILOAD2 = 3 A
ILOAD2 = 3 A
Required to drive NFET
Channel disabled
10 Hz to 100 kHz, ILOAD2 = 1 A
VPVIN2 = VPVOUT2 + 0.3 V, ILOAD2 = 1A
1 kHz
10 kHz
100 kHz
1000 kHz
1 kHz
10 kHz
100 kHz
1000 kHz
Limited by minimum PVINSYS to PVOUT2 and VREG_LDO to PVOUT2 voltage.
The LDO output voltage accuracy is relative to the nominal output voltage and accounts for reference voltage, gain, and offset error.
3
PVINSYS must be higher than PVOUT2 by at least VPVINSYS-PVOUT2 to keep the LDO regulating.
4
PVOUT2 must be lower than VREG_LDO by at least VVREG_LDO-PVOUT2 to keep the LDO regulating.
5
The dropout voltage is the input to output voltage differential when the input voltage is set to the nominal output voltage.
6
The current-limit threshold is the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V output
voltage is the current that causes the output voltage to drop to 90% of 1.0 V or 0.9 V.
1
2
ADAPTIVE HEADROOM CONTROLLER SPECIFICATIONS
VPVIN1 = VPVINSYS = 4.2 V to 15 V, VPVIN2 = 0.65 V to 5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical
specifications, unless otherwise noted.
Table 4.
Parameter
HEADROOM VOLTAGE (PVIN2 − PVOUT2)
Symbol
VHR
Min
Typ
160
280
400
Rev. A | Page 6 of 31
Max
Unit
mV
mV
mV
Test Conditions/Comments
ILOAD2 = 1 mA
ILOAD2 = 1.5 A
ILOAD2 = 3 A
Data Sheet
ADP5003
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
Parameter
PVIN1/PVINSYS to AGND1/AGND2
PVIN2 to AGND1/AGND2
AGND1 to AGND2
PGND1 to AGND1/AGND2
PVOUT2 to AGND1/AGND2
VFB2N to AGND1/AGND2/PGND1
VOUT1, VFB2P, EN1, EN2, SYNC, RT,
REFOUT, VBUF, VSET1, VSET2,
COMP1 to AGND1/AGND2
SW1 to PGND1
VREG, VREG_LDO to
AGND1/AGND2/PGND1/VFB2N
VREG to VREG_LDO
Storage Temperature Range
Operating Junction Temperature
Range
Soldering Conditions
Rating
−0.3 V to +16 V
−0.3 V to +6.0 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to the lower of
(PVIN2 + 0.3 V) or +6.0 V
−0.3 V to +0.3 V
−0.3 V to the lower of (VREG
+ 0.3 V) or +6.0 V
Thermal performance is directly linked to PCB design and
operating environment. Careful attention to PCB thermal
design is required.
−0.3 V to (PVIN1 + 0.3 V)
−0.3 V to the lower of
(PVINSYS + 0.3 V) or +6.0 V
−0.3 V to +0.3 V
−65°C to +150°C
−40°C to +125°C
ESD CAUTION
Table 6. Thermal Resistance
Package Type
CP-32-7
1
θJA1
46.91
θJC1
20.95
Unit
°C/W
θJA and θJC are based on a 4-layer PCB (two signal and two power planes)
with nine thermal vias connecting the exposed pad to the ground plane as
recommended in the Layout Considerations section.
JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 7 of 31
ADP5003
Data Sheet
32
31
30
29
28
27
26
25
PGND1
PGND1
SW1
SW1
SW1
PVIN1
PVIN1
PVINSYS
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
ADP5003
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
AGND1
VREG
RT
COMP1
PWRGD
VSET1
REFOUT
VSET2
NOTES
1. EXPOSED THERMAL PAD. CONNECT THE
EXPOSED THERMAL PAD TO AGND1.
15021-002
PVOUT2
PVOUT2
PVOUT2
VFB2P
VFB2N
VBUF
AGND2
VREG_LDO
9
10
11
12
13
14
15
16
PGND1
VOUT1
EN1
EN2
SYNC
PVIN2
PVIN2
PVIN2
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1, 31, 32
2
3
Mnemonic
PGND1
VOUT1
EN1
4
EN2
5
SYNC
6 to 8
9 to 11
12
PVIN2
PVOUT2
VFB2P
13
VFB2N
14
15
16
VBUF
AGND2
VREG_LDO
17
18
VSET2
REFOUT
19
VSET1
20
21
22
23
PWRGD
COMP1
RT
VREG
24
25
26, 27
28 to 30
AGND1
PVINSYS
PVIN1
SW1
EPAD
Description
Buck Regulator Dedicated Power Ground.
Buck Regulator Feedback Input. Connect a short sense trace to the buck output capacitor.
Buck Regulator Precision Enable Pin. Drive the EN1 pin high to turn on the buck regulator, and drive the EN1 pin
low to turn off the buck regulator.
LDO Precision Enable Pin. Drive the EN2 pin high to turn on the LDO regulator, and drive the EN2 pin low to turn
off the LDO regulator.
Synchronization Input. To synchronize the switching frequency of the device to an external clock, connect this
pin to an external clock with a frequency from 300 kHz to 2.5 MHz.
LDO Regulator Power Input. Connect a 10 µF ceramic capacitor between this pin and AGND2.
LDO Regulator Power Output. Connect a 10 µF ceramic capacitor between this pin and AGND2.
LDO Regulator Positive Sense Feedback Input. Connect a sense trace to the LDO output at the load. Route this
pin alongside the VFB2N pin on the PCB.
LDO Regulator Ground Sense Feedback Input. Connect a sense trace to ground at the load. Route this pin
alongside the VFB2P pin on the PCB.
Output of the LDO Reference Buffer. Connect a 0.1 µF ceramic capacitor between this pin and VFB2N.
LDO Dedicated Analog Ground.
Internal Regulator Output for the LDO. Connect a 1 µF ceramic decoupling capacitor between this pin and
AGND2. Do not use this pin to power external devices.
LDO Regulator Output Voltage Configuration Input.
Internal Reference Output Required for Driving the External Resistor Dividers for VSET1 and VSET2. Connect a
0.22 µF ceramic capacitor between this pin and AGND2.
Buck Regulator Output Voltage Configuration Input. Connect this pin to VREG to enable adaptive headroom
control.
Power-Good Digital Output (Open-Drain NFET Pull-Down Driver).
Buck Regulator External Compensation Pin.
Resistor Adjustable Frequency Programming Input.
Internal Regulator Output. Connect a 1 µF ceramic decoupling capacitor between this pin and AGND1. Do not
use this pin to power external devices.
Analog Ground.
System Power Supply for the ADP5003. Connect a 10 µF ceramic capacitor between this pin and AGND1.
Buck Regulator Power Input. Connect a 10 µF ceramic capacitor between this pin and PGND1.
Buck Regulator Switching Output.
Exposed Thermal Pad. Connect the exposed thermal pad to AGND1.
Rev. A | Page 8 of 31
Data Sheet
ADP5003
100
100
90
90
80
80
70
70
EFFICIENCY (%)
60
50
40
30
0.5
1.0
1.5
2.0
2.5
3.0
10
0
0
0.5
1.0
1.5
2.0
2.5
3.0
LOAD CURRENT (A)
Figure 6. Adaptive Mode Efficiency vs. Load Current, VPVIN1 = 5 V,
fSW = 600 kHz at Various LDO Output Voltages
Figure 3. Buck Efficiency vs. Load Current, VPVIN1 = 5 V, fSW = 600 kHz at
Various Buck Output Voltages
100
90
90
80
80
70
60
50
40
30
0
0
0.5
1.0
1.5
2.0
2.5
40
30
3.3V
2.5V
1.8V
1.3V
1.1V
10
3.0
LOAD CURRENT (A)
0
15021-306
10
50
20
3.3V
2.5V
1.8V
1.3V
1.1V
20
60
0
0.5
1.0
1.5
2.0
2.5
3.0
LOAD CURRENT (A)
Figure 4. Buck Efficiency vs. Load Current, VPVIN1 = 12 V, fSW = 600 kHz at
Various Buck Output Voltages
15021-408
EFFICIENCY (%)
70
Figure 7. Adaptive Mode Efficiency vs. Load Current, VPVIN1 = 12 V,
fSW = 600 kHz at Various LDO Output Voltages
100
90
90
80
80
70
EFFICIENCY (%)
70
60
50
40
30
60
50
40
30
20
20
300kHz
600kHz
1MHz
0
0.5
1.0
1.5
2.0
LOAD CURRENT (A)
2.5
300kHz
600kHz
1MHz
10
3.0
0
15021-308
10
0
3.3V
2.5V
1.8V
1.3V
1.1V
20
15021-407
0
LOAD CURRENT (A)
EFFICIENCY (%)
40
15021-307
10
EFFICIENCY (%)
50
30
3.3V
2.5V
1.8V
1.3V
1.1V
20
0
60
0
0.5
1.0
1.5
2.0
2.5
3.0
LOAD CURRENT (A)
Figure 5. Buck Efficiency vs. Load Current, VPVIN1 = 12 V, VPVOUT1 = 3.3 V at
Various Buck Switching Frequencies
Rev. A | Page 9 of 31
Figure 8. Adaptive Mode Efficiency vs. Load Current, VPVIN1 = 12 V,
VPVOUT2 = 3.3 V at Various Buck Switching Frequencies
15021-311
EFFICIENCY (%)
TYPICAL PERFORMANCE CHARACTERISTICS
ADP5003
Data Sheet
0
–20
–20
–30
–40
–40
PSRR (dB)
–30
–50
–60
–50
–60
–70
–70
–80
–80
–90
–100
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
15021-304
–90
–100
1
0
–40
10k
100k
1M
10M
0.2V
0.3V
0.4V
0.5V
–60
–50
–60
–70
–70
–80
–80
–90
–90
1
10
100
1k
10k
100k
1M
10M
–100
Figure 10. LDO PSRR vs. Frequency, VPVOUT2 = 1.3 V, ILOAD2 = 1 A at Various LDO
Headroom Voltages
1
10
100
1k
10k
100k
1M
Figure 13. LDO PSRR vs. Frequency, VPVOUT2 = 3.3 V, ILOAD2 = 1 A at Various LDO
Headroom Voltages
1000
1000
0.1A
1A
3A
NOISE SPECTRAL DENSITY (nV/√Hz)
0.9V
3.3V
100
10
1
IPVOUT2 = 1A
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
10M
Figure 11. LDO Noise Spectral Density vs. Frequency at Various LDO Output
Voltages
100
10
1
0.1
15021-231
1
10M
FREQUENCY (Hz)
VPVOUT2 = 3.3V
1
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
10M
15021-232
–50
FREQUENCY (Hz)
NOISE SPECTRAL DENSITY (nV/√Hz)
1k
15021-303
PSRR (dB)
–30
–40
0.1
100
–20
15021-305
PSRR (dB)
0
–10
–30
–100
10
Figure 12. LDO PSRR vs. Frequency, VHR = 0.3 V, VPVOUT2 = 3.3 V at
Various LDO Load Currents
0.2V
0.3V
0.4V
0.5V
–20
1
FREQUENCY (Hz)
Figure 9. LDO PSRR vs. Frequency, VHR = 0.3 V, VPVOUT2 = 1.3 V at
Various LDO Load Currents
–10
0.1A
1A
2A
3A
–10
15021-302
–10
PSRR (dB)
0
0.1A
1A
2A
3A
Figure 14. LDO Noise Spectral Density vs. Frequency, VPVOUT2 = 3.3 V at
Various LDO Load Currents
Rev. A | Page 10 of 31
Data Sheet
ADP5003
0.5
100
10
0.1
3A
2A
1A
10
1k
100
10k
100k
1M
10M
FREQUENCY (Hz)
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
Figure 15. Adaptive Mode Noise Spectral Density vs. Frequency at various
Load Currents, VPVOUT1 = VPVIN2 =3.7 V, VPVOUT2 = 3.3 V, fSW = 2 MHz, L = 1.5 μH,
RC = 23.7 kΩ, CC = 1 nF, CCP = 10 pF, CPVOUT1 = 22 μF
1.0
1.5
2.0
2.5
3.0
Figure 18. Buck Load Regulation, VPVIN1 = 12 V, VPVOUT1 = 3.3 V, fSW = 600 kHz
DEVIATION FROM AVERAGE VPVOUT2 (%)
0.5
0.4
0.3
0.2
0.1
0
0.4
0.3
0.2
0.1
0
–0.1
–0.1
–0.2
–0.2
–0.3
–0.3
–0.4
4.2 5.0
6.0
7.0
8.0
9.0
10.0 11.0 12.0 13.0 14.0 15.0
INPUT VOLTAGE (V)
15021-418
–0.5
–0.5
0
0.5
1.5
1.0
2.0
2.5
3.0
LOAD CURRENT (A)
Figure 16. Buck Line Regulation, VPVOUT1 = 3.3 V, ILOAD1 = 1 A, fSW = 600 kHz
15021-314
–0.4
Figure 19. LDO Load Regulation, VPVOUT2 = 3.3 V, VHR = 0.3 V
0.5
0.5
DEVIATION FROM AVERAGE VREFOUT (%)
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.5
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
HEADROOM (V)
15021-315
–0.4
Figure 17. LDO Line Regulation, VPVOUT2 = 3.3 V, ILOAD2 = 1 A
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–50
–20
10
40
70
100
TEMPERATURE (°C)
Figure 20. REFOUT Voltage (VREFOUT) vs. Temperature
Rev. A | Page 11 of 31
130
15021-300
DEVIATION FROM AVERAGE VVOUT1 (%)
0.5
LOAD CURRENT (A)
0.5
DEVIATION FROM AVERAGE VPVOUT2 (%)
0
15021-312
1000
1
0.4
DEVIATION FROM AVERAGE VVOUT1 (%)
10000
15021-515
NOISE SPECTRAL DENSITY (nV/√Hz)
100000
Data Sheet
3
3.0
2
2.5
QUIESCENT CURRENT (mA)
1
0
–1
2.0
1.5
1.0
0.5
–2
–20
10
40
70
100
130
TEMPERATURE (°C)
0
15021-301
–3
–50
4
6
14
12
10
8
15021-320
DEVIATION FROM AVERAGE
SWITCHING FREQUENCY (%)
ADP5003
INPUT VOLTAGE (V)
Figure 21. Switching Frequency vs. Temperature
Figure 24. Buck Quiescent Current vs. Input Voltage
0.50
4.0
0.45
3.5
0.35
HEADROOM (V)
2.5
2.0
1.5
0.30
0.25
0.20
0.15
1,0
0.10
0.5
0
0.5
1.0
1.5
2.0
2.5
0
15021-316
0
0.05
3.0
LOAD CURRENT( A)
0
0.5
1.0
1.5
2.0
2.5
3.0
LOAD CURRENT (A)
15021-319
QUIESCENT CURRENT (mA)
0.40
3.0
Figure 25. Adaptive Mode Headroom vs. Load Current
Figure 22. LDO Quiescent Current vs. Load Current
IL
IL
1
VSW1
VSW1
2
VPVOUT1
1
3
T
M200ns
94ns
A CH2
8V
15021-013
CH1 500mA
CH2 5V
CH3 10mV Ω BW
VPVOUT1
3
CH1 5.00V
CH3 500mA BW CH4 10.0mV ΩBW
Figure 23 SW1 Waveform, VPVOUT1 = 5 V, ILOAD1 = 100 mA, fSW = 2 MHz,
L = 2.2 μH, RC = 2.7 kΩ, CC = 22 nF, CCP = 22 pF, CPVOUT1 = 22 μF
M400ns
A CH1
T
0.000µs
5.70V
15021-526
4
Figure 26. SW1 Waveform, VPVOUT1 = 5 V, ILOAD1 = 3 A, fSW = 2 MHz, L = 2.2 μH,
RC = 2.7 kΩ, CC = 22 nF, CCP = 22 pF, CPVOUT1 = 22 μF
Rev. A | Page 12 of 31
Data Sheet
ADP5003
VPVOUT1
2
VPVOUT1
2
VSW1
VSW1
3
3
IL
IL
1
B
W
M20.0ms
A CH2
T
40.0080ms
510mV
CH1 5.00A BW CH2 500mV
CH3 10.0V BW
Figure 27. Entering Hiccup Mode
(VSW1 is the Voltage of the SW1 Pin, and IL is Inductor Current)
B
W
M20.0ms
A CH2
T
40.0080ms
510mV
15021-318
CH1 5.00A BW CH2 500mV
CH3 10.0V BW
15021-317
1
Figure 30. Exiting Hiccup Mode
VEN1 /VEN2
2
VEN1
3
VVOUT1
VPVOUT2
VPVOUT1
3
ILOAD1
4
1
ILOAD2
2
VSW1
B
W
CH2 2V BW
CH4 10V BW
M400µs
A CH2
1.56V
15021-004
CH1 1A
CH3 1V
CH1 1.00A
CH3 2.00V
VPVIN1
M1.00ms
A CH3
T
3.00400ms
2.04V
Figure 31. Adaptive Mode Startup, VPVOUT2 = 3.3 V, ILOAD2 = 1 A
(VEN2 is the EN2 voltage.)
Figure 28. Buck Startup, VPVOUT1 = 3.3V, ILOAD1 = 3 A
(VEN1 is the EN1 voltage.)
0.42V/µs
CH2 1.00V
CH4 1.00V
15021-238
1
4
ILOAD1
0.11V/µs
2.3A/µs
3.1A/µs
4
VPVOUT1
CH2 500mV BW CH4 20.0mV Ω BW M80µs
T 25.50%
A CH2
12.4V
CH2 500mV
Figure 29. Buck Line Transient, VPVIN1 = 12 V to 13 V, VPVOUT1 = 1.2 V, ILOAD1 = 1A,
fSW = 0.6 MHz, L = 2.2 μH, RC = 3.48 kΩ, CC = 2 nF, CCP = 22 pF, CPVOUT1 = 44 μF
CH4 1A
M200µs
A CH4
T
493.480µs
1.46A
15021-118
10V OFFSET
15021-116
2
VPVOUT1
2
4
Figure 32. Buck Load Transient, VPVIN1 = 12 V, VPVOUT1 = 1.2 V, ILOAD1 = 0.5 A to 3 A,
fSW = 0.6 MHz, L = 2.2 μH, RC = 3.48 kΩ, CC = 2 nF, CCP = 22 pF, CPVOUT1 = 44 μF
Rev. A | Page 13 of 31
ADP5003
Data Sheet
2.3A/µs
0.18V/µs
0.07V/µs
4
3V OFFSET
VPVOUT2
VPVOUT2
2
CH2 1.00mV
B
W
M80.0µs
A CH1
T
200.960µs
3.81V
15021-126
2
CH1 500mV
3A/µs
CH2 20.0mV
Figure 33. LDO Line Transient, VPVIN2 = 3.6 V to 4.1 V, VPVOUT2 = 3.3 V,
ILOAD2 = 1 A
CH4 1.00A
M8.00µs
A CH4
T
18.4800µs
1.34A
15021-129
1
VPVIN2
ILOAD2
Figure 36. LDO Load Transient, VPVIN2 = 3.6 V, VPVOUT2 = 3.3 V,
ILOAD2 = 0.5 A to 3 A
0.45V/µs
0.14V/µs
VPVIN1
1.2A/µs
ILOAD2
1.3A/µs
3
VPVOUT2
VPVOUT2
4
CH2 500mV BW CH4 1.00mV Ω BW
M80µs
A CH2
T 25.90%
12.5V
CH3 500mA
Figure 34. Adaptive Mode Line Transient, VPVIN1 = 11 V to 13 V, VPVOUT2 = 3.3 V,
ILOAD2 = 1 A, fSW = 1.5 MHz, L = 2.2 μH, RC = 3.48 kΩ, CC = 22 nF, CCP = 22 pF,
CPVOUT1 = 64 μF
IPVIN1
VPVOUT2
15021-535
4
920mA
A CH2
1.52V
Figure 37. Adaptive Mode Load Transient, VPVIN1 = 12 V, VPVOUT2 = 3.3 V,
ILOAD2 = 1 A to 1.5 A, fSW = 1.5 MHz, L = 2.2 μH, RC = 3.48 kΩ, CC = 22 nF,
CCP = 22 pF, CPVOUT1 = 64 μF
3
CH3 1.00 A
M8.00µs
A CH3
24.7%
CH4 20.0mV Ω BW T
CH4 10.0mV Ω BW M80µs
T 24.70%
15021-141
10V OFFSET
15021-140
2
4
Figure 35. Adaptive Mode Load Transient, VPVIN1 = 12 V, VPVOUT2 = 3.3 V,
ILOAD2 = 0.5 A to 3 A, fSW = 1.5 MHz, L = 2.2 μH, RC = 3.48 kΩ, CC = 22 nF,
CCP = 22 pF, CPVOUT1 = 64 μF
Rev. A | Page 14 of 31
Data Sheet
ADP5003
THEORY OF OPERATION
POWER MANAGEMENT UNIT
Active Pull Down
The ADP5003 is a micropower management unit combining a
step-down (buck) dc-to-dc converter and an ultralow noise low
dropout linear (LDO)regulator. The high switching frequency
and 5 mm × 5 mm, 32-lead LFCSP package allow a compact
power management solution.
Both regulators have active pull-down resistors discharging the
respective output capacitors when the regulators are disabled.
The pull-down resistors are connected between VOUT1 to
AGND1 and PVOUT2 to AGND2. Active pull-down resistors
are disabled when the regulators are turned on.
Adaptive Headroom Control
When the enable pins are asserted low, or a TSD or UVLO
event occurs, the active pull-down resistors enable to quickly
discharge the output capacitors. The pull-down resistors remain
engaged until the enable pins are asserted high, the fault event is
no longer present, or the VREG supply voltage falls to less than
the voltage required (approximately 1 V) to guarantee that the
pull-down resistor remains enabled.
The ADP5003 features a scheme to control the LDO headroom
voltage to ensure optimal operating efficiency while maintaining a
consistent power supply rejection ratio (PSRR) across the full
range of the LDO load current.
The scheme works by varying the headroom voltage across the
LDO NFET with respect to the LDO load current. Lower and
upper limits prevent the headroom from approaching zero volts
at light loads and from increasing more than necessary at high
loads.
Precision Enable/Shutdown
The ADP5003 has individual enable pins (EN1 and EN2) to
control the regulators.
Soft Start (SS)
Both regulators have an internal soft start function that ramps
the output voltage in a controlled manner on startup, thereby
limiting the inrush current. The soft start function reduces the
risk of noise spikes and voltage drops on the upstream supplies.
Power-Good
The precision enable function allows a precise turn on point for
the regulators to allow the possibility of external sequencing. A
voltage level higher than VTH_H applied to the EN1 or EN2 pin
activates a regulator, whereas a level below VTH_L turns off a
regulator. The buck is controlled by EN1, and the LDO is
controlled by the EN2 pin. When both EN1 and EN2 fall below
VTH_S, the ADP5003 enters shutdown mode.
Undervoltage Lockout (UVLO)
To protect against the input voltage being too low, UVLO
circuitry is integrated into the system. If the input voltage on
PVINSYS drops to less than the UVLOPVINSYSFALL threshold, all
channels shut down.
The device is enabled again when the voltage on PVINSYS rises
to more than the UVLOPVINSYSRISE threshold, provided the enable
pins remain active.
Thermal Shutdown (TSD)
In the event that the junction temperature rises above TSD, the
thermal shutdown circuit turns off both regulators. Extreme
junction temperatures can be the result of high current operation,
poor circuit board design, or a high ambient temperature. A
hysteresis value of TSD-HYS is included so that when thermal
shutdown occurs, the regulators do not return to operation until
the on-chip temperature drops below TSD − TSD-HYS. When
emerging from thermal shutdown, both regulators restart with
soft start control.
The ADP5003 has a dedicated power-good, open-drain, output
(PWRGD). PWRGD indicates whether one or more regulators
are outside the voltage limits specified by the power-good lower
limit (PWRGDF) and the power-good upper limit (PWRGDF +
PWRGDFH). When either one or both of the regulator outputs
are outside the power-good limits, the PWRGD output pulls low.
PWRGD will continue to pull low, provided the VREG supply
voltage remains above approximately 1 V.
When in adaptive mode, PWRGD only monitors the LDO
output, and when in standalone mode, PWRGD only monitors
the regulator/regulators that are enabled.
BUCK REGULATOR
Control Scheme
The buck regulator operates with a fixed frequency, emulated
peak current mode, pulse-width modulation (PWM) control
architecture, where the duty cycle of the integrated switches is
adjusted and regulates the output voltage. At the start of each
oscillator cycle, the positive channel field effect transistor (PFET)
switch is turned on, sending a positive voltage across the inductor.
Current in the inductor increases until the emulated current
sense signal crosses the peak inductor current threshold, which
turns off the PFET switch and turns on the NFET synchronous
rectifier. Turning on the NFET synchronous rectifier creates a
negative voltage across the inductor, which causes the inductor
current to decrease. The synchronous rectifier stays on for the
remainder of the cycle. By adjusting the peak inductor current
threshold, the buck regulator can regulate the output voltage.
Rev. A | Page 15 of 31
ADP5003
Data Sheet
The emulated inductor current scheme senses the current in the
inductor during the off phase of the cycle, when the NFET is
conducting, and uses this inductor current to generate the
emulated current sense signal during the on time of the cycle.
This scheme allows the low duty cycles necessary for high input
voltage, VIN, to output voltage, VOUT, conversion ratios.
Oscillator Frequency Control
The ADP5003 buck regulator oscillator frequency is controlled
by using the RT pin or the SYNC pin. To define the buck
regulator internal switching frequency, connect the RT pin via a
resistor to AGND1. Figure 38 shows the relationship of the buck
oscillator frequency and the RT resistor value.
3.0
The SYNC pin is dedicated for oscillator synchronization and
allows the ADP5003 to lock to an external clock.
When an applied external clock signal is present at the SYNC pin,
the buck regulator operates in sync with this signal.
When alternating between external clocks and the internal
oscillator, the presence of an external frequency causes a
multiplexer to switch between the internal oscillator and the
external SYNC frequency. The output of this multiplexer acts as
the frequency reference to an internal phase-locked loop (PLL),
which ensures that changing between the two modes of operation
results in a smooth transition between the different frequencies.
Buck Startup
The buck regulator turns on with a controlled soft start ramp to
limit inrush current. The reference of the buck is ramped
during tSSBUCK, which is typically 2 ms (see Figure 39).
2.5
FREQUENCY (MHz)
External Oscillator Synchronization
2.0
1.5
2
tSSBUCK
VEN1
1.0
0.5
0
10k
100k
RT RESISTOR (Ω)
1M
15021-538
4
VPVOUT1
ILOAD1
1
Figure 38. Buck Oscillator Frequency vs. RT Resistor (RRT)
VSW1
To determine the oscillator frequency (fSW), use the following
equation:
(1)
An upper limit prevents out of range frequencies when the RT
pin is shorted to ground or connected with a resistor value less
than 70 kΩ.
Rev. A | Page 16 of 31
CH1 1.00A
CH3 5.00V
B
W
B
W
CH2 5.0V
CH4 1.0V
B
W
B
W
4.00µs
A CH2
T
1.60ms
Figure 39. Buck Startup
1.20V
15021-441
fSW = (1.78 × 1011)/RRT
3
Data Sheet
ADP5003
Current-Limit and Short-Circuit Protection
LDO REGULATOR
The buck regulator includes current-limit protection circuitry
to limit the amount of forward current through the field effect
transistor (FET) switches. When the valley inductor current
exceeds the overcurrent limit threshold for a number of clock
cycles during an overload or short-circuit condition, the
regulator enters hiccup mode. The regulator stops switching
and then restarts with a new soft start cycle after the hiccup
time, tHICCUP, and repeats until the over-current condition is
removed. If the buck regulator output voltage falls below 50%
of the nominal output voltage, the regulator immediately enters
hiccup mode. When the valley inductor current falls below the
negative current-limit threshold, the NFET turns off and the
PFET remains off allowing the inductor current to be discharged
via the PFET body diode. The PFET turns on again with the
next clock edge after the inductor current no longer exceeds
the negative current-limit threshold.
The ADP5003 contains a single low noise, low dropout (LDO)
linear regulator that uses an NFET pass device to provide high
PSRR with low headroom voltage and an output current up to 3 A.
3.5A
LDO Startup
The LDO regulator turns on with a controlled soft start ramp to
limit inrush current. This soft start ramp is dictated by tSSLDO,
which is typically 400 µs.
4.0
3.5
3.5
2.5
3.0
0.5
2.0
–0.5
1.5
VEN2 (V)
VPVOUT2 (V)
1.5
2.5
–1.5
1.0
–2.5
0.5
–3.5
0
–0.4
3
0.1A
1A
3A
VEN2
–0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
–4.5
1.6
TIME (ms)
tHICCUP
15021-019
2
The LDO regulator can operate with an input voltage of 0.65 V
to 5 V while providing excellent line and load transient response
using 10 µF ceramic input and output capacitors.
Figure 41. LDO Startup
1
Current Limit
The LDO operates in current limit when the output load exceeds
ILIMIT2. When in current limit operation, the output voltage
reduces to maintain a constant output current.
Differential Remote Sensing
VVOUT1
The LDO can sense at the point of load by using VFB2P and
VFB2N as shown in Figure 42. Differential remote sensing
compensates for both the source drop and the return drop to
provide a more precise supply scheme at the point of load.
3.5A
IL
3
LOW NOISE
LDO ACTIVE
FILTER
3A
VSW1
1
PVOUT2
PVOUT2
PVOUT2
–
+
VFB2P
CH2 2.00V
B
W
20.0ms
A CH2
T
79.7600ms
1.08V
15021-440
CH1 10.0V
CH3 2.0A
+
LOAD
VFB2N
Figure 40. Short-Circuit Response (Current Limit and Hiccup Mode)
AGND1
–
AGND2
–
+
Figure 42. Differential Remote Sensing
Rev. A | Page 17 of 31
15021-443
2
ADP5003
Data Sheet
POWER-GOOD
OUTPUT VOLTAGE OF THE LDO REGULATOR
An external pull-up resistor is necessary to drive the PWRGD
output high (see Figure 43). Through the value of the pull-up
resistor is not critical, it is recommended to use a 10 kΩ to
300 kΩ resistor. The resistor must be pulled to a voltage level
no greater than 5.5 V.
The output voltage on the LDO regulator is adjustable through
an external resistor divider. The LDO adjustable output voltage
configuration is shown in Figure 45.
PVOUT2
PVIN2
REFOUT
VPULLUP
RTOP2
R PULLUP
VFB2P
LDO
VFB2N
VSET2
GPIO
VPWRGD
15021-444
RBOT2
Figure 45. LDO Adjustable Output Voltage Configuration
Figure 43. Power-Good Setup
To calculate the LDO output voltage, use the following
equation:
OUTPUT VOLTAGE OF THE BUCK REGULATOR
The output voltage on the buck regulator is adjustable through
an external resistor divider. When using adaptive mode, the
ADP5003 controls the buck output voltage.
The adjustable output voltage configuration is shown in Figure 44.
SW1
PVIN1
REFOUT
RTOP1
PVOUT1
VOUT1
BUCK
15021-057
To calculate the buck output voltage, use the following equation:
where:
VREFOUT is the REFOUT output voltage.
ABUCK is the buck regulator gain.
RBOT1 is the bottom divider resistor.
RTOP1 is the top divider resistor.
(3)
where:
ALDO is the LDO gain.
RBOT2 is the bottom divider resistor.
RTOP2 is the top divider resistor.
For a given input voltage and switching frequency, an upper
and lower limitation on the output voltage exists due to the
minimum on time and minimum off time. The minimum on
time limits the minimum output voltage for a given input
voltage and switching frequency.
Figure 44. Buck Regulator Adjustable Output Voltage
R BOT 1
VPVOUT 1 VREFOUT A BUCK
RTOP 1 R BOT 1
R BOT 2
VPVOUT 2 VREFOUT ALDO
R
TOP 2 R BOT 2
VOLTAGE CONVERSION LIMITATIONS
VSET1
RBOT1
15021-059
PWRGD
(2)
If the minimum on time is exceeded, the ADP5003 may not
switch at a fixed frequency because the device can switch at an
effective zero on time, resulting in unpredictable switching
frequencies and unwanted noise.
To calculate the minimum output voltage for a given input
voltage and fixed switching frequency, use the following
equation:
VOUT_MIN = VPVIN1 × tMIN_ON × fSW − (RPFET – RNFET) ×
IOUT_MIN × tMIN_ON × fSW − (RNFET + RL) × IOUT_MIN
where:
VOUT_MIN is the minimum output voltage.
VPVIN1 is the input voltage.
tMIN_ON is the minimum on time.
fSW is the switching frequency.
RPFET is the high-side PFET on resistance.
RNFET is the low-side NFET on resistance.
IOUT_MIN is the minimum output current.
RL is the resistance of the output inductor.
Rev. A | Page 18 of 31
(4)
Data Sheet
ADP5003
The minimum off time limits the maximum duty cycle which
in turn limits the maximum output voltage for a given input
voltage and switching frequency. Calculate the maximum output
voltage for a given input voltage and switching frequency by
using the following equation:
Use the following equation to calculate the worst case capacitance,
accounting for capacitor variation over temperature, component
tolerance, and voltage:
VOUT_MAX = VPVIN1 × (1 − tMIN_OFF × fSW) − (RPFET – RNFET) × IOUT_MAX ×
(1 − tMIN_OFF × fSW) − (RNFET + RL) × IOUT_MAX
(5)
where:
VOUT_MAX is the maximum output voltage.
IOUT_MAX is the maximum output current.
tMIN_OFF is the minimum off time.
where:
CEFFECTIVE is the effective capacitance at the operating voltage.
CNOMINAL is the nominal data sheet capacitance.
TEMPCO is the worst case capacitor temperature coefficient.
DCBIASCO is the dc bias derating at the output voltage.
Tolerance is the worst case component tolerance.
As shown in Equation 4 and Equation 5, reducing the switching
frequency eases the minimum on time and minimum off time
limitations.
To guarantee the performance of the device, it is imperative to
evaluate the dc bias effects, temperature, and tolerances on the
behavior of the capacitors for each application.
COMPONENT SELECTION
Capacitors with lower effective series resistance (ESR) and
effective series inductance (ESL) are preferred to minimize
output voltage ripple.
Output Capacitors
Higher output capacitor values reduce the output voltage ripple
and improve the load transient response.
Ceramic capacitors are manufactured with a variety of dielectrics,
each with a different behavior over temperature and applied
voltage. Capacitors must have a dielectric adequate to ensure
the minimum capacitance over the necessary temperature range
and dc bias conditions. X5R or X7R dielectrics with a voltage
rating of 25 V are recommended for best performance. Y5V
and Z5U dielectrics are not recommended for use with any dcto-dc converter because of their poor temperature and dc bias
characteristics.
CEFFECTIVE = CNOMINAL × (1 − TEMPCO) × (1 − DCBIASCO) ×
(1 − Tolerance)
(6)
Use the following equation to calculate the minimum
capacitance needed for a specific output voltage ripple:
COUT_MIN ≅
ΔI L
8 × f SW × (VRIPPLE — ΔI L × R ESR )
(7)
where:
ΔIL is the current ripple.
fSW is the switching frequency.
VRIPPLE is the allowed peak-to-peak voltage ripple.
RESR is the effective series resistance of the capacitor.
The minimum capacitance needed for stability considering
temperature and dc bias effects is 22 µF.
The minimum capacitance recommended for the LDO is 10 µF.
Table 8. Recommended Output Capacitors
Vendor
Wurth
Murata
Part No.
885 012 207 026
885 012 209 006
885 012 109 012
885 012 109 004
GRM21BR71A106KE51
GRM32ER71C226KEA8
GRM32ER71A476KE15
Value (µF)
10
22
47
100
10
22
47
Rev. A | Page 19 of 31
Type
X7R
X7R
X5R
X5R
X7R
X7R
X7R
Voltage Rating (V)
10
10
25
6.3
10
16
10
Case
0805
1210
1210
1210
0805
1210
1210
ADP5003
Data Sheet
Input Capacitor
To calculate the inductor value, L, use the following equation:
The input current to the buck converter steps from zero to a
positive value that is dependent on inductor value, switching
frequency, and load current (typically between 1 A and 4 A) and
then drops quickly to zero again every switching cycle. Because
these current pulses occur at relatively high frequencies (0.3 MHz
to 2.5 MHz), the input bypass capacitor provides most of the
high frequency current while the input power source supplies
only the average current. Higher value input capacitors reduce
the input voltage ripple and improve transient response.
To minimize supply noise, it is recommended to place a low
ESR capacitor as close as possible to the relevant supply pin.
L = ((VPVIN1 − VPVOUT1) × D)/(ΔIL × fSW)
where:
VPVIN1 is the input voltage.
VPVOUT1 is the output voltage.
D is the duty cycle (D = VVOUT1/VPVIN1).
ΔIL is the inductor ripple current.
fSW is the switching frequency.
The minimum dc current rating of the inductor must be greater
than the inductor peak current. Use the following equation to
calculate the inductor peak current:
IPEAK = ILOAD1 + (ΔIL/2)
Inductor
The high switching frequency of the ADP5003 buck allows the
selection of small chip inductors. A small inductor leads to larger
inductor current ripple that provides improved transient response
but degrades efficiency. The sizing of the inductor is a trade-off
between efficiency and transient response. As a guideline, the
inductor peak-to-peak current ripple is typically set to 1/3 of
the maximum load current for optimal transient response and
efficiency.
(8)
(9)
where:
ILOAD1 is the output current.
ΔIL is the inductor ripple current.
Inductor conduction losses are minimized by using larger sized
inductors that have smaller dc resistance; this in turn improves
efficiency at the cost of solution size. Due to the high switching
frequency of the ADP5003, shielded ferrite core material is
recommended for its low core losses and low electromagnetic
interference (EMI).
Table 9. Recommended Inductors
Vendor
Coilcraft
Wurth
Part No.
XAL4020-102
XAL4020-122
XAL4020-152
XAL4020-222
XAL5030-102
XAL5030-122
XAL5030-222
XAL5030-332
XAL5050-562
XAL5050-682
XEL6030-102
XEL6030-152
XEL6030-222
XEL6030-332
XEL6060-472
XAL6060-562
XEL6060-682
XEL6060-822
XAL6060-103
744 383 570 10
744 383 570 12
744 383 570 15
744 383 570 18
744 383 570 22
Value (µH)
1
1.2
1.5
2.2
1
1.2
2.2
3.3
5.6
6.8
1
1.5
2.2
3.3
4.7
5.6
6.8
8.2
10
1
1.2
1.5
1.8
2.2
Saturation Current, ISAT (A)
8.7
7.9
7.1
5.6
14
12.5
9.2
8.7
6.3
6
18
15
13
10.5
11.4
9.9
7.9
7.6
7.6
9.6
8.8
8.5
8
7
RMS Current, IRMS (A)
6.7
6.6
5.2
4
8.7
7.9
7.2
5.9
5.3
4.7
12
10
7
6
9
7.5
7.3
7
5
7.4
7
6.2
5.8
5.2
Rev. A | Page 20 of 31
DC Resistance (mΩ)
13.25
17.75
21.45
35.2
8.5
11.4
13.2
21.2
23.45
26.75
6.32
9.57
12.7
19.92
13.65
14.46
20.82
22.71
27
11.6
13.4
17.1
18
22
Size (mm)
4×4
4×4
4×4
4×4
5×5
5×5
5×5
5×5
5×5
5×5
6×6
6×6
6×6
6×6
6×6
6×6
6×6
6×6
6×6
4×4
4×4
4×4
4×4
4×4
Data Sheet
ADP5003
COMPENSATION COMPONENTS DESIGN
CCP = (RESR × CPVOUT1)/RC
For the peak current mode control architecture, the power stage
can be simplified as a voltage controlled current source that
supplies current to the output capacitor and load resistor. The
simplified loop is composed of one dominant pole and a zero
contributed by the output capacitor ESR.
The ADP5003 uses a transconductance amplifier as the error
amplifier to compensate the system. Figure 46 shows the
simplified peak current mode control, small signal circuit.
VPVOUT1
VREFOUT
RTOP1
–
VSET1
ABUCK
VCOMP1
gm
AVI
CPVOUT1
+
R
RC
RBOT1
+
CCP
–
JUNCTION TEMPERATURE
In cases where the ambient temperature (TA) is known, the
thermal resistance parameter (θJA) can estimate the junction
temperature rise (TJ). TJ is calculated with TA and the power
dissipation (PD) using the following formula:
TJ = TA + (PD × θJA)
VPVOUT1
RESR
15021-043
CC
The following procedure shows how to select the compensation
components (RC, CC, and CCP) for ceramic output capacitor
applications:
1.
2.
Determine the cross frequency (fC). Generally, fC is
between fSW/12 and fSW/6.
Use the following equation to calculate RC:
RC =
2 × π × C PVOUT1 × ABUCK
g m × AVI
(10)
If the case temperature can be measured, the junction
temperature is calculated by
To achieve reliable operation of the buck converter and LDO
regulator, the estimated die junction temperature of the
ADP5003 must be less than 125°C. Reliability and mean time
between failures (MTBF) is highly affected by increasing the
junction temperature. Additional information about product
reliability can be found in the Analog Devices, Inc., Reliability
Handbook at www.analog.com/reliability_handbook.
where:
PDBUCK = (VPVIN1 × IPVIN1) − (VPVOUT1 × ILOAD1).
PDLDO = ((VPVIN2 − VPVOUT2) × ILOAD2) + (VPVIN2 × IGND).
(11)
where:
RESR is the equivalent series resistance of the output
capacitor.
4.
(14)
where:
TC is the case temperature.
θJC is the junction to case thermal resistance provided in Table 6.
PD = PDBUCK + PDLDO
Place the compensation zero at the domain pole (fP).
Determine CC as follows:
CC = ((R + RESR) × CPVOUT1)/RC
TJ = TC + (PD × θJC)
The total power dissipation in the ADP5003 simplifies to
where:
CPVOUT1 is the output capacitance.
AVI = 7 A/V.
3.
(13)
The typical θJA value for the 32-lead, 5 mm × 5 mm LFCSP is
46.91°C/W. An important factor to consider is that θJA is based
on a 4-layer, 4 inches × 3 inches, 2.5 ounces copper PCB, as per
the JEDEC standard, and applications may use different sizes
and layers. It is important to maximize the copper used to
remove the heat from the device. Copper exposed to air
dissipates heat better than copper used in the inner layers.
Connect the exposed pad to the ground plane with several vias.
Figure 46. Simplified Peak Current Mode Control, Small Signal Circuit
The compensation components, RC and CC, contribute a zero,
and the optional CCP and RC contribute an optional pole.
(12)
CCP is optional. It can cancel the zero caused by the ESR of
the output capacitor. Determine CCP as follows:
Rev. A | Page 21 of 31
(15)
ADP5003
Data Sheet
BUCK REGULATOR DESIGN EXAMPLE
This section provides an example of the step by step design
procedures and the external components required for the buck
regulator. Table 10 lists the design requirements for this
example.
Table 10. Example Design Requirements for the Buck Regulator
Parameter
Input Voltage
Output Voltage
Output Current
Output Ripple
Load Transient
SELECTING THE INDUCTOR FOR THE BUCK
REGULATOR
The peak-to-peak inductor ripple current, ΔIL, is set to 35% of
the maximum output current. Use Equation 8 to estimate the
value of the inductor:
L = ((VPVIN1 − VPVOUT1) × D)/(ΔIL × fSW)
Specification
VPVIN1 = 12 V
VPVOUT1 = 2.5 V
ILOAD1 = 3 A
ΔVOUT1_RIPPLE = 25 mV
±5% at 20% to 80% load transient
SETTING THE SWITCHING FREQUENCY FOR THE
BUCK REGULATOR
The first step is to determine the switching frequency for the
ADP5003 design. In general, higher switching frequencies
produce a smaller solution size due to the lower component
values required, whereas lower switching frequencies result in
higher conversion efficiency due to lower switching losses.
The switching frequency of the ADP5003 can be set from
0.3 MHz to 2.5 MHz by connecting a resistor from the RT pin
to ground. The selected resistor allows the user to make decisions
based on the trade-off between efficiency and solution size. (For
more information, see the Oscillator Frequency Control section.)
However, the highest supported switching frequency must be
assessed by checking the voltage conversion limitations enforced
by the minimum on time and the minimum off time (see the
Voltage Conversion Limitations section).
In this design example, a switching frequency of 600 kHz is
used to achieve an ideal combination of small solution size and
high conversion efficiency. To set the switching frequency to
600 kHz, use Equation 1 to calculate the resistor value, RRT. This
gives a standard resistor value of RT = 294 kΩ.
where:
VPVIN1 = 12 V.
VPVOUT1 = 2.5 V.
D is the duty cycle (D = VPVOUT1/VPVIN1).
ΔIL = 35% × 3 A = 1.05 A.
fSW = 600 kHz.
The resulting value for L is 3.14 µH. The selected standard
inductor value is 3.3 µH; therefore, ΔIL is 1 A.
To calculate the peak inductor current (IPEAK), use Equation 9:
IPEAK = ILOAD1 + (ΔIL/2)
The calculated peak current for the inductor is 3.5 A.
SELECTING THE OUTPUT CAPACITOR FOR THE
BUCK REGULATOR
The output capacitor must meet the output voltage ripple, load
transient requirements and stability requirements. To meet the
output voltage ripple requirement, use Equation 7 to calculate
the capacitance:
COUT_MIN ≅
RBOT1 = (RTOP1 × VPVOUT1)/((VREFOUT × ABUCK) − VPVOUT1) (16)
where:
VPVOUT1 is the buck output voltage.
VREFOUT is 2 V.
ABUCK is the buck regulator gain.
8 × f SW × (VRIPPLE — ΔI L × R ESR )
The calculated capacitance, COUT_MIN, is 8.7 µF.
To meet the ±5% overshoot and undershoot requirements, use
the following equations to calculate the capacitance:
COUT_UV =
SETTING THE OUTPUT VOLTAGE FOR THE BUCK
REGULATOR
Select a value for the top resistor (RTOP1) and then calculate the
bottom feedback (RBOT1) resistor by using the following
equation:
ΔI L
COUT_OV =
KUV × ΔI STEP 2 × L
2 × (VPVIN1 – VPVOUT1 ) × ΔVOUT _ UV
K OV × ΔI STEP 2 × L
(VPVOUT1 + ΔVOUT _ OV )2 – VPVOUT12
where:
KUV and KOV are factors (typically set to 2).
ΔISTEP is the load step.
ΔVOUT_UV is the allowable undershoot on the output voltage.
ΔVOUT_OV is the allowable overshoot on the output voltage.
For estimation purposes, use KOV = KUV = 2; therefore,
COUT_OV = 33.4 µF and COUT_UV = 9 µF.
It is recommended to use two 22 µF ceramic capacitors.
To set the output voltage to 2.5 V, RTOP1 is set to 100 kΩ, giving
an RBOT1 value of 100 kΩ.
Rev. A | Page 22 of 31
(17)
(18)
Data Sheet
ADP5003
DESIGNING THE COMPENSATION NETWORK FOR
THE BUCK REGULATOR
Figure 47 shows the load transient waveform.
0.02A/µs
For better load transient and stability performance, set the cross
frequency, fC, to fSW/10. In this example, fSW is set to 600 kHz;
therefore, fC is set to 60 kHz.
2 × π × 44 μ F × 60 kHz × 2.5
CC =
CCP =
600 μ S × 7 A/V
(0.833 Ω + 0.001 Ω) × 44 μF
7.18 kΩ
0.001 Ω × 44 μF
7.18 kΩ
ILOAD2
2
= 9.87 kΩ
VVOUT1
3
= 3.72 nF
VPVOUT2
4
= 4.46 pF
Choose standard components: RC = 9.76 kΩ, CC = 4.7 nF,
CCP = 4.7 pF.
CH2 1.00A
CH3 200mV
CH4 20.0mV BW
B
W
M200µs
A CH2
T
432.000µs
1.08A
15021-550
RC =
0.015A/µs
Figure 47. 0.6 A to 2.4 A Load Transient for 2.5 V Output, fSW = 0.6 MHz,
L = 3.3 μH, RC = 9.76 kΩ, CC = 4.7 nF, CCP = 4.7 pF, CPVOUT1 = 44 μF
SELECTING THE INPUT CAPACITOR FOR THE BUCK
REGULATOR
For the input capacitor, select a ceramic capacitor with a
minimum capacitance of 10 µF. Place the input capacitor close
to the PVIN1 pin. In this example, one 10 µF, X5R, 25 V
ceramic capacitor is recommended.
Rev. A | Page 23 of 31
ADP5003
Data Sheet
ADAPTIVE HEADROOM CONTROL DESIGN EXAMPLE
This section provides an example of the step by step design
procedures and the external components required for the buck
regulator using adaptive headroom control. Table 11 lists the
design requirements for this example.
Table 11. Example Design Requirements for the Buck
Regulator Using Adaptive Headroom Control
Parameter
Input Voltage
Output Voltage
Output Current
Buck Load Transient
Specification
VPVIN1 = 12 V
VPVOUT2 = 1.3 V
ILOAD1 = ILOAD2 = 3 A
±100 mV at 20% to 80% load transient
SETTING THE SWITCHING FREQUENCY FOR THE
BUCK REGULATOR USING ADAPTIVE HEADROOM
CONTROL
Similar to the buck design example, a switching frequency of
600 kHz is used to achieve a good combination of small solution
size and high conversion efficiency. To set the switching frequency
to 600 kHz, use Equation 1 to calculate the resistor value, RRT:
RRT (kΩ) = 1.78 × 1011/fSW (kHz)
Therefore, select standard resistor RT = 294 kΩ.
The peak-to-peak inductor ripple current, ΔIL, is set to 35% of
the maximum output current. Use the Equation 8 to estimate
the value of the inductor:
L = ((VPVIN1 – VPVOUT1) × D)/(ΔIL × fSW)
where:
VPVIN1 = 12 V.
VPVOUT1 = VPVOUT2 + VHR = 1.7 V.
VPVOUT2 = 1.3 V.
VHR is the adaptive headroom voltage at steady state current. See
Table 4 and Figure 25 for the approximate values of VHR vs. load
current. For this example, use VHR equal to 0.4 V for steady state
load current of 3 A.
D is the duty cycle (D = VVOUT1/VPVIN1).
ΔIL = 35% × 3 A = 1.05 A.
fSW = 600 kHz.
The resulting value for L is 2.32 μH. The selected standard
inductor value is 2.2 μH; therefore, ΔIL is 1.1 A.
To calculate the peak inductor current (IPEAK), use Equation 9:
SETTING THE OUTPUT VOLTAGE FOR THE LDO
REGULATOR USING ADAPTIVE HEADROOM
CONTROL
IPEAK = ILOAD1 + (ΔIL/2)
The calculated peak current for the inductor is 3.55 A.
SELECTING THE OUTPUT CAPACITORS FOR THE
BUCK REGULATOR USING ADAPTIVE HEADROOM
CONTROL
Select a value for the top feedback resistor (RTOP2) and then
calculate the bottom resistor (RBOT2) by using the following
equation:
RBOT2 = (RTOP2 × VPVOUT2)/((VREFOUT × ALDO) – VPVOUT2)
SELECTING THE INDUCTOR FOR THE BUCK
REGULATOR USING ADAPTIVE HEADROOM
CONTROL
(19)
where:
VPVOUT2 is the LDO output voltage.
VREFOUT is 2 V.
ALDO is the LDO regulator gain.
To set the output voltage to 1.3 V, RTOP2 is set to 100 kΩ giving
an RBOT2 value of 65 kΩ.
To ensure that the LDO regulator does not track the buck
output, the undershoot voltage must be set to a value less than
the minimum adaptive headroom voltage. Use Equation 17 and
Equation 18 to calculate the capacitance.
For estimation purposes, use KOV = KUV = 2; therefore,
COUT_OV = 40.7 μF and COUT_UV = 6.92 μF.
It is recommended to use a single 47 μF ceramic capacitor for the
output of the buck and a single 10 μF for the output of the LDO.
Rev. A | Page 24 of 31
Data Sheet
ADP5003
DESIGNING THE COMPENSATION NETWORK FOR
THE BUCK REGULATOR USING ADAPTIVE
HEADROOM CONTROL
VPVOUT1
4
Due to the addition of the adaptive headroom scheme in the
feedback loop, a lower bandwidth is required. Set the crossover
frequency, fC, to fSW/60. In this example, fSW is set to 600 kHz;
therefore, fC is set to 10 kHz.
2 × π × 47 μ F × 10 kHz × 2.5
CC =
CCP =
600 μ S × 7 A/V
(0.433 Ω + 0.001 Ω) × 47 μF
1.76 kΩ
0.001 Ω × 47 μF
1.76 kΩ
ILOAD1
1
= 1.76 kΩ
= 15.2 nF
= 26.7 pF
Choose standard components: RC = 1.74 kΩ, CC = 22 nF,
CCP = 22 pF.
Figure 48 shows the load transient waveform.
CH1 1.00A BW CH4 100mV
B
W
200µs
T
508µs
A CH3
1.38A
15021-449
RC =
0.013A/µs
0.02A/µs
Figure 48. 0.6 A to 2.4 A Load Transient for 2.5 V Output, fSW = 600 kHz,
L = 2.2 μH, RC = 1.74 kΩ, CC = 22 nF, CCP = 22 pF, CPVOUT1 = 47μF
SELECTING THE INPUT CAPACITOR FOR THE BUCK
REGULATOR USING ADAPTIVE HEADROOM
CONTROL
For the input capacitor, select a ceramic capacitor with a
minimum value of 10 µF. Place the input capacitor close to the
PVIN1 pin. In this example, one 10 µF, X5R, 25 V ceramic
capacitor is recommended.
Rev. A | Page 25 of 31
ADP5003
Data Sheet
RECOMMENDED EXTERNAL COMPONENTS FOR THE BUCK REGULATOR
Table 12 lists the recommended external components for buck applications up to 3 A operation (±5% tolerance at an ~60% step transient),
and Table 13 lists the recommended buck external components for adaptive headroom applications up to 3 A operation (VPVOUT2 ±
100 mV at an ~60% step transient).
Table 12. Recommended External Components for Buck Applications up to 3 A Operation (±5% Tolerance at an ~60% Step Transient)
fSW (kHz)
300
600
1000
VIN (V)
12
12
12
12
12
12
12
5
5
5
5
5
5
12
12
12
12
12
5
5
5
5
5
5
12
12
12
5
5
5
5
5
5
VOUT (V)
1
1.2
1.5
1.8
2.5
3.3
5
1
1.2
1.5
1.8
2.5
3.3
1.5
1.8
2.5
3.3
5
1
1.2
1.5
1.8
2.5
3.3
2.5
3.3
5
1
1.2
1.5
1.8
2.5
3.3
L (μH)
3.3
4.7
4.7
5.6
6.8
8.2
10
3.3
3.3
4.7
4.7
4.7
4.7
2.2
3.3
3.3
4.7
5.6
1.5
1.8
1.8
2.2
2.2
2.2
2.2
3.3
3.3
1
1
1.2
1.2
1.5
1.2
COUT (μF)
210
204.7
147
110
69
47
26.7
210
147
132
94
47
51.7
69
69
32
26.7
22
94
147
49.2
47
23
24.2
22
22
22
69
47
32
23
22
22
RTOP1 (kΩ)
200
150
174
150
100
49.9
0
200
150
174
150
100
49.9
150
150
100
49.9
0
200
150
174
150
100
49.9
100
49.9
0
200
150
174
150
100
49.9
Rev. A | Page 26 of 31
RBOT1 (kΩ)
49.9
47.5
75
84.5
100
97.6
open
49.9
47.5
75
84.5
100
97.6
84.5
84.5
100
97.6
Open
49.9
47.5
75
84.5
100
97.6
100
97.6
Open
49.9
47.5
75
84.5
100
97.6
RC (kΩ)
23.7
23.2
16.5
12.4
7.68
5.23
3.01
23.7
16.5
14.7
10.5
5.23
5.76
15.4
15.4
7.15
6.04
4.99
21
33.2
11
10.5
5.11
5.49
8.25
8.25
8.25
25.5
17.4
12.1
8.66
8.25
8.25
CC (nF)
3.3
3.3
4.7
4.7
6.8
10
15
3.3
3.3
4.7
4.7
6.8
10
2.2
2.2
3.3
4.7
6.8
1.5
1.5
2.2
2.2
3.3
4.7
2.2
3.3
4.7
1
1
1.5
1.5
2.2
3.3
CCP (pF)
10
10
10
10
10
10
10
10
10
10
10
10
10
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
Data Sheet
ADP5003
Table 13. Recommended Buck External Components for Adaptive Headroom Applications up to 3 A Operation (VPVOUT2 ± 100 mV
at an ~60% Step Transient)
fSW (kHz)
600
VIN (V)
12
12
12
12
12
5
5
5
5
5
VOUT2 (V)
3.3
2.5
1.8
1.3
1.1
3.3
2.5
1.8
1.3
1.1
L (µH)
4.7
3.3
3.3
2.2
1.8
1.5
1.8
1.8
1.8
1.5
COUT1 (µF)
47
44
57
47
47
44
32
32
44
44
RC (kΩ)
1.74
1.65
2.15
1.74
1.74
1.65
1.21
1.21
1.65
1.65
CC (nF)
33
22
22
22
10
33
22
22
22
10
Rev. A | Page 27 of 31
CCP (pF)
22
22
22
22
22
22
22
22
22
22
RTOP2 (kΩ)
Short
37.4
100
100
100
Short
37.4
100
100
100
RBOT2 (kΩ)
Open
118
121
64.9
49.9
Open
118
121
64.9
49.9
COUT2 (µF)
10
10
10
10
10
10
10
10
10
10
ADP5003
Data Sheet
BUCK CONFIGURATIONS
80
The buck and LDO regulators can operate independently of
each other (see Figure 50) to provide two voltage rails from a
single supply. In this way, the buck regulator can provide an
intermediate supply rail for the LDO regulator with a fixed
headroom voltage between the buck output voltage and the
LDO output voltage. The LDO regulator acts to filter the voltage
ripple and switching noise generated by the buck regulator for
noise sensitive supplies. Where additional filtering is required, a
second stage LC filter can be added between the buck output
and the LDO input. Because the regulators are independently
operated to provide a single voltage rail, the PSRR and efficiency
can be configured as required by the application by either
setting a lower headroom voltage for greater efficiency or a
higher headroom voltage for greater PSRR.
70
CVREG
1µF
0.5
1.0
1.5
2.0
LOAD CURRENT (A)
2.5
VPVIN1: 12V
CPVIN1
10µF
L1
3.3µH
VPVOUT1 = 2.5V
PGND1
VREG
PVINSYS
CPVINSYS
10µF
ADAPTIVE HEADROOM CONTROL
INDEPENDENT, 150mV HEADROOM
INDEPENDENT, 500mV HEADROOM
CPVOUT1
44µF
RT
VPVINSYS: 12V
20
Figure 49. Efficiency vs. Load Current for
Different Operating Modes
SW1
VSET1
RTOP1
100kΩ
30
0
VOUT1
RBOT1
100kΩ
40
0
PVIN1
BUCK
REGULATOR
3A
50
10
EN1
CC
RC
4.7nF 9.76kΩ COMP1
60
RRT
294kΩ
PWRGD
SYSTEM
ANALOG DEVICES
RF TRANSCEIVER,
HIGH SPEED
ADC/DAC, CLOCK,
ASIC/PROCESSOR
SYNC
REFOUT
CREFOUT
0.22µF
RTOP2
100kΩ
PVIN2
VSET2
CPVIN2
10µF
VBUF
CVBUF
0.1µF
VREG_LDO
LOW NOISE
LDO ACTIVE
FILTER
3A
PVOUT2
VPVOUT2 = 1.3V
CPVOUT2
10µF
CVREG_LDO
1µF
EN2
VFB2P
VFB2N
AGND1
AGND2
Figure 50. Independent Configuration (Dual Output)
Rev. A | Page 28 of 31
15021-062
RBOT2
64.9kΩ
3.0
15021-450
INDEPENDENT EFFICIENCY (%)
INDEPENDENT
Data Sheet
ADP5003
ADAPTIVE HEADROOM
0
The ADP5003 features a scheme to control the buck regulator
output voltage and thus the LDO headroom voltage to provide
better efficiency with the same noise performance of a standalone
LDO regulator. When the buck regulator uses the adaptive
headroom control configuration, the ADP5003 manages the
buck regulator output voltage vs. the LDO load current (see
Figure 25). The adaptive headroom control also optimizes the
LDO headroom when the remote sense feedback corrects any
output voltage drop due to additional filtering or high trace
impedance under high load conditions. The headroom profile
of the adaptive headroom control is set to deliver a consistent
PSRR across the load range while optimizing efficiency of the
overall system (see Figure 51). To enable adaptive headroom
control, connect VSET1 to VREG (see Figure 52).
EN1
0.2V, 1A
0.28V, 1.5A
0.35V, 2A
0.4V, 2.5A
0.4V, 3A
–10
LDO PSRR (dB)
–20
LDO PSRR
VPVIN1 = 12V, VPVOUT2 = 0.9V
–30
–40
–50
–60
–70
–90
10
1
100
1k
10k
1M
100k
FREQUENCY (Hz)
Figure 51. LDO PSRR vs. Frequency
PVIN1
VPVIN1: 12V
PVIN1
CPVIN1
10µF
VOUT1
CC
RC
2.2nF 1.74kΩ
COMP1
BUCK
REGULATOR
3A
L1
2.2µH
SW1
SW1
SW1
VPVOUT1
(ADAPTIVE)
CPVOUT1
47µF
PGND1
VSET1
PGND1
PGND1
CVREG
1µF
VREG
RT
VPVINSYS: 12V
PVINSYS
CPVINSYS
10µF
RRT
294kΩ
PWRGD
SYSTEM
SYNC
REFOUT
CREFOUT
0.22µF
PVIN2
VSET2
RBOT2
64.9kΩ
CVBUF
0.1µF
PVIN2
PVIN2
VBUF
VREG_LDO
LOW NOISE
LDO ACTIVE
FILTER
3A
CVREG_LDO
1µF
EN2
CPVIN2
10µF
PVOUT2
VVPOUT2 = 1.3V
PVOUT2
PVOUT2
CPVOUT2
10µF
ANALOG DEVICES
RF TRANSCEIVER,
HIGH SPEED ADC/DAC,
CLOCK, ASIC/
PROCESSOR
VFB2P
VFB2N
AGND1
15021-061
RTOP2
100kΩ
AGND2
Figure 52. Adaptive Headroom Configuration
Rev. A | Page 29 of 31
10M
15021-145
–80
ADP5003
Data Sheet
LAYOUT CONSIDERATIONS
Layout is important for all switching regulators but is
particularly important for regulators with high switching
frequencies. To achieve high efficiency, proper regulation,
stability, and low noise, a well designed PCB layout is required.
Follow these guidelines when designing PCBs:
•
13.2mm
L1
PVIN
2
23
3
22
4
21
ADP5003
5
20
15
16
14
17
13
8
12
18
11
19
7
9
6
RRT 0201
CVREG
1µF
10V/X5R
0406
CC
0402
RC
0201
24
0402
RTOP1 RBOT1 CCP
0201
1
0201
26
25
28
27
29
31
30
32
CVOUT1
22µF
25V/X5R
1206
0201
0201
CREFOUT
0.22µF
10V/X5R
0402
RTOP2 RBOT2
PVOUT2
CPVOUT2
10µF
25V/X5R
0805
Figure 53. Example Outline Layout
Rev. A | Page 30 of 31
CVREG_LDO
1µF
10V/X5R
0402
CVBUF
0.1µF
10V/X5R
0402
15021-063
CPVIN2
10µF
50V/X5R
1206
CPVINSYS
10µF
35V/X5R
0805
CPVIN1
10µF
50V/X5R
1206
10
PVOUT1
•
•
Keep high current loops as short and wide as possible.
• Keep the input bypass capacitors close to the PVIN1,
PVIN2, and PVINSYS pins.
• Keep the inductor and output capacitor close to SW1
and PGND1.
Route the VFB2P and VFB2N LDO sense traces side by
side connecting them each as close as possible to the point
18.7mm
•
of load. Keep them as short as possible and away from
noise sources.
Place the frequency setting resistor close to the RT pin.
Keep AGND1 and PGND1 separate on the top layer of the
board. This separation avoids pollution of AGND1 with
switching noise. Do not connect PGND1 to the EPAD on
the top layer of the layout. Connect both AGND1 and
PGND1 to the board ground plane with vias. Ideally,
connect PGND1 to the plane at a point between the input
and output capacitors.
Connect the negative terminal of CVBUF to the VFB2N pin.
Data Sheet
ADP5003
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
0.30
0.25
0.18
25
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
32
24
1
0.50
BSC
3.25
3.10 SQ
2.95
EXPOSED
PAD
17
TOP VIEW
0.80
0.75
0.70
SIDE VIEW
PKG-003898
SEATING
PLANE
0.50
0.40
0.30
8
9
16
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
BOTTOM VIEW
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD
10-19-2017-B
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
Figure 54. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADP5003ACPZ-R7
ADP5003CP-EVALZ
1
Temperature Range
−40°C to +125°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Z = RoHS Compliant Part.
©2017–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15021-0-3/19(A)
Rev. A | Page 31 of 31
Package Option
CP-32-7
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