FEATURES
TYPICAL APPLICATION CIRCUIT
Input voltage range: 2.75 V to 6.0 V
Programmable output voltage range: 0.5 V to 0.9 × PVINx
Low output noise: ~25 μV rms when VOUT ≤ VREF
±1.0% output accuracy over full temperature range
500 kHz to 2.5 MHz adjustable switching frequency
Power regulation
Channel 1 and Channel 2: programmable 2 A/4 A sync
buck regulators, or single 8 A output in parallel
Channel 3 and Channel 4: programmable 1 A/2 A sync
buck regulators, or single 4 A output in parallel
Flexible parallel operation
Precision enable with 0.6 V threshold
Manual or sequence mode for power-up and power-down
sequence
Selective FPWM or PSM operation mode
Precision undervoltage comparator
Frequency synchronization input or output
Active output discharge switch
Power-good flag on selective channels via factory fuse
UVLO, OVP, OCP, and TSD protection
40-lead, 6 mm × 6 mm LFCSP package
−40°C to +125°C junction temperature
ADP5014
RRT
RT
RF transceiver, high speed analog-to-digital converter
(ADC)/digital-to-analog converter (DAC), mixed signal ASIC
FPGA and processor applications
Security and surveillance
Medical applications
LOGIC DECODER
CFG2
GPIO
EN4/DL34
AVIN
FB1
2.75V TO 6.0V PVIN1
C2
PVIN1
VREF VSET1
C1
CFG1
EN2/DL12
EN3/UV
VREF
REF
EN1/ENALL
CH 1
LOW-NOISE BUCK
(2A/4A)
SW1
L1
VOUT1
C3
PGND1
COMP1
FB2
PVIN2
C4
VREF VSET2
CH 2
LOW-NOISE BUCK
(2A/4A)
SW2
L2
VOUT2
C5
PGND2
COMP2
PVIN3
C6
VREF VSET3
SW3
CH 3
LOW-NOISE BUCK
(1A/2A)
L3
FB3
VOUT3
C7
PGND3
COMP3
PVIN4
C8
VREF VSET4
APPLICATIONS
OSC
SW4
CH 4
LOW-NOISE BUCK
(1A/2A)
FB4
L4
VOUT4
C9
PGND4
COMP4
15496-001
Data Sheet
Integrated Power Solution
with Quad Low Noise Buck Regulators
ADP5014
AGND
EXPOSED PAD
Figure 1.
GENERAL DESCRIPTION
The ADP5014 combines four high performance, low noise
buck regulators in a 40-lead LFCSP package. Relying on its low
output noise (~25 μV rms when VOUT ≤ VREF), the low noise
buck regulator enables the powering up of the noise sensitive
signal chain products.
All channels in the ADP5014 integrate high-side and low-side
power metal-oxide semiconductor field effect transistors
(MOSFET). Channel 1 and Channel 2 deliver a programmable
output current of 2 A or 4 A. Combining Channel 1 and
Channel 2 in a parallel configuration provides a single output
with up to 8 A of current.
Channel 3 and Channel 4 deliver a programmable output current
of 1 A or 2 A. Combining Channel 3 and Channel 4 in a parallel
configuration can provide a single output with up to 4 A of
current.
Rev. A
The ADP5014 features two enable modes. The manual mode
has four individual precision enable pins to enable each
regulator manually. Alternatively, the sequence mode has one
grouped precision enable signal with programmable power-up
and power-down delay timers on each rail for specific rail
sequence requirements.
The switching frequency of the ADP5014 can be programmed
or synchronized to an external clock from 500 kHz to 2.5 MHz.
The ADP5014 offers other key features like selective forced
pulse width modulation (FPWM)/power saving mode (PSM),
an undervoltage output (UVO), active output discharge, and a
power-good flag. Other safety features include input undervoltage lockout (UVLO), overvoltage protection (OVP),
overcurrent protection (OCP) and thermal shutdown (TSD).
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Technical Support
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ADP5014
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Overvoltage Protection .............................................................. 20
Applications ....................................................................................... 1
Undervoltage Lockout ............................................................... 20
Typical Application Circuit ............................................................. 1
Active Output Discharge Switch .............................................. 21
General Description ......................................................................... 1
Thermal Shutdown .................................................................... 21
Revision History ............................................................................... 2
Applications Information .............................................................. 22
Detailed Functional Block Diagram .............................................. 3
ADIsimPower Design Tool ....................................................... 22
Specifications..................................................................................... 4
Programming the Output Voltage ........................................... 22
Buck Regulator Specifications .................................................... 5
Voltage Conversion Limitations ............................................... 22
Absolute Maximum Ratings............................................................ 7
Current-Limit Setting ................................................................ 23
Thermal Resistance ...................................................................... 7
Soft Start Setting ......................................................................... 23
ESD Caution .................................................................................. 7
Inductor Selection ...................................................................... 23
Pin Configuration and Function Descriptions ............................. 8
Output Capacitor Selection....................................................... 24
Typical Performance Characteristics ........................................... 10
Input Capacitor Selection .......................................................... 24
Theory of Operation ...................................................................... 14
Programming the UVLO Input ................................................ 24
Buck Regulator Operational Modes......................................... 14
Compensation Components Design ....................................... 24
Low Noise Architecture ............................................................. 14
Power Dissipation....................................................................... 25
Internal Reference (VREF) ........................................................ 14
Junction Temperature ................................................................ 26
Adjustable Output Voltage ........................................................ 14
Design Examples ............................................................................ 27
Function Configurations (CFG1 and CFG2) ......................... 15
Setting the Switching Frequency .............................................. 27
Parallel Operation....................................................................... 16
Setting the Output Voltage ........................................................ 27
Manual/Sequence Mode ............................................................ 16
Setting the Configuations (CFG1 and CFG2) ........................ 27
General Purpose Input/Output (GPIO) .................................. 18
Selecting the Inductor ................................................................ 27
Oscillator ..................................................................................... 18
Selecting the Output Capacitor ................................................ 28
Synchronization Input/Output ................................................. 19
Designing the Compensation Network ................................... 28
Power-Good Function ............................................................... 19
Low Noise Output Design ......................................................... 28
UV Comparator (Sequence Mode Only) ................................ 19
PCB Layout Recommendations.................................................... 30
Soft Start ...................................................................................... 20
Typical Application Circuits ......................................................... 31
Startup with Precharged Output .............................................. 20
Factory Programmable Options ................................................... 33
Current-Limit Protection .......................................................... 20
Factory Default Options ............................................................ 33
Frequency Fold Back .................................................................. 20
Outline Dimensions ....................................................................... 34
Short-Circuit Protection (SCP) ................................................ 20
Ordering Guide .......................................................................... 34
REVISION HISTORY
8/2019—Rev. 0 to Rev. A
Changes to Parallel Operation Section ........................................ 16
Updated Outline Dimensions ....................................................... 34
6/2017—Revision 0: Initial Version
Rev. A | Page 2 of 34
Data Sheet
ADP5014
DETAILED FUNCTIONAL BLOCK DIAGRAM
CHANNEL 1 – BUCK
EN1/ENALL
+
0.6V
UVLO1
PVIN1
EN_BUF
+
–
A CS1
–
3µA
+
CLK1
OCP
HICCUP
MODE
–
PVIN1
DRIVER
SLOPE
COMP
+
CMP1
–
COMP1
VSET1
PVIN1
+
EA1
CLK1
–
CONTROL LOGIC
AND MOSFET
DRIVER WITH
ANTICROSS
PROTECTION
FREQ
FOLDBACK
FB1
–
+
0.9
VID1
Q1
SW1
Q2
DISCHARGE
SWITCH
1µA
DRIVER
PGND1
ZERO
CROSS
OVP
LATCH-UP
NEG CURRENT
CMP
1.15
+
–
PWRGD1
CURRENT BALANCE
EN2/DL12
COMP2
PVIN2
CHANNEL 2 – BUCK
DUPLICATE
CHANNEL 1
VSET2
FB2
RT
CFG1
CFG2
SW2
PGND2
OSCILLATOR
CLK
HOUSE-KEEPING
LOGIC
FUNCTION
DECODER
GPIO
CHANNEL 3 – BUCK
EN3/UV
+
0.6V
REF
VREF
UVLO
AVIN
PVIN3
UVLO3
EN_BUF
+
–
ACS3
–
3µA
CLK3
OCP
+
–
PVIN3
+
CMP3
–
COMP3
+
EA3
SW3
PVIN3
CLK3
–
CONTROL LOGIC
AND MOSFET
DRIVER WITH
ANTICROSS
PROTECTION
FREQ
FOLDBACK
FB3
–
+
VID3
Q5
DRIVER
SLOPE
COMP
VSET3
HICCUP
MODE
0.9
+
–
DRIVER
Q6
DISCHARGE
SWITCH
1µA
PGND3
ZERO
CROSS
OVP
LATCH-UP
NEG CURRENT
CMP
1.15
PWRGD3
CURRENT BALANCE
COMP4
VSET4
PVIN4
CHANNEL 4 – BUCK
DUPLICATE
CHANNEL 3
SW4
PGND4
FB4
Figure 2.
Rev. A | Page 3 of 34
15496-002
EN4/DL34
ADP5014
Data Sheet
SPECIFICATIONS
VIN = 5 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 1.
Parameter
INPUT SUPPLY VOLTAGE RANGE
Symbol
VIN
Min
2.75
Typ
Max
6.0
Unit
V
5.4
47
7.0
85
mA
µA
2.65
2.40
0.25
2.75
V
V
V
QUIESCENT CURRENT
Operating Quiescent Current
Shutdown Current
UNDERVOLTAGE LOCKOUT
IQ
ISHDN
UVLO
Threshold, Rising
Threshold, Falling
Hysteresis
REFERENCE
Output Voltage
Accuracy
Maximum Load
OSCILLATOR CIRCUIT
Switching Frequency Range
Switching Frequency
Sync Input
Input Clock Range
Input Clock Pulse Width
Minimum On Time
Minimum Off Time
Input Clock High Voltage
Input Clock Low Voltage
Sync Output
Clock Frequency
Positive Pulse Duty Cycle
Rise or Fall Time
High Level Voltage
PRECISION ENABLING
High Level Threshold
Low Level Threshold
Source Current
DELAY TIMER
Programmable Delay Timer Range
Delay Timer
VUVLO-RISING
VUVLO-FALLING
VHYS
POWER GOOD
Internal Power-Good Rising Threshold
Internal Power-Good Hysteresis
Internal Power-Good Falling Delay
Rising Delay for PWRGD Pin
Leakage Current for PWRGD Pin
Output Low Voltage for PWRGD Pin
2.30
VREF
2.0
−1.0
1
fSW
500
1000
fSYNC
500
tSYNC_MIN_ON
tSYNC_MIN_OFF
VH(SYNC)
VL(SYNC)
100
100
1.3
1200
fCLK
tCLK_PULSE_DUTY
tCLK_RISE_FALL
VH(SYNC_OUT)
fSW
50
10
VAVIN
VTH_H(EN)
VTH_L(EN)
ITH_L(EN)
0.6
0.57
4
+1.0
V
%
mA
2500
1400
kHz
kHz
2500
kHz
0.4
ns
ns
V
V
Test Conditions/Comments
AVIN, PVIN1, PVIN2, PVIN3,
PVIN4 pins
AVIN, PVIN1, PVIN2, PVIN3,
PVIN4 pins
No switching, all ENx pins high
All ENx pins low
AVIN, PVIN1, PVIN2, PVIN3,
PVIN4 pins
RRT = 82.5 kΩ
kHz
%
ns
V
EN1, EN2, EN3, EN4 pins
0.52
tDELAY
tDELAY
6
VPWRGD(RISE)
VPWRGD(HYS)
tPWRGD_FALL
tPWRGD_PIN_RISE
87
IPWRGD_LEAKAGE
VPWRGD_LOW
0.65
48
6
48
90
3
50
2
16
0.1
70
Rev. A | Page 4 of 34
93
1
150
V
V
µA
Below the falling threshold
ms
ms
ms
Timer ×1 option
Timer ×8 option
%
%
µs
ms
ms
µA
mV
Timer ×1 option
Timer ×8 option
IPWRGD = 1 mA
Data Sheet
Parameter
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
ADP5014
Symbol
Min
TSHDN
THYS
Typ
Max
150
15
Unit
Test Conditions/Comments
°C
°C
BUCK REGULATOR SPECIFICATIONS
VIN = 5 V, fSW = 1.2 MHz for all channels, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical
specifications, unless otherwise noted.
Table 2.
Parameter
CHANNEL 1 SYNC BUCK REGULATOR
Load Current
Output Characteristics
VFB1 Voltage Accuracy
Symbol
Typ
ILOAD1
VFB1
Feedback Bias Current
VSET1 Bias Current
SW1 Pin
High-Side Power Field Effect
Transistor (FET) On Resistance
Low-Side Power FET
On Resistance
Current-Limit Threshold
IFB1
IVSET1
Minimum On Time
Minimum Off Time
Error Amplifier, COMP1 Pin
EA Transconductance
Soft Start Time
tMIN_ON1
tMIN_OFF1
Programmable Soft Start Range
Hiccup Time
COUT Discharge Switch On
Resistance
CHANNEL 2 SYNC BUCK REGULATOR
Load Current
Output Characteristics
VFB2 Voltage Accuracy
Min
−0.6
−1.0
Max
Unit
4
A
+0.6
+1.0
0.1
0.1
%
%
µA
μA
Test Conditions/Comments
−40°C ≤ TJ ≤ +125°C
VSET1 = VREF
VSET1 = ½ × VREF
RDS(ON)1H
49
80
mΩ
Pin to pin measurement
RDS(ON)1L
37
60
mΩ
Pin to pin measurement
5.2
2.5
6.9
3.5
60
50
8.6
4.5
90
80
A
A
ns
ns
RCFG1 = 0 kΩ
RCFG1 = 17.8 kΩ
fSW = 500 kHz to 2.5 MHz
fSW = 500 kHz to 2.5 MHz
700
800
2
16
900
µS
ms
ms
ms
ms
Ω
ITH(ILIM1)
gm1
tSS1
2
tHICCUP1
RDIS1
16
7 × tSS1
85
ILOAD2
VFB2
Feedback Bias Current
VSET2 Bias Current
SW2 Pin
High-Side Power FET On
Resistance
Low-Side Power FET On
Resistance
Current-Limit Threshold
IFB2
IVSET2
Minimum On Time
Minimum Off Time
Error Amplifier, COMP2 Pin
Transconductance
tMIN_ON2
tMIN_OFF2
−0.6
−1.0
4
A
+0.6
+1.0
0.1
0.1
%
%
µA
µA
Timer ×1 option
Timer ×8 option
−40°C ≤ TJ ≤ +125°C
VSET2 = VREF
VSET2 = ½ × VREF
RDS(ON)2H
49
80
mΩ
Pin to pin measurement
RDS(ON)2L
37
60
mΩ
Pin to pin measurement
6.9
3.5
60
50
8.6
4.5
90
80
A
A
ns
ns
RCFG1 = 0 kΩ
RCFG1 = 17.8 kΩ
fSW = 500 kHz to 2.5 MHz
fSW = 500 kHz to 2.5 MHz
800
900
µS
ITH(ILIM2)
gm2
5.2
2.5
700
Rev. A | Page 5 of 34
ADP5014
Parameter
Soft Start Time
Programmable Soft Start Range
Hiccup Time
COUT Discharge Switch On
Resistance
CHANNEL 3 SYNC BUCK REGULATOR
Load Current
Output Characteristics
VFB3 Voltage Accuracy
Data Sheet
Symbol
tSS2
IFB3
IVSET3
Minimum On Time
Minimum Off Time
Error Amplifier, COMP3 Pin
EA Transconductance
Soft Start Time
tMIN_ON3
tMIN_OFF3
Max
16
7 × tSS2
85
ILOAD3
Feedback Bias Current
VSET3 Bias Current
SW3 Pin
High-Side Power FET On
Resistance
Low-Side Power FET On
Resistance
Current-Limit Threshold
−0.6
−1.0
Unit
ms
ms
ms
ms
Ω
2
A
+0.6
+1.0
0.1
0.1
%
%
µA
µA
Test Conditions/Comments
Timer ×1 option
Timer ×8 option
−40°C ≤ TJ ≤ +125°C
VSET3 = VREF
VSET3 = ½ × VREF
RDS(ON)3H
95
135
mΩ
Pin to pin measurement
RDS(ON)3L
73
110
mΩ
Pin to pin measurement
2.5
1.2
3.5
1.8
60
50
4.5
2.4
90
80
A
A
ns
ns
RCFG1 = 0 kΩ
RCFG1 = 17.8 kΩ
fSW = 500 kHz to 2.5 MHz
fSW = 500 kHz to 2.5 MHz
700
800
2
16
900
µS
ms
ms
ms
ms
Ω
ITH(ILIM3)
gm3
tSS3
2
tHICCUP3
RDIS3
16
7 × tSS3
85
ILOAD4
VFB4
Feedback Bias Current
VSET4 Bias Current
SW4 Pin
High-Side Power FET On
Resistance
Low-Side Power FET On
Resistance
Current-Limit Threshold
IFB4
IVSET4
Minimum On Time
Minimum Off Time
Error Amplifier, COMP4 Pin
EA Transconductance
Soft Start Time
tMIN_ON4
tMIN_OFF4
Programmable Soft Start Range
Hiccup Time
COUT Discharge Switch On Resistance
Typ
2
16
2
tHICCUP2
RDIS2
VFB3
Programmable Soft Start Range
Hiccup Time
COUT Discharge Switch On Resistance
CHANNEL 4 SYNC BUCK REGULATOR
Load Current
Output Characteristics
VFB4 Voltage Accuracy
Min
−0.6
−1.0
2
A
+0.6
+1.0
0.1
0.1
%
%
µA
μA
Timer ×1 option
Timer ×8 option
−40°C ≤ TJ ≤ +125°C
VSET4 = VREF
VSET4 = ½ × VREF
RDS(ON)4H
95
135
mΩ
Pin to pin measurement
RDS(ON)4L
73
110
mΩ
Pin to pin measurement
2.5
1.2
3.5
1.8
60
50
4.5
2.4
90
80
A
A
ns
ns
RCFG1 = 0 kΩ
RCFG1 = 17.8 kΩ
fSW = 500 kHz to 2.5 MHz
fSW = 500 kHz to 2.5 MHz
700
800
2
16
900
µS
ms
ms
ms
ms
Ω
ITH(ILIM4)
gm4
tSS4
2
tHICCUP4
RDIS4
16
7 × tSS4
85
Rev. A | Page 6 of 34
Timer ×1 option
Timer ×8 option
Data Sheet
ADP5014
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
AVIN to Ground
PVIN1 to PGND1
PVIN2 to PGND2
PVIN3 to PGND3
PVIN4 to PGND4
SW1 to PGND1
SW2 to PGND2
SW3 to PGND3
SW4 to PGND4
PGND to Ground
CFG1, CFG2 to Ground
EN1/ENALL, EN2/DL12, EN3/UV,
EN4/DL34 to Ground
GPIO to Ground
RT to Ground
VREF to Ground
FB1, FB2, FB3, FB4 to Ground 1
COMP1, COMP2, COMP3, COMP4
to Ground
VSET1, VSET2, VSET3, VSET4 to
Ground
Storage Temperate Range
Operational Junction Temperature
Range
1
Rating
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to + 0.3 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Close attention to
PCB thermal design is required.
Table 4. Thermal Resistance
Package Type
CP-40-10
ESD CAUTION
−0.3 V to +6.5 V
−65°C to +150°C
−40°C to +125°C
The rating for the FB1, FB2, FB3, and FB4 pins applies to the adjustable
output voltage models of the ADP5014.
Rev. A | Page 7 of 34
θJA
40
θJC
11.1
Unit
°C/W
ADP5014
Data Sheet
40
39
38
37
36
35
34
33
32
31
VSET4
VSET3
VREF
VSET2
VSET1
RT
AVIN
FB1
COMP1
PVIN1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADP5014
TOP VIEW
(Not to Scale)
30
29
28
27
26
25
24
23
22
21
PVIN1
SW1
SW1
PGND1
PGND1
PGND2
PGND2
SW2
SW2
PVIN2
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED AND SOLDERED TO AN EXTERNAL
GROUND PLANE.
15496-003
GPIO
EN4/DL34
EN3/UV
CFG2
CFG1
EN2/DL12
EN1/ENALL
FB2
COMP2
PVIN2
11
12
13
14
15
16
17
18
19
20
FB3 1
COMP3 2
PVIN3 3
SW3 4
PGND3 5
PGND4 6
SW4 7
PVIN4 8
COMP4 9
FB4 10
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
Mnemonic
FB3
COMP3
PVIN3
SW3
PGND3
PGND4
SW4
PVIN4
COMP4
FB4
GPIO
12
EN4/DL34
13
EN3/UV
14
CFG2
15
CFG1
16
EN2/DL12
17
EN1/ENALL
18
19
20, 21
22, 23
24, 25
26, 27
28, 29
FB2
COMP2
PVIN2
SW2
PGND2
PGND1
SW1
Description
Feedback Sensing Input for Channel 3.
Error Amplifier Output for Channel 3. Connect a resistor capacitor (RC) network from this pin to ground.
Power Input for Channel 3.
Switching Node Output for Channel 3.
Power Ground for Channel 3
Power Ground for Channel 4.
Switching Node Output for Channel 4.
Power Input for Channel 4.
Error Amplifier Output for Channel 4. Connect an RC network from this pin to ground.
Feedback Sensing Input for Channel 4.
General-Purpose Input or Output Signal. This pin can be configured as power good, synchronization clock
output (CLK-OUT) or undervoltage comparator output (UVO).
Enable Input for Channel 4 in Manual Mode (EN4).
Delay Timer Setting for Channel 3 and Channel 4 in Sequence Mode (DL34). Connect one resistor from this pin
to ground to program the start-up and shutdown sequence delay timer for Channel 3 and Channel 4.
Enable Input for Channel 3 in Manual Mode (EN3).
Under Voltage Comparator Input in Sequence Mode (UV).
System Configuration Pin 1. Connect one resistor from this pin to ground to program sequence or manual
mode, the delay timer, PSM or FPWM operation mode, and GPIO mapping for all channels.
System Configuration Pin 2. Connect one resistor from this pin to ground to program current limit, and the
parallel output for all channels.
Enable Input for Channel 2 in Manual Mode (EN2).
Delay Timer Setting for Channel 1 and Channel 2 in Sequence Mode (DL12). Connect one resistor from this pin
to ground to program the start-up and shutdown sequence delay timer for Channel 1 and Channel 2.
Enable Input for Channel 1 in Manual Mode (EN1).
Grouped Enable Input for All Channels in Sequence Mode (ENALL).
Feedback Sensing Input for Channel 2.
Error Amplifier Output for Channel 2. Connect an RC network from this pin to ground.
Power Input for Channel 2.
Switching Node Output for Channel 2.
Power Ground for Channel 2.
Power Ground for Channel 1.
Switching Node Output for Channel 1.
Rev. A | Page 8 of 34
Data Sheet
Pin No.
30, 31
32
33
34
Mnemonic
PVIN1
COMP1
FB1
AVIN
35
36
37
38
39
40
RT
VSET1
VSET2
VREF
VSET3
VSET4
Exposed Pad
ADP5014
Description
Power Input for Channel 1.
Error Amplifier Output for Channel 1. Connect an RC network from this pin to ground.
Feedback Sensing Input for Channel 1.
Analog Power Input for the Internal Control Circuitry. Connect a bypass capacitor between this pin and ground.
Connect a small (10 Ω) resistor between this pin and PVINx.
Frequency Setting. Connect a resistor from RT to ground to program the switching frequency.
Channel 1 Reference Voltage Setting Input.
Channel 2 Reference Voltage Setting Input.
Internal Low Noise Voltage Reference Output.
Channel 3 Reference Voltage Setting Input.
Channel 4 Reference Voltage Setting Input.
Analog Ground. The exposed pad must be connected and soldered to an external ground plane.
Rev. A | Page 9 of 34
ADP5014
Data Sheet
100
100
90
90
80
80
70
70
60
50
40
VOUT = 1.2V
VOUT = 1.5V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
10
0
1.0
2.0
3.0
4.0
Figure 4. Channel 1/Channel 2 Efficiency Curve, VIN = 5 V, fSW = 1.2 MHz,
FPWM Mode
0
0.01
90
80
80
70
70
EFFICIENCY (%)
90
50
40
30
10
60
50
40
30
1.0
2.0
3.0
4.0
IOUT (A)
10
0
15496-005
0
VOUT = 1.2V
VOUT = 1.5V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
20
VOUT = 1.2V
VOUT = 1.5V
VOUT = 1.8V
VOUT = 2.5V
10
Figure 5. Channel 1/Channel 2 Efficiency Curve, VIN = 3.3 V, fSW = 1.2 MHz,
FPWM Mode
0
0.5
1.0
1.5
2.0
IOUT (A)
15496-008
20
Figure 8. Channel 3/Channel 4 Efficiency Curve, VIN = 5 V, fSW = 1.2 MHz,
FPWM Mode
100
100
90
80
80
70
70
EFFICIENCY (%)
90
60
50
40
30
60
50
40
30
20
fSW = 500kHz
fSW = 1.2MHz
fSW = 2.4MHz
0
1.0
2.0
IOUT (A)
3.0
4.0
VOUT
VOUT
VOUT
VOUT
10
0
15496-006
10
Figure 6. Channel 1/Channel 2 Efficiency Curve, VIN = 5 V, VOUT = 3.3 V, FPWM
Mode
0
0.5
1.0
IOUT (A)
1.5
= 1.2V
= 1.5V
= 1.8V
= 2.5V
2.0
15496-009
20
0
1
Figure 7. Channel 1/Channel 2 Efficiency Curve, VIN = 5 V, fSW = 1.2 MHz,
FPWM and Automatic PWM/PSM Modes
100
60
0.1
IOUT (A)
100
0
VOUT = 1.2V FPWM
VOUT = 1.8V FPWM
VOUT = 3.3V FPWM
VOUT = 1.2V PSM
VOUT = 1.8V PSM
VOUT = 3.3V PSM
10
IOUT (A)
EFFICIENCY (%)
40
20
15496-004
20
EFFICIENCY (%)
50
30
30
0
60
15496-007
EFFICIENCY (%)
EFFICIENCY (%)
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 9. Channel 3/Channel 4 Efficiency Curve, VIN = 3.3 V, fSW = 1.2 MHz,
FPWM Mode
Rev. A | Page 10 of 34
Data Sheet
ADP5014
100
1500
90
1400
80
FREQUENCY (kHz)
EFFICIENCY (%)
70
60
50
40
1300
1200
30
fSW = 500kHz
fSW = 1.2MHz
fSW = 2.5MHz
0
1.0
0.5
0
2.0
1.5
IOUT (A)
1000
–50
15496-010
10
–20
10
40
70
100
15496-013
1100
20
130
TEMPERATURE (°C)
Figure 13. Frequency vs. Temperature, VIN = 5 V, fSW = 1.2 MHz
Figure 10. Channel 3/Channel 4 Efficiency Curve, VIN = 5 V, VOUT = 3.3 V,
FPWM Mode
6.0
100
5.5
QUIESCENT CURRENT (mA)
60
40
VOUT = 1.2V FPWM
VOUT = 1.8V FPWM
VOUT = 3.3V FPWM
VOUT = 1.2V PSM
VOUT = 1.8V PSM
VOUT = 3.3V PSM
0
0.01
0.1
1
5.0
4.5
4.0
3.5
10
IOUT (A)
3.0
–50
100
50
TEMPERATURE (°C)
Figure 11. Channel 3/Channel 4 Efficiency Curve, VIN = 5 V, fSW = 1.2 MHz,
FPWM and Automatic PWM/PSM Modes
Figure 14. Quiescent Current vs. Temperature (Includes PVIN1, PVIN2, PVIN3,
and PVIN4)
90
2.010
SHUTDOWN CURRENT (µA)
85
2.005
2.000
1.995
VIN = 3.3V
VIN = 5V
VIN = 6V
80
75
70
65
60
55
50
1.990
–50
–20
10
40
70
100
130
TEMPERATURE (°C)
Figure 12. 2.0 V Reference Voltage Accuracy vs. Temperature
40
–50
–20
10
40
70
TEMPERATURE (°C)
100
130
15496-015
45
15496-012
REFERENCE VOLTAGE ACCURACY (V)
0
15496-014
20
15496-011
EFFICIENCY (%)
80
Figure 15. Shutdown Current vs. Temperature (EN1/ENALL, EN2/DL12,
EN3/UV, and EN4/DL34 Low)
Rev. A | Page 11 of 34
ADP5014
Data Sheet
3.0
2.9
UVLO THRESHOLD (V)
2.8
1
2.7
2.6
2.5
2.4
2.3
2
2.1
RISING
FALLING
–20
10
40
70
100
130
TEMPERATURE (°C)
15496-016
2.0
–50
CH1 10mV
B
W
CH2 2.00V
M400ns
T 25.60%
A CH2
2.96V
15496-019
2.2
Figure 19. Steady State Waveform at Heavy Load, VIN = 5 V, VOUT = 1.2 V,
IOUT = 3 A, fSW = 1.2 MHz, L = 0.8 µH, COUT = 47 µF × 2, FPWM Mode,
Channel 1 = VOUTX, Channel 2 = SWX
Figure 16. UVLO Threshold vs. Temperature
10
9
4A RATED
2A RATED
CURRENT LIMIT (A)
8
1
7
6
5
4
3
2
–20
10
40
70
100
130
TEMPERATURE (°C)
CH1 50mV
B
W
CH4 2.00A Ω
M100µs
T 25.60%
A CH2
2.96A
15496-020
1
–50
15496-017
2
Figure 20. Channel 1/Channel 2 Load Transient, 0.5 A to 3.5 A, VIN = 5 V,
VOUT = 1.2 V, fSW = 1.2 MHz, L = 0.8 µH, COUT = 47 µF × 2, Channel 1 = VOUTX,
Channel 2 = IOUTX
Figure 17. Channel 1/Channel 2 Current Limit vs. Temperature
4
2A RATED
1A RATED
2
3
1
–50
–20
10
40
70
100
130
TEMPERATURE (°C)
Figure 18. Channel 3/Channel 4 Current Limit vs. Temperature
CH1 50mV
CH3 2A Ω
B
W
CH4 2.00A Ω
M 100µs
T 29.60%
A CH3
4.12A
15496-021
4
15496-018
CURRENT LIMIT (V)
1
3
Figure 21. Load Transient, Channel 1/Channel 2 Parallel Output, 1 A to 6 A,
VIN = 5 V, VOUT = 1.2 V, fSW = 1.2 MHz, L = 0.8 µH, COUT = 47 µF × 4, Channel 1 = VOUT,
Channel 3 = IL1, Channel 4 = IL2
Rev. A | Page 12 of 34
Data Sheet
ADP5014
1
1
2
2
3
3
CH1 1.00V
CH3 2.00V
B
W
B
W
CH2 2.00V
CH4 2.00V
B
B
W
W
M 4.00ms
T 24.20%
A CH1
820mV
CH1 5.00V
CH3 5.00V
Figure 22. Startup for All Channels Under Sequence Enable Mode,
Channel 1 = VOUT1, Channel 2 = VOUT2, Channel 3 = VOUT3, Channel 4 = VOUT4
B
B
CH2 500mV
CH4 5.00A Ω
W
W
B
B
W
W
M 20.0ms
T 42.8%
A CH2
780mV
15496-025
4
15496-022
4
Figure 25. Channel 1 Shutdown with Active Output Discharge, VIN = 5 V, VOUT =
1.2 V, fSW = 1.2 MHz, L = 0.8 µH, COUT = 47 µF × 2, Channel 1 = EN1/ENALL,
Channel 2 = VOUT1, Channel 3 = PWRGD, Channel 4 = IOUT1
1
1
2
2
3
CH1 1.00V
CH3 2.00V
B
B
W
W
CH2 2.00V
CH4 2.00V
B
W
B
W
M 10.0ms
T 72.00%
A CH1
780mV
CH1 500mV
Figure 23. Shutdown for All Channels Under Sequence Enable Mode,
Channel 1 = VOUT1, Channel 2 = VOUT2, Channel 3 = VOUT3, Channel 4 = VOUT4
B
W
CH2 5.00V
CH4 5.00A Ω
B
W
M 10.0ms A CH1
T 25.60%
520mV
15496-026
4
15496-023
4
Figure 26. Short-Circuit Protection Entry, VIN = 5 V, VOUT = 1.2 V, fSW = 1.2 MHz,
L = 0.8 µH, COUT = 47 µF × 2, Channel 1 = VOUTX, Channel 2 = SWX,
Channel 4 = ILX
1
1
2
2
3
4
B
B
W
W
CH2 500mV BW M 1.00ms A CH2
CH4 5.00A Ω BW T 42.80%
780mV
Figure 24. Channel 1 Startup with Full Load, VIN = 5 V, VOUT = 1.2 V,
Channel 1 = EN1/ENALL, Channel 2 = VOUT1, Channel 3 = PWRGD,
Channel 4 = IOUT1
CH1 500mV
B
W
CH2 5.00V
CH4 5.00A Ω BW
M10.0ms
T 80.60%
A CH1
1.01V
15496-027
CH1 5.00V
CH3 5.00V
15496-024
4
Figure 27. Short-Circuit Protection Recovery, VIN = 5 V, VOUT = 1.2 V, fSW = 1.2 MHz,
L = 0.8 µH, COUT = 47 µF × 2, Channel 1 = VOUTX, Channel 2 = SWX,
Channel 4 = ILX
Rev. A | Page 13 of 34
ADP5014
Data Sheet
THEORY OF OPERATION
BUCK REGULATOR OPERATIONAL MODES
PWM Mode
In PWM mode, the buck regulators in the ADP5014 operate at
a fixed frequency; this frequency is set by an internal oscillator
that is programmed by the RT pin. At the start of each
oscillator cycle, the high-side MOSFET switch turns on and sends
a positive voltage across the inductor. The inductor current
increases until the current sense signal exceeds the peak
inductor current threshold that turns off the high-side
MOSFET switch. This threshold is set by the error amplifier
output. During the high-side MOSFET off time, the inductor
current decreases through the low-side MOSFET switch until
the next oscillator clock pulse starts a new cycle. The buck
regulators in the ADP5014 regulate the output voltage by
adjusting the peak inductor current threshold.
PSM Mode
To achieve higher efficiency, the buck regulators in the
ADP5014 smoothly transition to variable frequency PSM mode
operation when the output load falls below the PSM current
threshold. When the output voltage falls below regulation, the
buck regulator enters PWM mode for a few oscillator cycles
until the voltage increases to within regulation. During the idle
time between bursts, the MOSFET switch turns off, and the
output capacitor supplies all the output current.
The PSM mode comparator monitors the internal compensation
node, which represents the peak inductor current information.
The average PSM mode current threshold depends on the input
voltage (VIN), the output voltage (VOUT), the inductor, and the
output capacitor. Because the output voltage occasionally falls
below regulation and then recovers, the output voltage ripple in
PSM mode is larger than the ripple in the forced PWM mode of
operation under light load conditions.
FPWM and Automatic PWM/PSM Modes
The buck regulators can be configured to always operate in FPWM
mode using the CFG2 configuration pin. In forced PWM mode,
the regulator continues to operate at a fixed frequency even when
the output current is below the PWM/PSM threshold. In PWM
mode, the efficiency is lower compared to PSM mode under light
load conditions. The low-side MOSFET remains on when the
inductor current falls to less than 0 A, causing the ADP5014 to
enter continuous conduction mode (CCM).
operation; in PSM mode, the regulator operates with a reduced
switching frequency to maintain high efficiency. The low-side
MOSFET turns off when the output current reaches 0 A, causing
the regulator to operate in discontinuous mode (DCM).
Use the CFG2 pin to configure the operational mode of all four
buck regulators to operate in PWM mode or automatic
PWM/PSM mode.
LOW NOISE ARCHITECTURE
Traditional dc-to-dc or linear regulator output noise is typically
proportional to the output voltage setting. The ADP5014 optimizes
many analog blocks to achieve lower output noise at low frequency
range. The unity-gain voltage reference structure also makes its
output noise independent from the output voltage setting when
VOUT setting is less than VREF voltage.
The low noise buck regulator enables the device to power up noise
sensitive signal chain products directly with excellent output noise
performance, ~25 μV rms from 10 Hz to 100 kHz, which is similar
or even better than traditional low dropout regulators (LDOs).
The additional LC filter is still required because the fundamental
switching output ripple and its harmonic affects signal chain
performance and likely generates unexpected spurs. This
additional LC filter is typically relatively small due to the high
switching frequency operation of the buck regulator in the
ADP5014.
INTERNAL REFERENCE (VREF)
The ADP5014 provides an accurate, low noise, 2.0 V reference
voltage. One 0.47 μF ceramic capacitor must be connected
between VREF and ground. A larger value of capacitance provides
better noise suppression.
The VREF reference circuitry is mainly designed for internal use
and has very limited output load capacity ( VREF
Rev. A | Page 22 of 34
(1)
Data Sheet
ADP5014
The maximum output voltage for a given input voltage and
switching frequency is limited by the minimum off time or the
maximum duty cycle. The minimum off time for each channel
is 50 ns (typical).
The maximum output voltage for a given input voltage and
switching frequency is calculated using the following equation:
VOUT_MAX = VIN × (1 − tMIN_OFF × fSW) − (RDSON1 − RDSON2) ×
IOUT_MAX × (1 − tMIN_OFF × fSW) − (RDSON2 + RL) × IOUT_MAX (2)
where:
VOUT_MAX is the maximum output voltage.
tMIN_OFF is the minimum off time.
fSW is the switching frequency.
RDSON1 is the high-side MOSFET on resistance.
RDSON2 is the low-side MOSFET on resistance.
IOUT_MAX is the maximum output current.
RL is the resistance of the output inductor.
INDUCTOR SELECTION
The inductor value is determined by the operating frequency,
input voltage, output voltage, and inductor ripple current. Using
a small inductor yields faster transient response but degrades
efficiency due to the larger inductor ripple current. Using a large
inductor value yields a smaller ripple current and better efficiency,
but results in slower transient response. Therefore, a trade-off
must be made between the transient response and efficiency. As
a guideline, the inductor ripple current, ΔIL, is typically set to a
value from 30% to 40% of the maximum load current. The
inductor value is calculated using the following equation:
L = [(VIN − VOUT) × D]/(ΔIL × fSW)
As shown in Equation 1 and Equation 2, reducing the switching
frequency eases the minimum on time and off time limitations.
CURRENT-LIMIT SETTING
The ADP5014 has two selectable current-limit thresholds for
each channel. Ensure that the selected current-limit value is
larger than the peak current of the inductor, IPEAK. See Table 6
for the current-limit configuration for each channel.
SOFT START SETTING
The buck regulators in the ADP5014 include soft start circuitry
that ramps the output voltage in a controlled manner during
startup, thereby limiting the inrush current. To set the soft start
time to a value of 2 ms or 16 ms, connect a resistor from the
CFG2 pin to the ground (see the Soft Start section).
where:
VIN is the input voltage.
VOUT is the output voltage.
D is the duty cycle (D = VOUT/VIN).
ΔIL is the inductor ripple current.
fSW is the switching frequency.
The ADP5014 has internal slope compensation in the current
loop to prevent subharmonic oscillations when the duty cycle is
greater than 50%.The inductor peak current is calculated using
the following equation:
IPEAK = IOUT + (ΔIL/2)
The saturation current of the inductor must be larger than the
peak inductor current. For ferrite core inductors with a fast
saturation characteristic, the saturation current rating of the
inductor are higher than the current-limit threshold of the buck
regulator to prevent the inductor from becoming saturated.
The rms current of the inductor is calculated using the
following equation:
I RMS = I OUT 2 +
∆I L 2
12
Shielded ferrite core materials are recommended for low core
loss and low electromagnetic interference (EMI). Table 11 lists
the recommended inductors.
Table 11. Recommended Inductors
Vendor
Coilcraft
TOKO
Wurth
Part No.
XAL4020-601
XAL4020-102
XAL4020-152
XAL4020-222
DFE252012P-R68M
DFE252012P-1R0P
DFE252012P-1R5P
DFE252012P-2R2P
744383560068
74438356010
74438356015
74438356022
Value (µH)
0.6
1.0
1.5
2.2
0.68
1.0
1.5
2.2
0.68
1
1.5
2.2
ISAT (A)
10.4
8.7
7.1
5.6
5.3
4.8
3.9
3.4
9.4
9.0
7.8
6.2
Rev. A | Page 23 of 34
IRMS (A)
11.7
9.6
7.5
5.5
4.1
3.8
3.0
2.6
8.2
7.2
5.8
4.7
DCR (mΩ)
9.5
13.3
21.5
35.2
30
35
50
70
7.5
12
15
29
Size (mm)
4×4
4×4
4×4
4×4
2.5 × 2.0
2.5 × 2.0
2.5 × 2.0
2.5 × 2.0
4.1 × 4.1
4.1 × 4.1
4.1 × 4.1
4.1 × 4.1
ADP5014
Data Sheet
OUTPUT CAPACITOR SELECTION
INPUT CAPACITOR SELECTION
The selected output capacitor affects both the output voltage
ripple and the loop dynamics of the regulator. For example, during
load step transients on the output, when the load is suddenly
increased, the output capacitor supplies the load until the
control loop can ramp up the inductor current, causing an
undershoot of the output voltage.
The input decoupling capacitor attenuates high frequency noise
on the input and acts as an energy reservoir. This capacitor is a
ceramic capacitor and must be placed close to the PVINx pins.
The loop composed of the input capacitor, the high-side MOSFET,
and the low-side MOSFET must be kept as small as possible.
The voltage rating of the input capacitor must be greater than
the maximum input voltage. The rms current rating of the
input capacitor (ICIN_rms)is larger than the following equation:
The output capacitance required to meet the voltage droop
requirement (COUT_UV) is calculated using the following equation:
C OUT _ UV
2 VIN VOUT VOUT _ UV
where D is the duty cycle (D = VOUT/VIN).
PROGRAMMING THE UVLO INPUT
where:
KUV is a factor (typically set to 2).
ΔISTEP is the load step.
ΔVOUT_UV is the allowable undershoot on the output voltage.
The precision enable input can be used to program the UVLO
threshold of the input voltage, as shown in Figure 32.
Another example of the effect of the output capacitor on the loop
dynamics of the regulator is when the load is suddenly removed
from the output. The energy stored in the inductor rushes into
the output capacitor, causing an overshoot of the output voltage.
The output capacitance required to meet the overshoot
requirement (COUT_UV) is calculated using the following equation:
C OUT _ OV
K OV I STEP 2 L
V
OUT
VOUT_OV 2 VOUT 2
where:
KOV is a factor (typically set to 2).
ΔISTEP is the load step.
ΔVOUT_OV is the allowable overshoot on the output voltage.
R ESR
The precision turn on threshold is 0.6 V. Use the following
equations to calculate RTOP_EN and RBOT_EN:
RTOP_EN = (0.57 V × VIN_RISING − 0.6 × VIN_FALLING)/(0.57 V ×
4 μA − 0.6 × 1 μA)
RBOT_EN = (0.6 V × RTOP_EN)/(VIN_RISING – RTOP_EN × 4 μA − 0.6 V)
where:
RTOP_EN is the resistor from PVINx to ENx.
VIN_RISING is the VIN rising threshold.
VIN_FALLING is the VIN falling threshold.
RBOT_EN is the resistor from ENx to ground.
COMPENSATION COMPONENTS DESIGN
The output voltage ripple is determined by the equivalent series
resistance (ESR) of the output capacitor and its capacitance
value. Use the following equation to select a capacitor that can
meet the output ripple requirements:
COUT _ RIPPLE
For the peak current-mode control architecture, the power stage
can be simplified as a voltage controlled current source that
supplies current to the output capacitor and load resistor. The
simplified loop is composed of one domain pole and a zero
contributed by the ESR of the output capacitor. The control to
output transfer function (Gvd) is shown in the following equations:
I L
8 f SW VOUT _ RIPPLE
G vd (s)
VOUT _ RIPPLE
VOUT (s )
AVI
VCOMP (s)
I L
where:
ΔVOUT_RIPPLE is the allowable output voltage ripple.
RESR is the ESR of the output capacitor.
fz
Select the largest output capacitance given by COUT_UV, COUT_OV,
and COUT_RIPPLE to meet both load transient and output ripple
requirements.
The selected output capacitor voltage rating must be greater
than the output voltage. The minimum rms current rating of
the output capacitor (ICOUT_rms) is determined by the following
equation:
ICOUT_rms =
D (1 D )
ICIN_rms = IOUT ×
K UV I STEP 2 L
I L
12
fp
s
1
2 f z
R
s
1
2
f
p
1
2 RESR COUT
1
2 R RESR COUT
where:
AVI = 16.67A/V for Channel 1 or Channel 2, and 8.33 A/V for
Channel 3 or Channel 4.
R is the load resistance.
fz is the frequency of the zero.
COUT is the output capacitance.
RESR is the equivalent series resistance of the output capacitor.
fp is the frequency of the pole.
Rev. A | Page 24 of 34
Data Sheet
ADP5014
Power Switch Conduction Loss (PCOND)
The ADP5014 uses a transconductance amplifier as the error
amplifier to compensate the system. Figure 40 shows the
simplified peak current-mode control small signal circuit.
Power switch conduction losses are caused by the flow of output
current through both the high-side and low-side power switches,
each of which has on resistance (RDS(ON).
VOUT
V OUT
Use the following equation to estimate the power switch
conduction loss:
RTOP
VCOMP
–
+
gm
AVI
COUT
RBOT
PCOND = (RDS(ON)_HS × D + RDS(ON)_LS × (1 − D)) × IOUT2
R
+
RC
CCP
–
RESR
15496-041
CC
Figure 40. Simplified Peak Current-Mode Control Small Signal Circuit
The compensation components, RC and CC, contribute a zero
and the optional CCP and RC contribute an optional pole.
The closed-loop transfer (TV(s)) equation is as follows:
TV (s) =
RBOT
×
−gm
×
1 + RC × CC × s
× Gvd(s)
R ×C ×C
C
C
CP
×s
s× 1+
CC + CCP
The following procedure shows how to select the compensation
components—RC, CC, and CCP,—for ceramic output capacitor
applications.
1.
2.
RBOT + RTOP
Determine the cross frequency (fC). Generally, fC is between
fSW/12 and fSW/6.
RC can be calculated using the following equation:
RC =
3.
2 × π × VOUT × COUT × f C
VSETx × g m × AVI
Place the compensation zero at the domain pole (fP).
CC can be determined as follows:
CC =
4.
CC + CCP
(R + RESR ) × COUT
RC
CCP is optional. It can be used to cancel the zero caused by
the ESR of the output capacitor.
CCP =
RESR × COUT
where:
RDS(ON)_HS is the high-side MOSFET on resistance.
RDS(ON)_LS is the low-side MOSFET on resistance.
D is the duty cycle (D = VOUT/VIN).
Switching Loss (PSW)
Switching losses are associated with the current drawn by the
driver to turn the power devices on and off at the switching
frequency. Each time a power device gate is turned on or off,
the driver transfers a charge from the input supply to the gate,
and then from the gate to ground. Use the following equation to
estimate the switching loss:
PSW = (CGATE_HS + CGATE_LS) × VIN2 × fSW
where:
CGATE_HS is the gate capacitance of the high-side switch.
CGATE_LS is the gate capacitance of the low-side switch.
fSW is the switching frequency.
Transition Loss (PTRAN)
Transition losses occur because the high-side switch cannot
turn on or off instantaneously. During a switch node transition,
the power switch provides all the inductor current. The source
to drain voltage of the power switch is half the input voltage,
resulting in power loss. Transition losses increase with both
load and input voltage and occur twice for each switching cycle.
Use the following equation to estimate the transition loss:
PTRAN = 0.5 × VIN × IOUT × (tR + tF) × fSW
where:
tR is the rise time of the switch node.
tF is the fall time of the switch node.
Thermal Shutdown
RC
POWER DISSIPATION
The total power dissipation in the ADP5014 (PD) simplifies to
PD = PBUCK1 + PBUCK2 + PBUCK3 + PBUCK4
Buck Regulator Power Dissipation
The power dissipation (PLOSS) for each buck regulator includes
power switch conductive losses (PCOND), switch losses (PSW), and
transition losses (PTRAN). Other sources of power dissipation exist,
but these sources are generally less significant at the high output
currents of the application thermal limit.
When the ADP5014 operates under a heavy load in a high
ambient temperature, the power loss can cause the junction
temperature to exceed the maximum junction temperature of
125°C. If the junction temperature exceeds 150°C, the regulator
enters thermal shutdown and recovers when the junction
temperature falls below 135°C.
Use the following equation to estimate the power dissipation of
the buck regulator:
PLOSS = PCOND + PSW + PTRAN
Rev. A | Page 25 of 34
ADP5014
Data Sheet
JUNCTION TEMPERATURE
The junction temperature of the die is the sum of the ambient
temperature of the environment and the temperature rise of the
package due to power dissipation, as shown in the following
equation:
TJ = TA + TR
where:
TJ is the junction temperature.
TA is the ambient temperature.
TR is the rise in temperature of the package due to power
dissipation.
The rise in temperature of the package is directly proportional
to the power dissipation in the package. The proportionality
constant for this relationship is the thermal resistance from the
junction of the die to the ambient temperature, as shown in the
following equation:
ambient temperature of the package (see Table 4). Thermal
performance is directly linked to PCB design and operating
environment. Careful attention to PCB thermal design is
required.
PD is the power dissipation in the package.An important factor
to consider is that the thermal resistance value is based on a
4-layer, 4 inch × 3 inch PCB with 2.5 oz of copper, as specified
in the JEDEC standard, whereas real world applications can use
PCBs with different dimensions and a different number of
layers.
It is important to maximize the amount of copper used to
remove heat from the device. Copper exposed to air dissipates
heat better than copper used in the inner layers. The exposed
pad is connected to the ground plane with several vias.
TR = θJA × PD
where:
TR is the rise in temperature of the package.
θJA is the thermal resistance from the junction of the die to the
Rev. A | Page 26 of 34
Data Sheet
ADP5014
DESIGN EXAMPLES
This section provides an example of the step by step design
procedures and the external components required for Channel 1.
Table 12 lists the design requirements for this example.
To set the output voltage to 1.2 V, choose the following resistor
values: R1 = 6.65 kΩ, and R2 = 10 kΩ.
Table 12. Example Design Requirements for Channel 1
The CFG1 pin can be used to program the load output
capability and parallel operation for all channels. For this
example, choose RCFG1 = 0 kΩ. For more information, see the
configuration in Function Configurations (CFG1 and CFG2).
Parameter
Input Voltage
Output Voltage
Output Current
Output Ripple
Load Transient
Specification
VPVIN1 = 5 V ± 5%
VOUT1 = 1.2 V
IOUT1 = 4 A
ΔVOUT1_RIPPLE = 5 mV in CCM mode
±5%, at 20% to 80% load transient, 1 A/µs
SETTING THE CONFIGUATIONS (CFG1 AND CFG2)
Although this example shows step by step design procedures for
Channel 1, the procedures apply to all other buck regulator
channels (Channel 2 to Channel 4).
The CFG2 pin can be used to program the operation mode
(FPWM or PWM/PSM mode), the enable mode (manual mode
or sequence mode), the timer (×1 or ×8), and GPIO functionalities
(PWRGD, SYNC-IN, CLK-OUT, UVO) for all channels. For
this example, choose RCFG2 = 0 kΩ. For more information, see the
configuration in Function Configurations (CFG1 and CFG2).
SETTING THE SWITCHING FREQUENCY
SELECTING THE INDUCTOR
The first step when setting the switching frequency is to determine
the switching frequency for the ADP5014 design. In general,
higher switching frequencies produce a smaller solution size
due to the lower component values required, whereas lower
switching frequencies result in higher conversion efficiency due
to lower switching losses.
The peak-to-peak inductor ripple current, ΔIL, is set to 30% of
the maximum output current. Use the following equation to
estimate the value of the inductor (L):
The switching frequency of the ADP5014 can be set to a value
from 500 kHz to 2.5 MHz by connecting a resistor from the RT
pin to ground. The selected resistor allows users to make
decisions based on the trade-off between efficiency and solution
size. For more information, see the Oscillator section.
where:
VIN = 5 V.
VOUT = 1.2 V.
D is the duty cycle (D = VOUT/VIN = 0.24).
ΔIL = 30% × 4 A = 1.2 A.
fSW = 1.2 MHz.
However, the highest supported switching frequency must be
assessed by checking the voltage conversion limitations
enforced by the minimum on time and the minimum off time
(see the Voltage Conversion Limitations section).
∆I L × f SW
The resulting value for L is 0.63 µH. The closest standard
inductor value is 0.8 µH; therefore, the inductor ripple current,
ΔIL1, is 0.95 A.
IPEAK = IOUT + (ΔIL/2)
The calculated peak current for the inductor is 4.48 A.
The rms current of the inductor can be calculated using the
following equation:
RRT (kΩ) = (100,000/fSW (kHz))
According to this equation, select standard resistor RRT =
82.5 kΩ.
I RMS = I OUT 2 +
SETTING THE OUTPUT VOLTAGE
Because the desired output voltage setting is less than VREF
voltage, use the resistor divider from the accurate internal
VREF reference voltage to set the desired output voltage and
directly tie the feedback pin (FB1) to the output (see Figure 38).
Select a 10 kΩ bottom resistor (R2) and then calculate the top
resistor using the following equation:
where:
VOUT is the output voltage.
VREF is 2.0 V for Channel 1 to Channel 4.
(VIN − VOUT ) × D
The inductor peak current is calculated using the following
equation:
In this design example, a switching frequency of 1.2 MHz
achieves a good combination of small solution size and high
conversion efficiency. To set the switching frequency to
1.2 MHz, use the following equation to calculate the resistor
value, RRT:
R1 = R2 × ((VREF − VOUT)/VOUT)
L=
∆I L 2
12
The rms current of the inductor is approximately 4.01 A.
Therefore, an inductor with a minimum rms current rating of
4.01 A and a minimum saturation current rating of 4.48 A is
required. However, to prevent the inductor from reaching its
saturation point in current-limit conditions, it is recommended
that the inductor saturation current be higher than the maximum
peak current limit, typically 6 A, for reliable operation.
Based on these requirements and recommendations, the
COILCRAFT XAL5030-801MEB, with a direct current
resistance (DCR) of 5.14 mΩ, is selected for this design.
Rev. A | Page 27 of 34
Data Sheet
C OUT _ RIPPLE =
R ESR =
8 × f SW
∆I L
× ∆VOUT _ RIPPLE
∆VOUT _ RIPPLE
120
120
100
100
80
80
60
60
40
40
20
20
0
0
–20
–20
–40
–40
–60
–60
–80
–80
∆I L
–100
The calculated capacitance, COUT_RIPPLE, is 19.8 µF, and the
calculated RESR is 5 mΩ.
–120
1k
C OUT _ OV =
10k
100k
1M
–120
FREQUENCY (Hz)
Figure 41. Bode Plot for 1.2 V Output
To meet the ±5% overshoot and undershoot requirements,
use the following equations to calculate the capacitance:
C OUT _ UV =
–100
CROSS FREQUENCY = 132kHz
PHASE MARGIN = 56°
15496-042
The output capacitor must meet the output voltage ripple and
load transient requirements. To meet the output voltage ripple
requirement, use the following equation to calculate the ESR
and capacitance:
MAGNITUDE (dB)
SELECTING THE OUTPUT CAPACITOR
PHASE (Degrees)
ADP5014
K UV × ∆I STEP 2 × L
2 × (V IN − VOUT ) × ∆VOUT _ UV
1
K OV × ∆I STEP 2 × L
(VOUT + ∆VOUT_OV ) 2
− VOUT 2
For estimation purposes, use KOV = KUV = 2; therefore,
COUT_OV = 62.4 µF and COUT_UV = 20.2 µF.
The ESR of the output capacitor must be less than 5 mΩ,
and the output capacitance must be greater than 62.4 µF. It is
recommended that two ceramic capacitors be used (47 µF, X5R,
6.3 V), such as the GRM21BR60J476ME15 from Murata with
an ESR of 2 mΩ.
For better load transient and stability performance, set the cross
frequency, fC, to fSW/10. In this example, fSW is set to 1.2 MHz;
therefore, fC is set to 120 kHz.
For the 1.2 V output rail, the 47 μF ceramic output capacitor has
a derated value of 32 µF.
2 × π × 1.2 V × 2 × 32 µ F ×120 kHz
CC =
CCP =
= 3.62 k Ω
1.2 V × 800 µ s × 16.67 A/V
(0.3 Ω + 0.001 Ω ) × 2 × 32 µ F
3.62 k Ω
0.001 Ω × 2 × 32 µ F
3.62 k Ω
B
W
CH4 2A Ω
M100µs
T
25.8%
A CH4
2.16A
15496-043
CH1 5.00mV
Figure 42. Selecting the Input Capacitor
DESIGNING THE COMPENSATION NETWORK
RC =
4
= 5.32 nF
= 17.7 pF
Choose standard components: RC = 3.57 kΩ and CC = 5.6 nF.
CCP is optional.
Figure 41 shows the bode plot for the 1.2 V output rail. The
cross frequency is 132 kHz, and the phase margin is 56°. The
load transient waveform is shown in Figure 42.
For the input capacitor, select a ceramic capacitor with a
minimum value of 10 µF. The input capacitor is placed close to
the PVINx pin. In this example, one ceramic capacitor of 10 µF,
X5R, 16 V is recommended.
LOW NOISE OUTPUT DESIGN
The ADP5014 optimizes many analog blocks and uses new unitygain reference architecture to achieve lower output noise in lowfrequency range. When the system design needs the low noise
output of ADP5014 , the device enables powering up the signal
chain products directly without LDOs. In this scenario, adding
an additional LC filter is highly recommended after the main
LC filter to filter the fundamental switching ripple and its
harmonic. This is because the switching ripples may generate
unexpected noise spurs for the noises sensitive signal chain
devices. Because this additional inductor filter may generate
voltage drop at the load, the inductor with small DCR is
recommended to minimize the voltage drop, especially for high
current applications.
Figure 43 and Figure 44 show the ADP5014 noise spectral
density measurement from a 10 Hz to 10 MHz frequency range
and integrated rms noise from a 10 Hz to 1 MHz frequency
range, compared to the ADP1740 as another traditional, 2 A,
low noise linear regulator.
Rev. A | Page 28 of 34
Data Sheet
50
ADP5014
ADP1740
45
1k
ADP5014
ADP1740
40
35
NOISE RMS (µV)
NOISE SPECTRAL DENSITY (nV/√Hz)
10k
ADP5014
100
10
30
25
20
15
1
10
1k
10k
100k
FREQUENCY (Hz)
1M
10M
0
10
15496-044
100
100
1k
10k
FREQUENCY (Hz)
Figure 43. ADP5014 Noise Spectral Density Measurement, VIN = 5 V, VOUT1 =
1.3 V, IOUT1 = 0.5 A, fSW = 1.2 MHz, L1 = 0.8 μH, COUT = 47 μF × 3, LFILTER = 1 μH,
CFILTER = 22 μF × 2
100k
1M
15496-045
5
0.1
10
Figure 44. ADP5014 Integrated RMS Noise, VIN = 5 V, VOUT1 = 1.3 V, IOUT1 = 0.5 A,
fSW = 1.2 MHz, L1 = 0.8 μH, COUT = 47 μF × 3, LFILTER = 1 μH, CFILTER = 22 μF × 2
Rev. A | Page 29 of 34
ADP5014
Data Sheet
•
Good circuit board layout is essential to obtain the best
performance from the ADP5014 (see Figure 45). Poor layout can
affect the regulation and stability of the device, as well as the
EMI and electromagnetic compatibility (EMC) performance.
Refer to the following guidelines for a good PCB layout.
C0402
2
COMP3
SW1
29
3
PVIN3
SW1
28
4
SW3
PGND1
27
5
PGND3
PGND1
26
6
PGND4
PGND2
25
7
SW4
PGND2
24
8
PVIN4
SW2
23
9
COMP4
SW2
22
PVIN2
21
ADP5014
6mm × 6mm
10µF
6.3V/XR5
0603
20
R0402
Figure 45. Typical PCB Layout for the ADP5014
Rev. A | Page 30 of 34
VOUT1
47µF
6.3V/XR5
0805
C0402
R0402
R0402
R0402
C0402
R0402
47µF
6.5V/XR5
0805
47µF
6.3V/XR5
0805
COMP2 PVIN2
19
FB2
18
17
EN2/ EN1/
DL12 ENALL
16
CFG1
15
14
13
EN4/
DL34 EN3/UV CFG2
12
10 FB4
GPIO
0.8µH
4mm × 4mm
10µF
6.3V/XR5
0603
R0402
FB1 COMP1 PVIN1
PVIN1 30
FB3
0.8µH
4mm × 4mm
AVIN
31
RT
32
34
R0402
35
36
37
38
39
40
0.1µF
6.3V/XR5
0402
R0402
33
R0402
1
11
R0402
•
R0402
0.1µF
6.3V/XR5
0402
R0402
R0402
R0402
R0402
10µF
6.3V/XR5
0603
47µF
6.3V/XR5
0603
•
•
•
•
R0402
VSET4 VSET3 VREF VSET2 VSET1
47µF
6.3V/XR5
0603
10µF
6.3V/XR5
0603
•
1.5µH
•
1.5µH
•
VOUT3
•
•
Place the input capacitor, inductor, and output capacitor
close to the IC.
Use short, thick traces to connect the input capacitors
to the PVINx pins, and use dedicated power ground to
connect the input and output capacitor grounds to
minimize the connection length.
Use several high current vias, if required, to connect
PVINx, PGNDx, or SWx to other power planes.
Use short, thick traces to connect the inductors to the
SWx pins and the output capacitors.
Ensure that the high current loop traces are as short and wide
as possible.
VOUT4
•
Maximize the amount of ground metal for the exposed pad,
and use as many vias as possible on the component side to
improve thermal dissipation.
Use a ground plane with several vias connecting to the
component side ground to further reduce noise
interference on sensitive circuit nodes.
Place the decoupling capacitors close to the VREF pin.
Place the RC filter close to the AVIN pin.
Place the frequency setting resistor close to the RT pin.
Place the VREF resistor divider close to the VSETx and the
feedback resistor divider close to the FBx pin. In addition,
keep the VSETx and FBx traces away from the high current
traces and the switch node to avoid noise pickup.
Use size 0402 or 0603 resistors and capacitors to achieve
the smallest possible footprint solution on boards where
space is limited.
VOUT2
47µF
6.3V/XR5
0805
15496-046
PCB LAYOUT RECOMMENDATIONS
Data Sheet
ADP5014
TYPICAL APPLICATION CIRCUITS
ADP5014
VREF 0.47µF
RT
82.5kΩ
OSC
REF
VREF
EN1/ENALL
CFG1
0Ω
EN2/DL12
0Ω
EN3/UV
LOGIC DECODER
EN4/DL34
GPIO
26.1kΩ
AVIN
5.0V
CFG2 31.6kΩ
FB1
PVIN1
C1
10µF
C2
1µF
PVIN1
SW1
L1
CH 1
BUCK
(2A/4A)
VREF
13.3kΩ VSET1
VOUT1
0.8µH
SW1
PGND1
1.2V/4A
C4
47µF
C3
47µF
VCORE
C5
47µF
20kΩ
COMP1
FPGA
PGND1
20kΩ
10nF 4.32kΩ
FB2
PVIN2
4.99kΩ
CH 2
BUCK
(2A/4A)
PVIN2
VREF VSET2
L2
SW2
PGND2
COMP2
0.8µH
VOUT2
C7
47µF
2.5V/2A
C8
47µF
PVIN3
SW3
C9
10µF
FB3
CH 3
BUCK
(1A/2A)
6.65kΩ VSET3
L3
1.5µH
VOUT3
BANK 0
BANK 1
BANK 2
1.5V/2A
I/Os
BANK 3
C10
47µF
DDR
TERM. LDO
PGND3
20kΩ
I/Os
PGND2
10nF 4.32kΩ
VREF
AUXILIARY
VOLTAGE
SW2
C6
10µF
COMP3
DDR3 MEMORY
10nF 4.32kΩ
PVIN4
SW4
C11
10µF
L4
1.5µH
VREF
FB4
CH 4
BUCK
(1A/2A)
VSET4
13kΩ
PGND4
COMP4
3.3V/2A
FLASH MEMORY
C12
47µF
20kΩ
6.04kΩ
AGND
EXPOSED PAD
ENALL
2ms
36ms
1.2V
2.5V/1.5V
3.3V
6ms
24ms
12ms
12ms
Figure 46. Typical Field Programmable Gate Array (FPGA) Application, 1.2 MHz Switching Frequency, Sequence Enable Mode
Rev. A | Page 31 of 34
15496-047
10nF
VOUT4
ADP5014
Data Sheet
ADP5014
VREF 0.47µF
RT
82.5kΩ
OSC
REF
VREF
EN1/ENALL
CFG1
0Ω
EN2/DL12
17.8kΩ
EN3/UV
LOGIC DECODER
EN4/DL34
GPIO
56.2kΩ
AVIN
5.0V
CFG2 31.6kΩ
5.1kΩ
FB1
RF TRANSCEIVER
PVIN1
C1
10µF
C2
1µF
PVIN1
SW1
CH 1
BUCK
(2A/4A)
VREF
10.7kΩ VSET1
3.3nF
L1
1µH
L5
220nH
VOUT1
SW1
PGND1
1.3V/3000mA
1.3V ANALOG
C4
47µF
C3
47µF
C5
47µF
20kΩ
COMP1
C6
47µF
0.1Ω
1.3V VDD_JESD
PGND1
10nF 4.32kΩ
5.1kΩ
FB2
PVIN2
C7
10µF
SW2
CH 2
BUCK
(2A/4A)
PVIN2
VREF
10.7kΩ VSET2
3.3nF
L2
1µH
L6
220nH
VOUT2
SW2
PGND2
1.3V/1500mA
1.3V DIGITAL
C8
47µF
C9
47µF
C10
47µF
20kΩ
COMP2
C11
47µF
0.1Ω
PGND2
10nF 4.32kΩ
PVIN3
SW3
C12
10µF
VOUT3
3.3V/600mA
3.3V VDD_GPO
C13
47µF
FB3
CH 3
BUCK
(1A/2A)
VREF VSET3
L3
1.5µH
13kΩ
20kΩ
COMP3
PGND3
18nF 6.04kΩ
PVIN4
1.8V LVDS/CMOS
C14
10µF
2.21kΩ VSET4
SW4
COMP4
PGND4
VOUT4
L8
220nH
3.3nF
1.8V/600mA
1.8V TX
C15
47µF
FB4
20kΩ
15nF
L4
1.5µH
C16
47µF
5.1kΩ
C17
47µF
0.1Ω
4.32kΩ
AGND
EXPOSED PAD
ENALL
2ms
36ms
1.3V DIG
1.3V ANA
3.3V VDD/
1.8V TX
6ms
24ms
12ms
12ms
Figure 47. Typical RF Transceiver Application, 1.2 MHz Switching Frequency, Sequence Enable Mode
Rev. A | Page 32 of 34
15496-048
VREF
CH 4
BUCK
(1A/2A)
Data Sheet
ADP5014
FACTORY PROGRAMMABLE OPTIONS
FACTORY DEFAULT OPTIONS
Table 13 lists the factory default options programmed into the ADP5014 when the device is ordered (see the Ordering Guide). To order
the device with options other than the default options, contact your local Analog Devices sales or distribution representative.
Table 13. Factory Default Options
Option
Channel 1 Output Voltage
Channel 2 Output Voltage
Channel 3 Output Voltage
Channel 4 Output Voltage
PWRGD Pin Output
Output Discharge Function
Hiccup Detection
Default Value
Adjustable output
Adjustable output
Adjustable output
Adjustable output
Monitor all Channel 4 outputs (enabled by the CFG2 configuration)
Enabled for all four buck regulators
Hiccup protection enabled for overcurrent events
Rev. A | Page 33 of 34
ADP5014
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
0.30
0.23
0.18
40
31
1
30
0.50
BSC
4.45
4.30 SQ
4.25
EXPOSED
PAD
21
TOP VIEW
0.80
0.75
0.70
SIDE VIEW
PKG-003438
SEATING
PLANE
0.45
0.40
0.35
10
20
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
P IN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)
11
BOTTOM VIEW
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5
10-08-2018-A
PIN 1
INDICATOR
AREA
6.10
6.00 SQ
5.90
Figure 48. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm Body, and 0.75 mm Package Height
(CP-40-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADP5014ACPZ-R7
ADP5014-EVALZ
1
2
Temperature Range
−40°C to +125°C
Package Description
40-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Package Option 2
CP-40-10
Z = RoHS Compliant Part.
Table 13 lists the factory default options for the device. For a list of factory programmable options, see the Factory Programmable Options section. To order a device
with options other than the default values, contact your local Analog Devices sales or distribution representative.
©2017–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15496-0-8/19(A)
Rev. A | Page 34 of 34
