ADP5063CP-EVALZ

Linear LiFePO4 Battery Charger with Power Path and USB Compatibility in LFCSP ADP5063 Data Sheet FEATURES GENERAL DESCRIPTION Default charging termination voltage at 3.6 V Fully compatible with USB 3.0 and USB Battery Charging 1.2 Compliance Plan Specification Operating input voltage from 4 V to 6.7 V Tolerant input voltage from −0.5 V to +20 V (USB VBUS) Fully programmable via I2C Flexible digital control inputs Up to 2.1 A current from an ac charger in LDO mode Built-in current sensing and limiting As low as 55 mΩ battery isolation FET between battery and charger output Thermal regulation prevents overheating Compliant with JEITA1 and JEITA2 Li-Ion battery charging temperature specifications SYS_EN flag permits the system to be disabled until battery is at the minimum required level for guaranteed system start-up 4 mm × 4 mm LFCSP package The ADP5063 charger is fully compliant with USB 3.0 and the USB Battery Charging 1.2 Compliance Plan Specification, and enables charging via the mini USB VBUS pin from a wall charger, car charger, or USB host port. The ADP5063 operates from a 4 V to 6.7 V input voltage range but is tolerant of voltages up to 20 V, thereby alleviating concerns about USB bus spikes during disconnection or connection scenarios. The ADP5063 features an internal field effect transistor (FET) between the linear charger output and the battery. This permits battery isolation and, therefore, system powering under a dead battery or no battery scenario, which allows immediate system function upon connection to a USB power supply. Based on the type of USB source, which is detected by an external USB detection chip, the ADP5063 can be set to apply the correct current limit for optimal charging and USB compliance. The ADP5063 has three factory-programmable digital input/output pins that provide maximum flexibility for different systems. These digital input/output pins permit a combination of features, such as input current limits, charging enable and disable, charging current limits, and a dedicated interrupt output pin. APPLICATIONS Single cell lithium iron phosphate (LiFePO4) portable equipment Portable medical devices Portable instrumentation devices Portable consumer devices TYPICAL APPLICATION CIRCUIT ADP5063 VBUS PROGRAMMABLE C4 10µF ISO_Sx VINx CBP C1 100nF C3 22µF SCL SDA DIG_IO1 DIG_IO2 DIG_IO3 SYSTEM ISO_Bx CHARGER CONTROL BLOCK BAT_SNS + Li-Ion C2 22µF THR SYS_EN ILED AGND VLED 11593-001 AC OR USB Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADP5063 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Battery Isolation FET ................................................................. 21 Applications ....................................................................................... 1 Battery Detection ....................................................................... 21 General Description ......................................................................... 1 Battery Pack Temperature Sensing .......................................... 22 Typical Application Circuit ............................................................. 1 I2C Interface ................................................................................ 26 Revision History ............................................................................... 2 I2C Register Map......................................................................... 27 Specifications..................................................................................... 3 Register Bit Descriptions ........................................................... 28 Recommended Input and Output Capacitances ...................... 6 Applications Information .............................................................. 36 I C-Compatible Interface Timing Specifications ..................... 6 External Components ................................................................ 36 Absolute Maximum Ratings............................................................ 8 PCB Layout Guidelines.............................................................. 38 Thermal Resistance ...................................................................... 8 Power Dissipation and Thermal Considerations ....................... 39 ESD Caution .................................................................................. 8 Charger Power Dissipation ....................................................... 39 Pin Configuration and Function Descriptions ............................. 9 Junction Temperature ................................................................ 39 Typical Performance Characteristics ........................................... 10 Factory-Programmable Options .................................................. 40 Temperature Characteristics ..................................................... 12 Charger Options ......................................................................... 40 Typical Waveforms ..................................................................... 14 I2C Register Defaults .................................................................. 41 Theory of Operation ...................................................................... 15 Digital Input and Output Options ........................................... 41 Summary of Operation Modes ................................................. 15 Packaging and Ordering Information ......................................... 43 Introduction ................................................................................ 16 Outline Dimensions ................................................................... 43 Charger Modes............................................................................ 18 Ordering Guide .......................................................................... 43 2 Thermal Management ............................................................... 21 REVISION HISTORY 7/13—Revision 0: Initial Version Rev. 0 | Page 2 of 44 Data Sheet ADP5063 SPECIFICATIONS −40°C < TJ < +125°C, VVINx = 5.0 V, RHOT_RISE < RTHR < RCOLD_FALL, VBAT_SNS = 3.6 V, VISO_Bx = VBAT_SNS, CVINx = 10 µF, CISO_Sx = 22 µF, CISO_Bx = 22 µF, CCBP = 100 nF, all registers are at default values, unless otherwise noted. Table 1. Parameter GENERAL PARAMETERS Undervoltage Lockout Hysteresis Total Input Current VINx Current Consumption Battery Current Consumption Symbol Min Typ Max Unit Test Conditions/Comments VUVLO 2.25 50 74 114 2.35 100 92 2.5 150 100 150 300 V mV mA mA mA 425 470 500 900 1500 5 mA mA mA mA mA µA µA 0.9 mA Falling threshold, higher of VVINx or VBAT_SNS 1 Hysteresis, higher of VVINx or VBAT_SNS rising1 Nominal USB initialized current level 2 USB super speed USB enumerated current level (specification for China) USB enumerated current level Dedicated charger input Dedicated wall charger Charging or LDO mode DIS_LDO = high, TJ = −40°C to +85°C LDO mode, VISO_Sx > VBAT_SNS Standby, includes ISO_Sx pin leakage, VVINx = 0 V, TJ = −40°C to +85°C Standby, battery monitor active ILIM IQVIN IQVIN_SUSPEND IQBATT 2 1.0 20 0.5 CHARGER Fast Charge Current Constant Current (CC) Mode Fast Charge Current Accuracy Trickle Charge Current2 Weak Charge Current2, 3 Trickle to Weak Charge Threshold Dead Battery Hysteresis Weak Battery Threshold Weak to Fast Charge Threshold Battery Termination Voltage Termination Voltage Accuracy ICHG 1.8 750 −9 mA +9 % ICHG = 400 mA to 1300 mA, VISO_Bx = 3.3 V, TJ = 0°C to 115°C ITRK_DEAD ICHG_WEAK 16 20 ITRK_DEAD + ICHG 25 mA mA VTRK_DEAD ΔVTRK_DEAD 1.9 2.0 100 2.1 V mV VTRK_DEAD < VBAT_SNS < VWEAK2, 4 On BAT_SNS2 VWEAK ΔVWEAK VTRM 2.89 3.0 100 3.600 3.11 V mV V % % % V mA mA On BAT_SNS2, 4 mA mV V mA V mA ms IEND = 92.5 mA, TJ = 0°C to 115°C Relative to VTRM, BAT_SNS falling2 −0.6 −1.55 −1.7 Battery Overvoltage Threshold Charge Complete Current Charging Complete Current Threshold Accuracy VBATOV IEND Recharge Voltage Differential Battery Node Short Threshold Voltage2 Battery Short Detection Current Charging Start Voltage Limit Charging Soft Start Current Charging Soft Start Time VRCH VBAT_SHR ITRK_SHORT VCHG_VLIM ICHG_START tCHG_START 15 17 59 160 2.2 3.1 185 +0.6 +1.45 +1.7 VIN − 0.075 52.5 260 2.4 20 3.2 260 3 98 83 123 390 2.5 3.3 365 Rev. 0 | Page 3 of 44 On BAT_SNS, TJ = 25°C, IEND = 52.5 mA2 TJ = 0°C to 115°C2 TJ = −40°C to +125°C Relative to VINx voltage, BAT_SNS rising VBAT_SNS = VTRM IEND = 52.5 mA, TJ = 0°C to 115°C2 ITRK_SHORT = ITRK_DEAD2 Voltage limit is not active by default VBAT_SNS > VTRK_DEAD ADP5063 Parameter BATTERY ISOLATION FET Pin to Pin Resistance Between ISO_Sx and ISO_Bx Regulated System Voltage: VBAT Low Battery Supplementary Threshold LDO AND HIGH VOLTAGE BLOCKING Regulated System Voltage Load Regulation High Voltage Blocking FET (LDO FET) On Resistance Maximum Output Current VINx Input Voltage, Good Threshold Rising VINx Falling VINx Input Overvoltage Threshold Hysteresis VINx Transition Timing THERMAL CONTROL Isothermal Charging Temperature Thermal Early Warning Temperature Thermal Shutdown Temperature THERMISTOR CONTROL Thermistor Current 10,000 NTC (Negative Temperature Coefficient) Resistor 100,000 NTC Resistor Thermistor Capacitance Cold Temperature Threshold Resistance Thresholds Cool to Cold Resistance Cold to Cool Resistance Hot Temperature Threshold Resistance Thresholds Hot to Typical Resistance Typical to Hot Resistance JEITA1 Li-ION BATTERY CHARGING SPECIFICATION DEFAULTS 5 JEITA Cold Temperature Resistance Thresholds Cool to Cold Resistance Cold to Cool Resistance JEITA Cool Temperature Resistance Thresholds Typical to Cool Resistance Cool to Typical Resistance JEITA Warm Temperature Resistance Thresholds Warm to Typical Resistance Typical to Warm Resistance Data Sheet Symbol Min Typ Max Unit Test Conditions/Comments 55 89 mΩ VTHISO 3.6 3.2 0 3.8 3.4 5 4.0 3.5 12 V V mV On battery supplement mode, VINx = 0 V, VISO_Bx = 3.6 V, IISO_Bx = 500 mA VTRM[5:0] programming ≥ 4.00 V VTRM[5:0] programming < 4.00 V VISO_Sx < VISO_Bx, system voltage rising VISO_STRK 4.214 4.3 4.386 V −0.56 330 485 %/A mΩ 2.1 3.9 4.0 A V RDSON_ISO VISO_SFC RDS(ON)HV VVIN_OK_RISE VVIN_OK_FALL VVIN_OV ΔVVIN_OV tVIN_RISE tVIN_FALL 3.75 6.7 3.6 6.9 0.1 10 10 TLIM TSDL TSD 115 130 140 110 INTC_10k INTC_100k CNTC TNTC_COLD RCOLD_FALL RCOLD_RISE TNTC_HOT RHOT_FALL RHOT_RISE 20,500 2750 25,600 24,400 60 3700 3350 20,500 RTYP_FALL RTYP_RISE TJEITA_WARM 13,200 4260 Minimum rise time for VINx from 5 V to 20 V Minimum fall time for VINx from 4 V to 0 V °C °C °C °C TJ rising TJ falling 40 μA pF °C No battery charging occurs Ω Ω °C No battery charging occurs 30,720 3950 Ω Ω °C 25,600 24,400 10 30,720 16,500 15,900 45 19,800 5800 5200 V V V µs µs μA 0 RCOLD_FALL RCOLD_RISE TJEITA_COOL VISO_Sx = 4.3 V, LDO mode 400 100 0 TJEITA_COLD RWARM_FALL RWARM_RISE 3.7 7.2 VSYSTEM[2:0] = 000 (binary) = 4.3 V, IISO_Sx = 100 mA, LDO mode2 IISO_Sx = 0 mA to 1500 mA IVINx = 500 mA 6140 Rev. 0 | Page 4 of 44 Ω Ω °C Ω Ω °C Ω Ω No battery charging occurs Battery charging occurs at 50% of programmed level Battery termination voltage (VTRM) is reduced by 100 mV Data Sheet Parameter JEITA Hot Temperature Resistance Thresholds Hot to Warm Resistance Warm to Hot Resistance JEITA2 Li-ION BATTERY CHARGING SPECIFICATION DEFAULTS JEITA Cold Temperature Resistance Thresholds Cool to Cold Resistance Cold to Cool Resistance JEITA Cool Temperature Resistance Thresholds Typical to Cool Resistance Cool to Typical Resistance JEITA Warm Temperature Resistance Thresholds Warm to Typical Resistance Typical to Warm Resistance JEITA Hot Temperature Resistance Thresholds Hot to Warm Resistance Warm to Hot Resistance BATTERY DETECTION Sink Current Source Current Battery Threshold Low High Battery Detection Timer TIMERS Clock Oscillator Frequency Start Charging Delay Trickle Charge Fast Charge Charge Complete Deglitch Watchdog2 Safety Battery Short2 ILED OUTPUT PINS Voltage Drop over ILED Maximum Operating Voltage over ILED SYS_EN OUTPUT Pin SYS_EN FET On Resistance ADP5063 Symbol TJEITA_HOT RHOT_FALL RHOT_RISE Min 2750 TJEITA_COLD 3700 3350 Max 3950 0 RCOLD_FALL RCOLD_RISE TJEITA_COOL 20,500 RTYP_FALL RTYP_RISE TJEITA_WARM 13,200 RWARM_FALL RWARM_RISE TJEITA_HOT Typ 60 4260 30,720 16,500 15,900 45 19,800 6140 Ω Ω °C Ω Ω °C Ω Ω °C RHOT_FALL RHOT_RISE 2750 3700 3350 3950 Ω Ω ISINK ISOURCE 13 7 20 10 34 13 mA mA VBATL VBATH tBATOK 1.8 1.9 3.4 333 2.0 V V ms fCLK tSTART tTRK tCHG tEND tDG 2.7 3 1 60 600 7.5 31 3.3 MHz sec min min min ms tWD tSAFE tBAT_SHR 36 32 40 30 VILED VMAXILED 200 RON_SYS_EN 10 44 5.5 Rev. 0 | Page 5 of 44 Test Conditions/Comments No battery charging occurs Ω Ω °C 25,600 24,400 10 5800 5200 60 Unit °C No battery charging occurs Battery termination voltage (VTRM) is reduced by 100 mV Battery termination voltage (VTRM) is reduced by 100 mV No battery charging occurs VBAT_SNS = VTRM, ICHG < IEND Applies to VTRK_DEAD, VRCH, IEND, VWEAK, VVIN_OK_RISE, and VVIN_OK_FALL sec min sec mV V IILED = 20 mA Ω ISYS_EN = 20 mA ADP5063 Parameter LOGIC INPUT PINS Maximum Voltage on Digital Inputs Maximum Logic Low Input Voltage Minimum Logic High Input Voltage Pull-Down Resistance Data Sheet Symbol VDIN_MAX VIL VIH Min 1.2 215 Typ 350 Max Unit Test Conditions/Comments 5.5 0.5 V V V kΩ Applies to SCL, SDA, DIG_IO1, DIG_IO2, DIG_IO3 Applies to SCL, SDA, DIG_IO1, DIG_IO2, DIG_IO3 Applies to SCL, SDA, DIG_IO1, DIG_IO2, DIG_IO3 Applies to DIG_IO1, DIG_IO2, DIG_IO3 610 Undervoltage lockout generated normally from ISO_Sx or ISO_Bx; in certain transition cases, it can be generated from VINx. These values are programmable via I2C. Values are given with default register values. The output current during charging may be limited by the input current limit or by the isothermal charging mode. 4 During weak charging mode, the charger provides at least 20 mA of charging current via the trickle charge branch to the battery unless trickle charging is disabled. Any residual current that is not required by the system is also used to charge the battery. 5 Either JEITA1 (default) or JEITA2 can be selected in I2C, or both JEITA functions can be enabled or disabled in I2C. 1 2 3 RECOMMENDED INPUT AND OUTPUT CAPACITANCES Table 2. Parameter CAPACITANCES VINx CBP ISO_Sx ISO_Bx Symbol Min Typ CVINx CCBP CISO_Sx CISO_Bx 4 60 10 10 100 22 22 Max Unit 10 140 100 μF nF μF μF Test Conditions/Comments Effective capacitance I2C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS Table 3. Parameter 1 I2C-COMPATIBLE INTERFACE 2 Capacitive Load for Each Bus Line SCL Clock Frequency SCL High Time SCL Low Time Data Setup Time Data Hold Time Setup Time for Repeated Start Hold Time for Start/Repeated Start Bus Free Time Between a Stop and a Start Condition Setup Time for Stop Condition Rise Time of SCL/SDA Fall Time of SCL/SDA Pulse Width of Suppressed Spike 1 2 Symbol CS fSCL tHIGH tLOW tSU, DAT tHD, DAT tSU, STA tHD, STA tBUF tSU, STO tR tF tSP Min 0.6 1.3 100 0 0.6 0.6 1.3 0.6 20 20 0 Typ Max Unit 400 400 pF kHz µs µs ns µs µs µs µs µs ns ns ns 0.9 300 300 50 Guaranteed by design. A master device must provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL (see Figure 2). Rev. 0 | Page 6 of 44 Data Sheet ADP5063 Timing Diagram SDA tLOW tF tSU, DAT tR tSP tBUF tR tHD, STA tF SCL tHD, DAT tHIGH tSU, STO tSU, STA Sr P S 11593-002 S S = START CONDITION Sr = REPEATED START CONDITION P = STOP CONDITION Figure 2. I2C Timing Diagram Rev. 0 | Page 7 of 44 ADP5063 Data Sheet ABSOLUTE MAXIMUM RATINGS Maximum Power Dissipation Table 4. Parameter VIN1, VIN2, VIN3 to AGND All Other Pins to AGND Continuous Drain Current, Battery Supplementary Mode, from ISO_Bx to ISO_Sx Storage Temperature Range Operating Junction Temperature Range Soldering Conditions Rating –0.5 V to +20 V –0.3 V to +6 V 2.1 A –65°C to +150°C –40°C to +125°C JEDEC J-STD-020 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The maximum safe power dissipation in the ADP5063 package is limited by the associated rise in junction temperature (TJ) on the die. At a die temperature of approximately 150°C (the glass transition temperature), the properties of the plastic change. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, thereby permanently shifting the parametric performance of the ADP5063. Exceeding a junction temperature of 175°C for an extended period can result in changes in the silicon devices, potentially causing failure. ESD CAUTION THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, θJA is specified for a device soldered in a circuit board for surfacemount packages. Table 5. Package Type 20-Lead LFCSP θJA 35.6 θJC 3.65 Unit °C/W Rev. 0 | Page 8 of 44 Data Sheet ADP5063 17 SDA 16 SYS_EN 18 THR 20 AGND 19 CBP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 15 ILED SCL 1 DIG_IO3 2 BAT_SNS 4 14 ISO_B3 ADP5063 13 ISO_B2 TOP VIEW (Not to Scale) 12 ISO_B1 DIG_IO1 5 9 ISO_S2 10 8 VIN3 ISO_S1 VIN2 7 VIN1 6 11 ISO_S3 NOTES 1. CONNECTION OF THE EXPOSED PAD IS NOT REQUIRED. THE EXPOSED PAD CAN BE CONNECTED TO ANALOG GROUND TO IMPROVE HEAT DISSIPATION FROM THE PACKAGE TO BOARD. 11593-003 DIG_IO2 3 Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2 Name SCL DIG_IO3 Type 1 I GPIO 3 DIG_IO2 GPIO 4 5 BAT_SNS DIG_IO1 I GPIO 6, 7, 8 9, 10, 11 I/O I/O I/O 15 16 VIN1, VIN2, VIN3 ISO_S1, ISO_S2, ISO_S3 ISO_B1, ISO_B2, ISO_B3 ILED SYS_EN 17 18 SDA THR I/O I 19 20 N/A 4 CBP AGND EP I/O G N/A4 12, 13, 14 O O Description I2C-Compatible Interface Serial Clock. Charging Enable. When DIG_IO3 = low or high-Z, charging is disabled. When DIG_IO3 = high, charging is enabled.2, 3 Set Input Current Limit. When DIG_IO2 = low or high-Z, the input limit is defined by DIG_IO1 setting. When DIG_IO2 = high, the input limit is 1500 mA.2, 3 Battery Voltage Sense Pin. Set Input Current Limit. This pin sets the input current limit directly. When DIG_IO1 = low or high-Z, the input limit is 100 mA. When DIG_IO1 = high, the input limit is 500 mA. 2, 3 Power Connections to USB VBUS. These pins are high current inputs when in charging mode. Linear Charger Supply Side Input to Internal Isolation FET/Battery Current Regulation FET. High current input/output. Battery Supply Side Input to Internal Isolation FET/Battery Current Regulation FET. Open-Drain Output to Indicator LED. System Enable. This pin is the battery OK flag/open-drain pull-down FET to enable the system when the battery reaches the VWEAK level. I2C-Compatible Interface Serial Data. Battery Pack Thermistor Connection. If this pin is not used, connect a dummy 10 kΩ resistor from THR to AGND. Bypass Capacitor Input. Analog Ground. Exposed Pad. Connection of the exposed pad is not required. The exposed pad can be connected to analog ground to improve heat dissipation from the package to the board. I is input, O is output, I/O is input/output, G is ground, and GPIO is the factory programmable general-purpose input/output. See the Digital Input and Output Options section for details. 3 The DIG_IOx setting defines the initial state of the ADP5063. If the parameter or the mode that is related to each DIG_IOx pin setting is changed (by programming an equivalent I2C register bit or bits), the I2C register setting takes precedence over the DIG_IOx pin setting. VINx connection or disconnection resets control to the DIG_IOx pin. 4 N/A = not applicable. 1 2 Rev. 0 | Page 9 of 44 ADP5063 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1000 4.38 900 4.36 800 4.34 4.32 4.30 4.28 4.26 500 400 300 4.22 100 0.1 1 0 1.8 3.3 2.8 2.3 3.8 BATTERY VOLTAGE (V) 70 LOAD = 100mA LOAD = 500mA LOAD = 1000mA ISOLATION FET RESISTANCE (mΩ) 4.4 TRICKLE CHARGE Figure 6. Battery Charge Current vs. Battery Voltage, ICHG[4:0] = 01001 (Binary) = 500 mA, ILIM[3:0] = 1111 (Binary) = 2100 mA Figure 4. System Voltage vs. System Output Current, LDO Mode, VSYSTEM[2:0] = 000 (Binary) = 4.3 V 4.5 FAST CHARGE 600 200 SYSTEM OUTPUT CURRENT (A) 4.3 SYSTEM VOLTAGE (V) 700 4.24 4.20 0.01 WEAK CHARGE 11593-009 CHARGE CURRENT (mA) 4.40 11593-004 SYSTEM VOLTAGE (V) VVINx = 5.0 V, CVINx = 10 µF, CISO_Sx = 44 µF, CISO_Bx = 22 µF, CCBP = 100 nF, all registers are at default values, unless otherwise noted. 4.2 4.1 4.0 3.9 3.8 3.7 65 60 55 50 45 4.4 4.8 5.2 5.6 6.0 INPUT VOLTAGE (V) 6.4 6.8 40 2.7 2.9 3.1 3.3 3.5 BATTERY VOLTAGE (V) Figure 7. Ideal Diode RON vs. Battery Voltage, IISO_Sx = 500 mA, VINx Open Figure 5. System Voltage vs. Input Voltage (in Dropout), LDO Mode, VSYSTEM[2:0] = 000 (Binary) = 4.3 V Rev. 0 | Page 10 of 44 3.7 11593-010 3.5 4.0 11593-005 3.6 Data Sheet ADP5063 3.5 3.8 DEFAULT STARTUP DIS_LDO = HIGH 3.7 2.0 1.5 1.0 0.5 0.4 3.5 3.4 0.3 3.3 0.2 3.2 2 3 4 5 7 6 8 INPUT VOLTAGE (V) 0 70 65 60 55 50 40 1.0 1.5 LOAD CURRENT (A) 2.0 11593-012 45 0.5 20 40 60 CHARGE TIME (Minutes) 80 Figure 10. Charge Profile, ILIM[3:0] = 0110 (Binary) = 500 mA, LiFePO4 Battery Capacity = 500 mAh Figure 8. Input Current vs. Input Voltage, VISO_Bx = 3.3 V 0 0 3.0 11593-011 0 0.1 VBAT_SNS IISO_B 3.1 Figure 9. Ideal Diode RON vs. Load Current, VISO_Bx = 3.6 V Rev. 0 | Page 11 of 44 11593-013 2.5 3.6 CHARGE CURRENT (A) 0.5 BATTERY VOLTAGE (V) INPUT CURRENT (mA) 3.0 ISOLATION FET RESISTANCE (mΩ) 0.6 ADP5063 Data Sheet TEMPERATURE CHARACTERISTICS 1.4 1.3 0.5 VISO_Bx = 3.6V VISO_Bx = 4.2V VISO_Bx = 5.5V 0.4 SYSTEM VOLTAGE ACCURACY (%) 1.5 STANDBY CURRENT (µA) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 VISO_Sx = 4.3V VISO_Sx = 5.0V 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –15 10 35 60 85 AMBIENT TEMPERATURE (°C) Figure 11. Battery Leakage (Standby) Current vs. Ambient Temperature, Standby Mode 5.0 1.8 4.5 1.4 1.2 1.0 0.8 0.6 0.4 0.2 –10 5 20 35 50 65 80 95 110 125 50 65 80 95 110 125 VIN = 4.0V VIN = 5.0V VIN = 6.7V 3.5 3.0 2.5 2.0 1.5 1.0 –25 –10 5 20 35 50 65 80 95 110 125 AMBIENT TEMPERATURE (°C) Figure 15. VINx Quiescent Current vs. Ambient Temperature, LDO Mode 0.5 0.5 VISO_Sx = 4.3V VISO_Sx = 5.0V VTRM VOLTAGE ACCURACY (%) 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 VTRM = 3.5V VTRM = 3.8V VTRM = 4.2V 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –25 –10 5 20 35 50 65 80 95 110 125 AMBIENT TEMPERATURE (°C) Figure 13. System Voltage Accuracy vs. Ambient Temperature, Load = 100 mA, VVINx = 5.5 V –0.5 –40 –25 –10 5 20 35 50 65 80 AMBIENT TEMPERATURE (°C) 95 110 125 11593-019 –0.4 11593-016 SYSTEM VOLTAGE ACCURACY (%) 35 4.0 0 –40 Figure 12. VINx Quiescent Current vs. Ambient Temperature, DIS_LDO = High –0.5 –40 20 11593-018 –25 AMBIENT TEMPERATURE (°C) 0.4 5 0.5 11593-015 0 –40 –10 Figure 14. System Voltage Accuracy vs. Ambient Temperature, Trickle Charge Mode, VISO_Sx = 4.3 V and VVINx = 5.0 V, or VISO_Sx = 5.0 V and VVINx = 6.0 V 2.0 1.6 –25 AMBIENT TEMPERATURE (°C) VINx QUIESCENT CURRENT (mA) VINx QUIESCENT CURRENT (mA) –0.5 –40 11593-014 0 –40 11593-017 0.1 Figure 16. Termination (VTRM) Voltage Accuracy vs. Ambient Temperature Rev. 0 | Page 12 of 44 ADP5063 1.4 1.3 ICHG = 1300mA INPUT CURRENT LIMIT (A) CHARGE CURRENT (A) 1.2 1.1 1.0 0.9 0.8 0.7 ICHG = 750mA 0.6 ICHG = 500mA 0.4 –40 10 –15 35 85 60 110 AMBIENT TEMPERATURE (°C) 11593-020 0.5 Figure 17. Fast Charge Current CC Mode vs. Ambient Temperature 6.90 6.85 –10 5 20 35 50 65 80 95 110 125 AMBIENT TEMPERATURE (°C) 11593-021 VINx OVERVOLTAGE THRESHOLD (V) 6.95 –25 20 35 50 65 80 95 110 AMBIENT TEMPERATURE (°C) Figure 19. Input Current Limit vs. Ambient Temperature 7.00 6.80 –40 1.6 1.5 ILIM = 1500mA 1.4 1.3 1.2 1.1 1.0 0.9 ILIM = 900mA 0.8 0.7 0.6 0.5 ILIM = 500mA 0.4 0.3 0.2 ILIM = 100mA 0.1 0 5 –40 –25 –10 Figure 18. VINx Overvoltage Threshold vs. Ambient Temperature Rev. 0 | Page 13 of 44 125 11593-022 Data Sheet ADP5063 Data Sheet TYPICAL WAVEFORMS T T VISO_Sx VISO_Sx VVINx VVINx 4 4 1 1 IISO_Bx 2 2 IVINx IISO_Bx IVINx M1.00ms A CH2 T 1.00ms 120mA 11593-023 CH1 2.00V CH2 200mA CH3 200mA CH4 2.00V CH1 2.00V CH2 200mA CH3 200mA CH4 2.00V Figure 20. Charging Startup, VVINx = 5.0 V, ILIM[3:0] = 0110 (Binary) = 500 mA, ICHG[4:0] = 01110 (Binary) = 750 mA M200.0µs T 0.00s A CH2 216mA 11593-026 3 3 Figure 23. USB VBUS Disconnection VISO_Sx T T VISO_Sx 1 3 1 IISO_Bx 2 IISO_Sx IISO_Sx M1.00ms A CH2 T 3.00ms 820mA CH1 1.00V CH2 500mA CH3 500mA M1.0ms A CH2 T 3.00ms –610mA 11593-027 CH1 100mV CH2 500mA 11593-024 2 Figure 21. Load Transient, IISO_Sx Load = 300 mA to 1500 mA to 300 mA Figure 24. Load Transient, IISO_Sx Load = 300 mA to 1500 mA to 300 mA, EN_CHG = High, ILIM[3:0] = 0110 (Binary) = 500 mA T T VISO_Sx 2 VVINx 1 VISO_Bx 2 IISO_Bx IISO_Bx 3 3 IVINx M40.0µs T 0.00s A CH3 610mA Figure 22. Input Current-Limit Transition from 100 mA to 900 mA, ISO_Sx Load = 66 Ω, Charging = 750 mA CH2 2.00V CH3 10.0mA M200ms T 0.00s A CH3 17.2mA 11593-028 CH1 200mV CH2 200mV CH3 500mA CH4 500mA 11593-025 4 Figure 25. Battery Detection Waveform, VSYSTEM[2:0] = 000 (Binary) = 4.3 V, No Battery Rev. 0 | Page 14 of 44 Data Sheet ADP5063 THEORY OF OPERATION SUMMARY OF OPERATION MODES Table 7. Summary of Operation Modes Mode Name IC Off, Standby IC Off, Suspend LDO Mode Off, Isolation FET On LDO Mode Off, Isolation FET Off (System Off) LDO Mode, Charger Off Trickle Charge Mode Weak Charge Mode Fast Charge Mode Charge Mode, No Battery Charge Mode, Battery (ISO_Bx) Shorted 1 VVINx Condition 0V Battery Condition Any battery condition Trickle Charge Off LDO FET State Off Battery Isolation FET On 5V 5V Any battery condition Any battery condition Off Off Off Off On On System Voltage ISO_Sx Battery voltage or 0 V Battery voltage Battery voltage 5V Any battery condition Off Off Off 0V DIS_LDO = high Disable LDO and enable isolation FET Enable battery charging 5V 5V 5V 5V 5V 5V Any battery condition Battery < VTRK_DEAD VTRK_DEAD ≤ battery < VWEAK Battery ≥ VWEAK Open Shorted Off On On Off Off On LDO LDO CHG CHG LDO LDO Off Off CHG CHG Off Off 4.3 V 4.3 V 3.4 V 3.4 V (minimum) 4.3 V 4.3 V Enable battery charging Enable battery charging Enable battery charging Enable battery charging Enable battery charging Enable battery charging Additional Conditions 1 See Table 8 for details. Table 8. Operation Mode Controls Pin Configuration Enable Battery Charging DIG_IOx DIG_IO3 Disable LDO and Enable Isolation FET Not applicable Equivalent I2C Address, Data Bit(s) 0x07, D0 0x07, D3, D0 Description Low = all charging modes disabled (fast, weak, trickle). High = all charging modes enabled (fast, weak, trickle). Low = LDO enabled. High = LDO disabled. In addition, when EN_CHG = low, the battery isolation FET is on; when EN_CHG = high, the battery isolation FET is off. Rev. 0 | Page 15 of 44 ADP5063 Data Sheet INTRODUCTION The ADP5063 is a fully programmable I2C charger for single cell lithium ion or lithium polymer batteries, suitable for a wide range of portable applications. The linear charger architecture enables up to 2.1 A output current at 4.3 V to 5.0 V (I2C programmable) on the system power supply, and up to 1.3 A of charge current into the battery from a dedicated charger. The ADP5063 operates from an input voltage of 4 V up to 6.7 V but is tolerant of voltages of up to 20 V. The 20 V voltage tolerance alleviates the concerns of the USB bus spiking during disconnection or connection scenarios. The ADP5063 features an internal FET between the linear charger output and the battery. This feature permits battery isolation and, therefore, system powering under a dead battery or no battery scenario, which allows immediate system function upon connection to a USB power supply. The ADP5063 is fully compliant with USB 3.0 and the USB Battery Charging 1.2 Compliance Plan Specification. The ADP5063 is chargeable via the mini USB VBUS pin from a wall charger, car charger, or USB host port. Based on the type of USB source, which is detected by an external USB detection device, the ADP5063 can be set to apply the correct current limit for optimal charging and USB compliance. The USB charger permits correct operation under all USB compliant sources such as wall chargers, host chargers, hub chargers, and standard host and hubs. A processor can control the USB charger using the I2C interface to program the charging current and numerous other parameters, including • • • • • • • • • • • • Rev. 0 | Page 16 of 44 Trickle charge current level Trickle charge voltage threshold Weak charge (constant current) current level Fast charge (constant current) current level Fast charge (constant voltage) voltage level Fast charge safety timer period Watchdog safety timer parameters Weak battery threshold detection Charging complete threshold Recharge threshold Charging enable/disable Battery pack temperature detection and automatic charger shutdown Data Sheet 6 TO USB VBUS OR WALL ADAPTER 7 8 ADP5063 VIN1 ISO_S1 HIGH VOLTAGE BLOCKING LDO FET ISO_S2 VIN2 VIN3 ISO_S3 + 6.85V + LDO FET CONTROL – VIN LIMIT 9 TO SYSTEM LOAD 10 11 – VIN OVERVOLTAGE CBP BATTERY ISOLATION FET 19 TRICKLE CURRENT SOURCE + 3.9V – 3MHz OSC ISO_B1 12 VIN GOOD EOC 1 17 5 3 2 ISO_B2 SCL CHARGE CONTROL ISO_B3 SDA 14 CV MODE RECHARGE DIG_IO1 DIG_IO2 I2C INTERFACE AND CONTROL LOGIC WEAK DIG_IO3 BATTERY DETECTION SINK TRICKLE BATTERY: OPEN SHORT BAT_SNS 4 3.4V 1.9V BATTERY DETECTION – SYS_EN + 16 13 SYS_EN OUTPUT LOGIC VIN – 150mV BATTERY OVERVOLTAGE TSD 140°C WARNING 130°C ISOTHERMAL 115°C TSD DOWN 110°C WARM NTC CURRENT CONTROL HOT THR THERMAL CONTROL AGND 0.5V 18 NTC 20 SINGLE CELL Li-Ion Figure 26. Block Diagram Rev. 0 | Page 17 of 44 11593-029 ILED OUTPUT LOGIC COLD COOL – ILED + 15 ADP5063 Data Sheet Table 9. DIG_IO1 Operation The ADP5063 includes a number of significant features to optimize charging and functionality, including • • • • Thermal regulation for maximum performance. USB host current limits. Termination voltage accuracy: ±1.7%. Battery thermistor input with automatic charger shutdown in the event that the battery temperature exceeds limits (compliant with the JEITA Li-Ion battery charging temperature specification). • Three external pins (DIG_IO1, DIG_IO2, and DIG_IO3) that directly control a number of parameters. These pins are factory programmable for maximum flexibility. They can be factory programmed for functions such as • Enable/disable charging. • Control of the 100 mA or 500 mA input current limit. • Control of the 1500 mA input current limit. • Control of the battery charge current. • An interrupt output pin. See the Digital Input and Output Options section for details. CHARGER MODES Input Current Limit The VINx input current limit is controlled via the internal I2C ILIM bits. The input current limit can also be controlled via the DIG_IO1 pin (if factory programmed to do so) as outlined in Table 9. Any change from the 100 mA I2C default takes precedence over the pin setting. DIG_IO1 0 1 Function 100 mA input current limit or I2C programmed value 500 mA input current limit or I2C programmed value (or reprogrammed I2C value from 100 mA default) USB Compatibility The ADP5063 features an I2C-programmable input current limit to ensure compatibility with the requirements listed in Table 10. The current limit defaults to 100 mA to allow compatibility with a USB host or hub that is not configured. The I2C register default is 100 mA. An I2C write command to the ILIM bits overrides the DIG_IOx pins, and the I2C register default value can be reprogrammed for alternative requirements. When the input current-limit feature is used, the available input current may be too low for the charger to meet the programmed charging current, ICHG, thereby reducing the rate of charge and setting the VIN_ILIM flag. When connecting voltage to VINx without the proper voltage level on the battery side, the high voltage blocking mechanism is in a state wherein it draws a current of