Data Sheet
Triple 1800 mA Buck Regulator with
Precision Enables and Power-Good Outputs
ADP5135
FEATURES
TYPICAL APPLICATION CIRCUIT
Input voltage range: 3.0 V to 5.5 V
Three 1800 mA buck regulators
24-lead, 4 mm × 4 mm LFCSP package
Regulator accuracy: ±1.8%
Factory programmable or external adjustable VOUTx pins
Precision enables for easier power sequencing
Power-good pins for monitoring each regulator
3 MHz buck operation with forced PWM and auto PWM/PSM
modes
BUCK1/BUCK2/BUCK3: output voltage range from 0.8 V to 3.8 V
ADP5135
3.0V
TO
5.5V
AVIN
C7
0.1µF
AGND
VIN1
C1
10µF
PGND1
ON
OFF
VDDIO
18
10
16
15
BUCK1
1.8A
14
11
VIN2
C3
10µF
PGND2
ON
OFF
EN2
VIN3
C5
10µF
PGND3
ON
OFF
EN3
VOUT1
SW1
L1 1µH
R1
FB1
C2
22µF
R2
12
13
APPLICATIONS
Power for processors, application specific integrated circuits
(ASICs), field-programmable gate arrays (FPGAs), and
radio frequency (RF) chipsets
Portable instrumentation and medical devices
Space constrained devices
EN1
17
HOUSEKEEPING
3
9
5
BUCK2
1.8A
4
7
8
21
22
PWM
MODE
AUTO
VOUT2
SW2
L2 1µH
R3
FB2
C4
22µF
R4
BUCK3
1.8A
19
20
23
VOUT3
SW3
L3 1µH
R5
FB3
24
C6
22µF
R6
POWER
GOOD
6
2
1
PG1
PG2
PG3
R7
100Ω
R8
100Ω
R9
100Ω
12604-001
VDDIO
Figure 1.
GENERAL DESCRIPTION
Table 1. Family Devices
The ADP5135 combines three high performance buck regulators
(BUCK1, BUCK2, and BUCK3). It is available in a 24-lead,
4 mm × 4 mm LFCSP.
Device
ADP5023
Channels
2 buck regulators, 1 LDO
ADP5024
2 buck regulators, 1 LDO
ADP5034
2 buck regulators, 2 LDOs
ADP5037
2 buck regulators, 2 LDOs
ADP5033
2 buck regulators, 2 LDOs
with 2 ENx pins
1 buck regulator, 2 LDOs
The high switching frequency of the buck regulators enables tiny
multilayer external components and minimizes the board space.
When the MODE pin is set to high, the buck regulators operate in
forced pulse-width modulation (PWM) mode. When the
MODE pin is set to low, the buck regulators operate in PWM
mode only when the load is above a predefined threshold. When
the load current falls below this predefined threshold, the
regulator operates in power save mode (PSM), improving the
light load efficiency.
ADP5040
ADP5041
BUCK1 and BUCK2 operate in synchronization, and BUCK3
operates out of phase to reduce the input capacitor requirement.
Regulators in the ADP5135 are activated through dedicated
enable pins. The default output voltages can be externally set in
the adjustable version, or factory programmable to a wide range
of preset values in the fixed voltage version.
Rev. 0
ADP5133
ADP5134
1 buck regulator, 2 LDOs
with supervisory circuit,
watchdog function, and
manual reset
2 buck regulators with
2 ENx pins
2 buck regulators, 2 LDOs
with precision enable and
power good
Max
Current
800 mA,
300 mA
1.2 A,
300 mA
1.2 A,
300 mA
800 mA,
300 mA
800 mA,
300 mA
1.2 A,
300 mA
1.2 A,
300 mA
Package
LFCSP (CP-24-10)
LFCSP (CP-24-10)
LFCSP (CP-24-10),
TSSOP (RE-28-1)
LFCSP (CP-24-10)
WLCSP (CB-16-8)
LFCSP (CP-20-10)
LFCSP (CP-20-10)
800 mA
WLCSP (CB-16-8)
1.2 A,
300 mA
LFCSP (CP-24-7)
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ADP5135
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 13
Applications ....................................................................................... 1
Power Management Unit........................................................... 13
Typical Application Circuit ............................................................. 1
Buck Regulators: BUCK1, BUCK2, AND BUCK3 ................ 15
General Description ......................................................................... 1
Applications Information .............................................................. 17
Revision History ............................................................................... 2
Buck External Component Selection....................................... 17
Specifications..................................................................................... 3
Typical Application Schematics................................................ 19
BUCK1, BUCK2, and BUCK3 .................................................... 4
Power Dissipation and Thermal Considerations ....................... 21
Input and Output Capacitors, Recommended ......................... 4
Buck Regulator Power Dissipation .......................................... 21
Absolute Maximum Ratings............................................................ 5
Junction Temperature ................................................................ 22
Thermal Resistance ...................................................................... 5
PCB Layout Guidelines .................................................................. 23
ESD Caution .................................................................................. 5
Outline Dimensions ....................................................................... 24
Pin Configuration and Function Descriptions ............................. 6
Ordering Guide .......................................................................... 24
Typical Performance Characteristics ............................................. 7
REVISION HISTORY
11/14—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
Data Sheet
ADP5135
SPECIFICATIONS
VAVIN = VIN1 = VIN2 = VIN3 = 3.0 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical
specifications, unless otherwise noted.
Table 2.
Parameter
INPUT VOLTAGE RANGE
THERMAL SHUTDOWN
Threshold
Hysteresis
START-UP TIME1
BUCK1
BUCK2
BUCK3
START-UP TIME, BUCK3 FIRST
BUCK3
BUCK1
BUCK2
SHUTDOWN CONTROL
Level High
Level Low
PRECISION ENABLE PINS
Analog Activation Threshold
Hysteresis (Regulator Deactivation)
Input Leakage Current
POWER-GOOD PINS
Falling Threshold
Rising Threshold
Delay
Leakage Current
Output Voltage Low
MODE PIN
Level High
Level Low
INPUT CURRENT
All Channels Enabled
All Channels Disabled
AVIN UNDERVOLTAGE LOCKOUT
Mid UVLO Input Voltage Rising
Mid UVLO Input Voltage Falling
1
Symbol
VAVIN, VIN1,
VIN2, VIN3
Test Conditions/Comments
TSSD
TSSD_HYS
TJ rising
Min
3.0
Typ
Max
5.5
Unit
V
150
20
°C
°C
tSTART1
tSTART2
tSTART3
450
550
550
μs
μs
μs
tSTART4
tSTART5
tSTART6
550
200
300
μs
μs
μs
V
All ENx pins below VIL_EN level to achieve ISHUTDOWN
VIH_EN
VIL_EN
VENR
VENH
VI-LEAKAGE
0.9
0.35
Regulator activation/deactivation thresholds
Device out of shutdown (VENx > VIH_EN)
0.94
0.97
80
0.05
V
V
1
1
mV
μA
Monitors VOUT falling out of regulation
VPGLOW
VPGHYS
tPGDLY
IPGIQ
VPGOL
91
VPG = VIN
Load current = 1 mA
VIH_MOD
VIL_MOD
85
94
20
0.02
1
0.15
% VOUT
% VOUT
μs
μA
V
0.4
V
V
110
1.5
μA
μA
2.95
V
V
97
1.1
No load, no buck switching
ISTBY_NOSW
ISHUTDOWN
85
0.3
TJ = −40°C to +85°C
UVLOAVINRISE
UVLOAVINFALL
2.45
Start-up time is defined as the time from EN1 = EN2 = EN3 at 0 V to VAVIN to VOUT1, VOUT2, and VOUT3 reaching 90% of their nominal level. Start-up times are shorter
for individual channels if another channel is already enabled. See the Typical Performance Characteristics section for more information.
Rev. 0 | Page 3 of 24
ADP5135
Data Sheet
BUCK1, BUCK2, AND BUCK3
VAVIN = VIN1 = VIN2 = VIN3 = 3.0 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical
specifications, unless otherwise noted.1
Table 3.
Parameter
OUTPUT CHARACTERISTICS
Output Voltage Accuracy
Line Regulation
Load Regulation
VOLTAGE FEEDBACK
OPERATING SUPPLY CURRENT
BUCK1 Only
Test Conditions/Comments
Min
ΔVOUT1/VOUT1, ΔVOUT2/VOUT2,
ΔVOUT3/VOUT3
(ΔVOUT1/VOUT1)/ΔVIN1,
(ΔVOUT2/VOUT2)/ΔVIN2,
(ΔVOUT3/VOUT3)/ΔVIN3
(ΔVOUT1/VOUT1)/ΔIOUT1,
(ΔVOUT2/VOUT2)/ΔIOUT2,
(ΔVOUT3/VOUT3)/ΔIOUT3
VFB1, VFB2
PWM mode; ILOAD1 = ILOAD2 = ILOAD3 = 0 mA
−1.8
IIN2
BUCK3 Only
IIN3
Current Limit
ACTIVE PULL-DOWN
RESISTANCE
OSCILLATOR FREQUENCY
IIN
IPSM
RNFET
RPFET
RNFET
RPFET
ILIMIT1, ILIMIT2, ILIMIT3
Max
Unit
+1.8
%
−0.05
%/V
ILOAD = 0 mA to 1800 mA, PWM mode
−0.1
%/A
VIN1 = VIN2 = VIN3 = 3.6 V
VIN1 = VIN2 = VIN3 = 3.6 V
VIN1 = VIN2 = VIN3 = 5.5 V
VIN1 = VIN2 = VIN3 = 5.5 V
Positive channel field effect transistor
(PFET) switch peak current limit
VIN1 = VIN2 = VIN3 = 3.6 V; channel
disabled
RPWDN
Typ
PWM mode
Models with adjustable outputs
MODE = ground
ILOAD1 = 0 mA, device not switching, all
other channels disabled
ILOAD2 = 0 mA, device not switching, all
other channels disabled
ILOAD3 = 0 mA, device not switching, all
other channels disabled
ILOAD1 = ILOAD2 = ILOAD3 = 0 mA, device
not switching
PSM to PWM operation
IIN1
BUCK2 Only
BUCK1, BUCK2, and
BUCK3
PSM CURRENT THRESHOLD
SWx CHARACTERISTICS
SWx On Resistance
1
Symbol
fSW
0.491
2250
0.5
0.509
42
μA
52
μA
52
μA
85
μA
100
mA
140
190
122
147
2600
225
295
189
228
2950
75
2.5
V
3.0
mΩ
mΩ
mΩ
mΩ
mA
Ω
3.5
MHz
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
INPUT AND OUTPUT CAPACITORS, RECOMMENDED
TA = −40°C to +125°C, unless otherwise specified.
Table 4.
Parameter
NOMINAL INPUT AND OUTPUT CAPACITOR RATINGS
BUCK1, BUCK2, and BUCK3
Input Capacitor Ratings
Output Capacitor Ratings
CAPACITOR ESR
Symbol
Min
CMIN1, CMIN2, CMIN3
CMIN4, CMIN5, CMIN6
RESR
4.7
10
0.001
Rev. 0 | Page 4 of 24
Typ
Max
Unit
40
40
1
μF
μF
Ω
Data Sheet
ADP5135
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
Parameter
AVIN to AGND
VIN1, VIN2, VIN3 to AVIN
PGND1, PGND2, PGND3 to AGND
VOUT1, VOUT2, VOUT3, FB1, FB2, FB3,
EN1, EN2, EN3, MODE, PG1, PG2, PG3
to AGND
SW1 to PGND1
SW2 to PGND2
SW3 to PGND3
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
−0.3 V to +6 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to (AVIN + 0.3 V)
−0.3 V to (VIN1 + 0.3 V)
−0.3 V to (VIN2 + 0.3 V)
−0.3 V to (VIN3 + 0.3 V)
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 6. Thermal Resistance
Package Type
24-Lead LFCSP
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
For detailed information on power dissipation, see the Power
Dissipation and Thermal Considerations section.
Rev. 0 | Page 5 of 24
θJA
35
θJC
3
Unit
°C/W
ADP5135
Data Sheet
20 SW3
19 PGND3
22 VOUT3
21 VIN3
24 EN3
23 FB3
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PG3 1
18 AGND
PG2 2
17 AVIN
ADP5135
VIN2 3
16 VIN1
TOP VIEW
(Not to Scale)
SW2 4
15 SW1
PGND2 5
14 PGND1
PG1 6
NOTES
1. SOLDER THE EXPOSED PAD TO THE GROUND
PLANE WITH SEVERAL VIAS.
12604-002
FB1 11
EN1 12
VOUT2 9
VOUT1 10
FB2 8
EN2 7
13 MODE
Figure 2. Pin Configuration—View from the Top of the Die
Table 7. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
PG3
PG2
VIN2
SW2
PGND2
PG1
EN2
FB2
9
10
11
VOUT2
VOUT1
FB1
12
13
14
15
16
17
18
19
20
21
22
23
EN1
MODE
PGND1
SW1
VIN1
AVIN
AGND
PGND3
SW3
VIN3
VOUT3
FB3
24
EN3
EP
Description
Open-Drain Power-Good Output to Monitor the Output Voltage of BUCK3.
Open-Drain Power-Good Output to Monitor the Output Voltage of BUCK2.
BUCK2 Input Supply (3.0 V to 5.5 V). Connect VIN2 to VIN1, VIN3, and AVIN.
BUCK2 Switching Node.
Dedicated Power Ground for BUCK2.
Open-Drain Power-Good Output to Monitor the Output Voltage of BUCK1.
BUCK2 Enable. A high level turns on this regulator, and a low level turns it off.
BUCK2 Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the
BUCK2 resistor divider. For device models with a fixed output voltage, leave this pin unconnected.
BUCK2 Output Voltage Sensing Input. Connect VOUT2 to the top of the capacitor on VOUT2.
BUCK1 Output Voltage Sensing Input. Connect VOUT1 to the top of the capacitor on VOUT1.
BUCK1 Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the
BUCK1 resistor divider. For device models with a fixed output voltage, leave this pin unconnected.
BUCK1 Enable. A high level turns on this regulator, and a low level turns it off.
BUCK1/BUCK2 Operating Mode. MODE = high: forced PWM operation. MODE = low: auto PWM/PSM operation.
Dedicated Power Ground for BUCK1.
BUCK1 Switching Node.
BUCK1 Input Supply (3.0 V to 5.5 V). Connect VIN1 to VIN2, VIN3, and AVIN.
Analog Input Supply (3.0 V to 5.5 V). Connect AVIN to VIN1, VIN2, and VIN3.
Analog Ground.
Dedicated Power Ground for BUCK3.
BUCK3 Switching Node.
BUCK3 Input Supply (3.0 V to 5.5 V). Connect VIN3 to VIN1, VIN2 and AVIN.
BUCK3 Output Voltage Sensing Input. Connect VOUT3 to the top of the capacitor on VOUT3.
BUCK3 Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the
BUCK3 resistor divider. For device models with a fixed output voltage, leave this pin unconnected.
BUCK3 Enable. A high level turns on this regulator, and a low level turns it off.
Exposed Pad. Solder the exposed pad to the ground plane.
Rev. 0 | Page 6 of 24
Data Sheet
ADP5135
TYPICAL PERFORMANCE CHARACTERISTICS
VIN1 = VIN2 = VIN3= 3.6 V, TA = 25°C, unless otherwise noted.
160
T
120
VSW3
2
100
IOUT3
3
80
60
VOUT3
1
40
VEN3
20
3.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE (V)
CH1 2.0V
CH2 5.0V
CH3 100mA CH4 5.0V
M100µs
T 10.30%
A CH4
12604-006
0
3.0
12604-003
4
2.60V
Figure 6. BUCK3 Startup, VOUT3 = 3.3 V, IOUT3 = 20 mA
Figure 3. System Quiescent Current vs. Input Voltage, VOUT1 = 3.3 V,
VOUT2 = 1.8 V, VOUT3 = 1.2 V, All Channels Unloaded
3.33
T
3.32
VSW1
2
VOUT1 (V)
3.31
IOUT1
VOUT1
3.30
3.29
1
VEN1
VIN1 = 3.9V
VIN1 = 4.2V
VIN1 = 5.5V
3.28
4
CH2 5.0V
CH4 5.0V
M100µs
T 10.30%
A CH4
2.60V
3.27
12604-004
CH1 1.0V
CH3 50mA
0.6
0.8
1.0
1.2
1.4
1.810
1.6
1.8
2.0
VIN2 = 3.0V
VIN2 = 3.6V
VIN2 = 4.2V
VIN2 = 5.5V
1.805
VOUT2 (V)
VSW2
IOUT2
VOUT2
1
0.4
Figure 7. BUCK1 Load Regulation Across Input Voltage, VOUT1 = 3.3 V,
PWM Mode
T
3
0.2
IOUT1 (A)
Figure 4. BUCK1 Startup, VOUT1 = 1.2 V, IOUT1 = 10 mA
2
0
12604-007
3
1.800
1.795
VEN2
1.790
CH1 2.0V
CH2 5.0V
CH3 100mA CH4 5.0V
M100µs
T 10.30%
A CH4
2.60V
1.785
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
IOUT2 (A)
Figure 8. BUCK2 Load Regulation Across Input Voltage, VOUT2 = 1.8 V,
PWM Mode
Figure 5. BUCK2 Startup, VOUT2 = 1.8 V, IOUT2 = 10 mA
Rev. 0 | Page 7 of 24
12604-008
4
12604-005
QUIESCENT CURRENT (µA)
140
ADP5135
Data Sheet
1.204
100
VIN3 = 3.0V
VIN3 = 3.6V
VIN3 = 4.2V
VIN3 = 5.5V
1.202
90
80
70
EFFICIENCY (%)
1.198
1.196
60
50
40
30
20
1.192
10
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
IOUT3 (A)
0
0.001
100
90
90
80
80
70
70
EFFICIENCY (%)
EFFICIENCY (%)
1
10
Figure 12. BUCK2 Efficiency vs. Load Current, Across Input Voltage,
VOUT2 = 1.8 V, Auto Mode
100
60
50
40
30
60
50
40
30
20
20
VIN1 = 3.9V
VIN1 = 4.2V
VIN1 = 5.5V
0.01
0.1
1
VIN2 = 3.0V
VIN2 = 3.6V
VIN2 = 4.2V
VIN2 = 5.5V
10
10
LOAD CURRENT (A)
0
0.001
12604-010
10
0.01
0.1
1
10
LOAD CURRENT (A)
Figure 10. BUCK1 Efficiency vs. Load Current, Across Input Voltage,
VOUT1 = 3.3 V, Auto Mode
Figure 13. BUCK2 Efficiency vs. Load Current, Across Input Voltage,
VOUT2 = 1.8 V, PWM Mode
100
90
90
80
80
70
70
EFFICIENCY (%)
100
60
50
40
30
60
50
40
30
20
20
VIN1 = 3.9V
VIN1 = 4.2V
VIN1 = 5.5V
0.01
0.1
1
VIN3 = 3.0V
VIN3 = 3.6V
VIN3 = 4.2V
VIN3 = 5.5V
10
10
LOAD CURRENT (A)
12604-011
10
0
0.001
0.1
LOAD CURRENT (A)
Figure 9. BUCK3 Load Regulation Across Input Voltage,
VOUT3 = 1.2 V, PWM Mode
0
0.001
0.01
12604-013
0
12604-009
1.190
EFFICIENCY (%)
VIN2 = 3.0V
VIN2 = 3.6V
VIN2 = 4.2V
VIN2 = 5.5V
12604-012
1.194
Figure 11. BUCK1 Efficiency vs. Load Current, Across Input Voltage,
VOUT1 = 3.3 V, PWM Mode
0
0.001
0.01
0.1
1
10
LOAD CURRENT (A)
Figure 14. BUCK3 Efficiency vs. Load Current, Across Input Voltage,
VOUT3 = 1.2 V, Auto Mode
Rev. 0 | Page 8 of 24
12604-014
VOUT3 (V)
1.200
ADP5135
100
100
90
90
80
80
70
70
EFFICIENCY (%)
60
50
40
60
50
40
30
30
0.01
0.1
1
10
LOAD CURRENT (A)
0
0.001
3.4
80
3.3
SWITCHING FREQUENCY (MHz)
3.5
90
EFFICIENCY (%)
70
60
50
40
30
20
TA = +85°C
TA = +25°C
TA = –40°C
0.1
1
1
10
LOAD CURRENT (A)
10
3.2
3.1
3.0
2.9
2.8
2.7
TA = +85°C
TA = +25°C
TA = –40°C
2.6
2.5
12604-016
0.01
0.1
Figure 18. BUCK3 Efficiency vs. Load Current, Across Temperature,
VOUT3 = 1.2 V, Auto Mode
100
0
0.001
0.01
LOAD CURRENT (A)
Figure 15. BUCK3 Efficiency vs. Load Current, Across Input Voltage,
VOUT3 = 1.2 V, PWM Mode
10
TA = +85°C
TA = +25°C
TA = –40°C
10
12604-015
10
0
0.001
20
VIN3 = 3.0V
VIN3 = 3.6V
VIN3 = 4.2V
VIN3 = 5.5V
Figure 16. BUCK1 Efficiency vs. Load Current, Across Temperature,
VOUT1 = 3.3 V, Auto Mode
0
200
400
600
800
1000
1200
1400
1600
1800
LOAD CURRENT (mA)
Figure 19. BUCK2 Switching Frequency vs. Load Current, Across Temperature,
VOUT2 = 1.8 V, PWM Mode
100
T
90
VOUT1
1
80
60
ISW1
3
50
40
VSW1
30
TA = +85°C
TA = +25°C
TA = –40°C
0
0.001
0.01
0.1
1
10
LOAD CURRENT (A)
CH1 20mV CH2 2.0V
CH3 500mA
M8.0µs
T 10.20%
A CH2
2.20V
12604-020
2
20
12604-017
EFFICIENCY (%)
70
10
12604-018
20
12604-019
EFFICIENCY (%)
Data Sheet
Figure 20. Typical Waveforms, VOUT1 = 3.3 V, Load Current = 50 mA,
Auto Mode
Figure 17. BUCK2 Efficiency vs. Load Current, Across Temperature,
VOUT2 = 1.8 V, Auto Mode
Rev. 0 | Page 9 of 24
ADP5135
Data Sheet
T
T
VOUT2
VOUT2
1
1
ISW2
ISW2
3
3
VSW2
CH1 50mV CH2 2.0V
CH3 500mA
M8.0µs
T 10.20%
A CH2
2.20V
12604-021
2
VSW2
CH1 50mV CH2 2.0V
CH3 500mA
M400ns
T 10.20%
A CH2
2.20V
12604-024
2
Figure 24. Typical Waveforms, VOUT2 = 1.8 V, Load Current = 50 mA,
PWM Mode
Figure 21. Typical Waveforms, VOUT2 = 1.8 V, Load Current = 50 mA,
Auto Mode
T
T
VOUT3
1
VOUT3
1
ISW3
ISW3
3
3
VSW3
CH1 50mV CH2 2.0V
CH3 500mA
M8.0µs
T 10.20%
A CH2
2.20V
12604-022
2
VSW3
CH1 50mV CH2 2.0V
CH3 500mA
Figure 22. Typical Waveforms, VOUT3 = 1.2 V, Load Current = 50 mA,
Auto Mode
M400ns
T 10.20%
A CH2
2.20V
12604-025
2
Figure 25. Typical Waveforms, VOUT3 = 1.2 V, Load Current = 50 mA,
PWM Mode
T
T
VIN1
VOUT1
1
ISW1
3
VOUT1
2
VSW1
3
2
VSW1
M400ns
T 10.20%
A CH2
2.20V
Figure 23. Typical Waveforms, VOUT1 = 3.3 V, Load Current = 50 mA,
PWM Mode
CH3 1.0V
CH2 50.0mV
CH4 2.0V
M1ms
T 10.10%
A CH3
5.08V
12604-026
CH1 50mV CH2 2.0V
CH3 500mA
12604-023
4
Figure 26. BUCK1 Response to Line Transient, Input Voltage from 4.5 V to
5.5 V, VOUT1 = 3.3 V, Load Current = 50 mA, PWM Mode
Rev. 0 | Page 10 of 24
Data Sheet
ADP5135
T
T
VIN2
VOUT2
1
IOUT2
VOUT2
2
VSW2
3
VSW2
3
4
CH2 50.0mV
CH4 2.0V
M1ms
T 10.10%
A CH3
5.08V
CH1 100mV CH2 2.0V
CH3 100mA
Figure 27. BUCK2 Response to Line Transient, Input Voltage from 4.5 V to
5.5 V, VOUT2 = 1.8 V, Load Current = 50 mA, PWM Mode
M200µs
T 10.0%
A CH3
140mA
12604-030
CH3 1.0V
12604-027
2
Figure 30. BUCK2 Response to Load Transient, Load Current from 50 mA to
200 mA, VOUT2 = 1.8 V, Auto Mode
T
T
VIN3
VOUT3
1
VOUT3
IOUT3
2
VSW3
3
VSW3
3
4
CH2 50.0mV
CH4 2.0V
M1ms
T 9.7%
A CH3
4.38V
CH1 100mV CH2 2.0V
CH3 200mA
Figure 28. BUCK3 Response to Line Transient, Input Voltage from 4.0 V to
5.0 V, VOUT3 = 1.2 V, Load Current = 50 mA, PWM Mode
M200µs
T 10.2%
A CH3
152mA
12604-031
CH3 1.0V
12604-028
2
Figure 31. BUCK3 Response to Load Transient, Load Current from 1 mA to
200 mA, VOUT3 = 1.2 V, Auto Mode
T
T
VOUT1
VOUT2
1
1
IOUT1
IOUT2
3
3
VSW2
VSW1
2
M200µs
T 10.1%
A CH3
30mA
CH1 50mV CH2 2.0V
CH3 200mA
Figure 29. BUCK1 Response to Load Transient, Load Current from 1 mA to
50 mA, VOUT1 = 3.3 V, Auto Mode
M200µs
T 10.0%
A CH3
136mA
12604-032
CH1 100mV CH2 5.0V
CH3 50mA
12604-029
2
Figure 32. BUCK2 Response to Load Transient, Load Current from 1 mA to
200 mA, VOUT3 = 1.2 V, PWM Mode
Rev. 0 | Page 11 of 24
ADP5135
Data Sheet
300
210
180
250
150
RDSON (mΩ)
RDSON (mΩ)
200
150
120
90
100
60
0
3.0
3.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE (V)
Figure 33. LFCSP PMOS RDSON vs. Input Voltage Across Temperature
TA = +125°C
TA = +85°C
TA = +25°C
TA = –40°C
30
0
3.0
12604-033
50
3.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE (V)
Figure 34. LFCSP NMOS RDSON vs. Input Voltage Across Temperature
Rev. 0 | Page 12 of 24
12604-034
TA = +125°C
TA = +85°C
TA = +25°C
TA = –40°C
Data Sheet
ADP5135
THEORY OF OPERATION
VOUT1 FB1 FB2 VOUT2
AVIN
ADP5135
GM ERROR
AMP
ENBK1
75Ω
ENBK2
75Ω
GM ERROR
AMP
PWM
COMP
PWM
COMP
VIN1
SOFT START
SOFT START
PSM
COMP
PSM
COMP
VIN2
ILIMIT
ILIMIT
LOW
CURRENT
PWM/
PSM
CONTROL
BUCK2
PWM/
PSM
CONTROL
BUCK1
LOW
CURRENT
SW2
SW1
OSCILLATOR
DRIVER
AND
ANTISHOOT
THROUGH
SYSTEM
UNDERVOLTAGE
LOCKOUT
EN2
EN3
SHUTDOWN
AND
PRECISION
ENABLE
CONTROL
POWER
GOOD
CONTROL
PGND2
MODE2
A
VOUT3
PWM
COMP
ENBK2
ENBK3
GM ERROR
AMP
ILIMIT
PG3
Y
B
MODE
ENBK1
FB1
PG1
PG2
SEL
THERMAL
SHUTDOWN
PGND1
EN1
DRIVER
AND
OP
ANTISHOOT
MODE THROUGH
FB2
PWM/
PSM
CONTROL
BUCK3
ENBK3
FB3
75Ω
SOFT START
FB3
LOW
CURRENT
PSM
COMP
NOTES
1. ENBKx ENABLES BUCKx.
VIN3
12604-035
DRIVER
AND
ANTISHOOT
THROUGH
SW3 PGND3
Figure 35. Detailed Functional Block Diagram
POWER MANAGEMENT UNIT
The ADP5135 is a micropower management unit (micro PMU)
combining three step-down (buck) dc-to-dc converters. The
high switching frequency and tiny 24-lead LFCSP package
provide a small power management solution.
A system controller combines these high performance
regulators in the micro PMU, allowing them to operate
together.
The buck regulators can operate in forced PWM mode if the
MODE pin is at a logic high level. In forced PWM mode, the
buck switching frequency is always constant and does not
change with the load current. If the MODE pin is at a logic low
level, the switching regulators operate in auto PWM/PSM
mode. In this mode, the regulators operate at a fixed PWM
frequency when the load current is above the PSM current
threshold. When the load current falls below the PSM current
threshold, the regulator enters PSM, where the switching occurs
in bursts. The burst repetition rate is a function of the current
load and the output capacitor value. This operating mode
reduces the switching and quiescent current losses. The auto
PWM/PSM mode transition is controlled independently for
each buck regulator. BUCK1 and BUCK2 operate in phase with
the internal clock, and BUCK3 operates out of phase from it.
The ADP5135 has individual enable pins (EN1, EN2, and EN3)
controlling the activation of each regulator. The regulators are
activated by a logic high level applied to the respective ENx pin.
EN1 controls BUCK1, EN2 controls BUCK2, and EN3 controls
BUCK3.
Rev. 0 | Page 13 of 24
ADP5135
Data Sheet
Regulator output voltages are set through external resistor
dividers or can be optionally factory programmed to default
values (see the Ordering Guide section).
When a regulator is turned on, the output voltage ramp rate is
controlled through a soft start circuit to avoid a large inrush
current caused by the charging of the output capacitors.
Power-Good Output
Power-good outputs are available for each buck channel to
monitor their respective output voltages. The PGx pin connects
to a pull-up current to drive external regulators or other
circuits. In this configuration, the PGx pin goes high when the
channel being monitored is in regulation and goes low when the
output voltage falls below 85% of the nominal VOUTx level.
The PGx pin can also drive an LED for fault monitoring. In this
configuration, a red LED, for example, is biased and current
sinks into the PGx pin when the output voltage falls below 85%
of the nominal VOUTx level, thereby turning the LED on, and
turns off when the output voltage is in regulation.
Thermal Protection
In the event that the junction temperature rises above 150°C,
the thermal shutdown circuit turns off all the regulators. Extreme
junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature.
A 20°C hysteresis is included so that when thermal shutdown
occurs, the regulators do not return to operation until the on-chip
temperature drops below 130°C. When coming out of thermal
shutdown, all regulators restart with soft start control.
Undervoltage Lockout
To protect against battery discharge, undervoltage lockout
(UVLO) circuitry is integrated into the system. If the input
voltage on AVIN drops below the UVLO threshold, 2.45 V
minimum, all channels shut down. In the buck channels, both
the power switch and the synchronous rectifier turn off. When
the voltage on AVIN rises above the UVLO threshold, the
device is enabled once more.
Alternatively, the user can request a new device model with a
UVLO set at a higher level, suitable for 5 V supply applications,
or to a lower level, suitable for low voltage operations. To order
a device with options other than the default options listed in the
Ordering Guide section, contact your local Analog Devices,
Inc., sales or distribution representative.
In case of a thermal or UVLO event, the active pull-downs (if
factory enabled) are enabled to quickly discharge the output
capacitors. The pull-down resistors remain engaged until the
thermal fault event is no longer present or when the input
supply voltage falls below the power-on reset voltage level
(VPOR). The typical value of VPOR is approximately 1 V.
Precision Enable and Shutdown Control
The ADP5135 has an individual enable control pin for each
regulator. A voltage input to the ENx pin above the VIH_EN level
puts the device out of shutdown and turns on the housekeeping
block of the ADP5135. As the VENx level continues to rise above
the precision enable threshold (VENR), the regulators activate.
When VENx goes 80 mV typical below the VENR level, the
regulators deactivate and, when all VENx levels continue to go
down below the VIL_EN level, the device goes into shutdown
mode. In this mode, the current consumption of the device
drops to below 1.5 μA.
Figure 36 shows the activation timings for the ADP5135 when
the regulators are in sequence. VOUT1 is controlling EN2, and
VOUT2 is controlling EN3. Also shown are the individual powergood signals (PGx) monitoring all regulators.
Rev. 0 | Page 14 of 24
Data Sheet
ADP5135
EN1
4
2
0
4
2
0
PE_GOOD_BUCK1
VOUT1
1
0
EN2
1
0
PE_GOOD_BUCK2
4
2
0
4
2
0
VOUT2
EN3
1
0
4
2
0
2
1
0
4
2
0
4
2
0
4
2
0
0.1
PE_GOOD_BUCK3
VOUT3
PG1
PG2
PG3
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
TIME (ms)
NOTES
1. PE_GOOD_BUCKx ARE INTERNAL SIGNALS.
1.9
2.0
12604-036
0.2
Figure 36. Regulator Sequencing on the ADP5135, Showing Precision Enable (PE) Thresholds, with Power Good
BUCK REGULATORS: BUCK1, BUCK2, AND BUCK3
Control Scheme
The buck regulators use a fixed frequency and high speed
current mode architecture. The buck operates with an input
voltage of 3.0 V to 5.5 V.
The buck regulators operate with a fixed frequency, current
mode PWM control architecture at medium to high loads for
high efficiency but shift to a power save mode (PSM) control
scheme at light loads to lower the regulation power losses.
When operating in fixed frequency PWM mode, the duty cycle
of the integrated switches is adjusted and regulates the output
voltage. When operating in PSM at light loads, the output
voltage is controlled in a hysteretic manner, with higher output
voltage ripple. During this time, the converter is able to stop
switching and enters an idle mode, which improves conversion
efficiency.
The buck regulator output voltage is resistor programmable
from 0.8 V up to 3.8 V, shown in Figure 37 for BUCK1. The
ratio of R1 and R2 multiplied by the feedback voltage
determines the voltage level at the output. If, for example, R1
and R2 have equal resistance values, the output voltage is set to
1.0 V. The output voltage can optionally be factory programmed
to default values, as indicated in the Ordering Guide section. In
this event, R1 and R2 are not needed, and FB1 can be left
unconnected. In all cases, VOUT1 must be connected to the
output capacitor. FB1 is 0.5 V.
VOUT1
VIN1
SW1
L1
1µH
VOUT1
BUCK1
AGND
VOUT1 = VFB1
R1
C2
22µF
R2
R1
+1
R2
Figure 37. BUCK1 External Output Voltage Setting
12604-037
FB1
PWM Mode
In PWM mode, the bucks operate at a fixed frequency of 3 MHz
set by an internal oscillator. At the start of each oscillator cycle,
the PFET switch turns on, sending a positive voltage across the
inductor. Current in the inductor increases until the current
sense signal crosses the peak inductor current threshold that
turns off the PFET switch and turns on the NFET synchronous
rectifier, sending a negative voltage across the inductor and
causing the inductor current to decrease. The synchronous
rectifier stays on for the rest of the cycle. The buck regulators
regulate the output voltage by adjusting the peak inductor
current threshold.
Rev. 0 | Page 15 of 24
ADP5135
Data Sheet
Power Save Mode (PSM)
Short-Circuit Protection
The buck regulators smoothly transition to PSM operation
when the load current decreases below the PSM current
threshold. When any of the bucks enters PSM, an offset is
induced in the PWM regulation level, which makes the output
voltage rise. When the output voltage reaches a level that is
approximately 1.5% above the PWM regulation level, PWM
operation turns off. At this point, both power switches are off,
and the buck regulators enter an idle mode. The output
capacitor discharges until the output voltage falls to the PWM
regulation voltage, at which point the device drives the inductor
to make the output voltage rise again to the upper threshold.
This process is repeated while the load current is below the
PSM current threshold.
The bucks include frequency foldback to prevent output current
runaway on a hard short. When the voltage at the feedback pin
falls below half the target output voltage, indicating the possibility of a hard short at the output, the switching frequency is
reduced to half the internal oscillator frequency. The reduction
in the switching frequency allows more time for the inductor to
discharge, preventing a runaway of output current.
The ADP5135 has a dedicated MODE pin controlling the PSM
and PWM operations. A logic high level applied to the MODE
pin forces all bucks to operate in PWM mode. A logic low level
sets the bucks to operate in auto PSM/PWM.
PSM Current Threshold
The PSM current threshold is set to 100 mA. The buck regulators
employ a scheme that enables this current to remain accurately
controlled, independent of input and output voltage levels. This
scheme also ensures that there is very little hysteresis between
the PSM current threshold for entry to and exit from PSM. The
PSM current threshold is optimized for excellent efficiency over
all load currents.
Oscillator/Phasing of Inductor Switching
The ADP5135 ensures that all three bucks operate at the same
switching frequency when all bucks are in PWM mode.
Additionally, the ADP5135 ensures that when all bucks are in
PWM mode, BUCK3 operates out of phase with BUCK1 and
BUCK2, whereby the BUCK3 PFET starts conducting exactly
half a clock period after the BUCK1 and BUCK2 PFETs start
conducting.
Buck Regulator Soft Start
The buck regulators have an internal soft start function that
ramps the output voltage in a controlled manner upon startup,
thereby limiting the inrush current. This prevents possible input
voltage drops when a battery or a high impedance power source
is connected to the input of the converter.
Current Limit
Each buck regulator has protection circuitry to limit the
amount of positive current flowing through the PFET switch
and the amount of negative current flowing through the
synchronous rectifier. The positive current limit on the power
switch limits the amount of current that can flow from the input
to the output. The negative current limit prevents the inductor
current from reversing direction and flowing out of the load.
100% Duty Operation
With a drop in input voltage, or with an increase in load
current, the buck regulators may reach a limit where, even with
the PFET switch on 100% of the time, the output voltage drops
below the desired output voltage. At this limit, the buck
regulators transition to a mode where the PFET switch stays on
100% of the time. When the input conditions change again and
the required duty cycle falls, the buck regulators immediately
restart PWM regulation without allowing overshoot on the
output voltage.
Active Pull-Down Resistors
All regulators have optional, factory programmable, active pulldown resistors that discharge the respective output capacitors
when the regulators are disabled. The pull-down resistors are
connected between VOUTx and AGND. The active pull-down
resistors are disabled when the regulators are turned on. The
typical value of the pull-down resistor is 75 Ω.
Rev. 0 | Page 16 of 24
Data Sheet
ADP5135
APPLICATIONS INFORMATION
BUCK EXTERNAL COMPONENT SELECTION
Trade-offs between performance parameters such as efficiency
and transient response can be made by varying the choice of
external components in the applications circuit, as shown in
Figure 1.
Feedback Resistors
For the adjustable model, the total combined resistance for R1
and R2 must not to exceed 400 kΩ (see Figure 37).
Inductor
The high switching frequency of the ADP5135 buck regulators
allows the selection of small chip inductors. For best performance,
use inductor values between 0.7 μH and 3 μH. Suggested inductors are shown in Table 8 and Table 9.
The peak-to-peak inductor current ripple (IRIPPLE) is calculated
using the following equation:
I RIPPLE
VOUT (VIN VOUT )
VIN f SW L
The worst-case capacitance accounting for capacitor variation
over temperature, component tolerance, and voltage is calculated using the following equation:
CEFF = COUT × (1 − TEMPCO) × (1 − TOL)
where:
CEFF is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient
(TEMPCO) over −40°C to +85°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and COUT is 9.2 μF at 1.8 V, as shown in Figure 38.
where:
fSW is the switching frequency.
L is the inductor value.
The minimum dc current rating of the inductor must be greater
than the inductor peak current. The inductor peak current
(IPEAK) is calculated using the following equation:
I PEAK I LOAD( MAX )
Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and
applied voltage. Capacitors must have a dielectric adequate
to ensure the minimum capacitance over the necessary
temperature range and dc bias conditions. X5R or X7R
dielectrics with a voltage rating of 6.3 V or 10 V are recommended for best performance. Y5V and Z5U dielectrics are
not recommended for use with any dc-to-dc converter because
of their poor temperature and dc bias characteristics.
I RIPPLE
2
Substituting these values in the equation yields
CEFF = 9.2 μF × (1 − 0.15) × (1 − 0.1) ≈ 7.0 μF
To guarantee the performance of the bucks, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
12
Inductor conduction losses are caused by the flow of current
through the inductor, which has an associated internal dc
resistance (DCR). Larger sized inductors have smaller DCR,
which may decrease inductor conduction losses. Inductor core
losses are related to the magnetic permeability of the core material.
Because the bucks are high switching frequency dc-to-dc
converters, shielded ferrite core material is recommended for
its low core losses and low electromagnetic interference (EMI).
CAPACITANCE (µF)
10
8
6
4
Output Capacitor
0
0
1
2
3
4
5
DC BIAS VOLTAGE (V)
6
12604-038
2
Higher output capacitor values reduce the output voltage ripple
and improve load transient response. When choosing this value,
it is also important to account for the loss of capacitance due to
output voltage dc bias.
Figure 38. Capacitance vs. DC Bias Voltage
Table 8. Suggested 1.0 μH Inductors
Vendor
Murata
Wurth Electronics
Coilcraft®
1
Model
LQM2HPN1R0MJHL
74438323010
XFL4020-102ME
Dimensions (mm)
2.5 × 2.0 × 1.2
2.5 × 2.0 × 1.0
4.0 × 4.0 × 2.1
ISAT is the saturation current.
Rev. 0 | Page 17 of 24
ISAT (mA)1
3500
4000
5100
DCR (mΩ)
50
75
11.9
ADP5135
Data Sheet
Table 9. Suggested 2.2 μH Inductors
Vendor
Wurth Electronics
TDK
Taiyo Yuden
Coilcraft
1
Model
74438335022
VLCF5020T-2R2N2R6-1
NP04SZB2R2N
XFL4020-222ME
ISAT (mA)1
3500
2620
2700
3500
Dimensions (mm)
3.0 ×3.0 × 1.5
5.0 × 5.0 × 2.0
5.0 × 5.0 × 2.0
4.0 × 4.0 × 2.1
DCR (mΩ)
108
71
42
23.5
ISAT is the saturation current.
The peak-to-peak output voltage ripple for the selected output
capacitor and inductor values is calculated using the following
equation:
VRIPPLE
I RIPPLE
VIN
8 f SW COUT 2 f SW 2 L COUT
Table 10. Suggested 22 μF Capacitors
Capacitors with lower effective series resistance (ESR) are
preferred to guarantee low output voltage ripple, as shown in
the following equation:
ESRCOUT
VRIPPLE
I RIPPLE
Vendor
Murata
TDK
Taiyo
Yuden
Type
X5R
X5R
X5R
Model
GRM188R60G226MEA0D
C1608X5R0J226M080AC
LMK212BJ226MG-T
Case
Size
0603
0603
0805
Voltage
Rating (V)
6.3
6.3
10.0
Table 11. Suggested 10 μF Capacitors
The effective COUT needed for stability, which includes
temperature and dc bias effects, is a minimum of 7 μF and a
maximum of 40 μF.
The buck regulators require 10 μF output capacitors to guarantee stability and response to rapid load variations. To transition
into and out of the PWM/PSM modes, a 22 μF output capacitor
can be used for applications that require larger load steps. A list of
suggested capacitors is shown in Table 10. In certain applications
where one or all buck regulators power a processor, the operating state is known because it is controlled by software. In this
condition, the processor can drive the MODE pin according to the
operating state; consequently, it is possible to reduce the output
capacitor from 10 μF to 4.7 μF because the regulator does not
expect a large load variation when working in PSM mode.
Input Capacitor
Higher value input capacitors help to reduce the input voltage
ripple and improve transient response. The maximum input
capacitor current is calculated using the following equation:
I CIN I LOAD( MAX)
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 3 μF and a
maximum of 10 μF. A list of suggested capacitors is shown in
Table 11 and Table 12.
VOUT (VIN VOUT )
VIN
Vendor
Murata
TDK
Taiyo Yuden
Panasonic
Type
X5R
X5R
X5R
X5R
Model
GRM188R60J106
C1608JB0J106K
JMK107BJ106MA-T
ECJ1VB0J106M
Case
Size
0603
0603
0603
0603
Voltage
Rating (V)
6.3
6.3
6.3
6.3
Table 12. Suggested 4.7 μF Capacitors
Vendor
Murata
Taiyo Yuden
Panasonic
Type
X5R
X5R
X5R
Model
GRM188R60J475ME19D
JMK107BJ475
ECJ-0EB0J475M
Case
Size
0402
0402
0402
Voltage
Rating (V)
6.3
6.3
6.3
Case
Size
0402
0402
0402
0402
0402
Voltage
Rating (V)
6.3
10.0
6.3
6.3
10.0
Table 13. Suggested 1.0 μF Capacitors
Vendor
Murata
Murata
TDK
Panasonic
Taiyo
Yuden
To minimize supply noise, place the input capacitor as close as
possible to the VINx pin of the buck regulator. As with the
output capacitor, a low ESR capacitor is recommended.
Rev. 0 | Page 18 of 24
Type
X5R
X5R
X5R
X5R
X5R
Model
GRM155B30J105K
GRM155R61A105KE15D
C1005JB0J105KT
ECJ0EB0J105K
LMK105BJ105MV-F
Data Sheet
ADP5135
TYPICAL APPLICATION SCHEMATICS
ADP5135
3.0V
TO
5.5V
AVIN
C7
0.1µF
AGND
VIN1
C1
10µF
PGND1
ON
EN1
OFF
17
FPGA
HOUSEKEEPING
18
10
16
15
14
BUCK1
1.8A
11
C3
10µF
PGND2
ON
EN2
OFF
VIN3
C5
10µF
PGND3
R2
ON
EN3
OFF
9
BUCK2
1.8A
4
7
8
21
22
19
R1
FB1
VIO
C2
22µF
PWM
3
5
L1 1µH
SW1
12
13
VIN2
VDDIO
VOUT1
AUTO
MODE
GPOx
VOUT2
L2 1µH
SW2
R3
FB2
R4
BUCK3
1.8A
20
23
VCORE
C4
22µF
VOUT3
L3 1µH
SW3
VMEM
R5
FB3
24
R6
C6
22µF
POWER GOOD
6
2
1
R7
100Ω
PG1
PG2
R8
100Ω
PG3
R9
100Ω
GPIx
12604-039
VDDIO
Figure 39. Processor System Power Management with PSM/PWM Control and Power Good
ADP5135
AVIN
C7
0.1µF
AGND
VIN1
C1
10µF
PGND1
ON
EN1
OFF
17
HOUSEKEEPING
18
10
16
14
FPGA
15
BUCK1
1.8A
11
C3
10µF
VEN2
PGND2
R10
EN2
R1
FB1
R2
9
BUCK2
1.8A
4
8
7
MODE
VIN3
VEN3
PGND3
R12
EN3
GPOx
TO VEN3
SW2
FB2
L2 1µH
R3
R4
22
21
19
AUTO
VOUT2
R11
C5
10µF
VIO
C2
22µF
PWM
3
5
L1 1µH
SW1
12
13
VIN2
TO VEN2
VOUT1
BUCK3
1.8A
20
23
VCORE
C4
22µF
VOUT3
SW3
FB3
24
L3 1µH
VMEM
R5
R6
C6
22µF
R13
VDDIO
POWER GOOD
6
2
1
PG1
R7
100Ω
R8
100Ω
R9
100Ω
PG2
PG3
Figure 40. ADP5135 Adjustable Output Voltages with Precision Enable Pins
Rev. 0 | Page 19 of 24
GPIx
12604-040
3.0V
TO
5.5V
ADP5135
Data Sheet
ADP5135
AVIN
C7
0.1µF
AGND
VIN1
C1
10µF
PGND1
ON
EN1
OFF
17
HOUSEKEEPING
18
10
16
14
FPGA
15
BUCK1
1.8A
11
C3
10µF
VEN2
PGND2
R10
EN2
VIO
FB1
C2
22µF
PWM
3
5
L1 1µH
SW1
12
13
VIN2
TO VEN2
VOUT1
9
BUCK2
1.8A
4
7
8
21
22
MODE
AUTO
GPOx
TO VEN3
VOUT2
SW2
L2 1µH
VCORE
FB2
C4
22µF
R11
VIN3
C5
10µF
VEN3
PGND3
R12
EN3
19
BUCK3
1.8A
20
23
VOUT3
SW3
L3 1µH
VMEM
FB3
C6
22µF
24
R13
VDDIO
POWER GOOD
6
2
1
PG1
R7
100Ω
R8
100Ω
R9
100Ω
PG2
PG3
Figure 41. ADP5135 Fixed Output Voltages with Precision Enable Pins
Rev. 0 | Page 20 of 24
GPIx
12604-041
3.0V
TO
5.5V
Data Sheet
ADP5135
POWER DISSIPATION AND THERMAL CONSIDERATIONS
The ADP5135 is a highly efficient micro PMU and, in most
cases, the power dissipated in the device is not a concern.
However, if the device operates at high ambient temperatures
and maximum loading conditions, the junction temperature
can reach the maximum allowable operating limit (125°C).
BUCK REGULATOR POWER DISSIPATION
The inductor losses are external to the device, and they do not
have any effect on the die temperature.
The inductor losses are estimated (without core losses) by
When the temperature exceeds 150°C, the ADP5135 turns off
all the regulators, allowing the device to cool down. When the
die temperature falls below 130°C, the ADP5135 resumes
normal operation.
This section provides guidelines to calculate the power dissipated in the device and to ensure that the ADP5135 operates
below the maximum allowable operating junction temperature.
The efficiency for each regulator on the ADP5135 is given by
POUT
100%
PIN
where:
IOUT1(RMS) is the rms load current of the buck regulator.
DCRL is the inductor series resistance.
I OUT1( RMS) I OUT1 1 +
r
12
(4)
where r is the normalized inductor ripple current.
(5)
where:
L is the inductance.
fSW is the switching frequency.
D is the duty cycle.
D = VOUT1/VIN1
(6)
The power loss of the buck regulator is approximated by
Power loss is given by
PLOSS = PDBUCK + PL
(2a)
or
PLOSS = POUT (1− η)/η
(3)
r = VOUT1 × (1 − D)/(IOUT1 × L × fSW)
(1)
where:
η is the efficiency.
POUT is the output power.
PIN is the input power.
PLOSS = PIN − POUT
PL ≈ IOUT1(RMS)2 × DCRL
(2b)
Power dissipation can be calculated in several ways. The most
intuitive and practical is to measure the power dissipated at the
input and all the outputs. Perform the measurements at the
worst-case conditions (voltages, currents, and temperature).
The difference between input and output power is dissipated in
the device and the inductor. Use Equation 3 to derive the power
lost in the inductor and, from this, use Equation 7 to calculate
the power dissipation in the ADP5135 buck converter.
(7)
where:
PDBUCK is the power dissipation on one of the ADP5135 buck
regulators.
PL is the inductor power losses.
The ADP5135 buck regulator power dissipation, PDBUCK,
includes the power switch conductive losses, the switch losses, and
the transition losses of each channel. There are other sources of
loss, but these are generally less significant at high output load
currents, where the thermal limit of the application is. Equation 8
captures the calculation that must be made to estimate the
power dissipation in the buck regulator.
A second method to estimate the power dissipation uses the
efficiency curves provided for the buck regulator. When the
buck efficiency is known, use Equation 2b to derive the total
power lost in the buck regulator and inductor, use Equation 3 to
derive the power lost in the inductor, and then calculate the
power dissipation in the buck converter using Equation 7. Add
the power dissipated in the three bucks to find the total
dissipated power.
The power switch conductive losses are due to the output current,
IOUT1, flowing through the P-channel MOSFET and the N-channel
MOSFET power switches that have internal resistance, RDSON_P
and RDSON_N, respectively. The amount of conductive power
loss is found by
Note that the buck efficiency curves are typical values and may
not be provided for all possible combinations of VIN, VOUT, and
IOUT. To account for these variations, it is necessary to include a
safety margin when calculating the power dissipated in the buck.
where RDSON_P is approximately 0.19 Ω, RDSON_N is approximately 0.14 Ω at a 25°C junction temperature, and VIN1 = VIN2 =
3.6 V. At VIN1 = VIN2 = 5.5 V, the values are 0.147 Ω and 0.122 Ω,
respectively.
PDBUCK = PCOND + PSW + PTRAN
PCOND = [RDSON_P × D + RDSON_N × (1 − D)] × IOUT1(RMS)2
A third way to estimate the power dissipation is analytical and
involves modeling the losses in the buck circuit provided by
Equation 8 to Equation 11.
Rev. 0 | Page 21 of 24
(8)
(9)
ADP5135
Data Sheet
Switching losses are associated with the current drawn by the
driver to turn on and turn off the power devices at the switching
frequency. The amount of switching power loss is given by
PSW = (CGATE_P + CGATE_N) × VIN12 × fSW
(10)
where:
CGATE_P is the P-channel MOSFET gate capacitance.
CGATE_N is the N-channel MOSFET gate capacitance.
The transition losses occur because the P-channel power
MOSFET cannot be turned on or off instantaneously, and the
SWx node takes some time to slew from near ground to near
VOUT1 (and from VOUT1 to ground). The amount of transition
loss (PTRAN) is calculated by
(11)
where tRISE and tFALL are the rise time and the fall time,
respectively, of the switching node, SWx. For the ADP5135, the
rise and fall times of SWx are in the order of 5 ns.
If Equation 1 to Equation 11 and their associated parameters are
used for estimating the converter efficiency, note that the
equations do not describe all of the converter losses, and the
parameter values given are typical numbers. The converter
performance also depends on the choice of passive components
and board layout; therefore, include a sufficient safety margin in
the estimate.
The total power dissipation in the ADP5135 simplifies to
PD = PDBUCK1 + PDBUCK2 + PDBUCK3
In cases where the board temperature, TA, is known, the
thermal resistance parameter, θJA, can be used to estimate the
junction temperature rise. TJ is calculated from TA and PD using
the formula
TJ = TA + (PD × θJA)
For the ADP5135, the total of (CGATE_P + CGATE_N) is
approximately 150 pF.
PTRAN = VIN1 × IOUT1 × (tRISE + tFALL) × fSW
JUNCTION TEMPERATURE
(12)
(13)
Refer to Table 6 for the thermal resistance values of the LFCSP
package. A very important factor to consider is that θJA is based
on a 4-layer, 4 in × 3 in, 2.5 oz copper printed circuit board
(PCB), as per JEDEC standard, and real applications may use
different sizes and layers. It is important to maximize the copper
used to remove the heat from the device. Copper exposed to air
dissipates heat better than copper used in the inner layers.
Solder the exposed pad to the ground plane with several vias.
If the case temperature can be measured, the junction
temperature is calculated by
TJ = TC + (PD × θJC)
(14)
where TC is the case temperature and θJC is the junction to case
thermal resistance provided in Table 6.
When designing an application for a particular ambient temperature range, calculate the expected ADP5135 power dissipation
(PD) due to the losses of all channels by using Equation 8 to
Equation 12. From this power calculation, the junction temperature, TJ, can be estimated using Equation 13.
The reliable operation of the converter can be achieved only
if the estimated die junction temperature of the ADP5135
(Equation 14) is less than 125°C. Reliability and mean time
between failures (MTBF) are highly affected by increasing the
junction temperature. Additional information about product
reliability can be found in the ADI Reliability Handbook at
www.analog.com/UG-311.
Rev. 0 | Page 22 of 24
Data Sheet
ADP5135
PCB LAYOUT GUIDELINES
Poor layout can affect ADP5135 performance, causing EMI and
electromagnetic compatibility (EMC) problems, ground
bounce, and voltage losses. Poor layout can also affect
regulation and stability. A good layout is implemented using the
following guidelines. Also, refer to the ADP5135CP-EVALZ
user guide.
Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies, and large tracks act as antennas.
Route the output voltage path away from the inductor and
SWx node to minimize noise and magnetic interference.
Maximize the size of ground metal on the component side
to help with thermal dissipation.
Rev. 0 | Page 23 of 24
Connect VIN1, VIN2, VIN3, and AVIN together close to
the IC using short tracks.
Use a ground plane with several vias connecting to the
component side ground to further reduce noise
interference on sensitive circuit nodes.
For best performance, connect the input capacitors very
close to the pins as follows: place the AVIN capacitor
between the AVIN and AGND pins, place the VIN1
capacitor between the VIN1 and PGND1 pins, place the
VIN2 capacitor between the VIN2 and PGND2 pins, and
place the VIN3 capacitor between VIN3 and PGND3.
ADP5135
Data Sheet
OUTLINE DIMENSIONS
0.30
0.25
0.18
1
0.50
BSC
2.70
2.60 SQ
2.50
EXPOSED
PAD
13
TOP VIEW
0.80
0.75
0.70
6
12
7
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
PKG-004273
0.50
0.40
0.30
PIN 1
INDICATOR
24
19
18
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8.
12-03-2013-A
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
Figure 42. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-24-15)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADP5135ACPZ-R7
ADP5135CP-EVALZ
Temperature
Range
−40°C to +125°C
Output Voltage2
Adjustable
UVLO3
Mid
Active Pull-Down4
Enabled on all channels
1
Package Description
24-Lead LFCSP_WQ
Evaluation Board
Z = RoHS Compliant Part.
For additional options, contact a local sales or distribution representative. Additional options available are:
BUCK1, BUCK2, BUCK3: 3.3 V, 3.0 V, 2.8 V, 2.5 V, 2.3 V, 2.0 V, 1.8 V, 1.6 V, 1.5 V, 1.4 V, 1.3 V, 1.2 V, 1.1 V, 1.0 V, 0.9 V, or adjustable.
3
UVLO: low, mid, or high. To order a device with other than the default options listed, contact your local Analog Devices sales or distribution representative.
4
BUCK1, BUCK2, BUCK3: active pull-down resistor is programmable to be either enabled or disabled.
2
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12604-0-11/14(0)
Rev. 0 | Page 24 of 24
Package
Option
CP-24-15
工商网监
湘ICP备2023018690号
