ADP5585CP-EVALZ

Keypad Decoder and I/O Expansion ADP5585 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VDD GND ADP5585 UVLO POR RST/R5 SDA OSCILLATOR I2C INTERFACE SCL INT KEY SCAN AND DECODE R0 R1 GPI SCAN AND DECODE R2 R3 R4 C0 C1 I/O CONFIG REGISTERS LOGIC PWM C2 C3 C4 RESET1 GEN RESET2 GEN 09841-001 16-element FIFO for event recording 10 configurable I/Os allowing functions such as Key pad decoding for a matrix of up to 5 × 5 11 GPIOs (5 × 6) with ADP5585ACxZ-01-R7 models Key press/release interrupts GPIO functions GPI with selectable interrupt level 100 kΩ or 300 kΩ pull-up resistors 300 kΩ pull-down resistors GPO with push-pull or open-drain Programmable logic block PWM generator Internal PWM generation External PWM with internal PWM AND function Reset generators I2C interface with fast mode plus (Fm+) support of up to 1 MHz Open-drain interrupt output 16-ball WLCSP, 1.59 mm × 1.59 mm 16-lead LFCSP, 3 mm × 3 mm Figure 1. APPLICATIONS Keypad entries and input/output expansion capabilities Smart phones, remote controls, and cameras Healthcare, industrial, and instrumentation GENERAL DESCRIPTION The ADP5585 is a 10 input/output port expander with a built in keypad matrix decoder, programmable logic, reset generator, and PWM generator. Input/output expander ICs are used in portable devices (phones, remote controls, and cameras) and nonportable applications (healthcare, industrial, and instrumentation). I/O expanders can be used to increase the number of I/Os available to a processor or to reduce the number of I/Os required through interface connectors for front panel designs. The ADP5585 handles all key scanning and decoding and can flag the main processor via an interrupt line that new key events have occurred. GPI changes and logic changes can also be tracked Rev. C as events via the FIFO, eliminating the need to monitor different registers for event changes. The ADP5585 is equipped with a FIFO to store up to 16 events. Events can be read back by the processor via an I2C-compatible interface. The ADP5585 frees up the main processor from having to monitor the keypad, thereby reducing power consumption and/or increasing processor bandwidth for performing other functions. The programmable logic functions allow common logic requirements to be integrated as part of the GPIO expander, thus saving board area and cost. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADP5585 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Functional Description .....................................................................9 Applications ....................................................................................... 1 Event FIFO .....................................................................................9 Functional Block Diagram .............................................................. 1 Key Scan Control ...........................................................................9 General Description ......................................................................... 1 GPI Input ..................................................................................... 12 Revision History ............................................................................... 2 GPO Output ................................................................................ 12 Specifications..................................................................................... 3 Logic Blocks ................................................................................ 12 Timing Diagram ........................................................................... 4 PWM Block ................................................................................. 13 Absolute Maximum Ratings ............................................................ 5 Reset Blocks ................................................................................ 14 Thermal Resistance ...................................................................... 5 Register Interface ............................................................................ 15 ESD Caution .................................................................................. 5 Register Map ................................................................................... 17 Pin Configurations and Function Descriptions ........................... 6 Detailed Register Descriptions ................................................. 19 Theory of Operation ........................................................................ 7 Applications Diagram .................................................................... 36 Device Enable ................................................................................ 8 Outline Dimensions ....................................................................... 37 Device Overview .......................................................................... 8 Ordering Guide .......................................................................... 38 REVISION HISTORY 1/13—Rev. B to Rev. C Changes to Detailed Register Description Section .................... 19 Changes to Table 31 and Table 32 ................................................ 24 Changes to Table 33, Table 34, and Table 35 ............................... 25 Changes to Table 37 ........................................................................ 26 Changes to Table 39 ........................................................................ 27 Changes to Table 41 and Table 43 ................................................ 28 Changes to Table 45 ........................................................................ 29 Changes to Table 47 ........................................................................ 30 Changes to Table 64 ........................................................................ 34 Changes to Figure 27 ...................................................................... 36 7/12—Rev. A to Rev B Changes to Table 5 ............................................................................ 8 Updated Outline Dimensions ....................................................... 36 Changes to Ordering Guide .......................................................... 37 10/11—Rev. Sp0 to Rev. A Added 16-Lead LFCSP_WQ Package .............................. Universal Changes to Features Section ............................................................1 Added Figure 4; Renumbered Sequentially ...................................6 Changes to Table 4.............................................................................6 Changes to Device Enable Section and Table 5 .............................8 Change to General Section ............................................................ 11 Changes to Logic Blocks Section .................................................. 12 Changes to PWM Block Section .................................................. 13 Changes to Interrupts Section ...................................................... 14 Changes to Register Interface Section ......................................... 15 Changes to Figure 27...................................................................... 35 Updated Outline Dimensions ....................................................... 36 Changes to Ordering Guide .......................................................... 38 5/11—Revision Sp0: Initial Version Rev. C | Page 2 of 40 Data Sheet ADP5585 SPECIFICATIONS VDD = 1.8 V to 3.3 V, TA = TJ = −40°C to +85°C, unless otherwise noted 1. Table 1. Parameter SUPPLY VOLTAGE VDD Input Voltage Range Undervoltage Lockout Threshold SUPPLY CURRENT Standby Current Operating Current (One Key Press) Symbol VDD UVLOVDD ISTNBY ISCAN1 ISCAN2 ISCAN3 ISCAN4 PULL-UP, PULL-DOWN RESISTANCE Pull-Up Option 1 Option 2 Pull-Down INPUT LOGIC LEVEL (RST, SCL, SDA, R0, R1, R2, R3, R4, R5, C0, C1, C2, C3, C4) Input Voltage Logic Low Logic High Input Leakage Current (Per Pin) PUSH-PULL OUTPUT LOGIC LEVEL (R0, R1, R2, R3, R4, R5, C0, C1, C2, C3, C4) Output Voltage Logic Low UVLO active, VDD falling UVLO inactive, VDD rising Min 1.65 1.2 VDD = 1.65 V VDD = 3.3 V Scan = 10 ms, CORE_FREQ = 50 kHz, scan active, 300 kΩ pull-up, VDD = 1.65 V Scan = 10 ms, CORE_FREQ = 50 kHz, scan active, 100 kΩ pull-up, VDD = 1.65 V Scan = 10 ms, CORE_FREQ = 50 kHz, scan active, 300 kΩ pull-up, VDD = 3.3 V Scan = 10 ms, CORE_FREQ = 50 kHz, scan active, 100 kΩ pull-up, VDD = 3.3 V 50 150 150 VIL VIH VI-Leak VOL1 VOL2 Logic High Logic High Leakage Current (Per Pin) OPEN-DRAIN OUTPUT LOGIC LEVEL (INT, SDA) Output Voltage Logic Low INT SDA Logic High Leakage Current (Per Pin) Logic Propagation Delay FF Hold Time 2 FF Setup Time2 GPIO Debounce2 Internal Oscillator Frequency 3 Test Conditions/Comments VOH VOH-Leak VOL3 VOL4 VOH-Leak Typ Max Unit 3.6 1.3 1.4 1.6 V V V 1 1 30 4 10 40 μA µA µA 35 45 µA 75 85 μA 80 90 μA 100 300 300 150 450 450 kΩ kΩ kΩ 0.3 VDD 1 V V µA 0.4 V 0.5 V 1 V µA 0.7 VDD 0.1 Sink current = 10 mA, maximum of five GPIOs active simultaneously Sink current = 10 mA, all GPIOs active simultaneously Source current = 5 mA 0.7 VDD 0.1 ISINK = 10 mA ISINK = 20 mA 0.1 125 0 175 OSCFREQ 900 Rev. C | Page 3 of 40 1000 0.4 0.4 1 300 70 1100 V V µA ns ns ns µs kHz ADP5585 Data Sheet Parameter I2C TIMING SPECIFICATIONS Delay from UVLO/Reset Inactive to I2C Access SCL Clock Frequency SCL High Time SCL Low Time Data Setup Time Data Hold Time Setup Time for Repeated Start Hold Time for Start/Repeated Start Bus Free Time for Stop and Start Condition Setup Time for Stop Condition Data Valid Time Data Valid Acknowledge Rise Time for SCL and SDA Fall Time for SCL and SDA Pulse Width of Suppressed Spike Capacitive Load for Each Bus Line Symbol Test Conditions/Comments Min fSCL tHIGH tLOW tSU; DAT tHD; DAT tSU; STA tHD; STA tBUF tSU; STO tVD; DAT tVD; ACK tR tF tSP CB4 Typ 0 0.26 0.5 50 0 0.26 0.26 0.5 0.26 Max Unit 60 1000 μs kHz μs μs ns μs μs μs μs μs μs μs ns ns ns pF 0.45 0.45 120 120 50 550 0 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Typical values are at TA = 25°C, VDD = 1.8 V. Guaranteed by design. All timers are referenced from the base oscillator and have the same ±10% accuracy. 4 CB is the total capacitance of one bus line in picofarads. 2 3 TIMING DIAGRAM tF tR tSU; DAT 70% 30% SDA 70% 30% tF tHD; DAT tR 70% 30% SCL 70% 30% 70% 30% tHD; STA S tVD; DAT tHIGH 70% 30% tLOW NINTH CLOCK 1/fSCL FIRST CLOCK CYCLE tBUF SDA SCL Sr VIL = 0.3VDD tVD; ACK tSP tSU; STO 70% 30% P NINTH CLOCK VIH = 0.7VDD Figure 2. I2C Interface Timing Diagram Rev. C | Page 4 of 40 S 09841-002 tHD; STA tSU; STA Data Sheet ADP5585 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VDD to GND SCL, SDA, RST, INT, R0, R1, R2, R3, R4, C0, C1, C2, C3, C4 to GND Temperature Range Operating (Ambient) Operating (Junction) Storage 1 Rating −0.3 V to +4 V −0.3 V to (VDD + 0.3 V) −40°C to +85°C1 −40°C to +125°C −65°C to +150°C In applications where high power dissipation and poor thermal resistance are present, the maximum ambient temperature may need to be derated. Maximum ambient temperature (TA (MAX)) is dependent on the maximum operating junction temperature (TJ (MAXOP) = 125°C), the maximum power dissipation of the device (PD (MAX)), and the junction-to-ambient thermal resistance of the device/package in the application (θJA), using the following equation: TA (MAX) = TJ (MAXOP) − (θJA × PD (MAX)). Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to GND. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a printed circuit board (PCB) for surface-mount packages. Table 3. Thermal Resistance 16-Ball WLCSP Maximum Power Dissipation 16-Lead LFCSP Maximum Power Dissipation ESD CAUTION Rev. C | Page 5 of 40 θJA 62 70 67.154 70 Unit °C/W mW °C/W mW ADP5585 Data Sheet A SDA SCL GND R0 INT RST/R5 C0 R2 R1 C1 C2 R4 R3 C3 C4 C 13 GND R2 3 10 C4 R1 4 9 C3 TOP VIEW Not to Scale D NOTES 1. THE EXPOSED PAD IS NOT CONNECTED. IT IS RECOMMENDED TO CONNECT THE EXPOSED PAD TO GROUND FOR THERMAL DISSIPATION. 09841-003 TOP VIEW (BALL SIDE DOWN) Not to Scale 11 RST(R5) R0 5 B 12 VDD R3 2 Figure 3. WLCSP Pin Configuration 09841-027 VDD R4 1 C1 7 4 C2 8 3 C0 6 2 1 14 SDA 16 INT BALL A1 CORNER 15 SCL PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. LFCSP Pin Configuration Table 4. Pin Function Descriptions Pin No. WLCSP LFCSP D1 1 D2 2 Mnemonic R4 R3 C1 3 R2 C2 4 R1 B1 5 R0 B4 C3 C4 D3 D4 B3 6 7 8 9 10 11 C0 C1 C2 C3 C4 RST/R5 A1 A4 A2 A3 B2 12 13 14 15 16 EP VDD GND SDA SCL INT EP Description GPIO 5 (GPIO Alternate Function: RESET1). This pin functions as Row 4 when used as a keypad. GPIO 4 (GPIO Alternate Function: Logic Block Input LC, PWM_OUT). This pin functions as Row 3 when used as a keypad. GPIO 3 (GPIO Alternate Function: Logic Block Input LB). This pin functions as Row 2 when used as a keypad. GPIO 2 (GPIO Alternate Function: Logic Block Input LA). This pin functions as Row 1 when used as a keypad. GPIO 1 (GPIO Alternate Function: Logic Block Output LY). This pin functions as Row 0 when used as a keypad. GPIO 7. This pin functions as Column 0 when used as a keypad. GPIO 8. This pin functions as Column 1 when used as a keypad. GPIO 9. This pin functions as Column 2 when used as a keypad. GPIO 10 (GPIO Alternate Function: PWM_IN). This pin functions as Column 3 when used as a keypad. GPIO 11 (GPIO Alternate Function: RESET2). This pin functions as Column 4 when used as a keypad. Input Reset Signal. To expand the keypad matrix, select the ADP5585ACBZ-01-R7 or the ADP5585ACPZ-01-R7 device model for this pin to function as GPIO 6/Row 5. Supply Voltage Input. Ground. I2C Data Input/Output. I2C Clock Input. Open-Drain Interrupt Output. Exposed Pad. The exposed pad is not connected. It is recommended to connect the exposed pad to ground for thermal dissipation. Rev. C | Page 6 of 40 Data Sheet ADP5585 THEORY OF OPERATION VDD GND ADP5585 UVLO POR RST/R5 OSCILLATOR SDA I2C INTERFACE INT SCL I2C BUSY? R0 KEY EVENT R2 (RST/R5) (C0) (C1) (C2) (C3) (C4) R3 R4 C0 (R0) (R1) (R2) (R3) (R4) (RST/R5) C1 C2 C3 C4 I/O CONFIGURATION ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 COL 0 COL 1 COL 2 COL 3 COL 4 GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 GPIO 6 (C0) (C1) (C2) (C3) (C4) GPIO 7 GPIO 8 GPIO 9 GPIO 10 GPIO 11 (R1) (R2) (R3) LA LB LC (R0) LY (C3) PWM_IN (R3) PWM_OUT (R4) RESET1 (C4) RESET2 GPI EVENT FIFO UPDATE LOGIC EVENT KEY SCAN AND DECODE REGISTERS GPI SCAN AND DECODE LOGIC PWM RESET1 GEN RST (R5) RESET2 GEN 09841-004 (R0) (R1) (R2) (R3) (R4) R1 Figure 5. Internal Block Diagram Rev. C | Page 7 of 40 ADP5585 Data Sheet DEVICE ENABLE When sufficient voltage is applied to VDD and the RST pin is driven with a logic high level, the ADP5585 starts up in standby mode with all settings at default. The user can configure the device via the I2C interface. When the RST pin is low, the ADP5585 enters a reset state and all settings return to default. The RST pin features a debounce filter. If using the ADP5585ACBZ-01-R7 or ADP5585ACPZ-01-R7 device model, the RST pin acts as an extra row pin. Without a reset pin, the only method to reset the device is by bringing VDD below the UVLO threshold. DEVICE OVERVIEW The ADP5585 contains 10 multiconfigurable input/output pins. Each pin can be programmed to enable the device to carry out its various functions, as follows: • • • • • Keypad matrix decoding (five-column by five-row matrix maximum). General-purpose I/O expansion (up to 10 inputs/outputs). PWM generation. Logic function building blocks (up to three inputs and one output). Two reset generators. All 10 input/output pins have an I/O structure as shown in Figure 6. Each I/O can be pulled up with a 100 kΩ or 300 kΩ resistor or pulled down with a 300 kΩ resistor. For logic output drive, each I/O has a 5 mA PMOS source and a 10 mA NMOS sink for a pushpull type output. For open-drain output situations, the 5 mA PMOS source is not enabled. For logic input applications, each I/O can be sampled directly or, alternatively, sampled through a debounce filter. The I/O structure shown in Figure 6 allows for all GPI and GPO functions, as well as PWM and clock divide functions. For key matrix scan and decode, the scanning circuit uses the 100 kΩ or 300 kΩ resistor for pulling up keypad row pins and the 10 mA NMOS sinks for grounding keypad column pins (see the Key Scan Control section for details about key decoding). Configuration of the device is carried out by programming an array of internal registers via the I2C interface. Feedback of device status and pending interrupts can be flagged to an external processor by using the INT pin. The ADP5585 is offered with three feature sets. Table 5 lists the options that are available for each model of the ADP5585. Table 5. Matrix Options by Device Model Model ADP5585ACBZ-00-R7 ADP5585ACBZ-01-R7 ADP5585ACBZ-02-R7 VDD 100kΩ 300kΩ ADP5585ACBZ-04-R7 I/O ADP5585ACPZ-00-R7 300kΩ ADP5585ACPZ-01-R7 DEBOUNCE Figure 6. I/O Structure 09841-005 I/O DRIVE ADP5585ACPZ-03-R7 1 Description GPIO pull up (default option) 5-row × 5-column matrix Row 5 added to GPIOs 6-row × 5-column matrix No pull-up resistors to special function pins 1 5-row × 5-column matrix Pull-down resistors to all GPIO pins on start-up 5-row × 5-column matrix GPIO pull up (default option) 5-row × 5-column matrix Row 5 added to GPIOs 6-row × 5-column matrix Alternate I2C address (0x30) 5-row × 5-column matrix Special function pins are defined as R0, R3, R4, and C4. See Table 4 for details. Rev. C | Page 8 of 40 Data Sheet ADP5585 FUNCTIONAL DESCRIPTION EVENT FIFO EC = 3 Before going into detail on the various ADP5585 blocks, it is important to understand the function of the event FIFO. The ADP5585 features an event FIFO that can record as many as 16 events. By default, the FIFO primarily records key events, such as key press and key release. However, it is possible to configure the general-purpose input (GPI) and logic activity to generate event information on the FIFO as well. An event count, EC[4:0], is composed of five bits and works in tandem with the FIFO so that the user knows how much of the FIFO must be read back at any given time. FIRST READ KEY 3 PRESSED KEY 3 RELEASED GPI 7 ACTIVE EC = 2 SECOND READ KEY 3 RELEASED GPI 7 ACTIVE EC = 1 THIRD READ GPI 7 ACTIVE The FIFO is composed of 16 eight-bit sections that the user accesses by reading the FIFO_x registers. The actual FIFO is not in user accessible registers until a read occurs. The FIFO can be thought of as a “first in first out” buffer that is used to fill Register 0x03 to Register 0x12. The event FIFO is made up of 16 eight-bit registers. In each register, Bits[6:0] hold the event identifier, and Bit 7 holds the event state. With seven bits, 127 different events can be identified. See Table 11 for event decoding. OVRFLOW_INT KEY EVENTS GPI EVENTS FIFO UPDATE EC[4:0] LOGIC EVENTS EVENT2[7:0] EVENT3[7:0] EVENT4[7:0] The FIFO registers (0x03 to 0x12) always point to the top of the FIFO (that is, the location of EVENT1[7:0]). If the user tries to read back from any location in a FIFO, data is always obtained from the top of that FIFO. This ensures that events can only be read back in the order in which they occurred, thus ensuring the integrity of the FIFO system. A FIFO overflow event occurs when more than 16 events are generated prior to an external processor reading a FIFO and clearing it. EVENT5[7:0] EVENT6[7:0] EVENT7[7:0] 7 6 5 4 3 2 1 0 If an overflow condition occurs, the overflow status bit is set. An interrupt is generated if overflow interrupt is enabled, signaling to the processor that more than 16 events have occurred. EVENT9[7:0] EVENT10[7:0] EVENT11[7:0] EVENT8_IDENTIFIER[6:0] EVENT12[7:0] KEY SCAN CONTROL EVENT13[7:0] General EVENT8_STATE EVENT15[7:0] EVENT16[7:0] 09841-006 EVENT14[7:0] Figure 8. FIFO Operation As stated above, some of the onboard functions of ADP5585 can be programmed to generate events on the FIFO. A FIFO update control block manages updates to the FIFO. If an I2C transaction is accessing any of the FIFO address locations, updates are paused until the I2C transaction has completed. EVENT1[7:0] EVENT8[7:0] 09841-007 EC = 0 Figure 7. Breakdown of Eventx[7:0] Bits When events are available on the FIFO, the user should first read back the event count, EC[4:0], to determine how many events must be read back. Events can be read from the top of the FIFO only. When an event is read back, all remaining events in the FIFO are shifted up one location, and the EC[4:0] count is decremented. The 10 input/output pins can be configured to decode a keypad matrix up to a maximum size of 25 switches (5 × 5 matrix). Smaller matrices can also be configured, freeing up the unused row and column pins for other I/O functions. The R0 through R4 I/O pins comprise the rows of the keypad matrix. The C0 through C4 I/O pins comprise the columns of the keypad matrix. Pins used as rows are pulled up via the internal 300 kΩ (or 100 kΩ) resistors. Pins used as columns are driven low via the internal NMOS current sink. Rev. C | Page 9 of 40 ADP5585 Data Sheet VDD low and sensing whether a row pin is low or not. All row/column pairs are scanned; therefore, if multiple keys are pressed, they are detected. KEY SCAN CONTROL C2 R0 1 2 3 4 5 6 7 8 9 R1 R2 If Switch 6 is released, the connection between R1 and C2 breaks, and R1 is pulled up high. The key scanner requires that the key be released for two scan cycles because the release of a key is not necessarily in sync with the key scanner, it may take up to two full wait/scan cycles for a key to register as released. When the key is registered as released, and no other keys are pressed, the key scanner returns to idle mode. 3 × 3 KEYPAD MATRIX For the remainder of this document, the press/release status of a key is represented as simply a logic signal in the figures. A logic high level represents the key status as pressed, and a logic low represents released. This eliminates the need to draw individual row/column signals when describing key events. Figure 9. Simplified Key Scan Block Figure 9 shows a simplified representation of the key scan block using three row and three column pins connected to a small 3 × 3, nine-switch keypad matrix. When the key scanner is idle, the row pins are pulled high and the column pins are driven low. The key scanner operates by checking the row pins to see if they are low. KEY PRESSED KEY x KEY RELEASED Figure 10. Logic Low: Released, Logic High: Pressed Figure 11 shows a detailed representation of the key scan block and its associated control and status signals. When all row and column pins are used, a matrix of 25 unique keys can be scanned. If Switch 6 in the matrix is pressed, R1 connects to C2. The key scan circuit senses that one of the row pins has been pulled low, and a key scan cycle begins. Key scanning involves driving all column pins high, then driving each column pin, one at a time, PIN_CONFIG_A[7:0] PIN_CONFIG_B[7:0] PIN_CONFIG_C[7:0] RESET_TRIG_TIME[2:0] RESET1_EVENT_A[7:0] RESET1_EVENT_B[7:0] RESET1_EVENT_C[7:0] RESET2_EVENT_A[7:0] RESET2_EVENT_B[7:0] KEY RELEASED RESET 1_INITIATE RESET 2_INITIATE KEY SCAN CONTROL EVENT_INT OVRFLOW_INT I2C BUSY? KEY EVENT GPI EVENT EC[4:0] FIFO UPDATE LOGIC EVENT FIFO COLUMN SINK ON/OFF ROW SENSE 1 2 3 4 5 32 6 7 8 9 10 33 11 12 13 14 15 34 16 17 18 19 20 35 21 22 23 24 25 36 26 27 28 29 30 09841-010 I/O CONFIGURATION C0 C1 C2 C3 C4 R0 R1 R2 R3 R4 R5 31 09841-009 C1 09841-008 C0 To prevent glitches or narrow press times being registered as a valid key press, the key scanner requires the key be pressed for two scan cycles. The key scanner has a wait time between each scan cycle; therefore, the key must be pressed and held for at least this wait time to register as being pressed. If the key is continuously pressed, the key scanner continues to scan, wait, scan, wait, and so forth. Figure 11. Detailed Key Scan Block Rev. C | Page 10 of 40 Data Sheet ADP5585 If a smaller 2 × 2 matrix is configured, for example, by using the C2 and C3 column pins and the R1 and R2 row pins, only the four event identifiers (8, 9, 13, and 14) can possibly be observed on the FIFO, as shown in Figure 11. By default, ADP5585 records key presses and releases on the FIFO. Figure 12 illustrates what happens when a single key is pressed and released. Initially, the key scanner is idle. When Key 3 is pressed, the scanner begins scanning through all configured row/column pairs. After the scan wait time, the scanner again scans through all configured row/column pairs and detects that Key 3 has remained pressed, which sets the EVENT_INT interrupt. The event counter, EC[4:0], is incremented to 1, EVENT1_IDENTIFIER[6:0] of the FIFO is updated with its event identifier set to 3, and its EVENT1_STATE bit is set to 1, indicating a press. 1 EC[4:0] KEY 3 PRESS FIFO 1 3 0 0 0 0 0 0 0 FIFO READ FIFO 0 0 0 0 0 0 0 0 1 FIFO KEY 32 RELEASE 0 3 0 0 0 0 0 0 Figure 13. Asserting the EVENT_INT Interrupt Key Pad Extension As shown in Figure 11, the keypad can be extended if each row is connected directly to ground by a switch. If the switch placed between R0 and ground is pressed, the entire row is grounded. When the key scanner completes scanning, it normally detects Key 1 to Key 5 as being pressed; however, this unique condition is decoded by the ADP5585, and Key Event 31 is assigned to it. Up to eight more key event assignments are possible, allowing the keypad size to extend up to 30. However, if one of the extended keys is pressed, none of the keys on that row is detectable. Activation of a ground key causes all other keys sharing that row to be undetectable. 09841-011 2 Figure 12. Press and Release Event The key scanner continues the scan/wait cycles while the key remains pressed. If the scanner detects that the key has been released for two consecutive scan cycles, the event counter, EC[4:0], is incremented to 2, and EVENT2_IDENTIFIER[6:0] of the FIFO is updated with its event identifier set to 3. Its EVENT2_STATE bit is set to 0, indicating a release. The key scanner returns to idle mode because no other keys are pressed. The solution to ghosting is to select a keypad matrix layout that takes into account three key combinations that are most likely to be pressed together. Multiple keys pressed across one row or across one column do not cause ghosting. Staggering keys so that they do not share a column also avoids ghosting. The most common practice is to place keys that are likely to be pressed together in the same row or column. Some examples of keys that are likely to be pressed together are as follows:    The navigation keys in combination with Select. The navigation keys in combination with the space bar. The reset combination keys, such as CTRL + ALT + DEL. COL0 The EVENT_INT interrupt can be triggered by both press and release key events. As shown in Figure 14, if Key 3 is pressed, EVENT_INT is asserted, EC[4:0] is updated, and the FIFO is updated. During the time that the key remains pressed, it is possible for the FIFO to be read, the event counter decremented to 0, and EVENT_INT cleared. When the key is finally released, EVENT_INT is asserted, the event counter is incremented, and the FIFO is updated with the release event information. COL1 COL2 PRESS PRESS GHOST PRESS ROW0 ROW1 ROW2 ROW3 09841-013 EVENT_INT FIFO KEY 3 PRESS 1 3 KEY 3 RELEASE 0 3 0 0 0 0 EVENT_INT CLEARED EVENT_INT Ghosting is an occurrence where, given certain key press combinations on a keypad matrix, a false positive reading of an additional key is detected. Ghosting is created when three or more keys are pressed simultaneously on multiple rows or columns (see Figure 14). Key combinations that form a right angle on the keypad matrix can cause ghosting. KEY SCAN 1 KEY SCAN Ghosting KEY 3 EC[4:0] KEY 3 09841-012 Use Registers PIN_CONFIG_A[7:0] and PIN_CONFIG_B[7:0] to configure I/Os for keypad decoding. The number label on each key switch represents the event identifier that is recorded if that switch was pressed. If all row/column pins are configured, it is possible to observe all 25 key identifiers on the FIFO. A larger 6 × 5 matrix can be configured by using the ADP5585ACBZ-01-R7 or the ADP5585ACPZ-01-R7. Figure 14. COL0: ROW3 is a Ghost Key Due to a Short Among ROW0, COL0, COL2, and ROW3 During Key Press Rev. C | Page 11 of 40 ADP5585 Data Sheet GPI INPUT GPI 7 Each of the 10 input/output lines can be configured as a general-purpose logic input line. Figure 15 shows a detailed representation of the GPI scan and detect block and its associated control and status signals. GPI 4 GPI 2 GPI SCAN PIN_CONFIG_A[7:0] EVENT_INT PIN_CONFIG_B[7:0] EVENT_INT GPIO_DIRECTION_B[7:0] GPI_INT EC[4:0] GPI_INT_LEVEL_A[7:0] GPI_INT_STAT_A[5:0] GPI_INT_LEVEL_B[7:0] GPI_INTERRUPT_EN_A[7:0] GPI_INT_STAT_B[4:0] GPI_STATUS_A[5:0] GPI_INTERRUPT_EN_B[7:0] GPI_STATUS_B[4:0] GPI_EVENT_EN_A[7:0] GPI 2 ACTIVE GPI 7 ACTIVE GPI 4 ACTIVE GPI 4 INACTIVE GPI 7 INACTIVE GPI 2 INACTIVE GPI_EVENT_EN_B[7:0] RESET_TRIG_TIME[2:0] RESET1_EVENT_A[7:0] RESET1_EVENT_B[7:0] RESET1_EVENT_C[7:0] GPI SCAN CONTROL RESET2_EVENT_A[7:0] (R0) GPIO 1 (R1) (R2) (R3) GPIO 2 GPIO 3 GPIO 4 (R4) GPIO 5 RST/(R5) GPIO 6 GPIO 7 (C0) (C1) (C2) 5 6 The GPI scanner is idle until it detects a level transition. It scans the GPI inputs and updates accordingly. It then returns to idle immediately, it does not scan/wait, like the key scanner. As such, the GPI scanner can detect narrow pulses once they get past the 50 μs input debounce filter. EC[4:0] KEY EVENT FIFO UPDATE LOGIC EVENT GPIO 8 GPIO 9 FIFO1:FIFO16 (C3) GPIO 10 (C4) GPIO 11 Figure 15. GPI Scan and Detect Block The current input state of each GPI can be read back using the GPI_STATUS_x registers. Each GPI can be programmed to generate an interrupt via the GPI_INTERRUPT_EN_x registers. The interrupt status is stored in the GPI_INT_STAT_x registers. GPI interrupts can be programmed to trigger on the positive or negative edge by configuring the GPI_INT_LEVEL_x registers. If any of the GPI interrupts is triggered, the master GPI_INT interrupt is also triggered. Figure 16 shows a single GPI and how it affects its corresponding status and interrupt status bits. GPO OUTPUT Each of the 10 input/output lines can be configured as a generalpurpose output (GPO) line. Figure 6 shows a detailed diagram of the I/O structure. See the Detailed Register Descriptions section for GPO configuration and usage. LOGIC BLOCKS Several of the ADP5585 input/output lines can be used as inputs and outputs for implementing some common logic functions. The R1, R2, and R3 input/output pins can be used as inputs, and the R0 input/output pin can be used as an output for the logic block. The outputs from the logic blocks can be configured to generate interrupts. They can also be configured to generate events on the FIFO. GPI 3 GPI_INT_LEVEL_A[3] GPI_INTERRUPT_EN_A[3] CLEARED BY READ CLEARED BY WRITE ‘1’ GPI_INT 09841-015 GPI_STATUS_A[3] GPI_INT_STAT_A[3] 4 Figure 17. Multiple GPI Example OVRFLOW_INT GPI EVENT 3 FIFO 1 38 1 43 1 40 0 40 0 43 0 38 I2C BUSY 09841-014 RESET2_EVENT_B[7:0] 2 1 09841-016 GPIO_DIRECTION_A[7:0] Figure 19 shows a detailed diagram of the internal make-up of the logic block, illustrating the possible logic functions that can be implemented. Figure 16. Single GPI Example GPIs can be programmed to generate FIFO events via the GPI_EVENT_EN_x registers. GPIs in this mode do not generate GPI_INT interrupts and instead generate EVENT_INT interrupts. Figure 17 shows several GPI lines and their effects on the FIFO and event count, EC[4:0]. Rev. C | Page 12 of 40 Data Sheet ADP5585 PWM BLOCK LOGIC BLOCK The ADP5585 features a PWM generator whose output can be configured to drive out on the R3 I/O pin. PWM on/off times are programmed via four 8-bit registers (see Figure 20). Each bit of the on or off time represents 1 µs. The highest frequency obtainable from the PWM is performed by setting the least significant bit of both the on and off time bit patterns, resulting in a 500 kHz signal with a 50% duty cycle. (R1) LA (R2) LB (R3) LC LA_INV LB_INV LY (R0) LC_INV LY_INV LOGIC_SEL[2:0] SET Q D CLR The PWM block provides support for continuous PWM mode as well as a one-shot mode (see Table 59). Additionally, an external signal can be AND’ed with the internal PWM signal. This option can be selected by writing a 1 to PWM_IN_AND (PWM_CFG[2]). The input to the external AND is the C3 I/O pin. C3 should be set to GPI. Note that the debounce for C3 results in a delay of the AND’ing, and can be turned on or off using Register 0x21. R3_EXTEND_CFG[1:0] OVRFLOW_INT LOGIC_INT_LEVEL I2C BUSY LOGIC_EVENT_EN KEY EVENT RESET_TRIG_TIME[2:0] GPI EVENT RESET1_EVENT_B[7:0] RESET1_EVENT_C[7:0] LOGIC EVENT/INT GENERATOR LOGIC EVENT FIFO EVENT_INT LOGIC_INT RESET2_EVENT_A[7:0] RESET2_EVENT_B[7:0] 09841-017 RESET1_EVENT_A[7:0] EC[4:0] FIFO UPDATE Newly programmed values are not latched until the final byte, PWM_ONT_HIGH_BYTE (Register 0x32, Bits[7:0]), is written. Figure 18. Logic Block Overview LA LA LA 0 OUT IN_LA 1 SEL IN_LA LA_INV AND 0 IN_LB AND IN_LC LB LB LB 0 OUT LC OUT OR 0 IN_LB LB_INV LC SEL MUX GND IN_LA 1 0 AND IN_LB SEL LC OUT 1 OR IN_LC IN_LC OR AND OR 1 SEL XOR FF IN_LA XOR 0 IN_LB 1 OUT SEL XOR IN_LC OUT XOR 1 IN_LA IN_LB SEL LC_INV IN_LC FF_SET 000 001 010 LY 011 OUT LY 100 0 OUT LY 1 SEL 101 LY_INV 110 111 SEL[2:0] SET IN_LA D Q FF LOGIC_SEL[2:0] IN_LB CLR FF_CLR 0 OUT IN_LC 1 09841-018 SEL R3_EXTEND_CFG[1:0] = 01 Figure 19. Logic Block PWM_EN PWM_MODE PWM_OFFT_LOW_BYTE[7:0] PWM_OFFT_HIGH_BYTE[7:0] PWM_ONT_LOW_BYTE[7:0] PWM_ONT_HIGH_BYTE[7:0] (C3) PWM_IN PWM_IN_AND OFF TIME[15:0] ON TIME[15:0] 0 OUT 1 SEL PWM GENERATOR AND Figure 20. PWM Block Diagram Rev. C | Page 13 of 40 (R3) PWM_OUT 09841-019 FF_SET FF_CLR ADP5585 Data Sheet RESET BLOCKS ADP5585 features two reset blocks that can generate reset conditions if certain events are detected simultaneously. Up to three reset trigger events can be programmed for RESET1. Up to two reset trigger events can be programmed for RESET2. The event scan control blocks monitor whether these events are present for the duration of RESET_TRIG_TIME[2:0] (Register 0x2E, Bits[4:2]). If they are, reset-initiate signals are sent to the reset generator blocks. The generated reset signal pulse width is programmable. RST RST_PASSTHRU_EN RESET_TRIG_TIME[2:0] RESET1_EVENT_A[7:0] RESET1_EVENT_B[7:0] RESET1_EVENT_C[7:0] RESET2_EVENT_A[7:0] RESET2_EVENT_B[7:0] KEY SCAN CONTROL RESET1_ (R4) INITIATE RESET RESET1 GEN 1 The reset generation signals are useful in situations where the system processor has locked up and the system is unresponsive to input events. The user can press one of the reset event combinations and initiate a system wide reset. This alleviates the need for removing the battery from the system and doing a hard reset. It is not recommended to use the immediate trigger time (see Table 54) because this setting may cause false triggering. Interrupts The INT pin can be asserted low if any of the internal interrupt sources is active. The user can select which internal interrupts interact with the external interrupt pin in Register 0x3C (refer to Table 68). Register 0x3B allows the user to choose whether the external interrupt pin remains asserted, or deasserts for 50 µs, then reasserts, in the case that there are multiple internal interrupts asserted and one is cleared (refer to Table 67). EVENT_INT GPI SCAN CONTROL EVENT_IEN RESET_PULSE_WIDTH[1:0] GPI_INT GPI_IEN LOGIC_IEN Figure 21. Reset Blocks OVRFLOW_INT OVRFLOW_IEN INT_CFG The Reset 1 signal uses the R4 I/O pin as its output. A pass through mode allows the main RST pin to be output on the R4 pin also. The Reset 2 signal uses the C4 I/O pin as its output. Rev. C | Page 14 of 40 Figure 22. Asserting INT Low 09841-021 RESET2_ INITIATE INT LOGIC_INT 09841-020 RESET GEN 2 LOGIC BLOCK CONTROL INT DRIVE (C4) RESET2 Data Sheet ADP5585 REGISTER INTERFACE Register access to the ADP5585 is acquired via its I2C-compatible serial interface. The interface can support clock frequencies of up to 1 MHz. If the user is accessing the FIFO or key event counter (KEC), FIFO/KEC updates are paused. If the clock frequency is very low, events may not be recorded in a timely manner. FIFO or KEC updates can happen up to 23 μs after an interrupt is asserted because of the number of I2C cycles required to perform an I2C read or write. This delay should not present an issue to the user. line low. The address of the register to which data is to be written is sent next. The ADP5585 acknowledges the register pointer byte by pulling the data line low. The data byte to be written is sent next. The ADP5585 acknowledges the data byte by pulling the data line low. The pointer address is then incremented to write the next data byte, until it finishes writing the n data byte. The ADP5585 pulls the data line low after every byte, and a stop condition completes the sequence. Figure 25 shows a typical byte read sequence for reading internal registers. The cycle begins with a start condition followed by the 7-bit device address (0x34 for all models except the ADP5585ACPZ-03-R7, 0x30 for the ADP5585ACPZ-03-R7 only), followed by the R/W bit set to 0 for a write cycle. The ADP5585 acknowledges the address byte by pulling the data line low. The address of the register from which data is to be read is sent next. The ADP5585 acknowledges the register pointer byte by pulling the data line low. A start condition is repeated, followed by the 7-bit device address (0x34 for all models except the ADP5585ACPZ-03-R7, 0x30 for the ADP5585ACPZ-03-R7 only), followed by the R/W bit set to 1 for a read cycle. The ADP5585 acknowledges the address byte by pulling the data line low. The 8-bit data is then read. The host pulls the data line high (no acknowledge), and a stop condition completes the sequence. Figure 23 shows a typical write sequence for programming an internal register. The cycle begins with a start condition, followed by the hard coded 7-bit device address, which for the ADP5585 is 0x34, followed by the R/W bit set to 0 for a write cycle. The ADP5585 acknowledges the address byte by pulling the data line low. The address of the register to which data is to be written is sent next. The ADP5585 acknowledges the register pointer byte by pulling the data line low. The data byte to be written is sent next. The ADP5585 acknowledges the data byte by pulling the data line low. A stop condition completes the sequence. Figure 24 shows a typical multibyte write sequence for programming internal registers. The cycle begins with a start condition followed by the 7-bit device address (0x34 for all models except the ADP5585ACPZ-03-R7, 0x30 for the ADP5585ACPZ-03-R7 only), followed by the R/W bit set to 0 for a write cycle. The ADP5585 acknowledges the address byte by pulling the data 0 = WRITE 7-BIT DEVICE ADDRESS 0 0 STOP 8-BIT REGISTER POINTER 0 8-BIT WRITE DATA 0 ADP5585 ACK ADP5585 ACK ADP5585 ACK 09841-022 START Figure 23. I2C Single Byte Write Sequence 0 = WRITE 7-BIT DEVICE ADDRESS 0 0 STOP 8-BIT REGISTER POINTER 0 WRITE BYTE 1 ADP5585 ACK ADP5585 ACK 0 WRITE BYTE 2 ADP5585 ACK 0 0 ADP5585 ACK WRITE BYTE n ADP5585 ACK 0 ADP5585 ACK Figure 24. I2C Multibyte Write Sequence REPEAT START 0 = WRITE 7-BIT DEVICE ADDRESS 0 0 8-BIT REGISTER POINTER ADP5585 ACK 0 1 = READ 7-BIT DEVICE ADDRESS ADP5585 ACK Figure 25. I2C Single Byte Read Sequence Rev. C | Page 15 of 40 1 0 ADP5585 ACK STOP 8-BIT READ DATA 1 NO ACK 09841-024 START 09841-023 START ADP5585 Data Sheet ADP5585ACPZ-03-R7, 0x30 for the ADP5585ACPZ-03-R7 only), followed by the R/W bit set to 1 for a read cycle. The ADP5585 acknowledges the address byte by pulling the data line low. The 8-bit data is then read. The address pointer is then incremented to read the next data byte, and the host continues to pull the data line low for each byte (master acknowledge) until the n data byte is read. The host pulls the data line high (no acknowledge) after the last byte is read, and a stop condition completes the sequence. START REPEAT START 0 = WRITE 7-BIT DEVICE ADDRESS 0 0 8-BIT REGISTER POINTER ADP5585 ACK 0 1 = READ 7-BIT DEVICE ADDRESS ADP5585 ACK 1 0 STOP READ BYTE 1 ADP5585 ACK Figure 26. I2C Multibyte Read Sequence Rev. C | Page 16 of 40 0 READ BYTE 2 MASTER ACK 0 MASTER ACK 0 READ BYTE n MASTER ACK 1 NO ACK 09841-025 Figure 26 shows a typical multibyte read sequence for reading internal registers. The cycle begins with a start condition, followed by the 7-bit device address (0x34 for all models except the ADP5585ACPZ-03-R7, 0x30 for the ADP5585ACPZ-03-R7 only), followed by the R/W bit set to 0 for a write cycle. The ADP5585 acknowledges the address byte by pulling the data line low. The address of the register from which data is to be read is sent next. The ADP5585 acknowledges the register pointer byte by pulling the data line low. A start condition is repeated, followed by the 7-bit device address (0x34 for all models except the Data Sheet ADP5585 REGISTER MAP Table 6. Reg Add 0x00 0x01 Reg Name ID INT_STATUS 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 R/W 1 R R/W Bit 7 R R R R R R R R R R R R R R R R R R Reserved LOGIC_STAT EVENT1_STATE EVENT2_STATE EVENT3_STATE EVENT4_STATE EVENT5_STATE EVENT6_STATE EVENT7_STATE EVENT8_STATE EVENT9_STATE EVENT10_STATE EVENT11_STATE EVENT12_STATE EVENT13_STATE EVENT14_STATE EVENT15_STATE EVENT16_STATE Reserved 0x1D Status FIFO_1 FIFO_2 FIFO_3 FIFO_4 FIFO_5 FIFO_6 FIFO_7 FIFO_8 FIFO_9 FIFO_10 FIFO_11 FIFO_12 FIFO_13 FIFO_14 FIFO_15 FIFO_16 GPI_INT_ STAT_A GPI_INT_ STAT_B GPI_STATUS_A GPI_STATUS_B R_PULL_ CONFIG_A R_PULL_ CONFIG_B R_PULL_ CONFIG_C R_PULL_ CONFIG_D GPI_INT_ LEVEL_A GPI_INT_ LEVEL_B GPI_EVENT_EN_A 0x1E GPI_EVENT_EN_B R/W 0x1F GPI_INTERRUPT_ EN_A GPI_INTERRUPT_ EN_B DEBOUNCE_ DIS_A DEBOUNCE_ DIS_B GPO_DATA_ OUT_A GPO_DATA_ OUT_B GPO_OUT_ MODE_A R/W 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x20 0x21 0x22 0x23 0x24 0x25 Bit 6 R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W Reserved GPI_6_INT Reserved Reserved R3_PULL_CFG GPI_6_STAT Bit 1 REV_ID OVRFLOW_ GPI_INT LOGIC_INT Reserved INT EC[4:0] EVENT1_IDENTIFIER[6:0] EVENT2_IDENTIFIER[6:0] EVENT3_IDENTIFIER[6:0] EVENT4_IDENTIFIER[6:0] EVENT5_IDENTIFIER[6:0] EVENT6_IDENTIFIER[6:0] EVENT7_IDENTIFIER[6:0] EVENT8_IDENTIFIER[6:0] EVENT9_IDENTIFIER[6:0] EVENT10_IDENTIFIER[6:0] EVENT11_IDENTIFIER[6:0] EVENT12_IDENTIFIER[6:0] EVENT13_IDENTIFIER[6:0] EVENT14_IDENTIFIER[6:0] EVENT15_IDENTIFIER[6:0] EVENT16_IDENTIFIER[6:0] GPI_5_INT GPI_4_INT GPI_3_INT GPI_2_INT C3_PULL_CFG Bit 3 Bit 2 GPI_4_STAT GPI_3_STAT GPI_10_STAT GPI_9_STAT R1_PULL_CFG GPI_2_STAT GPI_1_STAT GPI_8_STAT GPI_7_STAT R0_PULL_CFG R5_PULL_CFG R4_PULL_CFG C1_PULL_CFG C0_PULL_CFG Reserved Reserved GPI_6_ INT_LEVEL Reserved Reserved GPI_6_ EVENT_EN Reserved Reserved GPI_6_ INT_EN Reserved Reserved GPI_6_ DEB_DIS Reserved Reserved GPO_6_ DATA Reserved Reserved GPO_6_ OUT_MODE GPI_1_INT GPI_5_STAT GPI_11_STAT C2_PULL_CFG GPI_8_INT EVENT_INT GPI_10_INT R2_PULL_CFG GPI_9_INT Bit 0 GPI_11_INT Reserved R/W R/W Bit 4 Reserved R/W R/W Bit 5 MAN_ID Reserved GPI_7_INT C4_PULL_CFG GPI_5_ INT_LEVEL GPI_11_ INT_LEVEL GPI_5_ EVENT_EN GPI_11_ EVENT_EN GPI_5_ INT_EN GPI_11_ INT_EN GPI_5_ DEB_DIS GPI_11_ DEB_DIS GPO_5_ DATA GPO_11_ DATA GPO_5_ OUT_MODE Rev. C | Page 17 of 40 GPI_4_ INT_LEVEL GPI_10_ INT_LEVEL GPI_4_ EVENT_EN GPI_10_ EVENT_EN GPI_4_ INT_EN GPI_10_ INT_EN GPI_4_ DEB_DIS GPI_10_ DEB_DIS GPO_4_ DATA GPO_10_ DATA GPO_4_ OUT_MODE GPI_3_ INT_LEVEL GPI_9_ INT_LEVEL GPI_3_ EVENT_EN GPI_9_ EVENT_EN GPI_3_ INT_EN GPI_9_ INT_EN GPI_3_ DEB_DIS GPI_9_ DEB_DIS GPO_3_ DATA GPO_9_ DATA GPO_3_ OUT_MODE GPI_2_ INT_LEVEL GPI_8_ INT_LEVEL GPI_2_ EVENT_EN GPI_8_ EVENT_EN GPI_2_ INT_EN GPI_8_ INT_EN GPI_2_ DEB_DIS GPI_8_ DEB_DIS GPO_2_ DATA GPO_8_ DATA GPO_2_ OUT_MODE GPI_1_ INT_LEVEL GPI_7_ INT_LEVEL GPI_1_ EVENT_EN GPI_7_ EVENT_EN GPI_1_ INT_EN GPI_7_ INT_EN GPI_1_ DEB_DIS GPI_7_ DEB_DIS GPO_1_ DATA GPO_7_ DATA GPO_1_ OUT_MODE ADP5585 Reg Add 0x26 Data Sheet 0x29 Reg Name GPO_OUT_ MODE_B GPIO_ DIRECTION_A GPIO_ DIRECTION_B RESET1_EVENT_A 0x2A RESET1_EVENT_B R/W 0x2B RESET1_EVENT_C R/W 0x2C RESET2_EVENT_A R/W 0x2D RESET2_EVENT_B R/W 0x2E RESET2_CFG R/W 0x2F 0x30 0x31 0x32 0x33 PWM_OFFT_LOW PWM_OFFT_HIGH PWM_ONT_LOW PWM_ONT_HIGH PWM_CFG R/W R/W R/W R/W R/W 0x34 0x35 0x36 R/W R/W R/W 0x37 0x38 0x39 0x3A LOGIC_CFG LOGIC_FF_CFG LOGIC_INT_ EVENT_EN POLL_TIME_CFG PIN_CONFIG_A PIN_CONFIG_B PIN_CONFIG_C R/W R/W R/W R/W Reserved Reserved PULL_SELECT C4_EXTEND_CFG 0x3B GENERAL_CFG R/W OSC_EN 0x3C INT_EN R/W 0x27 0x28 1 R/W 1 R/W Bit 7 R/W Bit 5 GPO_6_ DIR Reserved R/W R/W Bit 6 Reserved Reserved RESET1_ EVENT_ A_LEVEL RESET1_ EVENT_ B_LEVEL RESET1_ EVENT_ C_LEVEL RESET2_ EVENT_ A_LEVEL RESET2_ EVENT_ B_LEVEL RESET2_POL Bit 4 Bit 3 Bit 2 GPO_11_ GPO_10_ GPO_9_ OUT_MODE OUT_MODE OUT_MODE GPO_5_ GPO_4_ GPO_3_ DIR DIR DIR GPO_11_ GPO_10_ GPO_9_ DIR DIR DIR RESET1_EVENT_A [6:0] Bit 1 GPO_8_ OUT_MODE GPO_2_ DIR GPO_8_ DIR Bit 0 GPO_7_ OUT_MODE GPO_1_ DIR GPO_7_ DIR RESET1_EVENT_B [6:0] RESET1_EVENT_C [6:0] RESET2_EVENT_A [6:0] RESET2_EVENT_B [6:0] RESET1_POL RESET_TRIG_TIME[2:0] RST_PASS THRU_EN RESET_PULSE_WIDTH[1:0] PWM_OFFT_LOW_BYTE[7:0] PWM_OFFT_HIGH_BYTE[7:0] PWM_ONT_LOW_BYTE[7:0] PWM_ONT_HIGH_BYTE[7:0] PWM_IN_ AND Reserved Reserved LY_INV LC_INV LB_INV Reserved Reserved Reserved R5_CONFIG R4_CONFIG C4_CONFIG R4_EXTEND Reserved _CFG CORE_FREQ[1:0] Reserved LOGIC_IEN R means read, W means write, and R/W means read/write. Rev. C | Page 18 of 40 LA_INV LY_DBNC_ DIS R3_CONFIG R2_CONFIG C3_CONFIG C2_CONFIG R3_EXTEND_CFG[1:0] Reserved Reserved OVRFLOW_ IEN PWM_MODE PWM_EN LOGIC_SEL[2:0] FF_SET FF_CLR LOGIC_ LOGIC_INT_ EVENT_EN LEVEL KEY_POLL_TIME[1:0] R1_CONFIG R0_CONFIG C1_CONFIG C0_CONFIG R0_EXTEND Reserved _CFG INT_CFG RST_CFG GPI_IEN EVENT_IEN Data Sheet ADP5585 DETAILED REGISTER DESCRIPTIONS Note that N/A throughout this section means not applicable. Note: All register default to 0000 0000 unless otherwise specified. ID Register 0x00 Table 7. ID Bit Descriptions Bit(s) 7 to 4 3 to 0 Bit Name MAN_ID REV_ID Access Read only Read only Description Manufacturer ID, default = 0010 Rev ID INT_STATUS Register 0x01 Table 8. INT_STATUS Bit Descriptions Bit(s) 7 to 5 4 Bit Name N/A LOGIC_INT 3 2 N/A OVERFLOW_INT Read/write 1 GPI_INT Read/write 0 EVENT_INT Read/write 1 Access Read/write Description 1 Reserved. 0 = no interrupt. 1 = interrupt due to a general logic condition. Reserved. 0 = no interrupt. 1 = interrupt due to an overflow condition. This bit is not set by a GPI that has been configured to update the FIFO and event count. This bit cannot be cleared until all GPI_x_INT bits are cleared. 0 = no interrupt. 1 = interrupt due to a general GPI condition. 0 = no interrupt. 1 = interrupt due to key event (press/release), GPI event (GPI programmed for FIFO updates), or logic event (programmed for FIFO updates). Interrupt bits are cleared by writing a 1 to the flag; writing a 0 or reading the flag has no effect. Status Register 0x02 Table 9. Status Bit Descriptions Bit(s) 7 6 Bit Name N/A LOGIC_STAT Access Read only 5 4 to 0 N/A EC[4:0] Read only Description Reserved. 0 = output from logic block (LY) is low. 1 = output from logic block (LY) is high. Reserved. Event count value. Indicates how many events are currently stored on the FIFO. FIFO_1 Register 0x03 Table 10. FIFO_1 Bit Descriptions Bit(s) 7 Bit Name EVENT1_STATE Access Read only 6 to 0 EVENT1_IDENTIFIER[6:0] Read only Description This bit represents the state of the event that is recorded in the EVENT1_IDENTIFIER[6:0] bit. For key events from Event 1 to Event 36, use the following settings: 1 = key is pressed. 0 = key is released. For GPI and logic events from Event 37 to Event 48, use the following settings: 1 = GPI/logic is active. 0 = GPI/logic is inactive. Active and inactive states for Event 37 to Event 48 are programmable. Contains the event identifier for the pin. Refer to Table 11. Rev. C | Page 19 of 40 ADP5585 Data Sheet Table 11. Event Decoding Event No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Meaning No event Key 1 (R0, C0) Key 2 (R0, C1) Key 3 (R0, C2) Key 4 (R0, C3) Key 5 (R0, C4) Key 6 (R1, C0) Key 7 (R1, C1) Key 8 (R1, C2) Key 9 (R1, C3) Key 10 (R1, C4) Key 11 (R2, C0) Key 12 (R2, C1) Key 13 (R2, C2) Key 14 (R2, C3) Key 15 (R2, C4) Key 16 (R3, C0) Key 17 (R3, C1) Key 18 (R3, C2) Key 19 (R3, C3) Key 20 (R3, C4) Key 21 (R4, C0) Key 22 (R4, C1) Key 23 (R4, C2) Key 24 (R4, C3) Key 25 (R4, C4) Key 26 (R5, C0) Key 27 (R5, C1) Key 28 (R5, C2) Key 29 (R5, C3) Key 30 (R5, C4) Key 31 (R0, GND) Event No. 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Meaning Key 32 (R1, GND) Key 33 (R2, GND) Key 34 (R3, GND) Key 35 (R4, GND) Key 36 (R5, GND) GPI 1 (R0) GPI 2 (R1) GPI 3 (R2) GPI 4 (R3) GPI 5 (R4) GPI 6 (R5) GPI 7 (C0) GPI 8 (C1) GPI 9 (C2) GPI 10 (C3) GPI 11 (C4) Logic Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Event No. 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 Meaning Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Event No. 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 FIFO_2 Register 0x04 Table 12. FIFO_2 Bit Descriptions Bit(s) 7 6 to 0 Bit Name EVENT2_STATE EVENT2_IDENTIFIER[6:0] Access Read only Read only Description Refer to Table 10. Refer to Table 10. Access Read only Read only Description Refer to Table 10. Refer to Table 10. Access Read only Read only Description Refer to Table 10. Refer to Table 10. FIFO_3 Register 0x05 Table 13. FIFO_3 Bit Descriptions Bit(s) 7 6 to 0 Bit Name EVENT3_STATE EVENT3_IDENTIFIER[6:0] FIFO_4 Register 0x06 Table 14. FIFO_4 Bit Descriptions Bit(s) 7 6 to 0 Bit Name EVENT4_STATE EVENT4_IDENTIFIER[6:0] Rev. C | Page 20 of 40 Meaning Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Data Sheet ADP5585 FIFO_5 Register 0x07 Table 15. FIFO_5 Bit Descriptions Bit(s) 7 6 to 0 Bit Name EVENT5_STATE EVENT5_IDENTIFIER[6:0] Access Read only Read only Description Refer to Table 10. Refer to Table 10. Access Read only Read only Description Refer to Table 10. Refer to Table 10. Access Read only Read only Description Refer to Table 10. Refer to Table 10. Access Read only Read only Description Refer to Table 10. Refer to Table 10. Access Read only Read only Description Refer to Table 10. Refer to Table 10. Access Read only Read only Description Refer to Table 10. Refer to Table 10. FIFO_6 Register 0x08 Table 16. FIFO_6 Bit Descriptions Bit(s) 7 6 to 0 Bit Name EVENT6_STATE EVENT6_IDENTIFIER[6:0] FIFO_7 Register 0x09 Table 17. FIFO_7 Bit Descriptions Bit(s) 7 6 to 0 Bit Name EVENT7_STATE EVENT7_IDENTIFIER[6:0] FIFO_8 Register 0x0A Table 18. FIFO_8 Bit Descriptions Bit(s) 7 6 to 0 Bit Name EVENT8_STATE EVENT8_IDENTIFIER[6:0] FIFO_9 Register 0x0B Table 19. FIFO_9 Bit Descriptions Bit(s) 7 6 to 0 Bit Name EVENT9_STATE EVENT9_IDENTIFIER[6:0] FIFO_10 Register 0x0C Table 20. FIFO_10 Bit Descriptions Bit(s) 7 6 to 0 Bit Name EVENT10_STATE EVENT10_IDENTIFIER[6:0] FIFO_11 Register 0x0D Table 21. FIFO_11 Bit Descriptions Bit(s) 7 6 to 0 Bit Name EVENT11_STATE EVENT11_IDENTIFIER[6:0] Access Read only Read only Description Refer to Table 10. Refer to Table 10. Access Read only Read only Description Refer to Table 10. Refer to Table 10. FIFO_12 Register 0x0E Table 22. FIFO_12 Bit Descriptions Bit(s) 7 6 to 0 Bit Name EVENT12_STATE EVENT12_IDENTIFIER[6:0] Rev. C | Page 21 of 40 ADP5585 Data Sheet FIFO_13 Register 0x0F Table 23. FIFO_13 Bit Descriptions Bit(s) 7 6 to 0 Bit Name EVENT13_STATE EVENT13_IDENTIFIER[6:0] Access Read only Read only Description Refer to Table 10. Refer to Table 10. Access Read only Read only Description Refer to Table 10. Refer to Table 10. Access Read only Read only Description Refer to Table 10. Refer to Table 10. Access Read only Read only Description Refer to Table 10. Refer to Table 10. FIFO_14 Register 0x10 Table 24. FIFO_14 Bit Descriptions Bit(s) 7 6 to 0 Bit Name EVENT14_STATE EVENT14_IDENTIFIER[6:0] FIFO_15 Register 0x11 Table 25. FIFO_15 Bit Descriptions Bit(s) 7 6 to 0 Bit Name EVENT15_STATE EVENT15_IDENTIFIER[6:0] FIFO_16 Register 0x12 Table 26. FIFO_16 Bit Descriptions Bit(s) 7 6 to 0 Bit Name EVENT16_STATE EVENT16_IDENTIFIER[6:0] GPI_INT_STAT_A Register 0x13 Table 27. GPI_INT_STAT_A Bit Descriptions Bit(s) 7 to 6 5 Bit Name N/A GPI_6_INT Access 4 GPI_5_INT Read only 3 GPI_4_INT Read only 2 GPI_3_INT Read only 1 GPI_2_INT Read only 0 GPI_1_INT Read only Read only Description Reserved. 0 = no interrupt 1 = interrupt due to GPI_6 (R5 pin). Cleared on read. 0 = no interrupt 1 = interrupt due to GPI_5 (R4 pin). Cleared on read. 0 = no interrupt 1 = interrupt due to GPI_4 (R3 pin). Cleared on read. 0 = no interrupt 1 = interrupt due to GPI_3 (R2 pin). Cleared on read. 0 = no interrupt 1 = interrupt due to GPI_2 (R1 pin). Cleared on read. 0 = no interrupt 1 = interrupt due to GPI_1 (R0 pin). Cleared on read. GPI_INT_STAT_B Register 0x14 Table 28. GPI_INT_STAT_B Bit Descriptions Bit(s) 7 to 5 4 Bit Name N/A GPI_11_INT Access 3 GPI_10_INT Read only Read only Description Reserved. 0 = no interrupt. 1 = interrupt due to GPI_11 (C4 pin). Cleared on read. 0 = no interrupt. 1 = interrupt due to GPI_10 (C3 pin). Cleared on read. Rev. C | Page 22 of 40 Data Sheet ADP5585 Bit(s) 2 Bit Name GPI_9_INT Access Read only 1 GPI_8_INT Read only 0 GPI_7_INT Read only Description 0 = no interrupt. 1 = interrupt due to GPI_9 (C2 pin). Cleared on read. 0 = no interrupt. 1 = interrupt due to GPI_8 (C1 pin). Cleared on read. 0 = no interrupt. 1 = interrupt due to GPI_7 (C0 pin). Cleared on read. GPI_STATUS_A Register 0x15 Table 29. GPI_STATUS_A Bit Descriptions Bit(s) 7 to 6 5 Bit Name N/A GPI_6_STAT Access 4 GPI_5_STAT Read only 3 GPI_4_STAT Read only 2 GPI_3_STAT Read only 1 GPI_2_STAT Read only 0 GPI_1_STAT Read only Read only Description Reserved. 0 = GPI_6 (R5 pin) is low. 1 = GPI_6 (R5 pin) is high. 0 = GPI_5 (R4 pin) is low. 1 = GPI_5 (R4 pin) is high. 0 = GPI_4 (R3 pin) is low. 1 = GPI_4 (R3 pin) is high. 0 = GPI_3 (R2 pin) is low. 1 = GPI_3 (R2 pin) is high. 0 = GPI_2 (R1 pin) is low. 1 = GPI_2 (R1 pin) is high. 0 = GPI_1 (R0 pin) is low. 1 = GPI_1 (R0 pin) is high. GPI_STATUS_B Register 0x16 Table 30. Register 0x16, GPI_STATUS_B Bit Descriptions Bit(s) 7 to 5 4 Bit Name N/A GPI_11_STAT Access 3 GPI_10_STAT Read only 2 GPI_9_STAT Read only 1 GPI_8_STAT Read only 0 GPI_7_STAT Read only Read only Description Reserved. 0 = GPI_11 (C4 pin) is low. 1 = GPI_11 (C4 pin) is high. 0 = GPI_10 (C3 pin) is low. 1 = GPI_10 (C3 pin) is high. 0 = GPI_9 (C2 pin) is low. 1 = GPI_9 (C2 pin) is high. 0 = GPI_8 (C1 pin) is low. 1 = GPI_8 (C1 pin) is high. 0 = GPI_7 (C0 pin) is low. 1 = GPI_7 (C0 pin) is high. Rev. C | Page 23 of 40 ADP5585 Data Sheet RPULL_CONFIG_A Register 0x17 Table 31. RPULL_CONFIG_A Bit Descriptions Bit(s) 7 to 6 Bit Name R3_PULL_CFG Access Read/write Description 00 = enable 300 kΩ pull-up resistor. 01 = enable 300 kΩ pull-down resistor. 10 = enable 100 kΩ pull-up resistor. 11 = disable all pull-up/pull-down resistors. 5 to 4 R2_PULL_CFG Read/write 00 = enable 300 kΩ pull-up resistor. 01 = enable 300 kΩ pull-down resistor. 10 = enable 100 kΩ pull-up resistor. 11 = disable all pull-up/pull-down resistors. 3 to 2 R1_PULL_CFG Read/write 00 = enable 300 kΩ pull-up resistor. 01 = enable 300 kΩ pull-down resistor. 10 = enable 100 kΩ pull-up resistor. 11 = disable all pull-up/pull-down resistors. 1 to 0 R0_PULL_CFG Read/write 00 = enable 300 kΩ pull-up resistor. 01 = enable 300 kΩ pull-down resistor. 10 = enable 100 kΩ pull-up resistor. 11 = disable all pull-up/pull-down resistors. ADP5585AC_Z-00-R7, ADP5585AC_Z-01-R7, ADP5585ACPZ-03-R7 Default = 0000 0000 ADP5585ACBZ-02-R7 Default = 1100 0011 ADP5585ACBZ-04-R7 Default = 0101 0101 RPULL_CONFIG_B Register 0x18 Table 32. RPULL_CONFIG_B Bit Descriptions Bit(s) 7 to 4 3 to 2 Bit Name N/A R5_PULL_CFG Access Description Reserved. Read/write (Reserved except for ADP5585ACBZ-01-R7 options) 00 = enable 300 kΩ pull-up resistor. 01 = enable 300 kΩ pull-down resistor. 10 = enable 100 kΩ pull-up resistor. 11 = disable all pull-up/pull-down resistors. 1 to 0 R4_PULL_CFG Read/write 00 = enable 300 kΩ pull-up resistor. 01 = enable 300 kΩ pull-down resistor. 10 = enable 100 kΩ pull-up resistor. 11 = disable all pull-up/pull-down resistors. ADP5585AC_Z-00-R7, ADP5585AC_Z-01-R7, ADP5585ACPZ-03-R7 Default = 0000 0000 ADP5585ACBZ-02-R7 Default = 0000 0011 ADP5585ACBZ-04-R7 Default = 0000 0101 Rev. C | Page 24 of 40 Data Sheet ADP5585 RPULL_CONFIG_C Register 0x19 Table 33. RPULL_CONFIG_C Bit Descriptions Bit(s) 7 to 6 Bit Name C3_PULL_CFG Access Read/write Description 00 = enable 300 kΩ pull-up resistor. 01 = enable 300 kΩ pull-down resistor. 10 = enable 100 kΩ pull-up resistor. 11 = disable all pull-up/pull-down resistors. 5 to 4 C2_PULL_CFG Read/write 00 = enable 300 kΩ pull-up resistor. 01 = enable 300 kΩ pull-down resistor. 10 = enable 100 kΩ pull-up resistor. 11 = disable all pull-up/pull-down resistors. 3 to 2 C1_PULL_CFG Read/write 00 = enable 300 kΩ pull-up resistor. 01 = enable 300 kΩ pull-down resistor. 10 = enable 100 kΩ pull-up resistor. 11 = disable all pull-up/pull-down resistors. 1 to 0 C0_PULL_CFG Read/write 00 = enable 300 kΩ pull-up resistor. 01 = enable 300 kΩ pull-down resistor. 10 = enable 100 kΩ pull-up resistor. 11 = disable all pull-up/pull-down resistors. ADP5585AC_Z-00-R7, ADP5585AC_Z-01-R7, ADP5585ACBZ-02-R7 , ADP5585ACPZ-03-R7 Default = 0000 0000 ADP5585ACBZ-04-R7 Default = 0101 0101 RPULL_CONFIG_D Register 0x1A Table 34. RPULL_CONFIG_D Bit Descriptions Bit(s) 7 to 2 1 to 0 Bit Name N/A C4_PULL_CFG Access Description Reserved. Read/write 00 = enable 300 kΩ pull-up resistor. 01 = enable 300 kΩ pull-down resistor. 10 = enable 100 kΩ pull-up resistor. 11 = disable all pull-up/pull-down resistors. ADP5585AC_Z-00-R7, ADP5585AC_Z-01-R7, ADP5585ACPZ-03-R7 Default = 0000 0000 ADP5585ACBZ-02-R7 Default = 0000 0011 ADP5585ACBZ-04-R7 Default = 0000 0001 GPI_INT_LEVEL_A Register 0x1B Table 35. GPI_INT_LEVEL_A Bit Descriptions Bit(s) 7 to 6 5 Bit Name N/A GPI_6_INT_LEVEL Access 4 GPI_5_INT_LEVEL Read/write 3 GPI_4_INT_LEVEL Read/write 2 GPI_3_INT_LEVEL Read/write 1 GPI_2_INT_LEVEL Read/write 0 GPI_1_INT_LEVEL Read/write Read/write Description Reserved. (Reserved except for ADP5585AC_Z-01-R7 options) 0 = GPI_6 interrupt is active low (GPI_6_INT sets whenever R5 is low). 1 = GPI_6 interrupt is active high (GPI_6_INT sets whenever R5 is high). 0 = GPI_5 interrupt is active low (GPI_5_INT sets whenever R4 is low). 1 = GPI_5 interrupt is active high (GPI_5_INT sets whenever R4 is high). 0 = GPI_4 interrupt is active low (GPI_4_INT sets whenever R3 is low). 1 = GPI_4 interrupt is active high (GPI_4_INT sets whenever R3 is high). 0 = GPI_3 interrupt is active low (GPI_3_INT sets whenever R2 is low). 1 = GPI_3 interrupt is active high (GPI_3_INT sets whenever R2 is high). 0 = GPI_2 interrupt is active low (GPI_2_INT sets whenever R1 is low). 1 = GPI_2 interrupt is active high (GPI_2_INT sets whenever R1 is high). 0 = GPI_1 interrupt is active low (GPI_1_INT sets whenever R0 is low). 1 = GPI_1 interrupt is active high (GPI_1_INT sets whenever R0 is high). Rev. C | Page 25 of 40 ADP5585 Data Sheet GPI_INT_LEVEL_B Register 0x1C Table 36. Register 0x1C, GPI_INT_LEVEL_B Bit Descriptions Bit(s) 7 to 5 4 Bit Name N/A GPI_11_INT_LEVEL Access 3 GPI_10_INT_LEVEL Read/write 2 GPI_9_INT_LEVEL Read/write 1 GPI_8_INT_LEVEL Read/write 0 GPI_7_INT_LEVEL Read/write Read/write Description Reserved. 0 = GPI_11 interrupt is active low (GPI_11_INT sets whenever R10 is low). 1 = GPI_11 interrupt is active high (GPI_11_INT sets whenever R10 is high). 0 = GPI_10 interrupt is active low (GPI_10_INT sets whenever R9 is low). 1 = GPI_10 interrupt is active high (GPI_10_INT sets whenever R9 is high). 0 = GPI_9 interrupt is active low (GPI_9_INT sets whenever R8 is low). 1 = GPI_9 interrupt is active high (GPI_9_INT sets whenever R8 is high). 0 = GPI_8 interrupt is active low (GPI_8_INT sets whenever R7 is low). 1 = GPI_8 interrupt is active high (GPI_8_INT sets whenever R7 is high). 0 = GPI_7 interrupt is active low (GPI_7_INT sets whenever R6 is low). 1 = GPI_7 interrupt is active high (GPI_7_INT sets whenever R6 is high). GPI_EVENT_EN_A Register 0x1D Table 37. GPI_EVENT_EN_A Bit Descriptions Bit(s) 7 to 6 5 Bit Name N/A GPI_6_EVENT_EN Access 4 GPI_5_EVENT_EN Read/write 3 GPI_4_EVENT_EN Read/write 2 GPI_3_EVENT_EN Read/write 1 GPI_2_EVENT_EN Read/write 0 GPI_1_EVENT_EN Read/write 1 Read/write Description Reserved. (Reserved except for ADP5585AC_Z-01-R7 options) 0 = disable GPI events from GPI 6. 1 = allow GPI 6 activity to generate events on the FIFO 1. 0 = disable GPI events from GPI 5. 1 = allow GPI 5 activity to generate events on the FIFO1. 0 = disable GPI events from GPI 4. 1 = allow GPI 4 activity to generate events on the FIFO1. 0 = disable GPI events from GPI 3. 1 = allow GPI 3 activity to generate events on the FIFO1. 0 = disable GPI events from GPI 2. 1 = allow GPI 2 activity to generate events on the FIFO1. 0 = disable GPI events from GPI 1. 1 = allow GPI 1 activity to generate events on the FIFO1. GPIs in this mode are considered FIFO events and can be used for unlock purposes. GPI activity in this mode causes EVENT_INT interrupts. GPIs in this mode do not generate GPI_INT interrupts. GPI_EVENT_EN_B Register 0x1E Table 38. GPI_EVENT_EN_B Bit Descriptions Bit(s) 7 to 5 4 Bit Name N/A GPI_11_EVENT_EN Access 3 GPI_10_EVENT_EN Read/write 2 GPI_9_EVENT_EN Read/write 1 GPI_8_EVENT_EN Read/write 0 GPI_7_EVENT_EN Read/write 1 Read/write Description Reserved. 0 = disable GPI events from GPI 11. 1 = allow GPI 11 activity to generate events on the FIFO1. 0 = disable GPI events from GPI 10. 1 = allow GPI 10 activity to generate events on the FIFO1. 0 = disable GPI events from GPI 9. 1 = allow GPI 9 activity to generate events on the FIFO1. 0 = disable GPI events from GPI 8. 1 = allow GPI 8activity to generate events on the FIFO1. 0 = disable GPI events from GPI 7. 1 = allow GPI 7 activity to generate events on the FIFO1. GPIs in this mode are considered FIFO events and can be used for unlock purposes. GPI activity in this mode cause EVENT_INT interrupts. GPIs in this mode do not generate GPI_INT interrupts. Rev. C | Page 26 of 40 Data Sheet ADP5585 GPI_EVENT_INTERRUPT_EN_A Register 0x1F Table 39. GPI_INTERRUPT_EN_A Bit Descriptions Bit(s) 7 to 6 5 Bit Name N/A GPI_6_INT_EN Access 4 GPI_5_INT_EN Read/write 3 GPI_4_INT_EN Read/write 2 GPI_3_INT_EN Read/write 1 GPI_2_INT_EN Read/write 0 GPI_1_INT_EN Read/write Read/write Description Reserved. (Reserved except for ADP5585AC_Z-01-R7 options) 0 = GPI_6_INT is disabled. 1 = GPI_6_INT enabled. Asserts the GPI_INT bit (Register 0x01, Bit 1) if GPI_6_INT is set and the GPI 6 interrupt condition is met. 0 = GPI_5_INT is disabled. 1 = GPI_5_INT enabled. Asserts the GPI_INT bit (Register 0x01, Bit 1) if GPI_5_INT is set and the GPI 5 interrupt condition is met. 0 = GPI_4_INT is disabled. 1 = GPI_4_INT enabled. Asserts the GPI_INT bit (Register 0x01, Bit 1) if GPI_4_INT is set and the GPI 4 interrupt condition is met. 0 = GPI_3_INT is disabled. 1 = GPI_3_INT enabled. Asserts the GPI_INT bit (Register 0x01, Bit 1) if GPI_3_INT is set and the GPI 3 interrupt condition is met. 0 = GPI_2_INT is disabled. 1 = GPI_2_INT enabled. Asserts the GPI_INT bit (Register 0x01, Bit 1) if GPI_2_INT is set and the GPI 2 interrupt condition is met. 0 = GPI_1_INT is disabled. 1 = GPI_1_INT enabled. Asserts the GPI_INT bit (Register 0x01, Bit 1) if GPI_1_INT is set and the GPI 1 interrupt condition is met. GPI_EVENT_INTERRUPT_EN_B Register 0x20 Table 40. GPI_INTERRUPT_EN_B Bit Descriptions Bit(s) 7 to 5 4 Bit Name N/A GPI_11_INT_EN Access 3 GPI_10_INT_EN Read/write 2 GPI_9_INT_EN Read/write 1 GPI_8_INT_EN Read/write 0 GPI_7_INT_EN Read/write Read/write Description Reserved. 0 = GPI_11_INT is disabled. 1 = GPI_11_INT enabled. Asserts the GPI_INT bit (Register 0x01, Bit 1) if GPI_11_INT is set and the GPI 11 interrupt condition is met. 0 = GPI_10_INT is disabled. 1 = GPI_10_INT enabled. Asserts the GPI_INT bit (Register 0x01, Bit 1) if GPI_10_INT is set and the GPI 10 interrupt condition is met. 0 = GPI_9_INT is disabled. 1 = GPI_9_INT enabled. Asserts the GPI_INT bit (Register 0x01, Bit 1) if GPI_9_INT is set and the GPI 9 interrupt condition is met. 0 = GPI_8_INT is disabled. 1 = GPI_8_INT enabled. Asserts the GPI_INT bit (Register 0x01, Bit 1) if GPI_8_INT is set and the GPI 8 interrupt condition is met. 0 = GPI_7_INT is disabled. 1 = GPI_7_INT enabled. Asserts the GPI_INT bit (Register 0x01, Bit 1) if GPI_7_INT is set and the GPI 7 interrupt condition is met. Rev. C | Page 27 of 40 ADP5585 Data Sheet DEBOUNCE_DIS_A Register 0x21 Table 41. DEBOUNCE_DIS_A Bit Descriptions Bit(s) 7 to 6 5 Bit Name N/A GPI_6_DEB_DIS Access 4 GPI_5_DEB_DIS Read/write 3 GPI_4_DEB_DIS Read/write 2 GPI_3_DEB_DIS Read/write 1 GPI_2_DEB_DIS Read/write 0 GPI_1_DEB_DIS Read/write Read/write Description Reserved. (Reserved except for ADP5585AC_Z-01-R7 options) 0 = debounce enabled on GPI 6. 1 = debounce disabled on GPI 6. 0 = debounce enabled on GPI 5. 1 = debounce disabled on GPI 5. 0 = debounce enabled on GPI 4. 1 = debounce disabled on GPI 4. 0 = debounce enabled on GPI 3. 1 = debounce disabled on GPI 3. 0 = debounce enabled on GPI 2. 1 = debounce disabled on GPI 2. 0 = debounce enabled on GPI 1. 1 = debounce disabled on GPI 1. DEBOUNCE_DIS_B Register 0x22 Table 42. DEBOUNCE_DIS_B Bit Descriptions Bit(s) 7 to 5 4 Bit Name N/A GPI_11_DEB_DIS Access 3 GPI_10_DEB_DIS Read/write 2 GPI_9_DEB_DIS Read/write 1 GPI_8_DEB_DIS Read/write 0 GPI_7_DEB_DIS Read/write Read/write Description Reserved. 0 = debounce enabled on GPI 11. 1 = debounce disabled on GPI 11. 0 = debounce enabled on GPI 10. 1 = debounce disabled on GPI 10. 0 = debounce enabled on GPI 9. 1 = debounce disabled on GPI 9. 0 = debounce enabled on GPI 8. 1 = debounce disabled on GPI 8. 0 = debounce enabled on GPI 7. 1 = debounce disabled on GPI 7. GPO_DATA_OUT_A Register 0x23 Table 43. GPO_DATA_OUT_A Bit Descriptions Bit(s) 7 to 6 5 Bit Name N/A GPO_6_DATA Access 4 GPO_5_DATA Read/write 3 GPO_4_DATA Read/write 2 GPO_3_DATA Read/write 1 GPO_2_DATA Read/write 0 GPO_1_DATA Read/write Read/write Description Reserved. (Reserved except for ADP5585AC_Z-01-R7 options) 0 = sets output low. 1 = sets output high. 0 = sets output low. 1 = sets output high. 0 = sets output low. 1 = sets output high. 0 = sets output low. 1 = sets output high. 0 = sets output low. 1 = sets output high. 0 = sets output low. 1 = sets output high. Rev. C | Page 28 of 40 Data Sheet ADP5585 GPO_DATA_OUT_B Register 0x24 Table 44. GPO_DATA_OUT_B Bit Descriptions Bit(s) 7 to 5 4 Bit Name N/A GPO_11_DATA Access 3 GPO_10_DATA Read/write 2 GPO_9_DATA Read/write 1 GPO_8_DATA Read/write 0 GPO_7_DATA Read/write Read/write Description Reserved. 0 = sets output low. 1 = sets output high. 0 = sets output low. 1 = sets output high. 0 = sets output low. 1 = sets output high. 0 = sets output low. 1 = sets output high. 0 = sets output low. 1 = sets output high. GPO_OUT_MODE_A Register 0x25 Table 45. Register 0x25, GPO_OUT_MODE_A Bit Descriptions Bit(s) 7 to 6 5 Bit Name N/A GPO_6_OUT_MODE Access 4 GPO_5_OUT_MODE Read/write 3 GPO_4_OUT_MODE Read/write 2 GPO_3_ OUT_MODE Read/write 1 GPO_2_OUT_MODE Read/write 0 GPO_1_OUT_MODE Read/write Read/write Description Reserved. (Reserved except for ADP5585AC_Z-01-R7 options) 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. GPO_OUT_MODE_B Register 0x26 Table 46. Register 0x26, GPO_OUT_MODE_B Bit Descriptions Bit(s) 7 to 5 4 Bit Name N/A GPO_11_OUT_MODE Access 3 GPO_10_OUT_MODE Read/write 2 GPO_9_OUT_MODE Read/write 1 GPO_8_OUT_MODE Read/write 0 GPO_7_OUT_MODE Read/write Read/write Description Reserved. 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. 0 = push/pull. 1 = open drain. Rev. C | Page 29 of 40 ADP5585 Data Sheet GPIO_DIRECTION_A Register 0x27 Table 47. GPIO_DIRECTION_A Bit Descriptions Bit(s) 7 to 6 5 Bit Name N/A GPIO_6_DIR Access 4 GPIO_5_DIR Read/write 3 GPIO_4_DIR Read/write 2 GPIO_3_DIR Read/write 1 GPIO_2_DIR Read/write 0 GPIO_1_DIR Read/write Read/write Description Reserved. (Reserved except for ADP5585AC_Z-01-R7 options) 0 = GPIO 6 is an input. 1 = GPIO 6 is an output. 0 = GPIO 5 is an input. 1 = GPIO 5 is an output. 0 = GPIO 4 is an input. 1 = GPIO 4 is an output. 0 = GPIO 3 is an input. 1 = GPIO 3 is an output. 0 = GPIO 2 is an input. 1 = GPIO 2 is an output. 0 = GPIO 1 is an input. 1 = GPIO 1 is an output. GPIO_DIRECTION_B Register 0x28 Table 48. Register 0x28, GPIO_DIRECTION_B Bit Descriptions Bit(s) 7 to 5 4 Bit Name N/A GPIO_11_DIR Access 3 GPIO_10_DIR Read/write 2 GPIO_9_DIR Read/write 1 GPIO_8_DIR Read/write 0 GPIO_7_DIR Read/write Read/write Description Reserved. 0 = GPIO 11 is an input. 1 = GPIO 11 is an output. 0 = GPIO 10 is an input. 1 = GPIO 10 is an output. 0 = GPIO 9 is an input. 1 = GPIO 9 is an output. 0 = GPIO 8 is an input. 1 = GPIO 8 is an output. 0 = GPIO 7 is an input. 1 = GPIO 7 is an output. RESET1_EVENT_A Register 0x29 Table 49. RESET1_EVENT_A Bit Descriptions Bit(s) 7 Bit Name RESET1_EVENT_A_LEVEL Access Read/write 6 to 0 RESET1_EVENT_A[6:0] Read/write Description Defines which level the first reset event should be to generate the RESET1 signal. For key events, use the following settings: 0 = not applicable; releases not used for reset generation. 1 = press is used as reset event. For GPIs and logic outputs configured for FIFO updates, use the following settings: 0 = inactive event used as reset condition. 1 = active event used as reset condition. Defines an event that can be used to generate the RESET1 signal. Up to three events can be defined for generating the RESET1 signal, using RESET1_EVENT_A[6:0], RESET1_EVENT_B[6:0], and RESET1_EVENT_C[6:0]. If one of the registers is 0, that register is not used for reset generation. All reset events must be detected at the same time to trigger the reset. Rev. C | Page 30 of 40 Data Sheet ADP5585 RESET1_EVENT_B Register 0x2A Table 50. RESET1_EVENT_B Bit Descriptions Bit(s) 7 Bit Name RESET1_EVENT_B_LEVEL Access Read/write 6 to 0 RESET1_EVENT_B[6:0] Read/write Description Defines which level the second reset event should be to generate the RESET1 signal. Refer to Table 49. Defines an event that can be used to generate the RESET1 signal. Refer to Table 11. RESET1_EVENT_C Register 0x2B Table 51. RESET1_EVENT_C Bit Descriptions Bit(s) 7 Bit Name RESET1_EVENT_C_LEVEL Access Read/write 6 to 0 RESET1_EVENT_C[6:0] Read/write Description Defines which level the second reset event should be to generate the RESET1 signal. Refer to Table 49. Defines an event that can be used to generate the RESET1 signal. Refer to Table 11. RESET2_EVENT_A Register 0x2C Table 52. RESET2_EVENT_A Bit Descriptions Bit(s) 7 Bit Name RESET2_EVENT_A_LEVEL Access Read/write 6 to 0 RESET2_EVENT_A[6:0] Read/write Description Defines which level the first reset event should be to generate the RESET2 signal. For key events, use the following settings: 0 = not applicable; releases not used for reset generation. 1 = press is used as reset event. For GPIs and logic outputs configured for FIFO updates, use the following settings: 0 = inactive event used as reset condition. 1 = active event used as reset condition. Defines an event that can be used to generate the RESET2 signal. Up to two events can be defined for generating the RESET2 signal, using RESET2_EVENT_A[6:0], and RESET2_EVENT_B[6:0]. If one of the registers is 0, that register is not used for reset generation. All reset events must be detected at the same time to trigger the reset. RESET2_EVENT_B Register 0x2D Table 53. RESET2_EVENT_B Bit Descriptions Bit(s) 7 Bit Name RESET2_EVENT_B_LEVEL Access Read/write 6 to 0 RESET2_EVENT_B[6:0] Read/write Description Defines which level the second reset event should be to generate the RESET2 signal. Refer to Table 52. Defines an event that can be used to generate the RESET2 signal. Refer to Table 11. RESET_CFG Register 0x2E Table 54. RESET_CFG Bit Descriptions Bit(s) 7 Bit Name RESET2_POL Access Read/write 6 RESET1_POL Read/write 5 RST_PASSTHRU_EN Read/write Description Sets the polarity of RESET2. 0 = RESET2 is active low. 1 = RESET2 is active high. Sets the polarity of RESET1. 0 = RESET1 is active low. 1 = RESET1 is active high. Allows the RST pin to override (OR with) the RESET1signal. This function not applicable to RESET2. Rev. C | Page 31 of 40 ADP5585 Data Sheet Bit(s) 4 to 2 Bit Name RESET_TRIG_TIME[2:0] Access Read/write 1 to 0 RESET_PULSE_WIDTH[1:0] Read/write Description Defines the length of time that the reset events must be active before a reset signal is generated. All events must be active at the same time for the same duration. RESET_TRIG_TIME[2:0] is common to both RESET1 and RESET2. 000 = immediate. 001 = 1.0 sec. 010 = 1.5 sec. 011 = 2.0 sec. 100 = 2.5 sec. 101 = 3.0 sec. 110 = 3.5 sec. 111 = 4.0 sec. Defines the pulse width of the reset signals. RESET_PULSE_WIDTH[1:0] is common to both RESET1 and RESET2. 00 = 500 µs. 01 = 1 ms. 10 = 2 ms. 11 = 10 ms. PWM_OFFT_LOW Register 0x2F Table 55. Register 0x2F, PWM_OFFT_LOW Bit Descriptions Bit(s) 7 to 0 Bit Name PWM_OFFT_LOW_BYTE[7:0] Access Read/write Description Lower eight bits of PWM off time. Access Read/write Description Upper eight bits of PWM off time. Access Read/write Description Lower eight bits of PWM on time. PWM_OFFT_HIGH Register 0x30 Table 56. PWM_OFFT_HIGH Bit Descriptions Bit(s) 7 to 0 Bit Name PWM_OFFT_HIGH_BYTE[7:0] PWM_ONT_LOW Register 0x31 Table 57. PWM_ONT_LOW Bit Descriptions Bit(s) 7 to 0 Bit Name PWM_ONT_LOW_BYTE[7:0] PWM_ONT_HIGH Register 0x32 Table 58. PWM_ONT_HIGH Bit Descriptions Bit(s) 7 to 0 Bit Name PWM_ONT_HIGH_BYTE[7:0] Access Read/write Description Upper eight bits of PWM on time. Note that updated PWM times are not latched until this byte is written to. PWM count times are referenced from the internal oscillator. The fastest oscillator setting is 500 kHz (2 µs increments). Therefore, the maximum period is 2 µs × 216 = 131 ms This gives PWM frequencies from 500 kHz down to 7.6 Hz. Description Reserved. 0 = no external AND’ing. 1 = PWM signal AND’ed with an externally supplied PWM signal (C3). Defines PWM mode. 0 = continuous. 1 = executes one PWM period, then sets PWM_EN to 0. Enable PWM generator. PWM_CFG Register 0x33 Table 59. PWM_CFG Bit Descriptions Bit(s) 7 to 3 2 Bit Name N/A PWM_IN_AND Access 1 PWM_MODE Read/write 0 PWM_EN Read/write Rev. C | Page 32 of 40 Data Sheet ADP5585 LOGIC_CFG Register 0x34 Table 60. LOGIC_CFG Bit Descriptions Bit(s) 7 6 Bit Name N/A LY_INV Access 5 LC_INV Read/write 4 LB_INV R/W 3 LA_INV R/W 2 to 0 LOGIC_SEL[2:0] R/W Read/write Description Reserved. 0 = LY output not inverted before passing into logic block. 1 = inverts output LY from the logic block. 0 = LC input not inverted before passing into the logic block. 1 = inverts input LC before passing it into the logic block. 0 = LB input not inverted before passing into the logic block. 1 = inverts input LB before passing it into the logic block. 0 = LA input not inverted before passing into the logic block. 1 = inverts input LA before passing it into the logic block. Configures the digital mux for the logic block. Refer to Figure 19. 000 = off/disable. 001 = AND. 010 = OR. 011 = XOR. 100 = FF. 101 = IN_LA. 110 = IN_LB. 111 = IN_LC. LOGIC_FF_CFG Register 0x35 Table 61. LOGIC_FF_CFG Bit Descriptions Bit(s) 7 to 2 1 Bit Name N/A FF_SET Access Read/write Read/write 0 FF_CLR Read/write Description Reserved. 0 = FF not set in the logic block. Refer to Figure 19. 1 = set FF in the logic block. 0 = FF not cleared in the logic block. Refer to Figure 19. 1 = clear FF in the logic block. LOGIC_INT_EVENT_EN Register 0x36 Table 62. LOGIC_INT_EVENT_EN Bit Descriptions Bit(s) 7 to 3 2 Bit Name N/A LY_DBNC_DIS Access 1 LOGIC_EVENT_EN Read/write 0 LOGIC_INT_LEVEL Read/write Read/write Description Reserved. 0 = output of the logic block is debounced before entering the event/interrupt block. 1 = output of the logic block is not debounced before entering the event/interrupt block. Use with caution because glitches may generate interrupts prematurely. 0 = LY cannot generate interrupt. 1 = allow LY activity to generate events on the FIFO. Configure the logic level of LY that generates an interrupt. 0 = LY is active low. 1 = LY is active high. Rev. C | Page 33 of 40 ADP5585 Data Sheet POLL_TIME_CFG Register 0x37 Table 63. Register 0x37, POLL_TIME_CFG Bit Descriptions Bit(s) 7 to 2 1 to 0 Bit Name N/A KEY_POLL_TIME[1:0] Access Read/write Description Reserved. Configure time between consecutive scan cycles. 00 = 10 ms. 01 = 20 ms. 10 = 30 ms. 11 = 40 ms. PIN_CONFIG_A Register 0x38 Table 64. PIN_CONFIG_A Bit Descriptions Bit(s) 7 to 6 5 Bit Name N/A R5_CONFIG Access 4 R4_CONFIG Read/write 3 R3_CONFIG Read/write 2 R2_CONFIG Read/write 1 R1_CONFIG Read/write 0 R0_CONFIG Read/write Read/write Description Reserved. Reserved except for ADP5585AC_Z-01-R7 options) 0 = GPIO 6. 1 = Row 5. 0 = GPIO 5 (see R4_EXTEND_CFG in Table 66 for alternate configuration, RESET1). 1 = Row 4 0 = GPIO 4 (see R3_EXTEND_CFG[1:0] in Table 66 for alternate configuration, LC/PWM_OUT). 1 = Row 3 0 = GPIO 3 1 = Row 2 0 = GPIO 2 1 = Row 1 0 = GPIO 1/LY (see R0_EXTEND_CFG in Table 66 for alternate configuration, LY). 1 = Row 0 PIN_CONFIG_B Register 0x39 Table 65. PIN_CONFIG_B Bit Descriptions Bit(s) 7 to 5 4 Bit Name N/A C4_CONFIG Access 3 C3_CONFIG Read/write 2 C2_CONFIG Read/write 1 C1_CONFIG Read/write 0 C0_CONFIG Read/write Read/write Description Reserved. 0 = GPIO 11 (see C4_EXTEND_CFG in Table 66 for alternate configuration, RESET2). 1 = Column 4. 0 = GPIO 10. 1 = Column 3. 0 = GPIO 9. 1 = Column 2. 0 = GPIO 8. 1 = Column 1. 0 = GPIO 7. 1 = Column 0. PIN_CONFIG_C Register 0x3A Table 66. PIN_CONFIG_D Bit Descriptions Bit(s) 7 Bit Name PULL_SELECT Access Read/write 6 C4_ EXTEND_CFG Read/write Description 0 = 300 kΩ resistor used for row pull-up during key scanning. 1 = 100 kΩ resistor used for row pull-up during key scanning. 0 = C4 remains configured as GPIO 11. 1 = C4 reconfigured as RESET2 output. Rev. C | Page 34 of 40 Data Sheet ADP5585 Bit(s) 5 Bit Name R4_ EXTEND_CFG Access Read/write 4 3 to 2 N/A R3_EXTEND_CFG[1:0] Read/write 1 0 N/A R0_ EXTEND_CFG Read/write Description 0 = R4 remains configured as GPIO 5. 1 = R4 reconfigured as RESET1 output. Reserved. 00 = R3 remains configured as GPIO 4. 01 = R3 reconfigured as LC input for the logic block. 10 = R3 reconfigured as PWM_OUT output from PWM block. 11 = unused. Reserved. 0 = R0 remains configured as GPIO 1. 1 = R0 reconfigured as LY output from the logic block. GENERAL_CFG Register 0x3B Table 67. GENERAL_CFG Bit Descriptions Bit(s) 7 Bit Name OSC_EN Access Read/write 6 to 5 OSC_FREQ[1:0] Read/write 4 to 2 1 N/A INT_CFG Read/write 0 RST_CFG R/W Configure the response ADP5585 has to the RST pin. 0 = ADP5585 resets if RST is low. 1 = ADP5585 does not reset if RST is low. Access Description Reserved. Read/write 0 = Logic 1 interrupt is disabled. 1 = assert the INT pin if LOGIC_INT is set. Description 0 = disable internal 1 MHz oscillator. 1 = enable internal 1 MHz oscillator. Sets the input clock frequency fed from the base 1 MHz oscillator to the digital core. Slower frequencies result in less quiescent current, but key and GPI scan times increase. 00 = 50 kHz. 01 = 100 kHz. 10 = 200 kHz. 11 = 500 kHz. Reserved. Configure the behavior of the INT pin if the user tries to clear it while an interrupt is pending. 0 = INT pin remains asserted if an interrupt is pending. 1 = INT pin deasserts for 50 µs and reasserts if an interrupt is pending. INT_EN Register 0x3C Table 68. INT_EN Bit Descriptions Bit(s) 7 to 5 4 Bit Name N/A LOGIC_IEN 3 2 N/A OVRFLOW_IEN Read/write 1 GPI_IEN Read/write 0 EVENT_IEN Read/write Reserved. 0 = overflow interrupt is disabled. 1 = assert the INT pin if OVRFLOW_INT is set. 0 = GPI interrupt is disabled. 1 = assert the INT pin if GPI_INT is set. 0 = event interrupt is disabled. 1 = assert the INT pin if EVENT_INT is set. Rev. C | Page 35 of 40 ADP5585 Data Sheet APPLICATIONS DIAGRAM VDD INT RST HOST PROCESSOR SCL SDA VDD KP/LOGIC1 OUTPUT/GPI/GPO KP/LOGIC1 INPUT/GPI/GPO SDA KP/LOGIC1 INPUT/GPI/GPO SCL RST VDD ADP5585 KP/LOGIC1 INPUT/GPI/GPO/PWM/CLK KP/RESET1 OUTPUT/GPI/GPO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 I2C INTERFACE UVLO POR OSCILLATOR R0 R1 KEY SCAN AND DECODE R2 R3 INT R4 GPI SCAN AND DECODE C4 C3 C2 I/O CONFIG C1 LOGIC PWM C0 REGISTERS RESET1 GEN GND Figure 27. Typical Application Schematic Rev. C | Page 36 of 40 09841-026 RESET2 GEN Data Sheet ADP5585 OUTLINE DIMENSIONS 1.630 1.590 SQ 1.550 3 4 2 1 A BALL A1 IDENTIFIER B 1.20 REF C D 0.40 REF SEATING PLANE BOTTOM VIEW (BALL SIDE UP) SIDE VIEW COPLANARITY 0.05 0.300 0.260 0.220 0.230 0.200 0.170 10-23-2012-A 0.545 0.500 0.455 TOP VIEW (BALL SIDE DOWN) Figure 28. 16-Ball Wafer Level Chip Scale Package [WLCSP] (CB-16-10) Dimensions shown in millimeters 0.30 0.23 0.18 0.50 BSC 13 PIN 1 INDICATOR 16 1 12 EXPOSED PAD 1.75 1.60 SQ 1.45 9 TOP VIEW 0.80 0.75 0.70 SEATING PLANE 0.50 0.40 0.30 4 8 5 0.25 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. Figure 29. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 x 3 mm Body, Very Very Thin Quad (CP-16-22) Dimensions shown in millimeters Rev. C | Page 37 of 40 08-16-2010-E PIN 1 INDICATOR 3.10 3.00 SQ 2.90 ADP5585 Data Sheet ORDERING GUIDE Model 1 ADP5585ACBZ-00-R7 ADP5585ACBZ-01-R7 ADP5585ACBZ-02-R7 ADP5585ACBZ-04-R7 ADP5585ACPZ-00-R7 ADP5585ACPZ-01-R7 ADP5585ACPZ-03-R7 ADP5585CP-EVALZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 16-Ball Wafer Level Chip Scale Package [WLCSP] 16-Ball Wafer Level Chip Scale Package [WLCSP] 16-Ball Wafer Level Chip Scale Package [WLCSP] 16-Ball Wafer Level Chip Scale Package [WLCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] LFCSP Evaluation Board Z = RoHS Compliant Part. Rev. C | Page 38 of 40 Package Option CB-16-10 CB-16-10 CB-16-10 CB-16-10 CP-16-22 CP-16-22 CP-16-22 CP-16-22 Branding LJM LJN LJP Data Sheet ADP5585 NOTES Rev. C | Page 39 of 40 ADP5585 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09841-0-1/13(C) Rev. C | Page 40 of 40