FEATURES
TYPICAL APPLICATIONS CIRCUITS
Input voltage: 2.7 V to 16 V
Maximum output current: −100 mA
Integrated power MOSFETs
Four LDO selectable output voltage options
−0.505 V, −1.5 V, −2.5 V, −5 V
Adjustable output voltage range: −0.505 V to –VIN + 0.5 V
Programmable charge pump switching frequency range
100 kHz to 1 MHz
Frequency synchronization via SYNC pin
Precision enable and power good
Internal soft start
Output short-circuit and overload protection
Shorted charge pump fly capacitor protection
Integrated LDO output discharge resistor
16-lead, 4 mm × 4 mm LFCSP
APPLICATIONS
ADP5600
VIN = 12V
CIN
10µF
RPGOOD
10kΩ
VIN
C1+
PGOOD
C1–
C2+
ON
EN
OFF
C2–
SYNC
CPOUT
RT
110kΩ
CC2
1µF
VCPOUT = ~–12V
CCPOUT
10µF
CPOUT
FREQ
VLDO_OUT = –2.5V
SEL1
LDO_OUT
SEL2
FB
CLDO_OUT
2.2µF
GND
Figure 1. Fixed Output Voltage, VLDO_OUT = −2.5 V
ADP5600
VIN = 12V
Powering the negative rail on bipolar/split supply
ADC/DAC/AMP/mux applications
CC1
1µF
21096-001
Data Sheet
Interleaved Inverting Charge Pump with
Negative LDO Regulator
ADP5600
C1+
VIN
CIN
10µF
RPGOOD
10kΩ
C1–
PGOOD
C2+
ON
OFF
CC1
1µF
EN
C2–
SYNC
CPOUT
RT
110kΩ
CPOUT
FREQ
CC2
1µF
VCPOUT = ~–12V
CCPOUT
10µF
VADJ = –7.5V
LDO_OUT
SEL2
FB
GND
CLDO_OUT
2.2µF
R2
100kΩ
Figure 2. Adjustable Output Voltage, VADJ = −7.5 V
GENERAL DESCRIPTION
The ADP5600 is an interleaved charge pump inverter with an
integrated, negative, low dropout (LDO) linear regulator. The
interleaved charge pump inverter exhibits reduced output voltage
ripple and reflected input current noise over conventional inductive
or conventional capacitive based solutions. The integrated LDO
provides a rail with good regulation at sufficient power supply
rejection ratio (PSRR).
The ADP5600 charge pump operates via resistor programming or
external clock synchronization at switching frequency range of
100 kHz to 1 MHz. Operating at a higher switching frequency
allows the use of small input, output, and fly capacitors. To combine
the high switching frequency with internal field effect transistors
(FETs), compensation, and soft start gives a best-in-class total
solution size for negative rail generation.
Rev. 0
R1
49.9kΩ
21096-002
SEL1
The ADP5600 also features comprehensive fault protection for
robust applications. These protections include overload protection,
shorted fly capacitor protection, undervoltage lockout (UVLO),
and thermal shutdown. For easy sequencing, the ADP5600 has a
power-good pin.
The integrated LDO of the ADP5600 uses an advanced proprietary architecture to provide high power supply rejection. It also
achieves decent line and load transient response with only a small
2.2 μF ceramic output capacitor. The output can be configured
via the SEL1 and SEL2 pins to one of four fixed output voltages and
is adjustable from −0.505 V to –VIN + 0.5 V via an external
feedback divider.
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©2020 Analog Devices, Inc. All rights reserved.
Technical Support
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ADP5600
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Oscillator ..................................................................................... 17
Applications ....................................................................................... 1
Synchronization .......................................................................... 17
Typical Applications Circuit............................................................ 1
Current-Limit and Output Short-Circuit Protection (SCP). 18
General Description ......................................................................... 1
Power Good ................................................................................ 18
Revision History ............................................................................... 2
Undervoltage Lockout (UVLO) ............................................... 18
Specifications..................................................................................... 3
Thermal Considerations............................................................ 19
Charge Pump Regulator Specifications ..................................... 4
Applications Information .............................................................. 20
LDO Regulator Specifications .................................................... 4
Capacitor Selection ...................................................................... 20
Recommended Input and Output Capacitor Specifications ... 5
Output Voltage Settings ............................................................. 20
Absolute Maximum Ratings............................................................ 6
Noise Reduction........................................................................... 21
Thermal Resistance ...................................................................... 6
Changing the Oscillator Source On-the-Fly ........................... 21
ESD Caution .................................................................................. 6
Design Example .............................................................................. 23
Pin Configuration and Function Descriptions ............................. 7
Setting the Switching Frequency of the Charge Pump.......... 23
Typical Performance Characteristics ............................................. 8
Selecting the Flying Capacitor of the Charge Pump.............. 23
Theory of Operation ...................................................................... 14
Setting the Output Voltage of the LDO Regulator ................. 23
Inverting Charge Pump Operation .......................................... 14
Determining the Minimum VIN Voltage ............................... 23
Interleaved Inverting Charge Pump Operation ..................... 15
Circuit Board Layout Recommendations ................................... 24
Charge Pump Output Resistance ............................................. 16
Outline Dimensions ....................................................................... 25
Negative LDO Regulator ........................................................... 16
Ordering Guide .......................................................................... 25
Startup and Soft Start ................................................................. 16
Precision Enable/Shutdown ...................................................... 17
REVISION HISTORY
7/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 25
Data Sheet
ADP5600
SPECIFICATIONS
VIN = VEN = 2.7 V or |VLDO_OUT − 0.5 V| whichever is higher to 16 V, VLDO_OUT = −2.5 V, CIN = CCPOUT = 10 µF, C1 = C2 = 1 µF, CLDO_OUT =
2.2 µF , ILDO_OUT = −10 mA, fOSC = 500 kHz, TJ = −40oC to +125°C for minimum/maximum specifications unless otherwise noted.
VIN = VEN = 12 V, TA = 25°C for typical specifications, unless otherwise noted.
Table 1.
Parameters
POWER SUPPLY REQUIREMENTS
Input Voltage
Active Switching Current
Shutdown Current
VIN Undervoltage Lockout
Threshold
SEL1, SEL2 PULL-UP CURRENT
THERMAL SHUTDOWN
Threshold
Hysteresis
EN
EN Shutdown Threshold (High to
Low)
EN Rising Threshold, Precision
EN Input Hysteresis, Precision
EN Noise Filter Time
EN Leakage Current
OSCILLATOR (FREQ)
Oscillator Frequency Range
FREQ Resistor Range
FREQ = GND Frequency Range
FREQ Voltage
SYNC
Synchronization Range
SYNC Minimum Pulse Width
SYNC Minimum Off Time
SYNC Input High Voltage
SYNC Input Low Voltage
SYNC Leakage Current
POWER-GOOD OUTPUT
Rising Threshold
Hysteresis
Power-Good Rising Deglitch Time
Power-Good Leakage Current
Power-Good Output Low Voltage
Symbol
Min
VIN
ISW
2.7
3.75
5
7.7
6.5
ISHDN
UVLORISING
UVLOFALLING
UVLOHYS
ISEL
Typ
2.58
2.46
4.5
TSDRISING
TSDHYS
ENSD2
0.5
ENTH
ENHYS
ENFILT_LO-HI
1.17
2.5
90
5
Max
Unit
Test Conditions/Comments
16
4
5.6
8.5
26.1
2.63
V
mA
mA
mA
mA
µA
V
VIN = 5 V, fOSC = 100 kHz
VIN = 5 V, fOSC = 500 kHz
VIN = 5 V, fOSC = 1 MHz
VIN = 16 V, fOSC = 500 kHz
EN = GND, VIN =16 V
VIN rising
5.7
V
mV
µA
VIN falling
VIN falling
VSELx = 0.5 V
150
20
°C
°C
0.71
V
Threshold to enter shutdown
Precision threshold
5.2
V
mV
µs
µA
1.26
70
5.4
3.5
fOSC
0.1
1.1
MHz
RT
fOSC_GND
VFREQ
0
0.85
530
1.1
kΩ
MHz
V
fSYNC
tSYNC_MIN_ON
tSYNC_MIN_OFF
VIH_SYNC
VIL_SYNC
ISYNC_LKG
0.2
100
150
1.3
2.2
MHz
ns
ns
V
V
nA
PGTH
PGHYS
tPG
IPG_LKG
VOL
91
1
4.5
93
3
16
5
130
0.5
100
95
100
209
%
%
1/fOSC
nA
mV
Rev. 0 | Page 3 of 25
EN low to high noise filter
VIN = VEN = 16 V
Frequency range of the resistor programmable
internal oscillator
RT = 0 Ω
Buffered output
fOSC = fSYNC/2
VSYNC = 5.5 V
Nominal VLDO_OUT
VPG =16 V
IPG = 1 mA
ADP5600
Data Sheet
CHARGE PUMP REGULATOR SPECIFICATIONS
Table 2.
Parameters
CHARGE PUMP OUTPUT IMPEDANCE
ON RESISTANCES
VIN to Cx+ PFET Switch
Cx− to GND PFET Switch
Cx+ to GND NFET Switch
Cx− to CPOUT NFET Switch
CURRENT LIMIT
Charge Pump Input Current Limit
Charge Pump Output Current Limit
OFF STATE ISOLATION LEAKAGE
POWER EFFICIENCY
Symbol
ROUT
Min
Typ
9.5
Max
Unit
Ω
Test Conditions/Comments
ICPOUT = −50 mA
RCPHx
2.9
4.55
Ω
x = inverting Charge Pump 1 or Charge
Pump 2
RCPGx
RFNGx
RFNOx
1.95
1.81
1.83
3.69
3.41
2.9
Ω
Ω
Ω
IPMOSLIMIT
INMOSLIMIT
ICPOUT_LKG
235
270
4
88
280
330
6
mA
mA
µA
%
VIN = 16 V, VEN = 0 V
VIN = 16 V, ICPOUT = −100 mA
LDO REGULATOR SPECIFICATIONS
Table 3.
Parameter
POWER-GOOD
THRESHOLD
Rising Threshold
Hysteresis
LDO OUTPUT VOLTAGE
SEL1 = GND||SEL2 = GND
SEL1 =NC||SEL2 = GND
SEL1 = GND||SEL2 = NC
SEL1 =NC||SEL2 = NC
LDO LINE REGULATION
LDO LOAD REGULATION
Symbol
Min
Typ
Max
Unit
PGTH_CP
PGHYS_CP
−1.87
−2
130
−2.1
V
mV
Test Conditions/Comments
LDO_OUT shorted to FB, VIN = +12 V, ILDO_OUT =
−10 mA
VLDO_OUT1
VLDO_OUT2
VLDO_OUT3
VLDO_OUT4
∆VLDO_OUT/∆VIN
−0.487
−1.47
−2.465
−4.925
−0.505
−1.5
−2.5
−5.0
−0.523
−1.53
−2.535
−5.075
V
V
V
V
−0.59
−1.04
−1.42
−2.33
mV/V
mV/V
mV/V
mV/V
VLDO_OUT1 = −0.505 V
VLDO_OUT2 = −1.5 V
VLDO_OUT3 = −2.5 V
VLDO_OUT4 = −5 V
ILDO_OUT = −1 mA to −100 mA
−0.10
−0.12
−0.13
−0.16
5
160
−21
−111
400
mV/mA
mV/mA
mV/mA
mV/mA
nA
mA
mV
mV
Ω
VLDO_OUT1 = −0.505 V
VLDO_OUT2 = −1.5 V
VLDO_OUT3 = −2.5 V
VLDO_OUT4 = −5 V
ILDO_OUT = −10 mA
ILDO_OUT = −100 mA
VEN = 0 V, ILDO_OUT = −1 mA
µs
µs
VLDO_OUT3 = −2.5 V
VLDO_OUT3 = −2.5 V
∆VLDO_OUT/∆ILDO_
OUT
FB BIAS CURRENT
LDO CURRENT LIMIT
DROPOUT VOLTAGE 1
IFB
ILIM_LDO
VDROPOUT
LDO_OUT DISCHARGE
RESISTOR
SOFT START TIME 2
TOTAL START-UP TIME 3
tss
tSTART-UP
110
100
−58
−190
430
160
900
Rev. 0 | Page 4 of 25
Data Sheet
Parameter
OUTPUT NOISE
POWER SUPPLY REJECTION
RATIO
ADP5600
Symbol
LDO_OUTNOISE
Min
Typ
59
57
163
Max
Unit
μV rms
μV rms
μV rms
158
μV rms
99
μV rms
96
μV rms
45
41
69
45
39
70
40
dB
dB
dB
dB
dB
dB
dB
43
dB
68
dB
Test Conditions/Comments
10 Hz to 100 kHz, VLDO_OUT3 = −2.5 V
100 Hz to 100 kHz, VLDO_OUT3 = −2.5 V
10 Hz to 100 kHz, VADJ = −7.5 V, CNR = open,
RNR = open, R1 = 150 kΩ, R2 = 75 kΩ
100 Hz to 100 kHz, VADJ = −7.5 V, CNR = open,
RNR = open, R1 = 150 kΩ, R2 = 75 kΩ
10 Hz to 100 kHz, VADJ= −7.5 V, CNR = 100 nF,
RNR = 75 kΩ, R1 = 150 kΩ, R2 = 75 kΩ
100 Hz to 100 kHz, VADJ = −7.5 V, CNR = 100 nF,
RNR = 75 kΩ, R1 = 150 kΩ, R2 = 75 kΩ
PSRR
10 kHz, VLDO_OUT3 = −2.5 V, VIN = +4.5 V
100 kHz, VLDO_OUT3 = −2.5 V, VIN = +4.5 V
1 MHz, VLDO_OUT = −2.5 V, VIN = +4.5 V
10 kHz, VLDO_OUT4 = −5 V, VIN = +6 V
100 kHz, VLDO_OUT4 = −5 V, VIN = +6 V
1 MHz, VLDO_OUT4 = −5 V, VIN = +6 V
10 kHz, VADJ = −7.5 V, VIN = +16 V, adjustable
mode, R1 = 150 kΩ, R2 = 75 kΩ
100 kHz, VADJ = −7.5 V, VIN = +16 V, adjustable
mode, R1 = 150 kΩ, R2 = 75 kΩ
1 MHz, VADJ = −7.5 V, VIN = +16 V, adjustable
mode, R1 = 150 kΩ, R2 = 75 kΩ
1
Dropout voltage is measured by forcing the input voltage at CPOUT to be equal to the nominal output voltage of LDO_OUT. Dropout applies only for output voltages
below −2.7 V.
2
Soft start time is defined as the time between 0% to 98% of VLDO_OUT.
3
Total start-up time is defined as the time between EN going high to PGTH going high.
RECOMMENDED INPUT AND OUTPUT CAPACITOR SPECIFICATIONS
Table 4.
Parameter
CAPACITANCE1
VIN
C1
C2
CPOUT
LDO_OUT
CAPACITOR EQUIVALENT SERIES RESISTANCE (ESR)
CIN, CCPOUT
CLDO_OUT
1
Symbol
CIN
CC1
CC2
CCPOUT
CLDO_OUT
RESR
Test Conditions/Comments
TA = −40°C to +125°C
Min
Typ
4.7
0.47
0.47
4.7
1.0
10
1
1
10
2.2
Max
Unit
μF
μF
μF
μF
μF
TA = −40°C to +125°C
0.001
0.001
0.1
0.1
Ω
Ω
The minimum capacitance over the full range of the operating conditions must be greater than the minimum specifications. Consider the full range of the operating
conditions in the application during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended.
Y5V and Z5U capacitors are not recommended.
Rev. 0 | Page 5 of 25
ADP5600
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
Parameter
VIN, C1+, C2+, EN to GND
PGOOD to GND
SYNC to GND
FREQ to GND
SEL1, SEL2 to GND
C1−, C2−, CPOUT, LDO_OUT to GND
FB to GND
Operating Junction Temperature Range
Storage Temperature Range
Soldering Conditions
Rating
−0.3 V to +20 V
−0.3V to +20 V
−0.3V to +5.5 V
−0.3V to +2.5 V
−0.3V to +2.5 V
−20 V to +0.3 V
−5.5 V to +0.3 V
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
θJA is specified for the worst-case conditions, that is, a device
soldered in the circuit board (4-layer, JEDEC standard board)
for surface mount packages.
Table 6. Thermal Resistance
Package Type
CP-16-171
1
θJA
45.42
θJC
2.22
ΨJT
0.52
Unit
°C/W
θJA, θJC, and ΨJT are based on a 4-layer PCB (two signal and two power planes)
with four thermal vias connecting the exposed pad to the ground plane.
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 6 of 25
Data Sheet
ADP5600
13 C1–
14 SEL2
15 SEL1
16 GND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VIN 1
12 C1+
ADP5600
TOP VIEW
SYNC 3
11 CPOUT
10 C2+
C2–
CPOUT 8
LDO_OUT 7
FB 6
9
PGOOD 5
FREQ 4
NOTES
1. EXPOSED PAD. IT IS RECOMMENDED
THAT THE EXPOSED PAD CONNECT TO
THE CPOUT PLANE ON THE BOARD.
21096-003
EN 2
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1
2
Mnemonic
VIN
EN
3
SYNC
4
FREQ
5
PGOOD
6
FB
7
9
10
8, 11
LDO_OUT
C2−
C2+
CPOUT
12
13
14
15
16
C1+
C1−
SEL2
SEL1
GND
EP
Description
Power Input. Connect Pin 1 to the input power source and connect a 10 µF bypass capacitor between Pin 1 and GND.
Precision Enable Pin. Pull EN high to enable the ADP5600 and pull EN low to disable ADP5600. The EN pin has
an internal pull-down resistor to GND to prevent operation if EN is left floating.
Synchronization Input (SYNC). Connect this pin to an external clock with a range of 180 kHz to 2.2 MHz, to
synchronize the charge pump oscillator to fSYNC/2. If this pin is shorted to GND or does not change for some
period of time, then the internal clock frequency determined by the FREQ pin is used instead of the external
clock connected to the SYNC pin. See the Oscillator and Synchronization sections for more information. Do not
leave the SYNC pin floating. If Pin 3 is not used, short SYNC to GND.
Frequency Setting. Connect a resistor between FREQ and GND to program the oscillator frequency between
100 kHz and 1.0 MHz. If FREQ is shorted to GND, the charge pump switching frequency is programmed to 1 MHz
(typical). Do not leave this pin floating.
Power-Good Output (Open Drain). A pull-up resistor of 10 kΩ to 100 kΩ is recommended. When not used, this
pin can be left floating or connected to GND.
Feedback Voltage Sense Input. For fixed output voltages, short FB to LDO_OUT. For adjustable mode, connect
an external resistor divider between LDO_OUT and GND through the FB pin to set the output voltage.
Output of the LDO. Connect a 2.2 μF or greater capacitor from LDO_OUT to GND.
C2 Flying Capacitor Negative Terminal.
C2 Flying Capacitor Positive Terminal.
Inverting Charge Pump Output. Connect CPOUT to the exposed pad. Connect a 10 μF or greater capacitor
from CPOUT to GND.
C1 Flying Capacitor Positive Terminal.
C1 Flying Capacitor Negative Terminal.
Output Voltage Selector 2. Short SEL2 to GND or leave floating to select one of four LDO_OUT voltage options.
Output Voltage Selector 1. Short SEL1 to GND or leave floating to select one of four LDO_OUT voltage options.
Ground.
Exposed Pad. It is recommended that the exposed pad connect to the CPOUT plane on the board.
Rev. 0 | Page 7 of 25
ADP5600
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25oC, VIN = 12 V, VLDO_OUT = −2.5 V, ILDO_OUT = −10 mA, CIN = CCPOUT = 10 µF, CLDO_OUT = 2.2 µF, C1 = C2 = 1 µF, fOSC = 500 kHz, unless
otherwise noted.
30
550
VIN = 16V
VIN = 12V
VIN = 5V
VIN = 2.7V
540
OSCILLATOR FREQUENCY (kHz)
SHUTDOWN CURRENT (µA)
25
20
VIN = 16V
VIN = 12V
VIN = 2.7V
15
10
5
530
520
510
500
490
480
470
–20
0
20
40
60
80
100
120
140
JUNCTION TEMPERATURE (ºC)
450
–50
21096-004
–40
25
50
75
100
125
150
Figure 7. Oscillator Frequency (fOSC) vs. Junction Temperature (TJ) at
Various Input Voltages (VIN)
10
8
7
6
5
4
3
2
0
100
200
300
400
500
600
700
800
900 1000 1100
OSCILLATOR FREQUENCY (kHz)
7
6
5
4
2
–60
90
CHARGE PUMP POWER EFFICIENCY (%)
100
90
80
70
60
50
40
30
fOSC = 100kHz
fOSC = 500kHz
fOSC = 1MHz
10
–80
–70
–60
–50
–40
–30
CPOUT LOAD CURRENT (mA)
–20
–10
0
0
20
40
60
80
100
120
140
80
70
60
50
40
30
20
10
0
–100
21096-006
–90
–20
Figure 8. Active Switching Current (ISW) vs. Junction Temperature (TJ) at
Various Input Voltages (VIN)
100
0
–100
–40
JUNCTION TEMPERATURE (ºC)
Figure 5. Active Switching Current (ISW) vs. Oscillator Frequency (fOSC) at
Various Input Voltages (VIN)
20
VIN = 16V
VIN = 12V
VIN = 5V
VIN = 2.7V
3
TJ = +125ºC
TJ = +25ºC
TJ = –40ºC
–90
–80
–70
–60
–50
–40
–30
CPOUT LOAD CURRENT (mA)
Figure 6. Charge Pump Power Efficiency vs. CPOUT Load Current (ICPOUT)
at Various Oscillator Frequencies (fOSC), VIN = 12 V
21096-008
8
–20
–10
0
21096-009
9
ACTIVE SWITCHING CURRENT (mA)
VIN = 16V
VIN = 12V
VIN = 5V
VIN = 2.7V
21096-005
ACTIVE SWITCHING CURRENT (mA)
0
JUNCTION TEMPERATURE (ºC)
Figure 4. Shutdown Current (ISHDN) vs. Junction Temperature (TJ) at
Various Input Voltages (VIN)
CHARGE PUMP POWER EFFICIENCY (%)
–25
21096-007
460
0
–60
Figure 9. Charge Pump Power Efficiency vs. CPOUT Load Current (ICPOUT)
at Various Junction Temperatures (TJ), VIN = 12 V
Rev. 0 | Page 8 of 25
Data Sheet
ADP5600
14
16
14
12
10
8
6
TJ = +125ºC
TJ = +25ºC
TJ = –40ºC
4
2
2
4
6
8
10
12
14
16
INPUT VOLTAGE (V)
12
11
10
9
8
fOSC = 100kHz
fOSC = 250kHz
fOSC = 500kHz
fOSC = 1MHz
7
6
–100
21096-010
0
13
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
CPOUT LOAD CURRENT (mA)
Figure 10. Charge Pump Output Impedance (ROUT) vs. Input Voltage (VIN)
at Various Junction Temperatures (TJ)
21096-013
18
CHARGE PUMP OUTPUT IMPEDENCE (Ω)
CHARGE PUMP OUTPUT IMPEDENCE (Ω)
20
Figure 13. Charge Pump Output Impedance (ROUT) vs. CPOUT Load
Current (ICPOUT) at Various Oscillator Frequencies (fOSC)
= –0.505V
= –1.5V
= –2.5V
= –5.0V
LINE REGULATION (mV/V)
LOAD REGULATION (mV/mA)
VLDO_OUT1
VLDO_OUT2
VLDO_OUT3
VLDO_OUT4
40
20
0
20
40
60
80
100
120
140
JUNCTION TEMPERATURE (°C)
0
20
40
60
80
100
120
140
JUNCTION TEMPERATURE (°C)
Figure 11. LDO Line Regulation vs. Junction Temperature (TJ)
21096-014
60
21096-011
VLDO_OUT1 = –0.505V
VLDO_OUT2 = –1.5V
VLDO_OUT3 = –2.5V
VLDO_OUT4 = –5.0V
Figure 14. LDO Load Regulation vs. Junction Temperature (TJ)
–2.45
TJ = +125°C
TJ = +25°C
TJ = –40°C
–2.46
LDO OUTPUT VOLTAGE (V)
LDO OUTPUT VOLTAGE (V)
–2.47
–2.48
–2.49
–2.5
–2.51
–2.52
–2.53
–90
–80
–70
–60
–50
–40
–30
LDO_OUT LOAD CURRENT (mA)
–20
–10
0
21096-012
–100
–2.55
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
INPUT VOLTAGE (V)
Figure 15. LDO Output Voltage (VLDO_OUT2) vs. Input Voltage (VIN) at
Various Junction Temperatures (TJ)
Figure 12. LDO Output Voltage (VLDO_OUT2) vs. LDO_OUT Load Current
(ILDO_OUT) at Various Junction Temperatures (TJ)
Rev. 0 | Page 9 of 25
21096-015
TJ = +125°C
TJ = +25°C
TJ = –40°C
–2.54
ADP5600
Data Sheet
ILDO_OUT = –10mA
ILDO_OUT = –50mA
ILDO_OUT = –100mA
LDO_OUT LOAD CURRENT (mA)
4.5
5.0
Figure 16. LDO Dropout Voltage vs. LDO_OUT Load Current (ILDO_OUT) at
Various Junction Temperatures (TJ), VLDO_OUT4 = −5 V
6.5
7.0
T
VIN/VEN
VIN/VEN
1
1
3
6.0
Figure 19. LDO Output Voltage (VLDO_OUT) vs. Input Voltage (VIN) in
Dropout at Various LDO Load Currents (ILDO_OUT), VDLO_OUT4 = −5 V
T
2
5.5
INPUT VOLTAGE (V)
VCPOUT
2
VLDO_OUT
VCPOUT
3
VLDO_OUT
4
CH1 5.00V
CH3 2.00V
CH2 5.00V
M400µs
600µs
CH4 5.00V BW T
A CH4
1.80V
PGOOD
CH1 5.00V
CH3 2.00V
T
2
A CH4
1.80V
Figure 20. Power-Down Response
Figure 17. Start-Up Response
1
CH2 5.00V
M2.00ms
CH4 5.00V BW T
236µs
21096-020
PGOOD
21096-017
4
T
VIN/VEN
VIN/
VEN
1
VCPOUT
2
VCPOUT
VLDO_OUT
3
3
VLDO_OUT
PGOOD
CH1 5.00V
CH3 5.00V
CH2 5.00V
M400µs
A CH1
1.164000ms
CH4 5.00V BW T
6.20V
PGOOD
CH1 5.00V BW CH2 5.00V BW M800µs
A CH1
CH3 5.00V BW CH4 5.00V BW T
1.260000ms
Figure 18. Start-Up Response, Adjustable Output Option, VADJ = −7.5 V,
ILDO_OUT = −100 mA
Rev. 0 | Page 10 of 25
6.20V
Figure 21. Power-Down Response, Adjustable Output Option,
VADJ = −7.5 V, ILDO_OUT = −100 mA
21096-021
4
21096-018
4
21096-019
21096-016
LDO OUTPUT VOLTAGE (V)
LDO DROPOUT VOLTAGE (V)
TJ = +125°C
TJ = +25°C
TJ = –40°C
Data Sheet
ADP5600
T
T
SYNC
2
1
4
VIN
VEN
VCPOUT
2
1
C1+
3
VLDO_OUT
3
4
VLDO_OUT
PGOOD
VCPOUT
A CH4
960mV
CH1 5.00V BW CH2 2.00V BW M4.00µs
CH3 5.00V BW CH4 5.00V BW T 9.200%
EN
T
SYNC
1
1.64V
Figure 25. Oscillator Frequency (fOSC) Transition,
RT = 110 kΩ to fSYNC = 2.2 MHz, ICPOUT = −100 mA
Figure 22. Start-Up Response, VIN First
T
A CH2
21096-026
CH1 5.00V
CH2 5.00V
M800µs
CH3 2.00V B W CH4 2.00V BW T
216µs
21096-022
0
1
2
2
0.023V/µs
0.025V/µs
VIN
VCPOUT
C1+
VLDO_OUT
3
3
C2+
C1+
4
A CH2
1.24V
CH1 500mV BW CH2 500mV BW M200µs
A CH1
CH3 5.00mVΩ BW CH4 5.00V BW T
492µs
Figure 26. Line Transient Response, VIN = 4 V to 4.2 V, ILDO_OUT = −100 mA
Figure 23. Oscillator Frequency (fOSC) Transition,
RT = 110 kΩ to fSYNC = 2.2 MHz
T
T
1
ILDO_OUT
1
4.17V
21096-028
CH1 5.00V BW CH2 2.00V BW M4.00µs
CH3 5.00V BW CH4 5.00V BW T 9.200%
21096-023
4
0.011A/µs
V IN
VEN
4
2
VCPOUT
VCPOUT
2
VLDO_OUT
VLDO_OUT
3
3
C1+
CH1 5.00V B W CH2 5.00V BW M800µs
CH3 2.00V B W CH4 2.00V BW T
368µs
A CH1
5.60V
4
CH1 50.0mA BW CH2 2.00mA BW M20.0ms A CH1
CH3 10.00mVΩ BW CH4 10V
T
60.20000ms
–58.0mA
21096-029
PGOOD
21096-025
0
Figure 27. Load Transient Response, ILDO_OUT = −10 mA to −100 mA
Figure 24. Start-Up Response, VEN First
Rev. 0 | Page 11 of 25
ADP5600
Data Sheet
= –0.505V
= –1.5V
= –2.5V
= –5.0V
100
1k
10
10k
100k
1M
–100
10M
–90
–80
FREQUENCY (Hz)
Figure 28. Noise Spectral Density vs. Frequency at Various LDO Output
Voltages
–60
–50
–40
–30
–20
–10
0
Figure 31. Total Integrated Noise vs. LDO_OUT Load Current (ILDO_OUT)
10Hz TO 100kHz
100Hz TO 100kHz
T
TOTAL INTEGRATED NOISE (µV rms)
VIN
1
–70
LDO_OUT LOAD CURRENT (mA)
21096-033
VLDO_OUT1
VLDO_OUT2
VLDO_OUT3
VLDO_OUT4
TOTAL INTEGRATED NOISE (µV rms)
NOISE SPECTRAL DENSITY (nV/√Hz)
10Hz TO 100kHz
100Hz TO 100kHz
0.12V/µs
VCPOUT
2
VLDO_OUT
3
C1+
11.7V
100
21096-031
CH1 2.00V BW
A CH1
CH2 1.00V BW M200µs
CH3 10.0mVΩ BW CH4 10.0V BW T
468µs
T
400
500
600
700
800
900
1000 1100
Figure 32. Total Integrated Noise vs. Oscillator Frequency (fOSC)
ILDO_OUT
ILDO_OUT
ILDO_OUT
ILDO_OUT
0.037A/µs
ILDO_OUT
= –1mA
= –10mA
= –50mA
= –100mA
VCPOUT
PSRR (dB)
2
0.029A/µs
300
OSCILLATOR FREQUENCY (kHz)
Figure 29. Line Transient Response, VIN = 11 V to 12 V, ILDO_OUT = −100 mA
1
200
21096-034
4
VLDO_OUT
3
CH1 100mA BW CH2 2.00V BW M20.0ms
A CH1
CH3 10.00mVΩ BW CH4 10V
T
60.20000ms
–82.0mA
1
21096-032
4
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 33. VIN to LDO_OUT PSRR vs. Frequency at Various ILDO_OUT
Figure 30. Load Transient Response, ILDO_OUT = −1 mA to −100 mA
Rev. 0 | Page 12 of 25
21096-035
C1+
Data Sheet
ADP5600
C1+
T
T
C1+
4
4
IIN
1
1
2
2
3
3
IIN
VCPOUT
VLDO_OUT
VCPOUT
VLDO_OUT
PGOOD
100µs
A CH2
T
191.0000µs
–3.40V
21096-036
0
CH1 200mA BW CH2 5.00V BW
CH3 1.00V BW CH4 10.0V BW
CH1 200mA BW CH2 5.00V BW M100µs
A CH2
CH3 1.00V B W CH4 10.0V BW T
191µs
–3.40V
21096-039
PGOOD
0
Figure 37. CPOUT Recovery from Short Circuit
Figure 34. CPOUT Entry to Short Circuit
C1+
VIN = 4.5V
VIN = 12V
VIN = 16V
T
4
2
PSRR (dB)
1
IIN
VCPOUT
3
VLDO_OUT
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
21096-037
1
CH1 100mA BW CH2 5.00V BW M400µs
A CH3
CH3 1.00V B W CH4 10.0V BW T
78.8µs
Figure 35. VIN to LDO_OUT PSRR vs. Frequency at
Various Input Voltages (VIN)
–480mV
21096-040
PGOOD
0
Figure 38. LDO_OUT Entry to Short Circuit
fOSC = 100kHz
fOSC = 250kHz
fOSC = 500kHz
fOSC = 1.1MHz
C1+
T
PSRR (dB)
4
2
VCPOUT
1
IIN
3
VLDO_OUT
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
Figure 36. VIN to LDO_OUT PSRR vs. Frequency at
Various Oscillator Frequencies (fOSC)
PGOOD
CH1 100mA BW CH2 5.00V BW M40µs
A CH3
CH3 1.00V B W CH4 10.0V BW T
60.8µs
–1.16V
Figure 39. LDO_OUT Recovery From Short Circuit
Rev. 0 | Page 13 of 25
21096-041
10
21096-038
0
1
ADP5600
Data Sheet
THEORY OF OPERATION
CHARGE
CONTROL
CPH1
VIN
FNG1
UVLO
GND
STARTUP
AND
PROTECTION
TSD
fSYNC
SYNC
RT
FREQ
C1+
C1–
CP
SOFT START
CPG1
INVERTING
CHARGE PUMP 1
÷2
VFREQ
FREQUENCY
CONTROL
×1
FNO1
fOSC
C2+
FNG2
CURRENT SENSE
C2–
ISEL
ENTH
ON
OFF
LEVEL
SHIFTER
EN
REFERENCE
AND
THRESHOLD
GENERATOR
–
CPG2
ENTH
PGTH
+
INVERTING
CHARGE PUMP 2
PGTH_CP
1MΩ
STARTUP
FNO2
VFREQ
CPOUT
LDO
SOFT START
–
+
ISEL
LDO
FLOAT
ISEL
FLOAT
SEL2
SEL1
GND
NC
GND
NC
SEL2 VREF
GND –0.5V
GND –1.5V
NC
–2.5V
NC
–5.0V
VREF
EN_LDO
×1
1µA
CSS
LDO_OUT
VIN
PGOOD
NC = NO CONNECTION (FLOATING)
NOISE
FILTER
–
400Ω
PGTH
FB
+
21096-042
GND
LDO_IN
SEL1
GND
ADP5600
Figure 40. Functional Block Diagram
INVERTING CHARGE PUMP OPERATION
The basic voltage conversion task is achieved using a switched
capacitor technique with two external charge storage capacitors.
An internal oscillator and switching network transfer charge
between the two charge storage capacitors. The basic principle
of the voltage inversion scheme is illustrated in Figure 41.
C+
S1
VIN
+
CIN
+
S2
S3
CFLY
+
S4
COUT
OUT = –VIN
C–
Ф1
OSCILLATOR
Ф2
Figure 41. Basic Inverting Charge Pump
Rev. 0 | Page 14 of 25
21096-043
The ADP5600 is unique among inverting regulators in that it has
two charge pump blocks that operate in an interleaving manner.
Interleaved operation gives greatly reduced input and output
voltage ripple without sacrificing efficiency, output resistance, or
ease of use compared to inductor-based solutions. An LDO
regulates the output voltage and filters out low frequency spurious
signals.
Data Sheet
ADP5600
The net result at steady state is voltage inversion at OUT with
respect to GND. Ideally, capacitor COUT maintains its voltage
during φ1. However, due to limited storage capacity, this voltage
drops due to the load (IOUT) until φ2 arrives. This discharging
and charging action of COUT is the output ripple. The charge
transfer efficiency depends on the on-resistance of the switches,
the frequency at which they are being switched, and on the
equivalent series resistance (ESR) of the external capacitors. For
minimum losses and maximum efficiency, capacitors with low
ESR are, therefore, recommended.
CIN
+
CPG1
FNG1
CC1
FNO1
C2+
CPG2
VIN
+
CPH2
FNO2
+
CC2
FNG2
CPOUT = –VIN
CCPOUT
C2–
Ф1
OSCILLATOR
Ф2
Figure 42. Interleaved Operation
This approach provides a roughly constant input and output
current that dramatically reduces the voltage ripple. For an
interleaved inverting charge pump, the output voltage ripple is
given by
ICPOUT
ICPOUT ROUT 2 RON
4 fOSC CCPOUT
1
VCPOUT
CC1
CCPOUT
where:
IOUT
2 fOSC COUT
ΔVCPOUT is the ripple voltage in CPOUT.
ICPOUT is the load current in CPOUT.
fOSC is the charge pump switching frequency.
CCPOUT is the output capacitor in CPOUT.
CC1 is the fly capacitor.
ROUT is the effective output resistance of the charge pump.
RON is the average on resistance of the four switches.
1
β= 8
.
e fOSC RON CC1
Similarly, the input voltage ripple is always
VIN
+
C1–
The charging and discharging current are always discontinuous
and the output voltage ripple for the charge pumps is always
VOUT
C1+
CPH1
VIN
21096-044
In Figure 41, an oscillator generating antiphase signals (φ1 and
φ2) controls the S1, S2, and S3, S4 switches. During the charging
phase, φ1, the S1 and S2 switches are closed, charging CFLY up to
the voltage at VIN. During output phase, φ2, S1 and S2 open
and S3 and S4 close. The positive terminal of CFLY is connected
to GND via S3 and the negative terminal of CFLY connects to
OUT via S4. The charge on CFLY is transferred to COUT during φ2.
IOUT
2 fOSC CIN
where:
ΔVOUT is the output voltage ripple.
ΔVIN is the input voltage ripple.
IOUT is the charge pump load current.
fOSC is the charge pump switching frequency.
CIN is the charge pump input capacitor.
COUT is the charge pump output capacitor.
A comparison of the conventional charge pump topology and the
interleaving approach is shown in Figure 43 and Figure 44.
T
Therefore, the voltage ripple (noise) can only be improved by
decreasing IOUT (impractical), increasing the switching frequency
(less efficient), or increasing the capacitance (costly).
By adding another charge pump of the opposite phase, the
ADP5600 offers a solution with an almost continuous current
flowing at the input and output nodes, greatly reducing the
voltage ripple.
1
VIN
2
CPOUT
INTERLEAVED INVERTING CHARGE PUMP
OPERATION
Rev. 0 | Page 15 of 26
3
C+
CH1 2.00mVΩ BW CH2 2.00mVΩ BW M1.00µs A CH4
CH3 10V BW
T
0s
6.80V
21096-045
The ADP5600 has two inverting charge pumps that operate in
an interleaving manner, requiring the use of two small flying
capacitors (CC1 and CC2), which are typically of the same value.
Each fly capacitor operates on a separate charge pump inverter that
runs out of phase with each other. The output is then combined at
CPOUT as shown in Figure 42. The interleaving operation
results in a periodic ripple that is twice the frequency of the
oscillator.
Figure 43. Noninterleaved Charge Pump Operation (fOSC = 500 kHz,
CIN = 10 μF, C1 = 1 μF, C2 = Float, CCPOUT = 10 μF)
ADP5600
Data Sheet
T
CPOUT
LDO_OUT
–
VIN
PGTH_CP
SEL1
SEL2
2
CPOUT
REFERENCE
GENERATOR
PGOOD
+
VREF
–
– +
×1
FB
GND
PGTH
21096-048
1
+
Figure 46. Simplified LDO Model
STARTUP AND SOFT START
C+
CH1 2.00mVΩ BW CH2 2.00mVΩ BW M1.00µs A CH4
CH3 10V BW
T
0s
6.80V
21096-046
Charge Pump Startup
Figure 44. Interleaved Charge Pump Operation (fOSC = 500 kHz, CIN = 10 μF,
C1 = C2 = 1 μF, CCPOUT = 10 μF)
CHARGE PUMP OUTPUT RESISTANCE
The output resistance is the main loss contributor in a charge
pump switching converter. A simplified model is shown in
Figure 45 where the output resistance is just before the output
capacitor. The model shows that when a load current, ICPOUT, is
pulled from VCPOUT, a resulting voltage drop is generated.
ICPOUT
ROUT
+
If VIN ≥ UVLORISING and VEN < ENTH, the output pull-down resistor
is enabled, discharging the output. If VIN < UVLORISING, the output
pull-down resistor is disabled.
LDO Soft Start
VCPOUT
CCPOUT
If the voltage magnitude at CPOUT exceeds PGTH_CP, the LDO
is enabled and starts to ramp up the reference voltage at the
input of the error amplifier, causing a soft start response at
LDO_OUT. Estimate the LDO soft start time, tSS, using the
following formula:
21096-047
–VIN
The ADP5600 starts switching when VIN ≥ UVLORISING and VEN ≥
ENTH. If left unprotected, large inrush currents can flow from CIN to
C1 and C2 until the capacitors reach their steady state values.
Therefore, the ADP5600 implements a controlled soft start profile
where the maximum input current is limited to 200 mA over a time
period.
Figure 45. Simplified Output Resistance Model
Always consider the output resistance when designing for a
desired output voltage because the voltage drop across the
charge pump scales with the load current.
tSS = (CSS × VLDO_OUT)/ISS
To estimate ADP5600 output resistance, ROUT, use the following
equation:
ROUT = 1/(2 × C1 × fOSC) + 4 × RON + 2 × RC1_ESR
where:
RON is the average on resistance of the four switches, the typical
value is ~2.1 Ω.
RC1_ESR is the ESR of C1.
where:
VLDO_OUT, output voltage according to SEL1 and SEL2.
CSS, internal soft start capacitor, is 98.4 pF.
ISS, internal source current to CSS, is 1 μA.
If VCPOUT is less negative than PGTH_CP, the LDO is disabled and
the output pull-down resistor is enabled.
Figure 47 shows the start-up response of ADP5600 at different
LDO output voltages.
NEGATIVE LDO REGULATOR
10
The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the
feedback voltage is more positive than the reference voltage, the
gate of the NMOS transistor is pulled toward GND, allowing
more current to pass and increasing the output voltage magnitude.
If the feedback voltage is more negative than the reference voltage,
the gate of the NMOS transistor is pulled toward VCPOUT,
allowing less current to pass and decreasing the output voltage.
8
VIN, EN, CPOUT, LDO_OUT (V)
Internally, the ADP5600 has a negative LDO regulator that consists
of a reference, an error amplifier, a feedback voltage divider, and an
N-channel metal-oxide-semiconductor (NMOS) pass transistor.
Current flows from CPOUT to LDO_OUT via the NMOS pass
transistor, which is controlled by the error amplifier.
Rev. 0 | Page 16 of 25
6
4
2
0
–2
VIN
VEN
VCPOUT
VLDO_OUT4 = –5.0V
VLDO_OUT3 = –2.5V
VLDO_OUT2 = –1.5V
VLDO_OUT1 = –0.505V
–4
–6
–8
–10
–4
–3
–2
–1
0
1
2
3
4
TIME (ms)
Figure 47. Start-Up Response at Various LDO Output Voltages
21096-049
3
Data Sheet
ADP5600
Through an internal switch, the precision EN pin has an internal
pull-down resistor of approximately 1 MΩ, providing a default
turn-off if the EN pin is open. However, it is not recommended
to leave EN open. EN should be pulled high or low to enable or
disable the device, respectively.
1000
900
800
700
ISW (mA)
4
3
2
0.2
0.4
0.6
0.8
1.0
1.2
1.4
EN VOLTAGE (V)
1.6
1.8
2.0
21096-050
1
0
200
100
0
0
100
200
300
400
500
600
RT (kΩ)
700
800
900
1000
Figure 49. fOSC vs. RT
To synchronize the ADP5600, connect an external clock to the
SYNC pin. The frequency of the external clock can be in the
range of 180 kHz to 2.2 MHz. The ADP5600 uses the rising
edge of this signal to create the 50% duty cycle charge pump
oscillator. Therefore, each of the two charge pumps operates at
one half of the SYNC frequency, and the input and output
voltage ripple frequency is exactly at the original SYNC input
frequency.
5
0
400
SYNCHRONIZATION
TJ = +125ºC
TJ = +25ºC
TJ = –40ºC
6
500
300
When the EN pin voltage exceeds 0.8 V (typical), the ADP5600
starts up and enables its housekeeping block. Below this voltage,
the device operates in a deep shutdown mode for minimum
current consumption. As EN voltage rises to 1.2 V, the precision
enable is triggered, turning on the oscillator, charge pump, and
LDO blocks.
7
600
21096-051
The EN input pin has a precision analog threshold of 1.2 V
(typical) with 70 mV of hysteresis. When the enable voltage
exceeds 1.2 V, the regulator turns on; when it falls below 1.13 V
(typical), the regulator turns off. To force the regulator to automatically start when input power is applied, connect EN to VIN.
Figure 49 shows the typical relationship between fOSC and RT.
The adjustable frequency allows the user to make decisions based
on the trade-off between efficiency and solution size.
fOSC (kHz)
PRECISION ENABLE/SHUTDOWN
Figure 48. ISW vs. EN Voltage
ADP5600 also includes an output discharge resistor to force the
CPOUT and LDO output voltages to zero when the ADP5600 is
disabled. This procedure ensures that the outputs of CPOUT and
the LDO are always in a well-defined state, whether enabled or not.
If this external clock is applied to the SYNC pin prior to EN,
then the ADP5600 starts up with the SYNC signal running the
oscillator. If the external clock is applied after the ADP5600
starts up, then the ADP5600 uses the oscillator set by the
condition of the FREQ pin until the SYNC signal becomes
available. In this way, the charge pump starts up normally even
if there is some delay between the enable of the ADP5600 and
the application of the synchronization clock.
OSCILLATOR
The oscillator frequency, fOSC, of the ADP5600 can be set to a value
from 100 kHz to 1 MHz by connecting a resistor, RT, from the
FREQ pin to ground. The oscillator frequency can be estimated
using the following equation:
fOSC [kHz] = 64,700/RT [kΩ]
If RT is approximately 50 kΩ or less, the oscillator frequency clamps
at near 1 MHz.
Rev. 0 | Page 17 of 25
ADP5600
Data Sheet
CURRENT-LIMIT AND OUTPUT SHORT-CIRCUIT
PROTECTION (SCP)
T
2
VCPOUT
1
IIN
3
–INMOSLIMIT
VLDO_OUT
CPOUT
CIN
+
CC1
+
+
CC2
+
CCPOUT
PGOOD
0
21096-052
VIN
CH1 100mA BW CH2 5.00V
CH3 1.00V B W CH4 10.0V
Figure 50. Current Limit, C1 Charging Phase and C2 Output Phase
B
W
B
W
M400µs
A CH3
T
78.8µs
–480V
21096-055
IPMOSLIMIT
C1+
4
The ADP5600 includes a current-limit protection circuitry to
limit the input and output current. The current-limit circuitry
clamps the current flow to 200 mA on both the charging phase
and output phase. Because C1 and C2 are out of phase, there is a
continuous 200 mA flowing at VIN and CPOUT, as shown in
Figure 50 and Figure 51.
Figure 53. LDO_OUT Entry to Short Circuit
IPMOSLIMIT
–INMOSLIMIT
POWER GOOD
CPOUT
CIN
+
C C2
+
+
CC1
+
CCPOUT
21096-053
VIN
Figure 51. Current Limit, C2 Charging Phase and C1 Output Phase
Figure 52 shows the response of ADP5600 when a hard short
from CPOUT to ground occurs.
C1+
T
4
Power good (PGOOD) is an active high, open-drain output and
requires a resistor to pull it up to a voltage. When PGOOD is
high, it indicates that the voltage on the FB pin, and therefore
the LDO output voltage, is near the desired value. A low on the
PGOOD pin indicates that the voltage on the FB pin is not
within the desired value. There is an eight-switching cycle
waiting period after FB goes below PGTH and PGOOD asserts
low. If VFB goes above PGTH within the eight switching cycles,
the event is ignored by the PGOOD circuitry.
UNDERVOLTAGE LOCKOUT (UVLO)
Undervoltage lockout circuitry is integrated in the ADP5600 to
prevent the occurrence of power-on glitches. If the VIN voltage
drops below UVLOFALLING, then the ADP5600 partially shuts
down with the oscillator, charge pump, and LDO regulator
turned off. When the VIN voltage rises again above UVLORISING,
the soft start period is initiated and the ADP5600 is fully
enabled.
2
3
VCPOUT
VLDO_OUT
PGOOD
0.1
UVLO_RISING
UVLO_FALLING
0
Figure 52. CPOUT Entry to Short Circuit
If the hard short occurs from LDO_OUT to GND, the
ADP5600 LDO current limit is hit first, so that only −160 mA is
conducted into the short.
–0.1
–0.2
–0.3
–0.4
Rev. 0 | Page 18 of 25
2.70
2.68
2.66
2.64
21096-056
INPUT VOLTAGE (V)
Figure 54. UVLO Threshold
2.62
2.60
2.58
2.56
2.54
2.52
2.50
2.48
2.40
–0.6
2.46
–0.5
2.44
–3.40V
2.42
CH1 200mA BW CH2 5.00V BW M100µs
A CH2
CH3 1.00V BW CH4 10.0V BW T
191µs
21096-054
0
LDO OUTPUT VOLTAGE (V)
1
IIN
Data Sheet
ADP5600
The junction temperature of the ADP5600 can be calculated by
TA = 25°C
TA = 50°C
TA = 85°C
TJ = TA + (PD × θJA)
where:
TA is the ambient temperature.
θJA is the JEDEC thermal resistance.
PD is the power dissipation in the die, given by
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
TOTAL POWER DISSIPATION (W)
Figure 55. Junction Temperature vs. Total Power Dissipation at Various
Ambient Temperatures
PD = ((VIN – VLDO_OUT) × ILDO_OUT) + (VIN × ISW)
where:
VIN and VLDO_OUT are the input and output voltages, respectively.
ILDO_OUT is the LDO load current.
ISW is the active switching current.
Rev. 0 | Page 19 of 25
21096-057
If the ADP5600 junction temperature rises above 150°C, the
internal thermal shutdown circuit turns off the oscillator, charge
pump, and LDO for self protection. Extreme junction temperatures
can be the result of high current operation, poor circuit board
thermal design, and/or high ambient temperature. TSDHYS is
included in the thermal shutdown circuit so that if an overtemperature event occurs, the ADP5600 does not return to normal
operation until the on-chip temperature drops below 135°C.
Upon recovery, both the charge pump and LDO soft starts are
initiated before normal operation begins.
Figure 55 shows junction temperature calculations for different
ambient temperatures and power dissipation.
JUNCTION TEMPERATURE (°C)
THERMAL CONSIDERATIONS
ADP5600
Data Sheet
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Charge Pump Input and Output Capacitor Selection
The input and output capacitors dictate the amount of ripple
voltage present in their respective nodes. The minimum effective
capacitance that is required to keep the input and output ripple at
a reasonable level is 4.7 μF. A 10 μF 10% X7R ceramic capacitor
with twice the voltage rating compared to the intended input
voltage is recommended for CIN and CCPOUT.
Charge Pump Flying Capacitor Selection
10.9
10.1
Figure 57. Output Transient Response, CLDO_OUT = 10 μF
OUTPUT VOLTAGE SETTINGS
9.9
VCPOUT = −(VIN + ICPOUT × ROUT)
9.7
where:
VCPOUT is the voltage at CPOUT.
VIN is the voltage at VIN.
ICPOUT is the load current at CPOUT.
ROUT is the charge pump output resistance.
9.5
9.3
9.1
8.9
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
ICPOUT (mA)
21096-058
8.7
8.5
–100
–49mA
21096-059
CH1 50mA BW
CH2 2.00V BW M20.0ms A CH1
CH3 10.0mV Ω BW CH4 10.0V BW T
60.20000ms
The inverting charge pump provides a voltage on CPOUT that
is approximately equal to the negative of its input voltage and
some loss, depending on the output current, ICPOUT, and output
resistance, ROUT. More specifically, the CPOUT voltage is given
by the equation
C1, C2 = 0.47µF
C1, C2 = 1µF
C1, C2 = 10µF
10.3
ROUT (Ω)
4
Figure 56. ROUT vs. ICPOUT at Different CFLY Values, fOSC = 500 kHz
LDO Capacitor Selection
ADP5600 is designed to operate with small space-saving
ceramic capacitors, as long as its ESR value is taken into
consideration. The ESR of the output capacitor affects the
stability of the LDO control loop. A minimum of 2.2 μF
capacitance with an ESR of 0.1 Ω or less is recommended to
ensure the stability of the ADP5600. Transient response to
changes in load current is also affected by output capacitance.
Using a larger value of output capacitance improves the transient
response of the ADP5600 to large changes in load current.
Figure 57 shows the transient response at CLDO_OUT = 10 μF.
The LDO output voltage of the ADP5600 can be configured for
preprogrammed, fixed ,output voltages or adjusted using feedback
resistors. Setting the SEL1 and SEL2 pins changes the LDO
fixed output voltage, according to Table 8.
Table 8. LDO Fixed Output Voltage Configurations
SEL1
GND
Floating
GND
Floating
SEL2
GND
GND
Floating
Floating
VLDO_OUT
−0.505 V
−1.5 V
−2.5 V
−5.0 V
If the desired output voltage of the LDO is −0.505 V, −1.5 V, −2.5 V,
or −5.0 V, set the SEL1 and SEL2 pins as shown in Table 8 and
connect the FB pin directly to LDO_OUT. To obtain any other
voltage between −0.505 V and –VIN, use a resistor divider on the
FB pin, as shown in Figure 58.
CPOUT
INVERTING
CHARGE PUMP
VIN
CPOUT
SEL1
SEL2
NEGATIVE
LDO
FB
R1
R2
Figure 58. LDO Output Voltage Setup
Rev. 0 | Page 20 of 25
VLDO_OUT
21096-060
10.5
VLDO_OUT
C1+
The flying capacitance affects the output resistance of the charge
pump, as seen in Figure 56. A low flying capacitance causes a
voltage drop from the input to output transfer due to the small
charge storage capacity and higher reactance. In general, higher
flying capacitance improves both the load transient response
and the steady state ripple.
10.7
VCPOUT
2
3
T
ILDO_OUT
1
Data Sheet
ADP5600
where:
VADJ is the programmed adjustable LDO output voltage.
VLDO_OUT is the LDO output voltage when the LDO_OUT pin is
shorted to the FB pin.
R1 is the feedback resistor between LDO_OUT and FB.
R2 is the feedback resistor between FB and GND (R2 is
recommended to be 40 kΩ or higher).
NOISE REDUCTION
The low output noise of the ADP5600 is achieved by keeping the
LDO error amplifier in unity gain and setting the reference
voltage equal to the output voltage. The ADP5600 uses two feedback resistors to adjust the output of the LDO. The disadvantage
of this LDO scheme is that the output voltage noise is proportional
to the error amplifier gain and total feedback resistance.
The LDO circuit can be modified slightly to reduce the output
voltage noise to levels close to that of the fixed output of the
ADP5600. The circuit shown in Figure 59 adds two additional
components to the output voltage setting resistor divider. CNR
and RNR are added in parallel with R2 to reduce the ac gain of
the error amplifier. RNR is chosen to be nearly equal to R2, limiting
the ac gain of the error amplifier to approximately 6 dB. The
actual gain is the parallel combination of RNR and R1 divided by R2.
This resistance ensures that the error amplifier always operates at
greater than unity gain.
CNR is chosen by setting the reactance of CNR equal to R1 − RNR
at a frequency between 10 Hz and 100 Hz. This capacitance sets
the frequency where the ac gain of the error amplifier is 3 dB down
from its dc gain.
GND
LDO_OUT
+
R2
75kΩ
DC gain of 3 (9.54 dB)
High frequency ac gain of 1.67 (4.44 dB)
Measured rms noise of the adjustable LDO at −100 mA
without noise reduction of ~163 μV rms
Measured rms noise of the adjustable LDO at −100 mA
with noise reduction circuit of ~99 μV rms
•
Figure 60 shows the difference in noise spectral density for the
adjustable ADP5600 set to −7.5 V with and without the noise
reduction network. In the 20 Hz to 20 kHz frequency range, the
reduction in noise is observable.
10,000
1,000
100
10
1
WITHOUT NOISE REDUCTION
WITH NOISE REDUCTION
0.1
10
1k
10k
100k
1M
10M
Figure 60. VADJ = −7.5 V Adjustable ADP5600 With and Without the
Noise Reduction Network (CNR and RNR)
CHANGING THE OSCILLATOR SOURCE ON-THE-FLY
The Synchronization section describes how the charge pumps
react on application and removal of an external clock on the
SYNC pin. The charge pump frequency transitions smoothly
upon syncing to the external clock. However, upon removal of
the external clock, the charge pump stops switching, which
causes a drop at CPOUT, leaving the CCPOUT supplying the
charge requirement of the output (see Figure 61).
T
C1+
RNR
75kΩ
190.65µs
1.1MHz
530kHz
3
+ CNR
100nF
R1
150kΩ
100
FREQUENCY (Hz)
VIN
VADJ = –7.5V
FB
–2.1V
4
VCPOUT
21096-061
CLDO_OUT
2.2µF
•
•
•
21096-062
VADJ
R1
VLDO_OUT 1
R2
Based on the component values shown in Figure 59, the
ADP5600 has the following characteristics:
NOISE SPECTRAL DENSITY (nV/√Hz)
For the best noise performance, choose the LDO output voltage
nearest to the desired adjustable LDO output voltage without
exceeding it. For example, if the desired adjustable LDO output
voltage is −3.3 V, then choose the −2.5 V LDO output voltage
(SEL1 = GND, SEL2 = floating), and place a resistor divider
between LDO_OUT, FB, and ground. The programmed
adjustable output voltage, VADJ, can be calculated as
SYNC
Figure 59. Noise Reduction Modification
2.2MHz
The noise of the adjustable LDO is found by using the following
formula, assuming the noise of a fixed output LDO is approximately 59 μV:
CH1 5.00V BW
CH3 5.00V BW
Noise = 59 μV × (RPAR + R2) ÷ R2
where RPAR is a parallel combination of R1 and RNR.
CH2 5.00V BW M40µs
CH4 5.00V BW
A CH2 TIMEOUT
21096-063
2
Figure 61. Response of CPOUT upon Removal of the External Clock on SYNC
Rev. 0 | Page 21 of 25
ADP5600
Data Sheet
If LDO is the only load of CPOUT and it has not reached its
dropout region then the LDO can be represented by a constant
current source and the effective circuit at the charge pump
output is shown in Figure 62.
+
ICPOUT
21096-064
VCPOUT
CCPOUT
Figure 62. Simplified Circuit of the Output
upon Removal of External Clock on SYNC
VSYNCOFF = (ICPOUT × tSYNCOFF)/CCPOUT
where:
VSYNCOFF is the drop from the initial CPOUT voltage.
tSYNCOFF is 189.63 µs (typical).
ICPOUT is the total current being pulled out of the CCPOUT
capacitor.
CCPOUT is the effective capacitance at CPOUT, this includes
tolerance, dc bias effect, and temperature coefficient.
The effective circuit is similar to a simple discharging of a
capacitor using a current source, ICPOUT. This drop can be
estimated using the following equation:
Rev. 0 | Page 22 of 25
Data Sheet
ADP5600
DESIGN EXAMPLE
This section provides an example of the step by step design
procedures and the external components required for ADP5600.
Table 9 lists the design requirements for this example.
Table 9. Example Design Requirements for ADP5600
Parameter
LDO Output Voltage
LDO Output Current
The flying capacitor dictates the amount of voltage drop across
the charge pump due to the output resistance ,which depends
on the charge pump switching frequency.
Operation at high switching frequencies allows the use of
smaller flying capacitances, however, the minimum value is
limited due to its inverse effect on the charge pump impedance.
Specification
VLDO_OUT = −3.3 V
ILDO_OUT = −100 mA
Refer to Table 10 for the recommended flying capacitor value for
each switching frequency.
SETTING THE SWITCHING FREQUENCY OF THE
CHARGE PUMP
The first step is to determine the switching frequency for the
ADP5600 design. In general, higher switching frequencies
produce a smaller solution size due to the lower component
values required, whereas lower switching frequencies result in
higher conversion efficiency due to lower switching losses.
100
90
Table 10. Recommended Minimum C1 and C2
fOSC
100 kHz
250 kHz
500 kHz
750 kHz
1 MHz
70
Select a value for R2 and then calculate R1 by using the following
equation:
60
50
R1 = ((VADJ/VLDO_OUT) −1) × R2
40
30
20
–90
–80
–70
–60
–50
–40
–30
–20
CPOUT LOAD CURRENT (mA)
–10
0
21096-065
fOSC = 100kHz
fOSC = 500kHz
fOSC = 1MHz
10
0
–100
C1 and C2 Capacitances
1 µF
1 µF
1 µF
0.47 µF
0.47 µF
SETTING THE OUTPUT VOLTAGE OF THE LDO
REGULATOR
80
POWER EFFICIENCY (%)
SELECTING THE CHARGE PUMP FLYING CAPACITOR
Figure 63. Power Efficiency vs. ICPOUT at Various Oscillator Frequencies
The oscillator frequency of the ADP5600 can be set from
0.1 MHz to 1 MHz by connecting a resistor from the FREQ pin
to ground. The selected resistor allows the user to make decisions
based on the trade-off between efficiency and solution size.
In this design example, a switching frequency of 500 kHz
achieves an ideal combination of small solution size and high
conversion efficiency. To set the switching frequency to 500 kHz,
use the following equation to calculate the RT value:
RT [kΩ] = 64,700/fOSC [kHz]
Therefore, select a standard resistor, RT = 130 kΩ.
where:
VLDO_OUT is −2.5 V.
R1 is the feedback resistor between LDO_OUT and FB.
R2 is the feedback resistor between FB and GND (R2 is
recommended to be 40 kΩ or higher).
To set the output voltage to −3.3 V, R1 is set to 40 kΩ, giving a
calculated R2 value of 155.9 kΩ.
DETERMINING THE MINIMUM VIN VOLTAGE
To achieve the desired performance of the ADP5600, a
minimum input voltage, VIN, is required per application. This
both considers the PSRR performance that requires a headroom
voltage across the LDO and the drop on the charge pump due to
the output resistance. To calculate the minimum VIN, use the
following formula:
VIN = VLDO_OUT + VHR + (ROUT × ICPOUT)
where:
ROUT is the output resistance of the charge pump.
VHR is the LDO headroom required to achieve a certain PSRR
performance. The recommended minimum headroom voltage
is 500 mV.
Rev. 0 | Page 23 of 25
ADP5600
Data Sheet
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Because the internal switches of the ADP5600 turn on and off
very fast, good printed circuit board (PCB) layout practices are
critical to ensure optimum operation of the device. Improper
layouts result in poor load regulation, especially under heavy
loads. Output performance can be improved by following these
simple layout guidelines:
•
•
Place the input capacitor (CIN) as close as possible to the
VIN and GND pins.
Place the output capacitors (CCPOUT) and CLDO_OUT as close
as possible to the CPOUT/LDO_OUT and GND pins.
Place fly capacitors (CC1 and CC2) close to the respective fly
capacitor pins (C1+/C2+ and C1−/C2−).
Use of 0603 and 0402 size capacitors and resistors achieves
the smallest possible footprint solution on boards where
area is limited.
Connect the exposed pad to CPOUT.
Use adequate ground and power traces or planes.
Use a single-point ground for device ground and input and
output capacitor grounds.
Keep external components as close to the device as possible.
Use short and wide traces/planes from the input and
output capacitors to the input and output pins, respectively.
•
•
•
•
•
10.2mm
CC1
0603
CIN
0805
CCPOUT
0805
10.2mm
CC2
0603
CLDO_OUT
0603
21096-066
•
•
Figure 64. Example PCB Layout
Rev. 0 | Page 24 of 25
Data Sheet
ADP5600
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
PIN 1
INDICATOR
AREA
4.10
4.00 SQ
3.90
0.35
0.30
0.25
0.65
BSC
16
13
P IN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)
12
1
2.70
2.60 SQ
2.50
EXPOSED
PAD
4
9
0.80
0.75
0.70
SIDE VIEW
PKG-004828
SEATING
PLANE
0.45
0.40
0.35
5
8
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
08-23-2018-C
TOP VIEW
Figure 65. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADP5600ACPZ-R7
ADP5600CP-EVALZ
1
Temperature Range
−40°C to +125°C
Package Description
16-Lead LFCSP
Evaluation Board
Z = RoHS Compliant Part.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D21096-7/20(0)
Rev. 0 | Page 25 of 25
Package Option
CP-16-17
工商网监
湘ICP备2023018690号
