ADP7156ACPZ-1.2-R7

Data Sheet ADP7156 1.2 A, Ultralow Noise, High PSRR, RF Linear Regulator FEATURES ► ► ► ► ► ► ► ► ► ► ► ► ► ► TYPICAL APPLICATION CIRCUIT Input voltage range: 2.3 V to 5.5 V 16 standard voltages between 1.2 V and 3.3 V available Maximum load current: 1.2 A Low noise ► 0.9 µV rms total integrated noise from 100 Hz to 100 kHz ► 1.6 µV rms total integrated noise from 10 Hz to 100 kHz Noise spectral density: 1.7 nV/√Hz from 10 kHz to 1 MHz Power supply rejection ratio (PSRR) ► 80 dB from 1 kHz to 100 kHz; 60 dB at 1 MHz, VOUT = 3.3 V, VIN = 4.0 V Dropout voltage: 120 mV typical at IOUT = 1.2 A, VOUT = 3.3 V Initial accuracy: ±0.6% at ILOAD = 10 mA Initial accuracy over line, load, and temperature: ±1.5% Quiescent current: IGND = 4.0 mA at no load, 7 mA at 1.2 A Low shutdown current: 0.2 μA Stable with a 10 µF ceramic output capacitor Precision enable 10-lead, 3 mm × 3 mm LFCSP and 8-lead SOIC packages Figure 1. APPLICATIONS Regulation to noise sensitive applications: phase-locked loops (PLLs), voltage controlled oscillators (VCOs), and PLLs with integrated VCOs ► Communications and infrastructure ► Backhaul and microwave links ► GENERAL DESCRIPTION The ADP7156 is a linear regulator that operates from 2.3 V to 5.5 V and provides up to 1.2 A of output current. Using an advanced proprietary architecture, it provides high power supply rejection and ultralow noise, achieving excellent line and load transient response with only a 10 µF ceramic output capacitor. There are 16 standard output voltages for the ADP7156. The following voltages are available from stock: 1.2 V, 1.8 V, 2.0 V, 2.5 V, 2.8 V, 3.0 V and 3.3 V. Additional voltages available by special order are 1.3 V, 1.5 V, 1.6 V, 2.2 V, 2.6 V, 2.7 V, 2.9 V, 3.1 V, and 3.2 V. The ADP7156 regulator typical output noise is 0.9 μV rms from 100 Hz to 100 kHz and 1.7 nV/√Hz for noise spectral density from 10 kHz to 1 MHz. The ADP7156 is available in a 10-lead, 3 mm × 3 mm LFCSP and 8‑lead SOIC packages, making it not only a very compact solution, but also providing excellent thermal performance for applications requiring up to 1.2 A of output current in a small, low profile footprint. Table 1. Related Devices Model ADP7158, ADP7159 ADP7157 Output Input Voltage Current Fixed/ Adj1 Package 2.3 V to 5.5 V 2A 2.3 V to 5.5 V 1.2 A Fixed/ Adj Fixed/ Adj Fixed/ Adj Fixed/ Adj Fixed ADM7150, 4.5 V to 16 V ADM7151 ADM7154, 2.3 V to 5.5 V ADM7155 ADM7160 2.2 V to 5.5 V 1 800 mA 600 mA 200 mA 10-lead LFCSP/8‑lead SOIC 10-lead LFCSP/8‑lead SOIC 8-lead LFCSP/8‑lead SOIC 8-lead LFCSP/8‑lead SOIC 6-lead LFCSP/5-lead TSOT Adj means adjustable. Rev. C DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Data Sheet ADP7156 TABLE OF CONTENTS Features................................................................ 1 Applications........................................................... 1 Typical Application Circuit......................................1 General Description...............................................1 Specifications........................................................ 3 Input and Output Capacitors, Recommended Specifications..........................4 Absolute Maximum Ratings...................................5 Thermal Data......................................................5 Thermal Resistance........................................... 5 ESD Caution.......................................................5 Pin Configurations and Function Descriptions.......6 Typical Performance Characteristics..................... 7 Theory of Operation.............................................13 Applications Information...................................... 14 Design Tools.....................................................14 Capacitor Selection.......................................... 14 Undervoltage Lockout (UVLO)......................... 15 Programmable Precision Enable......................15 Start-Up Time................................................... 16 REF, BYP, and VREG Pins...............................17 Current-Limit and Thermal Shutdown.............. 17 Thermal Considerations................................... 17 Printed Circuit Board (PCB) Layout Considerations...................................................20 Outline Dimensions............................................. 21 Ordering Guide.................................................21 Output Voltage Options.................................... 22 Evaluation Boards............................................ 22 REVISION HISTORY 10/2022—Rev. B to Rev. C Changes to Features Section.......................................................................................................................... 1 Deleted Figure 2; Renumbered Sequentially................................................................................................... 1 Changed ADIsimPOWER Design Tool Section to Design Tools Section.......................................................14 Changes to Design Tools Section.................................................................................................................. 14 Added Output Voltage Options Section......................................................................................................... 22 analog.com Rev. C | 2 of 22 Data Sheet ADP7156 SPECIFICATIONS VIN = VOUT + 0.5 V or 2.3 V, whichever is greater; VEN = VIN; ILOAD = 10 mA; CIN = COUT = 10 µF; CREG = CREF = CBYP = 1 µF; TA = 25°C for typical specifications; TA = −40°C to +125°C for minimum/maximum specifications, unless otherwise noted. Table 2. Parameter Symbol INPUT VOLTAGE RANGE LOAD CURRENT OPERATING SUPPLY CURRENT VIN ILOAD IGND SHUTDOWN CURRENT IIN_SD NOISE1 Output Noise OUTNOISE Noise Spectral Density POWER SUPPLY REJECTION RATIO1 OUTNSD PSRR OUTPUT VOLTAGE ACCURACY Output Voltage2 Initial Accuracy VOUT REGULATION Line Load3 CURRENT-LIMIT THRESHOLD4 REF VOUT DROPOUT VOLTAGE5 PULL-DOWN RESISTANCE VOUT VREG REF BYP START-UP TIME1, 6 VOUT VREG REF THERMAL SHUTDOWN1 Threshold Hysteresis UNDERVOLTAGE THRESHOLDS Input Voltage Rising Falling Hysteresis VREG UVLO THRESHOLDS7 Rising analog.com Test Conditions/Comments Typ Max Unit ILOAD = 0 µA ILOAD = 1.2 A EN = GND 4.0 7.0 0.2 5.5 1.2 8.0 12.0 4 V A mA mA µA VOUT = 1.2 V to 3.3 V 10 Hz to 100 kHz 100 Hz to 100 kHz 10 kHz to 1 MHz 1 kHz to 100 kHz, VIN = 4.0 V, VOUT = 3.3 V, ILOAD = 1.2 A 1 MHz, VIN = 4.0 V, VOUT = 3.3 V, ILOAD = 1.2 A 1 kHz to 100 kHz, VIN = 2.6 V, VOUT = 1.8 V, ILOAD = 1.2 A 1 MHz, VIN = 2.6 V, VOUT = 1.8 V, ILOAD = 1.2 A 1.6 0.9 1.7 80 60 80 60 2.3 ILOAD = 10 mA, TA = 25°C 10 mA < ILOAD < 1.2 A, TA= 25°C 10 mA < ILOAD < 1.2 A, TA = −40°C to +125°C ∆VOUT/∆VIN ∆VOUT/∆IOUT ILIMIT Min VIN = VOUT + 0.5 V or 2.3 V, whichever is greater to 5.5 V IOUT = 10 mA to 1.2 A 1.2 −0.6 −1.0 −1.5 3.3 +0.6 +1.0 +1.5 V % % % −0.1 +0.1 0.3 %/V %/A 2.4 80 170 mA A mV mV 1.4 VDROPOUT VOUT_PULL VREG_PULL VREF_PULL VBYP_PULL IOUT = 600 mA, VOUT = 3.3 V IOUT = 1.2 A, VOUT = 3.3 V EN = 0 V, VIN = 5.5 V VOUT = 1 V VREG = 1 V VREF = 1 V VBYP = 1 V VOUT = 3.3 V tSTART-UP tREG_START-UP tREF_START-UP TSSD TSSD_HYS UVLORISE UVLOFALL UVLOHYS VREGUVLORISE µV rms µV rms nV/√Hz dB dB dB dB TJ rising 1.95 22 1.8 60 120 650 31 850 650 Ω kΩ Ω Ω 1.2 0.6 0.5 ms ms ms 150 15 °C °C 2.22 2.02 200 2.29 V V mV 1.94 V Rev. C | 3 of 22 Data Sheet ADP7156 SPECIFICATIONS Table 2. Parameter Symbol Falling Hysteresis EN INPUT PRECISION EN Input Logic High Logic Low Logic Hysteresis LEAKAGE CURRENT REF_SENSE EN VREGUVLOFALL VREGUVLOHYS Test Conditions/Comments Min Typ Max 1.60 Unit V mV 185 2.3 V ≤ VIN ≤ 5.5 V VEN_HIGH VEN_LOW VEN_HYS IREF_SENSE_LKG IEN_LKG 1.13 1.05 1.22 1.13 90 10 0.01 EN = VIN or GND 1.31 1.22 V V mV nA µA 1 1 Guaranteed by characterization; not production tested. 2 The ADP7156 is available in 16 standard voltages between 1.2 V and 3.3 V, including 1.2 V, 1.3 V, 1.5 V, 1.6 V, 1.8 V, 2.0 V, 2.2 V, 2.5 V, 2.6 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.1 V, 3.2 V, and 3.3 V. 3 Based on an endpoint calculation using 10 mA and 1.2 A loads. 4 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V. 5 Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. Dropout voltage applies only for output voltages greater than 2.3 V. 6 Start-up time is defined as the time between the rising edge of VEN to VOUT, VREG, or VREF being at 90% of its nominal value. 7 The output voltage is disabled until the VREG UVLO rise threshold is crossed. The VREG output is disabled until the input voltage UVLO rising threshold is crossed. INPUT AND OUTPUT CAPACITORS, RECOMMENDED SPECIFICATIONS Table 3. Parameter MINIMUM CAPACITANCE Input1 Regulator Output1 Bypass Reference CAPACITOR EFFECTIVE SERIES RESISTANCE (ESR) COUT, CIN CREG, CREF CBYP 1 Symbol Test Conditions/Comments Min Typ 7.0 0.7 7.0 0.1 0.7 10.0 1.0 10.0 1.0 1.0 Max Unit TA = −40°C to +125°C CIN CREG COUT CBYP CREF µF µF µF µF µF TA = −40°C to +125°C RESR RESR RESR 0.1 0.2 2.0 Ω Ω Ω The minimum input and output capacitance must be greater than 7.0 μF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with any low dropout regulator. analog.com Rev. C | 4 of 22 Data Sheet ADP7156 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating VIN to Ground VREG to Ground −0.3 V to +7 V −0.3 V to VIN, or +4 V (whichever is less) −0.3 V to VREG, or +4 V (whichever is less) −0.3 V to VREG, or +4 V (whichever is less) ±0.3 V ±0.3 V −0.3 V to +7 V −0.3 V to VREG, or +4 V (whichever is less) −0.3 V to VREG, or +4 V (whichever is less) −0.3 V to +4 V −65°C to +150°C −40°C to +125°C JEDEC J-STD-020 VOUT to Ground VOUT_SENSE to Ground VOUT to VOUT_SENSE BYP to VOUT EN to Ground BYP to Ground REF to Ground REF_SENSE to Ground Storage Temperature Range Operational Junction Temperature Range Soldering Conditions Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL DATA Absolute maximum ratings apply individually only, not in combination. The ADP7156 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that TJ is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may need to be derated. In applications with moderate power dissipation and low printed circuit board (PCB) thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the ambient temperature (TA), the power dissipation of the device (PD), and the junction to ambient thermal resistance of the package (θJA). layout, and environmental conditions. The specified values of θJA are based on a 4-layer, 4 in. × 3 in. circuit board. See JESD51-7 and JESD51-9 for detailed information on the board construction. ΨJB is the junction to board thermal characterization parameter with units of °C/W. ΨJB of the package is based on modeling and calculation using a 4-layer board. JESD51-12, Guidelines for Reporting and Using Electronic Package Thermal Information, states that thermal characterization parameters are not the same as thermal resistances. ΨJB measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance, θJB. Therefore, ΨJB thermal paths include convection from the top of the package as well as radiation from the package, factors that make ΨJB more useful in real-world applications. Maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the following formula: TJ = TB + (PD × ΨJB) See JESD51-8 and JESD51-12 for more detailed information about ΨJB. THERMAL RESISTANCE θJA, θJC, and ΨJB are specified for the worst case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance Package Type θJA θJC ΨJB Unit 10-Lead LFCSP 8-Lead SOIC 53.8 50.4 15.6 42.3 29.1 30.1 °C/W °C/W ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Calculate the maximum junction temperature (TJ) from the ambient temperature (TA) and power dissipation (PD) using the following formula: TJ = TA + (PD × θJA) Junction to ambient thermal resistance (θJA) of the package is based on modeling and calculation using a 4-layer board. The junction to ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of θJA may vary, depending on PCB material, analog.com Rev. C | 5 of 22 Data Sheet ADP7156 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 3. 8-Lead SOIC Pin Configuration Figure 2. 10-Lead LFCSP Pin Configuration Table 6. Pin Function Descriptions Pin No. LFCSP SOIC Mnemonic Description 1, 2 3 1 2 VOUT VOUT_SENSE 4 3 BYP 5 4 EN 6 7 5 6 REF_SENSE REF 8 9, 10 7 8 VREG VIN EP Regulated Output Voltage. Bypass VOUT to ground with a 10 µF or greater capacitor. Output Sense. VOUT_SENSE is internally connected to VOUT with a 10 Ω resistor. Connect VOUT_SENSE as close to the load as possible. Low Noise Bypass Capacitor. Connect a 1 µF capacitor from the BYP pin to ground to reduce noise. Do not connect a load to this pin. Enable. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic startup, connect EN to VIN. Reference Sense. Connect REF_SENSE to the REF pin. Do not connect REF_SENSE to VOUT or GND. Low Noise Reference Voltage Output. Bypass REF to ground with a 1 µF or greater capacitor. Short REF_SENSE to REF for fixed output voltages. Do not connect a load to this pin. Regulated Input Supply Voltage to Low Dropout (LDO) Amplifier. Bypass VREG to ground with a 1 µF or greater capacitor. Regulator Input Supply Voltage. Bypass VIN to ground with a 10 µF or greater capacitor. Exposed Pad. The exposed pad is located on the bottom of the package. The exposed pad enhances thermal performance, and it is electrically connected to ground inside the package. Connect the exposed pad to the ground plane on the board to ensure proper operation. analog.com Rev. C | 6 of 22 Data Sheet ADP7156 TYPICAL PERFORMANCE CHARACTERISTICS VIN = VOUT + 0.5 V or 2.3 V, whichever is greater; VEN = VIN; ILOAD = 10 mA; CIN = COUT = 10 µF; CREG = CREF = CBYP = 1 µF; TA = 25°C unless otherwise noted. Figure 4. Shutdown Current (IIN_SD) vs. Temperature at Various Input Voltages (VIN), VOUT = 1.8 V Figure 7. Output Voltage (VOUT) vs. Input Voltage (VIN) at Various Loads, VOUT = 3.3 V Figure 5. Output Voltage (VOUT) vs. Temperature at Various Loads, VOUT = 3.3 V Figure 8. Ground Current (IGND) vs. Temperature at Various Loads, VOUT = 3.3 V Figure 6. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 3.3 V Figure 9. Ground Current (IGND) vs. Load Current (ILOAD), VOUT = 3.3 V analog.com Rev. C | 7 of 22 Data Sheet ADP7156 TYPICAL PERFORMANCE CHARACTERISTICS Figure 10. Ground Current (IGND) vs. Input Voltage (VIN) at Various Loads, VOUT = 3.3 V Figure 13. Ground Current (IGND) vs. Input Voltage (VIN) at Various Loads in Dropout, VOUT = 3.3 V Figure 11. Dropout Voltage (VDROPOUT) vs. Load Current (ILOAD), VOUT = 3.3 V Figure 14. Output Voltage (VOUT) vs. Temperature at Various Loads, VOUT = 1.8 V Figure 12. Output Voltage (VOUT) vs. Input Voltage (VIN) at Various Loads in Dropout, VOUT = 3.3 V analog.com Figure 15. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 1.8 V Rev. C | 8 of 22 Data Sheet ADP7156 TYPICAL PERFORMANCE CHARACTERISTICS Figure 16. Output Voltage (VOUT) vs. Input Voltage (VIN) at Various Loads, VOUT = 1.8 V Figure 19. Ground Current (IGND) vs. Input Voltage (VIN) at Various Loads, VOUT = 1.8 V Figure 17. Ground Current (IGND) vs. Temperature at Various Loads, VOUT = 1.8 V Figure 20. Power Supply Rejection Ratio (PSRR) vs. Frequency at Various Loads, VOUT = 3.3 V, VIN = 4.0 V Figure 18. Ground Current (IGND) vs. Load Current (ILOAD), VOUT = 1.8 V Figure 21. Power Supply Rejection Ratio (PSRR) vs. Frequency at Various Headroom Voltages, VOUT = 3.3 V, 1.2 A Load analog.com Rev. C | 9 of 22 Data Sheet ADP7156 TYPICAL PERFORMANCE CHARACTERISTICS Figure 22. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage at Various Frequencies, VOUT = 3.3 V, 1.2 A Load Figure 25. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage at Various Frequencies, VOUT = 1.8 V, 1.2 A Load Figure 23. Power Supply Rejection Ratio (PSRR) vs. Frequency at Various Loads, VOUT = 1.8 V, VIN = 2.6 V Figure 26. Power Supply Rejection Ratio (PSRR) vs. Frequency at Various CBYP Values, VOUT = 3.3 V, VIN = 4.0 V, 1.2 A Load Figure 24. Power Supply Rejection Ratio (PSRR) vs. Frequency at Various Headroom Voltages, VOUT = 1.8 V, 1.2 A Load Figure 27. RMS Output Noise vs. Load Current analog.com Rev. C | 10 of 22 Data Sheet ADP7156 TYPICAL PERFORMANCE CHARACTERISTICS Figure 28. RMS Output Noise vs. Output Voltage Figure 29. Noise Spectral Density vs. Frequency at Various Values of CBYP Figure 31. Output Noise Spectral Density vs. Frequency at Various Loads, 10 Hz to 10 MHz Figure 32. Load Transient Response, ILOAD = 100 mA to 1.2 A, VOUT = 3.3 V, VIN = 4.0 V, Channel 1 = IOUT, Channel 2 = VOUT Figure 30. Output Noise Spectral Density vs. Frequency at Various Loads, 0.1 Hz to 1 MHz Figure 33. Load Transient Response, ILOAD = 100 mA to 1.2 A, VOUT = 3.3 V, VIN = 4.0 V, COUT = 22 µF, Channel 1 = IOUT, Channel 2 = VOUT analog.com Rev. C | 11 of 22 Data Sheet ADP7156 TYPICAL PERFORMANCE CHARACTERISTICS Figure 34. Load Transient Response, ILOAD = 100 mA to 1.2 A, VOUT = 1.8 V, VIN = 2.5 V, Channel 1 = IOUT, Channel 2 = VOUT Figure 37. Line Transient Response, 1 V Input Step, ILOAD = 1.2 A, VOUT = 1.8 V, VIN = 2.5 V, Channel 1= VIN, Channel 2 = VOUT Figure 35. Load Transient Response, ILOAD = 100 mA to 1.2 A, VOUT = 1.8 V, VIN = 2.5 V, COUT = 22 µF, Channel 1 = IOUT, Channel 2 = VOUT Figure 38. VOUT Start-Up Time After VEN Rising, at Various Output Voltages, VIN = 5 V, CBYP = 1 μF Figure 36. Line Transient Response, 1 V Input Step, ILOAD = 1.2 A, VOUT = 3.3 V, VIN = 3.8 V, Channel 1 = VIN, Channel 2 = VOUT Figure 39. VOUT Start-Up Time Behavior at Various Values of CBYP, VOUT = 3.3 V analog.com Rev. C | 12 of 22 Data Sheet ADP7156 THEORY OF OPERATION The ADP7156 is an ultralow noise, high PSRR linear regulator targeting radio frequency (RF) applications. The input voltage range is 2.3 V to 5.5 V, and it can deliver up to 1.2 A of load current. Typical shutdown current consumption is 0.2 µA at room temperature. By heavily filtering the reference voltage, the ADP7156 can achieve 1.7 nV/√Hz typical output noise spectral density from 10 kHz to 1 MHz. Because the error amplifier is always in unity gain, the output noise is independent of the output voltage. Optimized for use with 10 µF ceramic capacitors, the ADP7156 provides excellent transient performance. The ADP7156 uses the EN pin to enable and disable the VOUT pin under normal operating conditions. When EN is high, VOUT turns on, and when EN is low, VOUT turns off. For automatic startup, tie EN to VIN. Figure 40. Simplified Internal Block Diagram Internally, the ADP7156 consists of a reference, an error amplifier, and a P-channel MOSFET pass transistor. The output current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to pass and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to pass and decreasing the output voltage. analog.com Figure 41. Simplified ESD Protection Block Diagram The ESD protection devices are shown in the block diagram as Zener diodes (see Figure 41). Rev. C | 13 of 22 Data Sheet ADP7156 APPLICATIONS INFORMATION DESIGN TOOLS The ADP7156 is supported by the ADIsimPower™, LTpowerCAD®, and LTspice® design tools to produce complete power designs and simulations. For more information on design tools, visit the ADP7156 product page, www.analog.com/adp7156. CAPACITOR SELECTION Multilayer ceramic capacitors (MLCCs) combine small size, low ESR, low ESL, and a wide operating temperature range, making them an ideal choice for bypass capacitors. They are not without faults, however. Depending on the dielectric material, the capacitance can vary dramatically with temperature, dc bias, and ac signal level. Therefore, selecting the proper capacitor results in the best circuit performance. Output Capacitor The ADP7156 is designed for operation with ceramic capacitors but functions with most commonly used capacitors when care is taken with regard to the ESR value. The ESR of the output capacitor affects the stability of the LDO control loop. A minimum of 10 µF capacitance with an ESR of 0.1 Ω or less is recommended to ensure the stability of the ADP7156. Output capacitance also affects transient response to changes in load current. Using a larger value of output capacitance improves the transient response of the ADP7156 to large changes in load current. Figure 42 shows the transient responses for an output capacitance value of 10 µF. REF Capacitor The REF capacitor, CREF, is necessary to stabilize the reference amplifier. Connect at 1 µF or greater capacitor between REF and ground. BYP Capacitor The BYP capacitor, CBYP, is necessary to filter the reference buffer. A 1 µF capacitor is typically connected between BYP and ground. Capacitors as small as 0.1 µF can be used; however, the output noise voltage of the LDO increases as a result. In addition, the BYP capacitor value can be increased to reduce the noise below 1 kHz at the expense of increasing the start-up time of the LDO regulator. Very large values of CBYP significantly reduce the noise below 10 Hz. Tantalum capacitors are recommended for capacitors larger than approximately 33 µF because solid tantalum capacitors are less prone to microphonic noise issues. A 1 μF ceramic capacitor in parallel with the larger tantalum capacitor is recommended to ensure good noise performance at higher frequencies. Figure 43. RMS Output Noise vs. Bypass Capacitance (CBYP) Figure 42. Output Transient Response, VOUT = 3.3 V, COUT = 10 µF, Channel 1 = Load Current, Channel 2 = VOUT Input and VREG Capacitor Connecting a 10 µF capacitor from VIN to ground reduces the circuit sensitivity to PCB layout, especially when long input traces or high source impedance are encountered. To maintain the best possible stability and PSRR performance, connect a 1 µF or greater capacitor from VREG to ground. analog.com Figure 44. Noise Spectral Density vs. Frequency at Various CBYP Values Rev. C | 14 of 22 Data Sheet ADP7156 APPLICATIONS INFORMATION Capacitor Properties Any good quality ceramic capacitors can be used with the ADP7156 if they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V to 50 V are recommended. However, Y5V and Z5U dielectrics are not recommended because of their poor temperature and dc bias characteristics. Figure 45 depicts the capacitance vs. dc bias voltage of a 1206, 10 µF, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is ~±15% over the −40°C to +85°C temperature range and is not a function of package or voltage rating. Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP7156, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. UNDERVOLTAGE LOCKOUT (UVLO) The ADP7156 also incorporates an internal UVLO circuit to disable the output voltage when the input voltage is less than the minimum input voltage rating of the regulator. The upper and lower thresholds are internally fixed with 200 mV (typical) of hysteresis. Figure 46. Typical UVLO Behavior at Various Temperatures, VOUT = 3.3 V Figure 46 shows the typical behavior of the UVLO function. This hysteresis prevents on/off oscillations that can occur when caused by noise on the input voltage as it passes through the threshold points. PROGRAMMABLE PRECISION ENABLE Figure 45. Capacitance vs. DC Bias Voltage Use Equation 1 to determine the worst case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage. CEFF = CBIAS × (1 − tempco) × (1 − TOL) where: CEFF is the worst case capacitance. CBIAS is the effective capacitance at the operating voltage. tempco is the worst case capacitor temperature coefficient. TOL is the worst case component tolerance. (1) The ADP7156 uses the EN pin to enable and disable the VOUT pin under normal operating conditions. As shown in Figure 47, when a rising voltage on EN crosses the upper threshold, nominally 1.22 V, VOUT turns on. When a falling voltage on EN crosses the lower threshold, nominally 1.13 V, VOUT turns off. The hysteresis of the EN threshold is typically 90 mV. The ADP7156 includes a discharge resistor on each VOUT, VREG, REF, and BYP pin. These resistors turn on when the device is disabled, and helps to discharge the associated capacitor very quickly. In this example, the worst case temperature coefficient (tempco) over −40°C to +85°C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and CBIAS is 9.72 µF at 5 V, as shown in Figure 45. Substituting these values in Equation 1 yields CEFF = 9.72 µF × (1 − 0.15) × (1 − 0.1) = 7.44 µF analog.com Rev. C | 15 of 22 Data Sheet ADP7156 APPLICATIONS INFORMATION where: REN2 typically ranges from 10 kΩ to 100 kΩ. VEN is the desired turn-on voltage. The hysteresis voltage increases by the factor (REN1 + REN2)/REN2 For the example shown in Figure 50, the EN threshold is 2.44 V with a hysteresis of 200 mV. Figure 47. Typical VOUT Response to EN Pin Operation Figure 50. Typical EN Pin Voltage Divider Figure 50 shows the typical voltage divider configuration of the EN pin. This configuration prevents on/off oscillations that can occur due to noise on the EN pin as it passes through the threshold points. START-UP TIME Figure 48. Typical VOUT Response to EN Pin Operation (VEN), VOUT = 3.3 V, VIN = 5 V, CBYP = 1 µF The ADP7156 uses an internal soft start to limit the inrush current when the output is enabled. The start-up time for a 3.3 V output is approximately 1.2 ms from the time the EN active threshold is crossed to when the output reaches 90% of its final value. The rise time in seconds of the output voltage (10% to 90%) is approximately 0.0012 × CBYP where CBYP is measured in microfarads. Figure 49. Typical EN Precision Threshold vs. Input Voltage (VIN) The upper and lower thresholds are user-programmable and can be set higher than the nominal 1.22 V threshold by using two resistors. Determine the resistance values, REN1 and REN2, from Figure 51. Typical Start-Up Behavior with CBYP = 1 µF to 10 µF REN1 = REN2 × (VEN − 1.22 V)/1.22 V analog.com Rev. C | 16 of 22 Data Sheet ADP7156 APPLICATIONS INFORMATION the junction temperature of the die to exceed the maximum junction temperature of 125°C. The junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown in Equation 2. To guarantee reliable operation, the junction temperature of the ADP7156 must not exceed 125°C. To ensure that the junction temperature stays below this maximum value, the user must be aware of the parameters that contribute to junction temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air (θJA). The θJA number is dependent on the package assembly compounds that are used and the amount of copper used to solder the exposed pad (ground) to the PCB. Figure 52. Typical Start-Up Behavior with CBYP = 10 µF to 100 µF REF, BYP, AND VREG PINS REF, BYP, and VREG generate voltages internally (VREF, VBYP, and VREG) that require external bypass capacitors for proper operation. Do not, under any circumstances, connect any loads to these pins, because doing so compromises the noise and PSRR performance of the ADP7156. Using larger values of CBYP, CREF, and CREG is acceptable but can increase the start-up time, as described in the Start-Up Time section. CURRENT-LIMIT AND THERMAL SHUTDOWN The ADP7156 is protected against damage due to excessive power dissipation by current and thermal overload protection circuits. The ADP7156 is designed to current limit when the output load reaches 1.8 A (typical). When the output load exceeds 1.8 A, the output voltage is reduced to maintain a constant current limit. When the ADP7156 junction temperature exceeds 150°C, the thermal shutdown circuit turns off the output voltage, reducing the output current to zero. Extreme junction temperature can be the result of high current operation, poor circuit board design or high ambient temperature. A 15°C hysteresis is included so that the ADP7156 does not return to operation after thermal shutdown until the on-chip temperature falls below 135°C. When the device exits thermal shutdown, a soft start is initiated to reduce the inrush current. Current-limit and thermal shutdown protections are intended to protect the device against accidental overload conditions. For example, a hard short from VOUT to ground or an extremely long soft start timer usually causes thermal oscillations between the current limit and thermal shutdown. THERMAL CONSIDERATIONS In applications with a low input to output voltage differential, the ADP7156 does not dissipate much heat. However, in applications with high ambient temperature and/or high input voltage, the heat dissipated in the package may become large enough that it causes analog.com Table 7 shows the typical θJA values of the 8-lead SOIC and 10‑lead LFCSP packages for various PCB copper sizes. Table 8 shows the typical ΨJB values of the 8-lead SOIC and 10-lead LFCSP. Table 7. Typical θJA Values θJA (°C/W) Copper Size (mm2) 10-Lead LFCSP 8-Lead SOIC 251 130.2 93.0 65.8 55.6 44.1 123.8 90.4 66.0 56.6 45.5 100 500 1000 6400 1 Device soldered to minimum size pin traces. Table 8. Typical ΨJB Values Package ΨJB (°C/W) 10-Lead LFCSP 8-Lead SOIC 29.1 30.1 Calculate the junction temperature (TJ) of the ADP7156 from the following equation: TJ = TA + (PD × θJA) (2) where: TA is the ambient temperature. PD is the power dissipation in the die, given by PD = ((VIN − VOUT) × ILOAD) + (VIN × IGND) (3) where: VIN and VOUT are the input and output voltages, respectively. ILOAD is the load current. IGND is the ground current. Power dissipation caused by ground current is quite small and can be ignored. Therefore, the junction temperature equation simplifies to the following: TJ = TA + (((VIN − VOUT) × ILOAD) × θJA) (4) Rev. C | 17 of 22 Data Sheet ADP7156 APPLICATIONS INFORMATION As shown in Equation 4, for a given ambient temperature, input to output voltage differential, and continuous load current, a minimum copper size requirement exists for the PCB to ensure that the junction temperature does not rise above 125°C. The heat dissipation from the package can be improved by increasing the amount of copper attached to the pins and exposed pad of the ADP7156. Adding thermal planes underneath the package also improves thermal performance. However, as shown in Table 7, a point of diminishing returns is eventually reached, beyond which an increase in the copper area does not yield significant reduction in the junction to ambient thermal resistance. Figure 53 to Figure 58 show junction temperature calculations for various ambient temperatures, power dissipation, and areas of PCB copper. Figure 53. Junction Temperature vs. Total Power Dissipation for the 10-Lead LFCSP, TA = 25°C Figure 54. Junction Temperature vs. Total Power Dissipation for the 10-Lead LFCSP, TA = 50°C analog.com Figure 55. Junction Temperature vs. Total Power Dissipation for the 10-Lead LFCSP, TA = 85°C Figure 56. Junction Temperature vs. Total Power Dissipation for the 8-Lead SOIC, TA = 25°C Figure 57. Junction Temperature vs. Total Power Dissipation for the 8-Lead SOIC, TA = 50°C Rev. C | 18 of 22 Data Sheet ADP7156 APPLICATIONS INFORMATION Figure 58. Junction Temperature vs. Total Power Dissipation for the 8-Lead SOIC, TA = 85°C Figure 60. Junction Temperature vs. Total Power Dissipation for the 8-Lead SOIC Thermal Characterization Parameter (ΨJB) When the evaluation board temperature is known, use the thermal characterization parameter, ΨJB, to estimate the junction temperature rise (see Figure 59 and Figure 60). Calculate the maximum junction temperature (TJ) from the evaluation board temperature (TB) and power dissipation (PD) using the following formula: TJ = TB + (PD × ΨJB) (5) The typical value of ΨJB is 29.1°C/W for the 10-lead LFCSP package and 30.1°C/W for the 8-lead SOIC package. Figure 59. Junction Temperature vs. Total Power Dissipation for the 10-Lead LFCSP analog.com Rev. C | 19 of 22 Data Sheet ADP7156 PRINTED CIRCUIT BOARD (PCB) LAYOUT CONSIDERATIONS Place the input capacitor as close as possible between the VIN pin and ground. Place the output capacitor as close as possible between the VOUT pin and ground. Place the bypass capacitors (CREG, CREF, and CBYP) for VREG, VREF, and VBYP close to the respective pins (VREG, REF, and BYP) and ground. The use of a 0805, 0603, or 0402 size capacitor achieves the smallest possible footprint solution on boards where area is limited. Maximize the amount of ground metal for the exposed pad, and use as many vias as possible on the component side to improve thermal dissipation. Figure 62. Sample 8-Lead SOIC PCB Layout Figure 61. Sample 10-Lead LFCSP PCB Layout analog.com Rev. C | 20 of 22 Data Sheet ADP7156 OUTLINE DIMENSIONS 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 10 6 PIN 1 INDEX ARE A 1.74 1.64 1.49 EXPOSED PAD 0.50 0.40 0.30 1 5 SEATING PLANE 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.30 0.25 0.20 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 02-05-2013-C 0.80 0.75 0.70 0.20 MIN PI N 1 INDICATOR (R 0.15) BOTTOM VIEW TOP VIEW 0.20 REF Figure 63. 10-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-10-9) Dimensions shown in millimeters 5.00 4.90 4.80 2.29 0.356 5 1 4 6.20 6.00 5.80 4.00 3.90 3.80 2.29 0.457 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. BOTTOM VIEW 1.27 BSC 3.81 REF TOP VIEW 1.65 1.25 1.75 1.35 SEATING PLANE 0.51 0.31 0.50 0.25 0.10 MAX 0.05 NOM COPLANARITY 0.10 8° 0° 45° 0.25 0.17 1.04 REF 1.27 0.40 06-02-2011-B 8 COMPLIANT TO JEDEC STANDARDS MS-012-A A Figure 64. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP] Narrow Body (RD-8-1) Dimensions shown in millimeters Updated: September 23, 2022 ORDERING GUIDE Table 9. Ordering Guide Model1 Temperature Range Package Description Packing Quantity Package Option Marking Code ADP7156ACPZ-1.2-R7 ADP7156ACPZ-1.8-R7 ADP7156ACPZ-2.0-R7 ADP7156ACPZ-2.5-R7 −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C 10-Lead LFCSP (3mm x 3mm) 10-Lead LFCSP (3mm x 3mm) 10-Lead LFCSP (3mm x 3mm) 10-Lead LFCSP (3mm x 3mm) Reel, 1500 Reel, 1500 Reel, 1500 Reel, 1500 CP-10-9 CP-10-9 CP-10-9 CP-10-9 LST LSU LTQ LSV analog.com Rev. C | 21 of 22 Data Sheet ADP7156 OUTLINE DIMENSIONS Table 9. Ordering Guide Model1 Temperature Range Package Description Packing Quantity Package Option ADP7156ACPZ-2.8-R7 ADP7156ACPZ-3.0-R7 ADP7156ACPZ-3.3-R7 ADP7156ARDZ-1.2-R7 ADP7156ARDZ-1.8-R7 ADP7156ARDZ-2.0-R7 ADP7156ARDZ-2.5-R7 ADP7156ARDZ-2.8-R7 ADP7156ARDZ-3.0-R7 ADP7156ARDZ-3.3-R7 −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C 10-Lead LFCSP (3mm x 3mm) 10-Lead LFCSP (3mm x 3mm) 10-Lead LFCSP (3mm x 3mm) 8-Lead SOIC w/ EP 8-Lead SOIC w/ EP 8-Lead SOIC w/ EP 8-Lead SOIC w/ EP 8-Lead SOIC w/ EP 8-Lead SOIC w/ EP 8-Lead SOIC w/ EP Reel, 1500 Reel, 1500 Reel, 1500 Reel, 1000 Reel, 1000 Reel, 1000 Reel, 1000 Reel, 1000 Reel, 1000 Reel, 1000 CP-10-9 CP-10-9 CP-10-9 RD-8-1 RD-8-1 RD-8-1 RD-8-1 RD-8-1 RD-8-1 RD-8-1 1 Marking Code LSW LSY LSZ Z = RoHS Compliant Part. OUTPUT VOLTAGE OPTIONS Table 10. Output Voltage Options Model1, 2 Output Voltage (V) ADP7156ACPZ-1.2-R7 ADP7156ACPZ-1.8-R7 ADP7156ACPZ-2.0-R7 ADP7156ACPZ-2.5-R7 ADP7156ACPZ-2.8-R7 ADP7156ACPZ-3.0-R7 ADP7156ACPZ-3.3-R7 ADP7156ARDZ-1.2-R7 ADP7156ARDZ-1.8-R7 ADP7156ARDZ-2.0-R7 ADP7156ARDZ-2.5-R7 ADP7156ARDZ-2.8-R7 ADP7156ARDZ-3.0-R7 ADP7156ARDZ-3.3-R7 1.2 1.8 2.0 2.5 2.8 3.0 3.3 1.2 1.8 2.0 2.5 2.8 3.0 3.3 1 Z = RoHS Compliant Part. 2 To order a device with voltage options of 1.3 V, 1.5 V, 1.6 V, 2.2 V, 2.6 V, 2.7 V, 2.9 V, 3.1 V, and 3.2 V, contact your local Analog Devices, Inc., sales or distribution representative. EVALUATION BOARDS Model1 Description ADP7156CP-3.3EVALZ Evaluation Board 1 Z = RoHS Compliant Part. ©2016-2022 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. C | 22 of 22