FEATURES
TYPICAL APPLICATION CIRCUITS
EP
VIN = –3.8V
CIN
4.7µF
VIN
ADP7185
+1.25V
OFF
0V
VOUT
SENSE
VA
EN
–1.3V
ON
VAFB
VREG
VOUT = –3.3V
COUT
4.7µF
CAFB
10nF
CA
1µF
GND
CREG
1µF
13932-001
Input voltage range: −2.0 V to −5.5 V
Maximum output current: −500 mA
Fixed output voltage options: −0.5 V to −4.5 V
Adjustable output from −0.5 V to −VIN + 0.5 V
Low output noise: 4 μV rms from 100 Hz to 100 kHz
Noise spectral density: 20 nV/√Hz, 10 kHz to 1 MHz
PSRR at −500 mA load
68 dB at 10 kHz
50 dB at 100 kHz
40 dB at 1 MHz
Low dropout voltage: −190 mV typical at −500 mA load
Initial output voltage (VOUT) accuracy: ±0.5%
Output voltage accuracy over line, load, and temperature:
±2.2%
Operating supply current (IGND): −0.6 mA typical at no load
Low shutdown current: −2 μA typical at VIN = −5.5 V
Stable with small 4.7 μF ceramic input and output capacitor
Positive or negative enable logic
Current-limit and thermal overload protection
8-lead, 2 mm × 2 mm LFCSP package
Supported by ADIsimPOWER voltage regulator design tool
Figure 1. ADP7185 with Fixed Output Voltage, −3.3 V
EP
VIN = –3V
CIN
4.7µF
VIN
SENSE
ADP7185
+1.25V
OFF
0V
VOUT
VA
EN
–1.3V
ON
VAFB
VREG
GND
COUT
4.7µF
R1
100kΩ
VOUT = –2.5V
CAFB
10nF
CA
1µF
R2
24.9kΩ
CREG
1µF
13932-002
Data Sheet
−500 mA, Ultralow Noise, High PSRR,
Low Dropout Linear Regulator
ADP7185
Figure 2. ADP7185 with Adjustable Output Voltage, VOUT = −2.5 V
APPLICATIONS
Regulation to noise sensitive applications: analog-to-digital
converters (ADCs), digital-to-analog converters (DACs),
precision amplifiers
Communications and infrastructure
Medical and healthcare
Industrial and instrumentation
GENERAL DESCRIPTION
The ADP7185 is a complementary metal oxide semiconductor
(CMOS), low dropout (LDO) linear regulator that operates
from −2.0 V to −5.5 V and provides up to −500 mA of output
current. This high output current LDO is ideal for regulation of
high performance analog and mixed signal circuits operating
from −0.5 V down to −4.5 V. Using an advanced proprietary
architecture, the ADP7185 provides high power supple rejection
ratio (PSRR) and low noise, and it achieves excellent line and load
transient response with a small 4.7 μF ceramic output capacitor.
The ADP7185 is available in 15 fixed output voltage options.
The following voltages are available from stock: −0.5 V, −1.0 V,
−1.2 V, −1.5 V, −1.8 V, −2.0 V, −2.5 V, −3.0 V, and −3.3 V.
Rev. 0
Additional voltages available by special order are −0.8 V, −0.9 V,
−1.3 V, −2.8 V, −4.2 V, and −4.5 V. An adjustable version is also
available which allows output voltages that range from −0.5 V to
−VIN + 0.5 V with an external feedback divider.
The enable logic feature is capable of interfacing with positive
or negative logic levels for maximum flexibility.
The ADP7185 regulator output noise is 4 μV rms independent
of the output voltage. The ADP7185 is available in an 8-lead,
2 mm × 2 mm LFCSP, making it not only a very compact
solution but also providing excellent thermal performance for
applications requiring up to −500 mA of output current in a
small, low profile footprint.
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Technical Support
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ADP7185
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 13
Applications ....................................................................................... 1
Adjustable Mode Operation ..................................................... 13
Typical Application Circuits............................................................ 1
Enable Pin Operation ................................................................ 13
General Description ......................................................................... 1
Start-Up Time ............................................................................. 14
Revision History ............................................................................... 2
Applications Information .............................................................. 15
Specifications..................................................................................... 3
ADIsimPower Design Tool ....................................................... 15
Input and Output Capacitor Recommended Specifications... 4
Capacitor Selection .................................................................... 15
Absolute Maximum Ratings............................................................ 5
Undervoltage Lockout (UVLO) ............................................... 16
Thermal Data ................................................................................ 5
Current-Limit and Thermal Overload Protection ................. 16
Thermal Resistance ...................................................................... 5
Thermal Considerations............................................................ 17
ESD Caution .................................................................................. 5
Outline Dimensions ....................................................................... 19
Pin Configuration and Function Descriptions ............................. 6
Ordering Guide .......................................................................... 19
Typical Performance Characteristics ............................................. 7
REVISION HISTORY
5/2017—Revision 0: Initial Version
Rev. 0 | Page 2 of 19
Data Sheet
ADP7185
SPECIFICATIONS
VIN = (VOUT − 0.5 V) or −2 V (whichever is more negative), EN = VIN, IOUT = −10 mA, CIN = COUT = 4.7 μF, CAFB = 10 nF, CA = CREG = 1 μF, TA =
25°C for typical specifications, and TJ = −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.
Table 1.
Parameter
INPUT VOLTAGE RANGE
LOAD CURRENT
OPERATING SUPPLY CURRENT
Symbol
VIN
ILOAD
IGND
SHUTDOWN CURRENT
OUTPUT NOISE1
IGND-SD
OUTNOISE
NOISE SPECTRAL DENSITY1
OUTNSD
POWER SUPPLY REJECTION RATIO1
PSRR
OUTPUT VOLTAGE
Accuracy
VOUT
OUTPUT VOLTAGE REFERENCE FEEDBACK
VAFB Accuracy
VAFB
LINE REGULATION
LOAD REGULATION2
INPUT BIAS CURRENT
SENSE
ΔVOUT/∆VIN
∆VOUT/∆IOUT
VAFB
SENSEI-BIAS
VAFB-BIAS
DROPOUT VOLTAGE3
VDROPOUT
PULL-DOWN RESISTANCE
Output Voltage
Regulated Input Supply Voltage
Low-Noise Reference Voltage
START-UP TIME4
VOUT-PULL
VREG-PULL
VA-PULL
TSTART-UP
CURRENT-LIMIT THRESHOLD5
THERMAL SHUTDOWN
Threshold
Hysteresis
Test Conditions/Comments
IOUT = 0 μA
IOUT = −500 mA
EN = GND, VIN = −5.5 V
10 Hz to 100 kHz, CAFB = 1 nF
10 Hz to 100 kHz, CAFB = 10 nF
100 Hz to 100 kHz, CAFB = 1 nF
100 Hz to 100 kHz, CAFB = 10 nF
100 Hz, CAFB = 1 nF
100 Hz, CAFB = 10 nF
10 kHz to 1 MHz, CAFB=1 nF to 1 μF
IOUT = −500 mA, VOUT = −3.3 V, VIN = −3.8 V
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
IOUT = −10 mA, TA = 25°C
−1 mA < IOUT < −500 mA, VIN = (VOUT − 0.5 V)
to −5.5 V
Adjustable model voltage reference
Adjustable model, −1 mA < IOUT < −500 mA,
VIN = (VOUT − 0.5 V) to −5.5 V
VIN = (VOUT − 0.5 V) to −5.5 V
IOUT = −1 mA to −500 mA
Rev. 0 | Page 3 of 19
Max
−5.5
−500
−0.90
−7.0
−7
80
68
50
40
–0.5
–0.5
–2.2
−0.489
−2.2
−0.5
−0.1
0.6
Unit
V
mA
mA
mA
μA
μV rms
μV rms
μV rms
μV rms
nV/√Hz
nV/√Hz
nV/√Hz
–4.5
+0.5
+2.2
dB
dB
dB
dB
V
%
%
−0.511
+2.2
V
%
+0.3
1.8
%/V
%/A
−10
nA
−10
nA
−30
−190
−600
TJ rising
Typ
−0.6
−5.5
−2
7
5
6
4
300
100
20
−1 mA < IOUT < −500 mA, VIN = (VOUT − 0.5 V)
to −5.5 V
−1 mA < IOUT < −500 mA, VIN = (VOUT − 0.5 V)
to −5.5 V
IOUT = −100 mA
IOUT = −500 mA
VEN = 0 V
VOUT = −1 V
VREG = −1 V
VA = −1 V
VOUT = −4.5 V, CAFB = 1 nF, CA = 1 μF
VOUT = −4.5 V, CAFB = 10 nF, CA = 1 μF
VOUT = −1.2 V, CAFB = 1 nF, CA = 1 μF
VOUT = −1.2 V, CAFB = 10 nF, CA = 1 μF
VOUT = −0.5 V, no CAFB, CA = 1 μF
ILIMIT
TSSD
TSSD-HYS
Min
−2.0
280
1.3
61
15
55
4
10
1.5
−900
150
15
−60
−360
mV
mV
−1100
Ω
kΩ
Ω
ms
ms
ms
ms
ms
mA
°C
°C
ADP7185
Parameter
UNDERVOLTAGE LOCKOUT THRESHOLDS
Input Voltage
Rising
Falling
Hysteresis
EN INPUT (NEGATIVE)
Logic High
Logic Low
Hysteresis
Leakage Current
EN INPUT (POSITIVE)
Logic High
Logic Low
Leakage Current
Data Sheet
Symbol
Test Conditions/Comments
UVLORISE
UVLOFALL
UVLOHYS
VEN-NEG-HIGH
VEN-NEG_LOW
ENHYS-NEG
IEN-LKG
VEN-POS-HIGH
VEN-POS-LOW
IEN-LKG
Min
Typ
Max
Unit
−1.77
V
V
mV
−1.58
90
−2 V ≤ VIN ≤ −5.5 V
VOUT = off to on
VOUT = on to off
EN = VIN or GND
−2 V ≤ VIN ≤ −5.5 V
VOUT = off to on
VOUT = on to off
VEN = 5 V, VIN = −5.5 V
−1.3
−1.16
−0.96
191
−0.25
0.96
0.89
4.0
0.5
-0.88
1.25
6.0
V
V
mV
μA
V
V
μA
1
Guaranteed by characterization but not production tested.
Based on an endpoint calculation using −1 mA and −500 mA loads.
3
Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. Dropout applies only for output
voltages below −2 V.
4
Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value.
5
Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit threshold for a
−3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of −3.0 V, or −2.7 V.
2
INPUT AND OUTPUT CAPACITOR RECOMMENDED SPECIFICATIONS
Table 2.
Parameter
CAPACITANCE
Minimum CIN and COUT Capacitance1
Minimum CA and CREG Capacitance2
Minimum CAFB Capacitance3
Capacitor Equivalent Series Resistance (ESR)
Symbol
Test Conditions/Comments
TA = −40°C to +125°C
CIN, COUT
CA, CREG
CAFB
RESR
1
Min
Typ
3.3
0.7
0.7
4.7
1
10
Max
Unit
0.1
μF
μF
nF
Ω
The minimum input and output capacitance must be greater than 3.3 μF over the full range of operating conditions. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with any LDO.
2
The minimum CA and CREG capacitance must be greater than 0.7 μF over the full range of operating conditions. X7R and X5R type capacitors are recommended; Y5V
and Z5U capacitors are not recommended for use with any LDO.
3
The minimum CAFB capacitance must be greater than 0.7 nF over the full range of operating conditions. X7R and X5R type capacitors are recommended; Y5V and Z5U
capacitors are not recommended for use with any LDO.
Rev. 0 | Page 4 of 19
Data Sheet
ADP7185
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
VOUT to GND
EN to GND
VA to GND
VAFB to GND
VREG to GND
SENSE to GND
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
+0.3 V to −6 V
+0.3 V to −VIN
+5.0 V to −6 V
+0.3 V to −6 V
+0.3 V to −6 V
+0.3 V to −2.16 V
+0.3 V to −6 V
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
temperature (TJ) of the device is dependent on the ambient
temperature (TA), the power dissipation of the device (PD), and
the junction to ambient thermal resistance of the package (θJA).
Use the following equation to calculate the junction temperature
(TJ) from the ambient temperature (TA) and power dissipation (PD):
TJ = TA + (PD × θJA)
The junction to ambient thermal resistance (θJA) of the package
is based on modeling and calculation using a 4-layer board. The
junction to ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The θJA value may vary, depending on
the PCB material, layout, and environmental conditions. The
specified θJA values are based on a 4-layer, 4 in. × 3 in. circuit board.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
THERMAL DATA
Table 4. Thermal Resistance
Absolute maximum ratings apply individually only, not in
combination. The ADP7185 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that TJ is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
have to be derated.
ESD CAUTION
Package Type
CP-8-27
In applications with moderate power dissipation and low printed
circuit board (PCB) thermal resistance, the maximum ambient
temperature can exceed the maximum limit as long as the
junction temperature is within specification limits. The junction
Rev. 0 | Page 5 of 19
θJA
68.8
θJC
10.0
Unit
°C/W
ADP7185
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VOUT 1
VA 3
VAFB 4
8 VIN
ADP7185
7 VREG
TOP VIEW
(Not to Scale)
6 GND
5 EN
NOTES
1. EXPOSED PAD. THE EXPOSED PAD ENHANCES THE
THERMAL PERFORMANCE AND IS ELECTRICALLY
CONNECTED TO VIN INSIDE THE PACKAGE. IT IS
RECOMMENDED THAT THE EXPOSED PAD CONNECT
TO THE INPUT VOLTAGE PLANE ON THE BOARD.
13932-003
SENSE 2
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
Mnemonic
VOUT
SENSE
VA
VAFB
5
EN
6
7
GND
VREG
8
VIN
EP
Description
Regulated Output Voltage. Bypass VOUT to GND with a 4.7 μF or greater capacitor.
Sense Input. Connect this pin to VOUT.
Low Noise Reference Voltage. Connect a 1 μF capacitor to GND to reduce noise. Do not connect a load to ground.
Output Voltage Reference Feedback (Adjust Mode). Connect a 1 nF to 1 μF capacitor between the VAFB pin and
the VA pin to reduce noise. Start-up time is increased as a function of the capacitance. Connect an external resistor
divider between the VA pin and the VAFB pin to set the output voltage in adjust mode.
Enable. Drive EN at least +1.25 V above or −1.3 V below ground to enable the regulator or drive EN to ground to
turn the regulator off. For automatic startup, connect EN to VIN.
Ground.
Regulated Input Supply to the LDO Amplifier. Bypass VREG to GND with a 1 μF or greater capacitor. Do not
connect a load to ground.
Regulator Input Supply. Bypass VIN to GND with a 4.7 μF or greater capacitor.
Exposed pad. The exposed pad enhances the thermal performance and is electrically connected to VIN inside the
package. It is recommended that the exposed pad connect to the input voltage plane on the board.
Rev. 0 | Page 6 of 19
Data Sheet
ADP7185
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = −3.8 V, VOUT = −3.3 V, IOUT = −10 mA, CIN = COUT = 4.7 μF, CAFB = 10 nF, CA = CREG = 1 μF, and TA = 25°C, unless otherwise noted.
0
NO LOAD
ILOAD = –10mA
ILOAD = –100mA
ILOAD = –300mA
ILOAD = –500mA
–1
GROUND CURRENT (mA)
–1.191
–1.201
–1.206
–1.211
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
–5
–6
–1
GROUND CURRENT (mA)
–1.191
–1.206
–1.211
10
35
60
85
110
135
–2
–3
–4
–10
–6
–500 –450 –400 –350 –300 –250 –200 –150 –100
13932-305
–100
ILOAD (mA)
–50
0
ILOAD (mA)
Figure 5. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = −1.2 V
13932-018
–5
–1.216
–1000
Figure 8. Ground Current vs. Load Current (ILOAD), VOUT = −1.2 V
–1.186
0
–1
GROUND CURRENT (mA)
–1.196
–1.206
–1.216
–1.226
NO LOAD
ILOAD = –10mA
ILOAD = –100mA
ILOAD = –300mA
ILOAD = –500mA
–5.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
VIN (V)
–2
–3
–4
–5
–6
–7
13932-306
–1.236
–1.246
–5.5
–15
Figure 7. Ground Current vs. Junction Temperature (TJ), VOUT = −1.2 V
0
–1.201
NO LOAD
ILOAD = –10mA
ILOAD = –100mA
ILOAD = –300mA
ILOAD = –500mA
JUNCTION TEMPERATURE (°C)
–1.186
–1.196
VOUT (V)
–4
–8
–40
Figure 4. Output Voltage (VOUT) vs. Junction Temperature, VOUT = −1.2 V
VOUT (V)
–3
–7
13932-304
–1.216
–60
–2
Figure 6. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = −1.2 V
–8
–5.5
NO LOAD
ILOAD = –10mA
ILOAD = –100mA
ILOAD = –300mA
ILOAD = –500mA
–5.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
VIN (V)
Figure 9. Ground Current vs. Input Voltage (VIN), VOUT = −1.2 V
Rev. 0 | Page 7 of 19
13932-019
VOUT (V)
–1.196
13932-017
–1.186
ADP7185
Data Sheet
–2.435
0
–2.455
–1.0
–2.475
–1.5
VOUT (V)
–2.0
–2.5
VIN = –2.0V
VIN = –2.5V
VIN = –3.0V
VIN = –3.5V
VIN = –4.0V
VIN = –4.5V
VIN = –5.0V
VIN = –5.5V
–3.5
–4.0
–4.5
–15
10
–2.535
35
60
85
110
135
–2.575
–5.5
–2.435
–4.5
–4.0
–3.5
–3.0
Figure 13. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = −2.5 V
0
NO LOAD
ILOAD = –10mA
ILOAD = –100mA
ILOAD = –300mA
ILOAD = –500mA
–1
GROUND CURRENT (mA)
–2.455
–5.0
VIN (V)
Figure 10. Shutdown Current vs. Junction Temperature at Various Input Voltages,
VOUT = −1.2 V
–2.475
VOUT (V)
NO LOAD
ILOAD = –10mA
ILOAD = –100mA
ILOAD = –300mA
ILOAD = –500mA
–2.555
JUNCTION TEMPERATURE (°C)
–2.495
–2.515
–2.535
–2
–3
–4
–5
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
–6
–500 –450 –400 –350 –300 –250 –200 –150 –100
13932-311
–2.555
–60
–2.515
–50
0
ILOAD (mA)
Figure 11. Output Voltage (VOUT) vs. Junction Temperature (TJ), VOUT = −2.5 V
13932-024
–5.0
–40
–2.495
13932-313
–3.0
13932-020
SHUTDOWN CURRENT (µA)
–0.5
Figure 14. Ground Current vs. Load Current (ILOAD), VOUT = −2.5 V
–2.455
0
–1
–2.495
–2.515
–2.535
–2
–3
–4
–5
–6
–100
–10
ILOAD (mA)
13932-312
–7
–2.555
–1000
Figure 12. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = −2.5 V
–8
–5.5
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
= –10mA
= –100mA
= –200mA
= –300mA
= –500mA
–5.0
–4.5
–4.0
–3.5
–3.0
VIN (V)
Figure 15. Ground Current vs. Input Voltage (VIN), VOUT = −2.5 V
Rev. 0 | Page 8 of 19
13932-025
GROUND CURRENT (mA)
VOUT (V)
–2.475
Data Sheet
ADP7185
–3.249
0
–20
–3.269
DROPOUT VOLTAGE (mV)
–40
–60
–3.289
VOUT (V)
–80
–100
–120
–3.309
–3.329
–140
–160
–3.349
–100
–10
ILOAD (mA)
–3.369
–1000
13932-316
–200
–1000
Figure 16. Dropout Voltage vs Load Current (ILOAD), VOUT = −2.5 V
–10
ILOAD (mA)
Figure 19. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = −3.3 V
–2.24
–3.26
NO LOAD
ILOAD = –10mA
ILOAD = –100mA
ILOAD = –300mA
ILOAD = –500mA
–2.26
–2.28
–2.30
–2.32
–3.28
NO LOAD
ILOAD = –10mA
ILOAD = –100mA
ILOAD = –300mA
ILOAD = –500mA
–3.30
–2.34
VOUT (V)
–2.36
VOUT (V)
–100
13932-319
–180
–2.38
–2.40
–2.42
–3.32
–3.34
–2.44
–2.46
–3.36
–2.48
–3.0
–2.9
–2.8
–2.7
–2.6
–2.5
–2.4
VIN (V)
–3.38
–5.5
13932-317
–4.9
–4.7
–4.5
–4.3
–4.1
–3.9
Figure 20. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = −3.3 V
–3.239
0
NO LOAD
ILOAD = –10mA
ILOAD = –100mA
ILOAD = –300mA
ILOAD = –500mA
–1
GROUND CURRENT (mA)
–3.259
–3.279
VOUT (V)
–5.1
VIN (V)
Figure 17. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout at
Various Loads, VOUT = −2.5 V
–3.299
–3.319
–2
–3
–4
–5
–6
–3.339
–7
–40
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
140
–8
–40
13932-318
–3.359
–60
–5.3
Figure 18. Output Voltage (VOUT) vs. Junction Temperature (TJ), VOUT = −3.3 V
NO LOAD
ILOAD = –10mA
ILOAD = –100mA
ILOAD = –300mA
ILOAD = –500mA
–15
10
35
60
85
JUNCTION TEMPERATURE (°C)
110
135
13932-007
–2.52
–3.1
13932-320
–2.50
Figure 21. Ground Current vs. Junction Temperature (TJ), VOUT = −3.3 V
Rev. 0 | Page 9 of 19
ADP7185
Data Sheet
0
0
–20
–40
DROPOUT VOLTAGE (mV)
GROUND CURRENT (mA)
–1
–2
–3
–4
–60
–80
–100
–120
–140
–160
–5
–50
0
ILOAD (mA)
–200
–1000
13932-008
–6
–500 –450 –400 –350 –300 –250 –200 –150 –100
0
–3.14
–1
–3.16
–3.18
–2
VOUT (V)
–4
–5
–3.22
–3.24
–3.26
NO LOAD
ILOAD = –10mA
ILOAD = –100mA
ILOAD = –300mA
ILOAD = –500mA
–5.3
–5.1
–4.9
–3.28
–3.30
–4.7
–4.5
–4.3
–4.1
–3.9
VIN (V)
–3.32
–3.9
–3.8
–3.7
–3.6
–3.5
–3.4
–3.3
–3.2
VIN (V)
Figure 23. Ground Current vs. Input Voltage (VIN), VOUT = −3.3 V
13932-326
–8
–5.5
NO LOAD
ILOAD = –10mA
ILOAD = –100mA
ILOAD = –300mA
ILOAD = –500mA
–3.20
–3
–7
–10
Figure 25. Dropout Voltage vs. Load Current (ILOAD), VOUT = −3.3 V
13932-009
GROUND CURRENT (mA)
Figure 22. Ground Current vs. Load Current (ILOAD), VOUT = −3.3 V
–6
–100
ILOAD (mA)
13932-325
–180
Figure 26. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout at
Various Loads, VOUT = −3.3 V
0
0
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–40
VIN = –3.8V
VIN = –4.0V
VIN = –4.5V
VIN = –5.0V
VIN = –5.5V
–20
0
–10
–15
–20
20
40
60
80
100
120
JUNCTION TEMPERATURE (°C)
140
Figure 24. Shutdown Current vs. Junction Temperature at
Various Input Voltages, VOUT = −3.3 V
–25
–3.9
ILOAD = –10mA
ILOAD = –100mA
ILOAD = –300mA
ILOAD = –500mA
–3.7
–3.5
–3.3
–3.1
–2.9
–2.7
VIN (V)
Figure 27. Ground Current vs. Input Voltage (VIN) in Dropout at
Various Loads, VOUT = −3.3 V
Rev. 0 | Page 10 of 19
13932-327
GROUND CURRRENT (mA)
–5
13932-010
SHUTDOWN CURRENT (µA)
–0.5
Data Sheet
–10
–20
–30
–40
–40
PSRR (dB)
–30
–50
–60
–80
–80
–90
–90
–100
–100
10
100
1k
10k
100k
1M
10M
0
ILOAD = –10mA
ILOAD = –100mA
ILOAD = –200mA
ILOAD = –300mA
ILOAD = –500mA
–20
–20
–40
–40
PSRR (dB)
–30
–50
–60
–80
–80
–90
–100
–100
1k
10k
100k
1M
10M
13932-032
–90
FREQUENCY (Hz)
1
0
–20
–30
1M
10M
10
100
1k
10k
100k
1M
10M
Figure 32. Power Supply Rejection Ratio (PSRR) vs. Frequency at
Various Input Voltages, VOUT = −2.5 V, ILOAD = −500 mA
0
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
100k
FREQUENCY (Hz)
Figure 29. Power Supply Rejection Ratio (PSRR) vs. Frequency at
Various Loads, VOUT = −2.5 V, VIN = −3 V
–10
10k
–60
–70
100
1k
–50
–70
10
100
VIN = –3.0V
VIN = –3.1V
VIN = –3.2V
VIN = –3.3V
VIN = –3.4V
VIN = –3.5V
–10
–30
1
10
Figure 31. Power Supply Rejection Ratio (PSRR) vs. Frequency at
Various Input Voltages, VOUT = −1.2 V, ILOAD = −500 mA
0
–10
= –10mA
= –100mA
= –200mA
= –300mA
= –500mA
VIN = –3.8V
VIN = –3.9V
VIN = –4.0V
VIN = –4.1V
VIN = –4.2V
VIN = –4.3V
–10
–20
–30
–40
PSRR (dB)
–40
–50
–60
–70
–50
–60
–70
–80
–80
–90
–90
–100
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
13932-033
1
–110
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 33. Power Supply Rejection Ratio (PSRR) vs. Frequency at
Various Input Voltages, VOUT = −3.3 V, ILOAD = −500 mA
Figure 30. Power Supply Rejection Ratio (PSRR) vs. Frequency at
Various Loads, VOUT = −3.3 V, VIN = −3.8 V
Rev. 0 | Page 11 of 19
13932-333
–100
–110
–120
1
FREQUENCY (Hz)
Figure 28. Power Supply Rejection Ratio (PSRR) vs. Frequency at
Various Loads, VOUT = −1.2 V, VIN = −2 V
PSRR (dB)
–60
–70
FREQUENCY (Hz)
PSRR (dB)
–50
–70
1
VIN = –2.0V
VIN = –2.1V
VIN = –2.2V
VIN = –2.3V
VIN = –2.4V
VIN = –2.5V
–10
13932-031
PSRR (dB)
–20
0
= –10mA
= –100mA
= –200mA
= –300mA
= –500mA
13932-331
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
13932-332
0
ADP7185
ADP7185
Data Sheet
4.40
10Hz TO 100kHz
100Hz TO 100kHz
4.35
VIN
4.30
1
NOISE (µV rms)
4.25
4.20
4.15
4.10
VOUT
4.05
2
4.00
3.95
3.90
–100
–10
LOAD CURRENT (mA)
–1.2V
–2.5V
–3.3V
–4.5V
–4.5V ADJ
NSD (nV/√Hz)
1k
CH2 –20.5mV 5.0µs/DIV
2.0mV
1MS 20GS/s
STOP 40mV
EDGE POSITIVE
Figure 37. Line Transient Response, 500 mV Step, VOUT = −3.3 V, ILOAD = −500 mA
Figure 34. RMS Noise vs. Load Current (ILOAD) at Various Frequencies,
VIN = −3.8 V, VOUT = −3.3 V
10k
CH1 995mV
500mV/DIV
13932-337
3.80
–1000
13932-037
3.85
VOUT
2
100
10
1
ILOAD
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 35. Noise Spectral Density (NSD) vs. Frequency at Various Output Voltages,
VIN = −3.8 V, VOUT = −3.3 V
CH1 –475mA CH2 5.0mV
500mA/DIV
9.9mV
10.0µs/DIV
2MS 20GS/s
STOP –220mA
EDGE POSITIVE
13932-338
0.1
10
13932-335
1
Figure 38. Load Transient Response, VOUT = −1.2 V, ILOAD = −10 mA to −500 mA
VIN
VOUT
1
2
VOUT
1
2
CH2 –2.00mV 5.0µs/DIV
2.0mV
1MS 20GS/s
STOP 40mV
EDGE POSITIVE
CH1 –215.0mA CH2 3.6mV 10.0µs/DIV
200mA/DIV
2.0mV
2MS 20GS/s
Figure 36. Line Transient Response, 500 mV Step, VOUT = −1.2 V, ILOAD = −500 mA
STOP –222mA
EDGE POSITIVE
13932-339
CH1 995mV
500mV/DIV
13932-336
ILOAD
Figure 39. Load Transient Response, VOUT = −2.5 V, ILOAD = −10 mA to −500 mA
Rev. 0 | Page 12 of 19
Data Sheet
ADP7185
THEORY OF OPERATION
The ADP7185 is a low quiescent current, LDO linear regulator
that operates from −2.0 V to −5.5 V and can provide up to
−500 mA of output current. Total integrated output noise is
4 μV rms independent of the output voltage, making it ideal for
high performance and noise sensitive applications. Shutdown
current consumption is −7 μA (maximum).
The ADP7185 is optimized for use with a 4.7 μF ceramic
capacitor for excellent transient performance. Using advanced
proprietary architecture, the ADP7185 provides ultralow noise
and high power supply rejection up to high frequencies of
operation. Figure 40 shows the fixed output voltage internal block
diagram of the ADP7185, and Figure 41 shows the adjustable
output voltage internal block diagram of the ADP7185.
R2 resistors that are connected across the VA and VAFB pins.
Because the reference voltage to the LDO regulator already
adjusts according to the desired VOUT, the LDO regulator now
connects in a buffer configuration for improved noise performance.
If the load draws higher current, the LDO regulator pulls the gate
of the NMOS device higher towards GND to allow more current
to pass. If the load draws less current, the LDO regulator pulls
the gate of the NMOS device lower toward −VIN to restrict the
amount of current passing through the device.
ADJUSTABLE MODE OPERATION
The adjustable mode version of the ADP7185 has an output that
can be set to from −0.5 V to −4.5 V by an external voltage divider.
To calculate the output voltage, use the following equation:
VOUT = −0.5 V(1 + R1/R2)
R2
Figure 42 shows an example of an adjustable setting where R1 =
280 kΩ and R2 = 49.9 kΩ, setting the output voltage to −3.3 V.
VAFB
VA
SENSE
R1
VOUT
–0.5V
REFERENCE
(1)
R2 must be at least 10 kΩ to maximize PSRR performance.
GM
VIN = –3.8V
OVER CURRENT
THERMAL
PROTECTION
VREG
EN
CIN
4.7µF
SENSE
Figure 40. Fixed Output Voltage Internal Block Diagram
VAFB
VA
VAFB
EN
CAFB
10nF
R1
280kΩ
CA
1µF
R2
49.9kΩ
–1.3V
ON
Figure 42. Setting the Adjustable Output Voltage
R2
ENABLE PIN OPERATION
R1
The ADP7185 uses the EN pin to enable and disable the VOUT pin
under normal operating conditions. When EN is +1.25 V above or
−1.3 V below with respect to GND, VOUT turns on, and when
EN is at 0 V, VOUT turns off, as shown in Figure 43. For
automatic startup, connect EN to VIN.
SENSE
VOUT
–0.5V
REFERENCE
0V
COUT
4.7µF
VA
+1.25V
OFF
VOUT = –3.3V
VOUT
ADP7185
GND
VIN
GM
GND
OVER CURRENT
THERMAL
PROTECTION
VREG
REG
VIN
Figure 41. Adjustable Output Voltage Internal Block Diagram
EN
2
Internally, the ADP7185 consists of a regulator block, reference
block, GM amplifier, feedback voltage divider, LDO regulator, and an
N-channel MOSFET pass transistor. The regulator block produces
an internal voltage rail (VREG) of −1.8 V to serve as the supply
voltage for the succeeding internal blocks. The GM amplifier
produces a reference voltage (VA) used as a reference to the
LDO regulator.
For fixed option models, the VA voltage is generated through the
resistor divider ratio depending on the VOUT option. For adjustable
models, the VA voltage generates externally through the R1 and
Rev. 0 | Page 13 of 19
VOUT
CH1 1.0V
–15mV
CH2 1.0V
0mV
200ms/DIV
2MS 1MS/s
A CH2
Figure 43. Typical EN Pin Operation
40mV
13932-149
EN
13932-046
EN
VREG
CREG
1µF
REG
13932-045
EN
EP
VIN
13932-047
GND
ADP7185
Data Sheet
0.5
START-UP TIME
–0.5
–1.5
–2.0
–2.5
–3.0
EN
VOUT = –4.5V
VOUT = –3.3V
VOUT = –2.5V
VOUT = –1.2V
0
–3.5
–4.0
–4.5
–1
10
30
50
70
90
110 130 150 170 190 210 230
TIME (ms)
–2
Figure 45. Start-Up Time at Various CAFB Capacitor Values, CA = 1 μF
A second time constant, τ2, is dependent mainly on CAFB. Figure 45
shows how the CAFB value affects the start-up time. Estimate τ2 by
–3
–4
τ2 ≈ CAFB × R1
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
TIME (ms)
13932-244
–5
–6
13932-245
1
VOUT, EN (V)
= 1nF
= 10nF
= 100nF
= 1µF
–1.0
VOUT (V)
When the output is enabled, the ADP7185 uses an internal soft
start to limit the inrush current. The start-up time for a −1.2 V
output is approximately 12 ms from the time the EN active
threshold is crossed to the time when the output reaches 90%
of its final value (see Figure 44). As shown in Figure 44 and
Figure 45, the start-up time is dependent upon the output
voltage option and the value of the CAFB capacitor.
EN
CAFB
CAFB
CAFB
CAFB
0
Figure 44. Start-Up Time at Various Output Voltages, CAFB = 10 nF, CA = 1 μF
The total start-up time depends mostly on the CA and CAFB
values expressed by the τ1 and τ2 equations (see Equation 2 and
Equation 3). During startup, an internal circuit, GM_START, turns
on and helps charge CA up to 90% of the final value. Estimate the
first time constant, τ1, due to CA by
τ1 ≈ CA × ((R1 + R2)//ZOUT)
(2)
During this time, keep ZOUT low to approximately 1 kΩ to allow
quick start-up times, keeping τ1 in the order of 1 ms.
(3)
The R1 value scales vs. the VOUT option. Table 6 shows the R1
value depending on the fixed output voltage option, whereas R2
is constant at 500 kΩ. For example, at a fixed VOUT = −3.3 V, R1
equals 2.8 MΩ. To keep τ2 at a minimum, it is recommended that
CAFB be in the approximately nanofarad range. A typical setup for
the ADP7185 is CAFB = 10 nF; therefore, τ2 = 28 ms. The total
time constant, τTOTAL, is the sum of τ1 and τ2. At 2.2 × τTOTAL, VA is
equal to ~90% of the final value. Therefore, for a fixed VOUT =
−3.3 V, the output voltage is ~90% of the final value after 63.8 ms.
Table 6. R1 and R2 Values for the Fixed Output Options
Output Voltage (V)
−1.2
−2.5
−3.3
−4.5
R1 (Ω)
700 k
2M
2.8 M
4M
R2 (kΩ)
500
500
500
500
Note that τ1 and τ2 are estimates only and do not take into account
that GM and ZOUT dynamically change. It is an accurate estimate
of ~90% of the start-up time for the CAFB < 10 nF recommended
setup, where ~100% of the settling time can easily be achieved.
Note that for setups with CAFB >> 10 nF, the equation may not
hold true anymore. However, it is still a convenient estimate on
the amount of time needed to achieve ~100% of the settling time.
Rev. 0 | Page 14 of 19
Data Sheet
ADP7185
APPLICATIONS INFORMATION
ADIsimPOWER DESIGN TOOL
CA and CAFB Capacitors
The ADIsimPower™ design tool set supports the ADP7185.
ADIsimPower is a collection of tools that produce complete
power designs optimized for a specific design goal. The tools
enable the user to generate a full schematic, bill of materials,
and calculate performance in minutes. ADIsimPower can
optimize designs for cost, area, efficiency, and parts count,
taking into consideration the operating conditions and
limitations of the IC and all external components. For more
information about, and to obtain ADIsimPower design tools,
visit www.analog.com/ADIsimPower.
The ultralow output noise of the ADP7185 is achieved by
keeping the LDO error amplifier in unity gain and setting the
reference voltage equal to the output voltage. In this architecture,
the resistor driven by the GM amplifier adjusts the reference
voltage to the selected output voltage. To ensure the GM amplifier
stability, the CA capacitor is needed to generate the dominant
pole and to keep the GM amplifier stable across all conditions.
CA also serves as a dampening capacitor to the inputs of the
LDO error amplifier for improved PSRR. However, the LDO
output noise scales by the GM amplifier amount of gain as a
function of the output voltage. To minimize the output voltage
noise contributed by the GM amplifier, the CAFB capacitor must
be connected between the VA and VAFB pins to keep the ac
gain of the GM amplifier in unity.
Output Capacitor
The ADP7185 operates with small, space-saving ceramic
capacitors; however, it also functions with general-purpose
capacitors as long as care is taken with regard to the effective
series resistance (ESR) value. The ESR of the output capacitor
affects the stability of the LDO regulator control loop. A
minimum of 4.7 μF capacitance with an ESR of 0.05 Ω or less is
recommended to ensure the stability of the ADP7185. Output
capacitance affects the transient response to changes in load
currents. Using a larger value for the output capacitance improves
the transient response of the ADP7185 to large changes in load
current. Figure 46 shows the transient response for an output
capacitance value (COUT) of 4.7 μF.
VOUT
1
CA
VAFB
CAFB
R1
REFERENCE
GM
VA
Figure 47. CA and CAFB Connection to the GM Amplifier
Input and Output Capacitor Properties
STOP –220mA
EDGE POSITIVE
13932-246
ILOAD
10.0µs/DIV
2MS 20GS/s
R2
Any good quality ceramic capacitors can be used with the
ADP7185 if they meet the minimum capacitance and maximum
ESR requirements. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior over temperature
and applied voltage. Capacitors must have a dielectric adequate to
ensure the minimum capacitance over the necessary temperature
range and dc bias conditions. X5R and X7R dielectrics with a
voltage rating from 6.3 V to 10 V are recommended. Due to their
poor temperature and dc bias characteristics, Y5V and Z5U
dielectrics are not recommended.
2
CH1 –475mA CH2 5.0mV
500mA/DIV
9.9mV
GND
13932-200
CAPACITOR SELECTION
Figure 46. Output Transient Response, COUT = 4.7 μF, VOUT = −1.2 V
Input Bypass Capacitor
Connecting a 4.7 μF or greater capacitor from VIN to GND
reduces the circuit sensitivity to the PCB layout, especially when
long input traces or high source impedance are encountered.
When more than 4.7 μF of output capacitance is required,
increase the input capacitance to match it.
Rev. 0 | Page 15 of 19
ADP7185
Data Sheet
0.05
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–0.35
4.70
–0.40
3.76
–0.45
2.82
–0.55
–1.74
–1.72
–1.70
–1.68
–1.66
–1.64
–1.62
–1.60
VIN (V)
1.88
Figure 49. Typical UVLO Behavior, VOUT = −0.5 V
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
0.94
0
13932-053
–0.50
0
2
4
6
8
10
DC BIAS VOLTAGE (V dc)
12
13932-052
CHANGE IN CAPACITANCE (µF)
5.64
A typical hysteresis of 90 mV within the UVLO circuitry prevents
the device from oscillating due to the noises from VIN.
VOUT (V)
Figure 48 shows the change in capacitance vs. the dc bias voltage
characteristics of a 0805 case, 4.7 μF, 10 V, X5R capacitor. The
capacitor size and voltage ratings strongly influence the voltage
stability of a capacitor. In general, a capacitor in a larger package
or with a higher voltage rating exhibits improved stability. The
temperature variation of the X5R dielectric is about ±15% over
the −55°C to +85°C temperature range and is not a function of
package size or voltage rating.
Figure 48. Change in Capacitance vs. DC Bias Voltage
Use Equation 4 to determine the worst-case capacitance,
accounting for capacitor variation over temperature, component
tolerance, and voltage.
CEFF = COUT × (1 − TEMPCO) × (1 − TOL)
(4)
where:
CEFF is the effective capacitance at the operating voltage.
COUT is the output capacitor.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient
(TEMPCO) over −55°C to +85°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and COUT = 4.7 μF at 1.0 V.
Substituting these values in Equation 4 yields
CEFF = 4.7 μF × (1 − 0.15) × (1 − 0.1) = 3.6 μF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temperature
and tolerance at the chosen output voltage.
To guarantee the performance of the ADP7185, it is imperative
to evaluate the effects of dc bias, temperature, and tolerances on
the behavior of the capacitors for each application.
UNDERVOLTAGE LOCKOUT (UVLO)
The UVLO circuitry protects the system from power supply
brownouts. If the input voltage on VIN is more positive than
the minimum −1.58 V UVLO falling threshold, the LDO output
shuts down. The LDO enables again when the voltage to VIN is
more negative than the maximum −1.77 V UVLO rising threshold.
The ADP7185 is protected against damage due to excessive
power dissipation by current-limit and thermal overload
protection circuits. The ADP7185 is designed to reach current
limit when the output load reaches −900 mA (typical). When
the output load exceeds −900 mA, the output voltage is reduced
to maintain a constant current limit.
Thermal overload protection is included, which limits the
junction temperature to a maximum of 150°C (typical). Under
extreme conditions (that is, high ambient temperature and
power dissipation) when the junction temperature begins to rise
above 150°C, the output is turned off, reducing the output
current to zero. When the junction temperature drops below
135°C (typical), the output is turned on again, and the output
current is restored to its nominal value.
Consider the case where a hard short from VOUT to GND occurs.
At first, the ADP7185 reaches current limit so that only −900 mA
is conducted into the short. If self-heating of the junction becomes
great enough to cause its temperature to rise above 150°C, thermal
shutdown activates, turning off the output and reducing the
output current to zero. As the junction temperature cools and
drops below 135°C, the output turns on and conducts −900 mA
into the short, again causing the junction temperature to rise
above 150°C. This thermal oscillation between 135°C and
150°C causes a current oscillation between −900 mA and 0 A
that continues as long as the short remains at the output. Currentlimit and thermal overload protections protect the device
against accidental overload conditions. For reliable operation,
externally limit device power dissipation so that junction
temperatures do not exceed 125°C.
Rev. 0 | Page 16 of 19
Data Sheet
ADP7185
Table 7 shows the typical θJA values for the 8-lead LFCSP
package and for various PCB copper sizes.
Table 7. Typical θJA Values
θJA (°C/W), 8-Lead LFCSP
146.6
105.4
75.38
65.16
53.5
TJ MAX
6400mm 2
1000mm 2
500mm 2
100mm 2
25mm 2
40
0
0
0.5
1.0
1.5
2.0
2.5
POWER DISSIPATION (W)
Figure 50. Junction Temperature vs. Total Power Dissipation, TA = −25°C
140
120
100
80
60
TJ MAX
6400mm 2
1000mm 2
500mm 2
100mm 2
25mm 2
40
0
0.5
1.0
1.5
2.0
2.5
POWER DISSIPATION (W)
Figure 51. Junction Temperature vs. Total Power Dissipation, TA = −50°C
(5)
140
120
Power dissipation due to ground current is quite small and can
be ignored. Therefore, the junction temperature equation
simplifies to
(7)
100
80
60
TJ MAX
6400mm 2
1000mm 2
500mm 2
100mm 2
25mm 2
40
20
0
0
0.5
1.0
1.5
POWER DISSIPATION (W)
2.0
2.5
13932-056
(6)
where:
VIN and VOUT are the input and output voltages, respectively.
ILOAD is the load current.
IGND is the ground current.
TJ = TA + (((VIN − VOUT) × ILOAD) × θJA)
60
0
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = ((VIN − VOUT) × ILOAD) + (VIN × IGND)
80
20
Calculate the junction temperatures of the ADP7185 by
TJ = TA + (PD × θJA)
100
20
JUNCTION TEMPERATURE (°C)
Copper Size (mm2)
25
100
500
1000
6400
120
13932-054
To guarantee reliable operation, the junction temperature of the
ADP7185 must not exceed 125°C. To ensure that the junction
temperature stays below this maximum value, the user must be
aware of the parameters that contribute to junction temperature
changes. These parameters include ambient temperature, power
dissipation in the power device, and thermal resistances between
the junction and ambient air (θJA). The θJA number is dependent
on the package assembly compounds that are used, and the amount
of copper used to solder the package VIN pins to the PCB.
140
13932-055
When the junction temperature exceeds 150°C, the converter
enters thermal shutdown. The converter recovers only after the
junction temperature decreases below 135°C to prevent any
permanent damage. Therefore, thermal analysis for the chosen
application is important to guarantee reliable performance over all
conditions. The junction temperature of the die is the sum of the
ambient temperature of the environment and the temperature
rise of the package due to the power dissipation, as shown in
Equation 5.
Figure 50 to Figure 52 show the junction temperature calculations
for the different ambient temperatures, power dissipation, and
areas of the PCB copper.
JUNCTION TEMPERATURE (°C)
In applications with a low input to output voltage differential,
the ADP7185 does not dissipate much heat. However, in
applications with high ambient temperature and/or high input
voltage, the heat dissipated in the package may become large
enough to cause the junction temperature of the die to exceed
the maximum junction temperature of 125°C.
As shown in Equation 7, for a given ambient temperature, input
to output voltage differential, and continuous load current,
there exists a minimum copper size requirement for the PCB to
ensure that the junction temperature does not rise above 125°C.
JUNCTION TEMPERATURE (°C)
THERMAL CONSIDERATIONS
Figure 52. Junction Temperature vs. Total Power Dissipation, TA = −85°C
Rev. 0 | Page 17 of 19
ADP7185
Data Sheet
PCB LAYOUT CONSIDERATIONS
13932-059
Place the input capacitor (CIN) as close as possible to the VIN
and GND pins. Place the output capacitor (COUT) as close as
possible to the VOUT and GND pins. Place bypass capacitors
(CA and CREG) close to their respective pins (VA and VREG) and
GND. Use of 0805 or 0603 size capacitors and resistors achieves
the smallest possible footprint solution on boards where area is
limited. Connect the exposed pad to VIN.
13932-058
Figure 54. Typical Board Layout, Top Side
13932-060
Figure 53. Evaluation Board
Figure 55. Typical Board Layout, Bottom Side
Rev. 0 | Page 18 of 19
Data Sheet
ADP7185
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
1.60
1.50
1.40
0.50 BSC
2.10
2.00 SQ
1.90
8
5
PIN 1 INDEX
AREA
1.10
1.00
0.90
EXPOSED
PAD
0.30
0.25
0.20
4
TOP VIEW
SIDE VIEW
0.30
0.25
0.20
PKG-004752
SEATING
PLANE
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
0.152 REF
08-24-2016-A
0.60
0.55
0.50
1
BOTTOM VIEW
Figure 56. 8-Lead Lead Frame Chip Scale Package [LFCSP]
2 mm × 2 mm Body and 0.55 mm Package Height
(CP-8-27)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADP7185ACPZN0.5-R7
ADP7185ACPZN1.0-R7
ADP7185ACPZN1.2-R7
ADP7185ACPZN1.5-R7
ADP7185ACPZN1.8-R7
ADP7185ACPZN2.0-R7
ADP7185ACPZN2.5-R7
ADP7185ACPZN3.0-R7
ADP7185ACPZN3.3-R7
ADP7185ACPZN-R7
ADP7185-3.3-EVALZ
ADP7185-ADJ-EVALZ
1
2
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Output Voltage (V)2
−0.5
−1.0
−1.2
−1.5
−1.8
−2.0
−2.5
−3.0
−3.3
Adjustable
−3.3
−2.5
Package Description
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
Evaluation Board for the
Fixed Voltage Option
Evaluation Board for the
Adjustable Voltage Option
Z = RoHS Compliant Part.
For additional voltage options, contact a local Analog Devices Inc., sales or distribution representative.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13932-0-5/17(0)
Rev. 0 | Page 19 of 19
Package Option
CP-8-27
CP-8-27
CP-8-27
CP-8-27
CP-8-27
CP-8-27
CP-8-27
CP-8-27
CP-8-27
CP-8-27
Branding
LTS
LTT
LTU
LTV
LTW
LTX
LTY
LTZ
LU0
LU1
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