ADPD188GG-ACEZR7

Integrated Optical Module with Ambient Light Rejection and Two LEDs ADPD188GG Data Sheet FEATURES GENERAL DESCRIPTION 3.8 mm × 5.0 mm × 0.9 mm module with integrated optical components 2 green LEDs, 2 PDs with IR cut filter 2 external sensor inputs 3, 370 mA LED drivers 20-bit burst accumulator enabling 20 bits per sample period On-board sample to sample accumulator enabling up to 27 bits per data read Custom optical package made to work under a glass window Optimized SNR for signal limited cases I2C or SPI communications The ADPD188GG is a complete photometric system designed to measure optical signals from ambient light and from synchronous reflected light emitting diode (LED) pulses. Synchronous measurement offers best-in-class rejection of ambient light interference, both dc and ac. The module integrates a highly efficient photometric front end, two LEDs, and two photodiode (PD). All of these items are housed in a custom package that prevents light from going directly from the LED to the photodiode without first entering the subject. The front end of the application specific integrated circuit (ASIC) consists of a control block, a 14-bit analog-to-digital converter (ADC) with a 20-bit burst accumulator, and three flexible, independently configurable LED drivers. The control circuitry includes flexible LED signaling and synchronous detection. The analog front end (AFE) features best-in-class rejection of signal offset and corruption due to modulated interference commonly caused by ambient light. The data output and functional configuration occur over a 1.8 V I2C interface or a serial peripheral interface (SPI) port. APPLICATIONS Optical heart rate monitoring Reflective PPG measurement CNIBP measurement FUNCTIONAL BLOCK DIAGRAM VDD1 VDD2 PDC ADPD188GG PD1 EXT_IN1 CH1 BPF ±1 INTEGRATOR TIA_VREF VREF PD2 EXT_IN2 1µF CH2 PDC BPF ±1 INTEGRATOR TIA_VREF PDET1 PD3 CH3 BPF CS ±1 INTEGRATOR TIME SLOT A DATA TIA_VREF CH4 BPF VLED1 GREEN SDA SCL TIA_VREF LED1/DNC LED1 DRIVER DIGITAL INTERFACE AND CONTROL GPIO0 GPIO1 LED3 DRIVER LED3 LED2 TIME SLOT B DATA ±1 INTEGRATOR MOSI MISO 14-BIT ADC PD4 LED2 DRIVER LGND NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN WHEN USING INTERNAL LEDs. AGND DGND 16111-001 PDET2 SCLK Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2018–2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADPD188GG Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Connection Diagram ................................................... 22 Applications ...................................................................................... 1 Land Pattern ............................................................................... 22 General Description ......................................................................... 1 Recommended Start-Up Sequence .......................................... 23 Functional Block Diagram .............................................................. 1 Reading Data............................................................................... 23 Revision History ............................................................................... 2 Clocks and Timing Calibration ................................................ 24 Specifications .................................................................................... 3 Optional Timing Signals Available on GPIO0 and GPIO1 . 25 Analog Specifications................................................................... 5 LED Driver Pins and LED Supply Voltage............................. 26 Digital Specifications ................................................................... 6 LED Driver Operation ............................................................... 26 Timing Specifications .................................................................. 7 Determining the Average Current........................................... 27 Absolute Maximum Ratings ........................................................... 9 Determining CVLED ..................................................................... 27 Thermal Resistance ...................................................................... 9 Using External LEDs ................................................................. 28 Recommended Soldering Profile ............................................... 9 Calculating Current Consumption.......................................... 28 ESD Caution.................................................................................. 9 Mechanical Considerations for Covering the ADPD188GG ... 31 Pin Configuration and Function Descriptions .......................... 10 TIA ADC Mode .......................................................................... 31 Typical Performance Characteristics ........................................... 11 Pulse Connect Mode .................................................................. 33 Theory of Operation ...................................................................... 13 Introduction ................................................................................ 13 Synchronous ECG and PPG Measurement Using TIA ADC Mode ............................................................................................ 34 Optical Components .................................................................. 13 Float Mode .................................................................................. 35 Dual Time Slot Operation ......................................................... 14 Register Listing ............................................................................... 42 Time Slot Switch ......................................................................... 15 LED Control Registers ............................................................... 46 Adjustable Sampling Frequency............................................... 16 AFE Configuration Registers.................................................... 48 External Synchronization for Sampling .................................. 16 Float Mode Registers ................................................................. 52 State Machine Operation .......................................................... 16 System Registers ......................................................................... 55 Normal Mode Operation and Data Flow................................ 17 ADC Registers ............................................................................ 59 Communications Interface ........................................................... 19 Data Registers ............................................................................. 60 I2C Interface ................................................................................ 19 Outline Dimensions ....................................................................... 61 SPI Port ........................................................................................ 20 Ordering Guide .......................................................................... 61 Applications Information.............................................................. 22 REVISION HISTORY 4/2020—Rev. A to Rev. B Change to Applications Section ..................................................... 1 Changes to Table 4 and Figure 2 .................................................... 7 Change to Reset Column, Table 26.............................................. 42 Added Endnote 1, Table 27 ........................................................... 46 Changes to Table 32 ....................................................................... 55 10/2018—Rev. 0 to Rev. A Changes to Figure 24 and Figure 25 ............................................ 22 Changes to Calibrating the 32 kHz Clock Section..................... 25 Added Improving SNR Using Integrator Chopping Section and Figure 32; Renumbered Sequentially ........................................... 29 Added Table 18; Renumbered Sequentially ............................... 30 Changes to Table 26 ....................................................................... 42 Changes to Table 29 ....................................................................... 50 Changes to Table 30 ....................................................................... 51 Changes to Address 0x58 Description Column, Table 31........ 53 2/2018—Revision 0: Initial Version Rev. B | Page 2 of 61 Data Sheet ADPD188GG SPECIFICATIONS The voltage applied at the VDD1 and VDD2 pins (VDD) = 1.8 V, and TA = full operating temperature range, unless otherwise noted. Table 1. Parameter CURRENT CONSUMPTION Peak VDD Supply Current VDD Standby Current Average VDD Supply Current 1 Pulse 10 Pulses Average VLED Supply Current 1 Pulse 10 Pulses SATURATION ILLUMINANCE1 Direct Illumination DATA ACQUISITION ADC Resolution Per Sample Per Data Read LED PERIOD Sampling Frequency 4 Test Conditions/Comments See the Calculating Current Consumption section for the relevant equations Single-channel (Register 0x3C, Bits[8:3] = 0x38) Min Rev. B | Page 3 of 61 Max Unit 4.5 0.3 mA µA 53 41 76 107 95 184 µA µA µA µA µA µA 3.75 7.5 15 38 75 150 µA µA µA µA µA µA 58.8 29.4 14.7 7.4 kLux kLux kLux kLux 14 20 27 19 17 2000 Bits Bits Bits µs µs Hz 0.122 1600 Hz 0.122 1600 Hz 0.122 1000 Hz 100 Hz data rate; LED offset = 25 µs; LED pulse period (tLED_PERIOD) = 13 µs; LED peak current = 25 mA Time Slot A only Time Slot B only Both Time Slot A and Time Slot B Time Slot A only Time Slot B only Both Time Slot A and Time Slot B LED peak current = 25 mA 50 Hz data rate 100 Hz data rate 200 Hz data rate 50 Hz data rate 100 Hz data rate 200 Hz data rate Blackbody color temperature (T = 5500 K) 2, PDET1 and PDET2 multiplexed into a single channel (1.2 mm2active area) Transimpedance amplifier (TIA) gain = 25 kΩ TIA gain = 50 kΩ TIA gain = 100 kΩ TIA gain = 200 kΩ Single pulse 64 pulses to 255 pulses 64 pulses to 255 pulses; 128 samples averaged AFE width = 4 µs 3 AFE width = 3 µs Time Slot A or Time Slot B; normal mode; 1 pulse; SLOTA_LED_OFFSET = 23 µs; SLOTA_PERIOD = 19 µs Both time slots; normal mode; 1 pulse; SLOTA_LED_OFFSET = 23 µs; SLOTA_PERIOD = 19 µs Time Slot A or Time Slot B; normal mode; 8 pulses; SLOTA_LED_OFFSET = 23 µs; SLOTA_PERIOD = 19 µs Both time slots; normal mode; 8 pulses; SLOTA_LED_OFFSET = 23 µs; SLOTA_PERIOD = 19 µs Typ 13 11 0.122 ADPD188GG Parameter CATHODE PIN (PDC) VOLTAGE During All Sampling Periods During Time Slot A Sampling During Time Slot B Sampling During Sleep Periods Data Sheet Test Conditions/Comments Min Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 1 5 Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 0 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x05 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x1 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x2 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x3 6 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x05 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x1 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x2 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x36 Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 1 Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 0 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x0 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x1 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x2 Dominant Wavelength 7 LED1; Green LED Luminous Intensity Photodiode Responsivity Active Area Photodiode 1 Photodiode 2 POWER SUPPLY VOLTAGES VDD VLED1 8, 9 DC Power Supply Rejection Ratio (PSRR) TEMPERATURE RANGE Operating Adjustable via the Register 0x22 through Register 0x25 settings IF = 40 mA λ = 525 nm, IF = 40 mA at 25°C 12 1.7 4 At 75% full scale input signal −40 Unit V V V V V V V V V V V V V V V V 370 mA 3200 nm mcd 525 2800 Wavelength, λ = 525 nm The ADPD188GG does not require a specific power-up sequence Applied at the VDD1 and VDD2 pins Max 1.8 1.3 1.8 1.3 TIA_VREF + 0.25 0 1.8 1.3 TIA_VREF + 0.25 0 1.8 1.3 1.8 1.3 TIA_VREF + 0.25 0 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x3 LEDs LED Peak Current Setting Typ 0.25 A/W 0.4 0.8 mm2 mm2 1.8 4.5 24 1.9 5.0 V V dB +85 °C Saturation illuminance refers to the amount of ambient light that saturates the ADPD188GG signal. Actual results may vary by factors of up to 2× from typical specifications. As a point of reference, Air Mass 1.5 (AM1.5) sunlight (brightest sunlight) produces 100 kLux. 2 Blackbody color temperature (T = 5800 K) closely matches the light produced by solar radiation (sunlight). 3 Minimum LED period = (2 × AFE width) + 5 µs. 4 The maximum values in this specification are the internal ADC sampling rates in normal mode. The I2C read rates in some configurations may limit the output data rate. 5 This mode may induce additional noise and is not recommended unless necessary. The 1.8 V setting uses VDD, which contains greater amounts of differential voltage noise with respect to the anode voltage. A differential voltage between the anode and cathode injects a differential current across the capacitance of the photodiode of the magnitude of C × dV/dt. 6 This setting is not recommended for photodiodes because it causes a 1.3 V forward bias of the photodiode. 7 IF is the forward current of the diode. 8 Set VLEDx such that the maximum desired LED current is achievable with the turn on voltage of the LEDs that are wired to the LEDx/DNC pins. The LEDx/DNC pins are connected to the LEDx driver, which can be modeled as current sinks (see Figure 1). When an appropriate VLEDx is used, the voltage at the LEDx/DNC pins adjusts automatically to accommodate the LED turn on voltage and the LED current. 9 See Figure 9 for the current limitation at the minimum VLED supply voltage, VLED. 1 Rev. B | Page 4 of 61 Data Sheet ADPD188GG ANALOG SPECIFICATIONS VDD1 = VDD2 = 1.8 V, and TA = full operating temperature range, unless otherwise noted. Table 2. Parameter EXT_INx SERIES RESISTANCE (R_IN) 1 PULSED SIGNAL CONVERSIONS, 3 μs WIDE LED PULSE 2 ADC Resolution 3 ADC Saturation Level Ambient Signal Headroom on Pulsed Signal PULSED SIGNAL CONVERSIONS, 2 μs WIDE LED PULSE2 ADC Resolution3 ADC Saturation Level Ambient Signal Headroom on Pulsed Signal FULL SIGNAL CONVERSIONS 4 TIA Saturation Level Pulsed Signal and Ambient Level TIA Linear Range Test Conditions/Comments Measured from −3 µA to +3 µA 4 μs wide AFE integration; normal operation, Register 0x43 and Register 0x45 = 0xADA5 TIA feedback resistor 25 kΩ 50 kΩ 100 kΩ 200 kΩ TIA feedback resistor 25 kΩ 50 kΩ 100 kΩ 200 kΩ TIA feedback resistor Min Typ 6.5 Max Unit kΩ 3.27 1.64 0.82 0.41 nA/LSB nA/LSB nA/LSB nA/LSB 26.8 13.4 6.7 3.35 μA μA μA μA 25 kΩ 50 kΩ 100 kΩ 200 kΩ 3 μs wide AFE integration; normal operation, Register 0x43 and Register 0x45 = 0xADA5 TIA feedback resistor 25 kΩ 50 kΩ 100 kΩ 200 kΩ TIA feedback resistor 25 kΩ 50 kΩ 100 kΩ 200 kΩ TIA feedback resistor 23.6 11.8 5.9 2.95 μA μA μA μA 4.62 2.31 1.15 0.58 nA/LSB nA/LSB nA/LSB nA/LSB 37.84 18.92 9.46 4.73 μA μA μA μA 25 kΩ 50 kΩ 100 kΩ 200 kΩ 12.56 6.28 3.14 1.57 μA μA μA μA 50.4 25.2 12.6 6.3 μA μA μA μA 42.8 21.4 10.7 5.4 μA μA μA μA TIA feedback resistor 25 kΩ 50 kΩ 100 kΩ 200 kΩ TIA feedback resistor 25 kΩ 50 kΩ 100 kΩ 200 kΩ Rev. B | Page 5 of 61 ADPD188GG Data Sheet Parameter SYSTEM PERFORMANCE Total Output Noise Floor Test Conditions/Comments Min Normal mode; per pulse; per channel; no LED; photodiode capacitance (CPD) = 25 pF 25 kΩ; referred to ADC input 25 kΩ; referred to peak input signal for 2 µs LED pulse 25 kΩ; referred to peak input signal for 3 µs LED pulse 25 kΩ; saturation signal-to-noise ratio (SNR) per pulse per channel 5 50 kΩ; referred to ADC input 50 kΩ; referred to peak input signal for 2 µs LED pulse 50 kΩ; referred to peak input signal for 3 µs LED pulse 50 kΩ; saturation SNR per pulse per channel5 100 kΩ; referred to ADC input 100 kΩ; referred to peak input signal for 2 µs LED pulse 100 kΩ; referred to peak input signal for 3 µs LED pulse 100 kΩ; saturation SNR per pulse per channel5 200 kΩ; referred to ADC input 200 kΩ; referred to peak input signal for 2 µs LED pulse 200 kΩ; referred to peak input signal for 3 µs LED pulse 200 kΩ; saturation SNR per pulse per channel5 Typ Max Unit 1.0 4.6 3.3 78.3 LSB rms nA rms nA rms dB 1.1 2.5 1.8 77.4 1.2 1.4 0.98 76.7 1.4 0.81 0.57 75.3 LSB rms nA rms nA rms dB LSB rms nA rms nA rms dB LSB rms nA rms nA rms dB The R_IN value can be ignored for current source inputs or for PD inputs. This value is important for calculating correct voltages for voltage inputs through a resistor. This saturation level applies to the ADC only and, therefore, includes only the pulsed signal. Any nonpulsatile signal is removed prior to the ADC stage. 3 ADC resolution is listed per pulse. If using multiple pulses, divide by the number of pulses. 4 This saturation level applies to the full signal path and, therefore, includes both the ambient signal and the pulsed signal. 5 The noise term of the saturation SNR value refers to the receive noise only and does not include photon shot noise or any noise on the LED signal itself. 1 2 DIGITAL SPECIFICATIONS VDD1 = VDD2 = 1.7 V to 1.9 V, unless otherwise noted. Table 3. Parameter LOGIC INPUTS Input Voltage Level High High Low Input Current Level High Low Input Capacitance LOGIC OUTPUTS Output Voltage Level High Low Output Voltage Level Low Output Current Level Low Symbol Test Conditions/Comments Min VIH VIH VIL GPIOx, SCLK, MOSI, CS SCL, SDA 0.7 × VDDx 0.7 × VDDx IIH IIL CIN VOH VOL VOL1 IOL Typ −10 −10 Max Unit VDDx 3.6 0.3 × VDDx V +10 +10 µA µA pF 10 GPIOx, MISO 2 mA high level output current 2 mA low level output current SDA 2 mA low level output current SDA VOL1 = 0.6 V Rev. B | Page 6 of 61 VDDx − 0.5 6 V 0.5 V V 0.2 × VDDx V mA Data Sheet ADPD188GG TIMING SPECIFICATIONS I2C Timing Specifications Table 4. Parameter SCL Frequency Minimum Pulse Width High Low START CONDITION Hold Time Setup Time SDA SETUP TIME SDA HOLD TIME SCL AND SDA Rise Time Fall Time STOP CONDITION Setup Time Symbol Min Typ Max Unit 1 0.4 Mb/sec t1 t2 370 530 ns ns t3 t4 t5 t9 260 260 50 0 ns ns ns ns t6 t7 1000 300 t8 t3 260 t5 t9 ns ns ns t3 SDA t6 t1 t2 t7 t4 Figure 2. I2C Timing Diagram Rev. B | Page 7 of 61 t8 16111-002 SCL ADPD188GG Data Sheet SPI Timing Specifications Table 5. Parameter SCLK Frequency Minimum Pulse Width High Low CS Setup Time Symbol Test Conditions/Comments Min Typ fSCLK tSCLKPWH tSCLKPWL Max Unit 10 MHz 20 20 ns ns tCSS CS setup to SCLK rising edge 10 ns Hold Time tCSH CS hold from SCLK rising edge 10 ns Pulse Width High tCSPWH CS pulse width high 10 ns MOSI Setup Time Hold Time MISO OUTPUT DELAY tMOSIS tMOSIH tMISOD MOSI setup to SCLK rising edge MOSI hold from SCLK rising edge MISO valid output delay from SCLK falling edge ns ns 10 10 21 ns tCSH tCSS tCSPWH tSCLKPWL tSCLKPWH CS SCLK MOSI tMOSIH MISO tMISOD Figure 3. SPI Timing Diagram Rev. B | Page 8 of 61 16111-003 tMOSIS Data Sheet ADPD188GG ABSOLUTE MAXIMUM RATINGS RECOMMENDED SOLDERING PROFILE Table 6. 1 Figure 4 and Table 8 provide details about the recommended soldering profile. TL L TSMIN tS 3000 V 1250 V 100 V RAMP-DOWN t25°C TO PEAK TIME Figure 4. Recommended Soldering Profile 260 (+0/−5)°C