ADPD4101BCBZR7

Multimodal Sensor Front End ADPD4100/ADPD4101 Data Sheet FEATURES GENERAL DESCRIPTION Multimodal analog front end 8 input channels with multiple operation modes for various sensor measurements Dual-channel processing with simultaneous sampling 12 programmable time slots for synchronized sensor measurements Flexible input multiplexing to support differential and single-ended sensor measurements 8 LED drivers, 4 of which can be driven simultaneously Flexible sampling rate from 0.004 Hz to 9 kHz using internal oscillators On-chip digital filtering SNR of transmit and receive signal chain: 100 dB AC ambient light rejection: 60 dB up to 1 kHz 400 mA total LED peak drive current Total system power dissipation: 30 µW (combined LED and AFE power), continuous PPG measurement at 75 dB SNR, 25 Hz ODR, 100 nA/mA CTR SPI and I2C communications supported 512-byte FIFO size The ADPD4100/ADPD4101 operate as a complete multimodal sensor front end, stimulating up to eight light emitting diodes (LEDs) and measuring the return signal on up to eight separate current inputs. Twelve time slots are available, enabling 12 separate measurements per sampling period. The data output and functional configuration utilize an I2C interface on the ADPD4101 or a serial port interface (SPI) on the ADPD4100. The control circuitry includes flexible LED signaling and synchronous detection. The devices use a 1.8 V analog core and 1.8 V/3.3 V compatible digital input/output (I/O). The analog front end (AFE) rejects signal offsets and corruption from asynchronous modulated interference, typically from ambient light, eliminating the need for optical filters or externally controlled dc cancellation circuitry. Multiple operating modes are provided, enabling the ADPD4100/ADPD4101 to be a sensor hub for synchronous measurements of photodiodes, biopotential electrodes, resistance, capacitance, and temperature sensors. The multiple operation modes accommodate various sensor measurements, including, but not limited to, photoplethysmography (PPG), electrocardiography (ECG), electrodermal activity (EDA), impedance, capacitance, temperature, gas detection, smoke detection, and aerosol detection for various healthcare, industrial, and consumer applications. APPLICATIONS Wearable health and fitness monitors: heart rate monitors (HRMs), heart rate variability (HRV), stress, blood pressure estimation, SpO2, hydration, body composition Industrial monitoring: CO, CO2, smoke, and aerosol detection Home patient monitoring The ADPD4100/ADPD4101 are available in a 3.11 mm × 2.14 mm, 0.4 mm pitch, 33-ball WLCSP and 35-ball WLCSP. FUNCTIONAL BLOCK DIAGRAM ADPD4100/ADPD4101 LED LEVEL AND MUX CONTROL LED DRIVERS AGND DGND IOGND HIGH FREQUENCY AND LOW FREQUENCY OSCILLATORS LGND INTEGRATOR TIMING IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 VC1 VC2 AVDD DVDD1 DVDD2 IOVDD CH 1 SIGNAL CONDITIONING ADC DIGITAL PROCESSING, INTERFACE AND TIMING CONTROL, FIFO, PROGRAM AND DATA REGISTERS, COMMUNICATIONS TIA_VREF CH 2 SIGNAL CONDITIONING CS SCLK MOSI MISO SCL SDA GPIO0 GPIO1 GPIO2 GPIO3 VREF INTEGRATOR TIMING VC1 VOLTAGE VREF VC2 REFERENCES TIA_VREF NOTES VICM 1. CS, SCLK, MOSI, AND MISO PINS ARE ON THE ADPD4100. 2. SCL AND SDA PINS ARE ON THE ADPD4101. 3. TIA_VREF IS THE INTERNAL VOLTAGE REFERENCE SIGNAL FOR THE TRANSIMPEDANCE AMPLIFIER. 23297-001 LED4B LED3B LED2B LED1B LED4A LED3A LED2A LED1A Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADPD4100/ADPD4101 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Time Slot Operation .................................................................. 23 Applications ....................................................................................... 1 Execution Modes ........................................................................ 24 General Description ......................................................................... 1 Host Interface.............................................................................. 24 Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 28 Revision History ............................................................................... 2 Operating Mode Overview ....................................................... 28 Specifications..................................................................................... 3 Analog Integration Mode .......................................................... 28 Temperature and Power Specifications ..................................... 3 Digital Integration Mode........................................................... 40 Performance Specifications ......................................................... 4 TIA ADC Mode .......................................................................... 42 Digital Specifications ................................................................... 6 Protecting Against TIA Saturation in Normal Operation .... 42 Timing Specifications .................................................................. 6 ECG Measurement with the ADPD4100/ADPD4101 .......... 44 Absolute Maximum Ratings............................................................ 9 Register Map ................................................................................... 51 Thermal Resistance ...................................................................... 9 Register Details ............................................................................... 70 Electrostatic Discharge (ESD) Ratings ...................................... 9 Global Configuration Registers ................................................ 70 ESD Caution .................................................................................. 9 Interrupt Status and Control Registers .................................... 72 Pin Configurations and Function Descriptions ......................... 10 Threshold Setup and Control Registers .................................. 82 Typical Performance Characteristics ........................................... 13 Clock and Timestamp Setup and Control Registers.............. 84 Theory of Operation ...................................................................... 15 System Registers ......................................................................... 84 Introduction ................................................................................ 15 I/O Setup and Control Registers .............................................. 86 Analog Signal Path ..................................................................... 15 Time Slot Configuration Registers........................................... 89 LED Drivers ................................................................................ 16 AFE Timing Setup Registers ..................................................... 94 Determining CVLED...................................................................... 17 LED Control and Timing Registers ......................................... 96 Datapath, Decimation, Subsampling, and FIFO .................... 18 ADC Offset Registers................................................................. 97 Clocking ....................................................................................... 21 Output Data Registers ............................................................... 97 Time Stamp Operation .............................................................. 22 Outline Dimensions ..................................................................... 100 Low Frequency Oscillator Calibration .................................... 22 Ordering Guide ........................................................................ 101 High Frequency Oscillator Calibration ................................... 22 REVISION HISTORY 6/2020—Revision 0: Initial Version Rev. 0 | Page 2 of 101 Data Sheet ADPD4100/ADPD4101 SPECIFICATIONS TEMPERATURE AND POWER SPECIFICATIONS Table 1. Operating Conditions Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE Supply, VDD Input/Output Driver Supply, IOVDD Test Conditions/Comments Min Typ −40 −65 Applied at the AVDD, DVDD1, and DVDD2 pins Applied at the IOVDD pin 1.7 1.7 1.8 1.8 Max Unit +85 +150 °C °C 1.9 3.6 V V AVDD = DVDDx = IOVDD = 1.8 V, TA = 25°C, unless otherwise noted. Table 2. Current Consumption Parameter POWER SUPPLY (VDD) CURRENT VDD Supply Current1 Symbol Total System Power Dissipation Peak VDD Supply Current (1.8 V) 1-Channel Operation Standby Mode Current 1 IVDD_PEAK IVDD_STANDBY Test Conditions/Comments Min Typ Max Unit Signal-to-noise ratio (SNR) = 75 dB, 25 Hz output data rate (ODR), single time slot, 1 MHz low frequency oscillator frequency SNR = 75 dB, 25 Hz ODR, single time slot, 32 kHz low frequency oscillator frequency Combined LED and AFE power, continuous PPG measurement at 75 dB SNR, 25 Hz ODR, 100 nA/mA current transfer ratio (CTR), 1 MHz low frequency oscillator frequency Combined LED and AFE power, continuous PPG measurement at 75 dB SNR, 25 Hz ODR, 100 nA/mA CTR, 32 kHz low frequency oscillator frequency 10 µA 8 µA 30 μW 26 μW Peak VDD current during time slot sampling 3.8 0.20 mA µA VDD is the voltage applied at the AVDD and DVDDx pins. Rev. 0 | Page 3 of 101 ADPD4100/ADPD4101 Data Sheet PERFORMANCE SPECIFICATIONS AVDD = DVDDx = IOVDD = 1.8 V, TA = full operating temperature range, unless otherwise noted. Table 3. Parameter DATA ACQUISITION Datapath Width FIRST IN, FIRST OUT (FIFO) SIZE LED DRIVER LED Peak Current per Driver LED Peak Current, Total Driver Compliance Voltage LEDxx Pin Voltage1 Highest LED Peak Current per Driver2 LED PERIOD SAMPLING RATE4 OSCILLATOR DRIFT 32 kHz Oscillator 1 MHz Oscillator 32 MHz Oscillator Test Conditions/Comments Min LED pulse enabled Using multiple LED drivers simultaneously For any LED driver output at LED_CURRENTx_x = 0x7F 1.5 For any LED driver at LED_CURRENTx_x = 0x7F AFE width = 4 µs3 AFE width = 3 µs Single time slot, four data bytes to FIFO, 2 µs LED pulse 176 11 9 0.004 Percent variation from 25°C to 85°C Percent variation from +25°C to −40°C Percent variation from 25°C to 85°C Percent variation from +25°C to −40°C Percent Variation from 25°C to 85°C Percent Variation from +25°C to −40°C Typ 200 Max Unit 32 512 Bits Bytes 200 400 300 3.6 208 mA mA mV V mA µs µs Hz 9000 6 −8.5 3 −4 1 −1.5 % % % % % % LEDxx refers to LED1A, LED2A, LED3A, LED4A, LED1B, LED2B, LED3B, and LED4B. The maximum value in this specification is the maximum value at LED driver current setting = 0x7F on LED Driver LED1A, and the minimum value in this specification is the minimum value at LED driver current setting = 0x7F on LED Driver LED4B. Typically, the LED peak current is the highest on LED1A and the lowest on LED4B, while the rest of the drivers fall in between, and the LED peak current of the LEDxA drivers are higher than that of LEDxB drivers of the same number. For example, the LED peak current of LED3A is higher than that of LED3B. 3 Minimum LED period = (2 × AFE width) + 3 µs. 4 The maximum value in this specification is the internal ADC sampling rate using the internal 1 MHz state machine clock. The I2C and SPI read rates in some configurations may limit the ODR. 1 2 Table 4. Parameter TRANSIMPEDANCE AMPLIFIER (TIA) GAIN PULSED SIGNAL CONVERSIONS, 3 μs LED PULSE ADC Resolution1 ADC Saturation Level2 Test Conditions/Comments Min 12.5 Typ Max 200 Unit kΩ 4 μs integration width, continuous connect mode TIA feedback resistor 12.5 kΩ 25 kΩ 50 kΩ 100 kΩ 200 kΩ TIA feedback resistor 12.5 kΩ 25 kΩ 50 kΩ 100 kΩ 200 kΩ Rev. 0 | Page 4 of 101 6.2 3.1 1.5 0.77 0.38 nA/LSB nA/LSB nA/LSB nA/LSB nA/LSB 50 25 12.5 6.22 3.11 μA μA μA μA μA Data Sheet Parameter PULSED SIGNAL CONVERSIONS, 2 μs LED PULSE ADC Resolution1 ADC Saturation Level2 FULL SIGNAL CONVERSIONS TIA Linear Dynamic Range (per Channel) SYSTEM PERFORMANCE Referred to Input Noise Referred to Input Noise SNR AC Ambient Light Rejection DC Power Supply Rejection Ratio (PSRR) 1 2 ADPD4100/ADPD4101 Test Conditions/Comments 3 μs integration width, continuous connect mode TIA feedback resistor 12.5 kΩ 25 kΩ 50 kΩ 100 kΩ 200 kΩ TIA feedback resistor 12.5 kΩ 25 kΩ 50 kΩ 100 kΩ 200 kΩ Total input current, 1% compression point, TIA_VREF = 1.265 V 12.5 kΩ 25 kΩ 50 kΩ 100 kΩ 200 kΩ Continuous connect mode, single pulse, single channel, floating input, TIA_VREF = 1.265 V, 3 μs integration time 12.5 kΩ TIA gain 25 kΩ TIA gain 50 kΩ TIA gain 100 kΩ TIA gain 200 kΩ TIA gain Continuous connect mode, single pulse, single channel, 90% full-scale input signal, no ambient light, TIA_VREF = 1.265 V, VCx = TIA_VREF + 215 mV, 2 μs LED pulse, photodiode capacitance (CPD) = 70 pF, input resistor = 500 Ω 12.5 kΩ TIA gain 25 kΩ TIA gain 50 kΩ TIA gain 100 kΩ TIA gain 200 kΩ TIA gain 12.5 kΩ TIA gain, single pulse 25 kΩ TIA gain, single pulse 50 kΩ TIA gain, single pulse 100 kΩ TIA gain, single pulse 200 kΩ TIA gain, single pulse 100 kΩ TIA gain, 100 Hz ODR, 80 pulses, CPD = 70 pF, 0.5 Hz to 20 Hz bandwidth, transmit and receive signal chain DC to 1 kHz, linear range of TIA, TIA gain = 25 kΩ, 50 kΩ, 100 kΩ, 200 kΩ DC to 1 kHz, linear range of TIA, TIA gain = 12.5 kΩ At 75% full scale input ADC resolution is listed per pulse. If using multiple pulses, divide by the number of pulses. ADC saturation level applies to pulsed signal only, because ambient signal is rejected prior to ADC conversion. Rev. 0 | Page 5 of 101 Min Typ Max Unit 8.2 4.1 2.04 1.02 0.51 nA/LSB nA/LSB nA/LSB nA/LSB nA/LSB 67 33 16.7 8.37 4.19 μA μA μA μA μA 72 38 18.7 9.3 4.6 μA μA μA μA μA 8.2 4.1 2.2 1.2 0.61 nA rms nA rms nA rms nA rms nA rms 10.3 5.3 2.7 1.5 0.97 76 76 75 74 72 100 nA rms nA rms nA rms nA rms nA rms dB dB dB dB dB dB 60 dB 55 50 dB dB ADPD4100/ADPD4101 Data Sheet DIGITAL SPECIFICATIONS IOVDD = 1.7 V to 3.6 V, unless otherwise noted. Table 5. Digital Specifications Parameter LOGIC INPUTS Input Voltage Level SCL, SDA High Low GPIOx, MISO, MOSI, SCLK, CS High Low Input Current Level High Low Input Capacitance LOGIC OUTPUTS Output Voltage Level GPIOx, MISO High Low SDA Low Output Current Level Low Symbol Test Conditions/Comments Min Typ Max Unit VIH VIL 0.7 × IOVDD −0.3 3.6 +0.3 × IOVDD V V VIH VIL 0.7 × IOVDD −0.3 IOVDD + 0.3 +0.3 × IOVDD V V 10 µA µA pF All logic inputs IIH IIL CIN −10 2 VOH VOL 2 mA high level output current 2 mA low level output current VOL1 3 mA low level output current SDA VOL1 = 0.4 V IOL IOVDD – 0.5 0.5 V V 0.4 V 20 mA TIMING SPECIFICATIONS Table 6. I2C Timing Specifications for the ADPD4101 Parameter TIMING REQUIREMENTS I2C Port1 SCL Frequency Minimum Pulse Width High Low Start Condition Hold Time Setup Time SDA Hold Time2 Setup Time SCL and SDA Rise Time Fall Time Stop Condition Setup Time 1 2 Symbol Test Conditions/Comments See Figure 2 Min Typ Max Unit 1 Mbps t1 t2 260 500 ns ns t3 t4 260 260 ns ns t5 t6 0 50 ns t7 t8 120 120 260 t9 Guaranteed by design. Both timing requirement and switching characteristic. Rev. 0 | Page 6 of 101 ns ns ns Data Sheet ADPD4100/ADPD4101 Table 7. SPI Timing Specifications for the ADPD4100 Parameter TIMING REQUIREMENTS SPI Port SCLK Frequency Minimum Pulse Width High Low CS Setup Time Symbol Test Conditions/Comments Min Typ fSCLK tSCLKPWH tSCLKPWL Max Unit 24 MHz 15 15 ns ns tCSS CS setup to SCLK rising edge 11 ns Hold Time tCSH CS hold from SCLK rising edge 5 ns Pulse Width High tCSPWH CS pulse width high 15 ns tMOSIS tMOSIH MOSI setup to SCLK rising edge MOSI hold from SCLK rising edge 5 5 ns ns tMISOD MISO valid output delay from SCLK falling edge Register 0x00B4 = 0x0050 (default) Register 0x00B4 = 0x005F (maximum slew rate, maximum drive strength for SPI) MOSI Setup Time Hold Time SWITCHING CHARACTERISTICS MISO Output Delay 21.5 14.0 Table 8. Timing Specifications for Provision of External Low Frequency Oscillator Parameter FREQUENCY 1 MHz Low Frequency Oscillator 32 kHz Low Frequency Oscillator DUTY CYCLE 1 MHz Low Frequency Oscillator 32 kHz Low Frequency Oscillator Min Rev. 0 | Page 7 of 101 Typ Max Unit 500 10 2000 100 kHz kHz 10 10 90 90 % % ns ns ADPD4100/ADPD4101 Data Sheet Timing Diagrams t6 t3 t3 SDA t5 t1 t7 t8 t2 t4 23297-002 SCL t9 Figure 2. I2C Timing Diagram for the ADPD4101 tCSH tCSS tCSPWH tSCLKPWL tSCLKPWH CS SCLK MOSI tMOSIH MISO tMISOD Figure 3. SPI Timing Diagram for the ADPD4100 Rev. 0 | Page 8 of 101 23297-003 tMOSIS Data Sheet ADPD4100/ADPD4101 ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE (ESD) RATINGS Table 9. Parameter AVDD to AGND DVDD1, DVDD2 to DGND IOVDD to DGND GPIOx, MOSI, MISO, SCLK, CS, SCL, SDA to DGND LEDxx to LGND Junction Temperature Rating −0.3 V to +2.2 V −0.3 V to +2.2 V −0.3 V to +3.9 V −0.3 V to +3.9 V The following ESD information is provided for handling of ESD sensitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001 and charged device model (CDM) per ANSI/ESDA/JEDEC JS-002. Machine model (MM) per ANSI/ESD STM5.2. MM voltage values are for characterization only. −0.3 V to +3.9 V 150°C ESD Ratings for ADPD4100/ADPD4101 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 11. ADPD4100/ADPD4101, 35-Ball and 33-Ball WLCSP ESD Model HBM CDM MM ESD CAUTION THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Close attention to PCB thermal design is required. θJA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. θJC is the junction to case thermal resistance. Table 10. Thermal Resistance Package Type1 CB-35-2 CB-33-1 1 θJA 41.89 42.15 θJC 0.98 0.98 Withstand Threshold (V) 2000 1250 100 Unit °C/W °C/W The thermal resistance values are defined as per the JESD51-12 standard. Rev. 0 | Page 9 of 101 Class 2 C3 Not applicable ADPD4100/ADPD4101 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADPD4100 5 4 3 2 1 A LED1A LED2A LED3A LED4A LED4B B LGND LED1B LED2B LED3B GPIO2 C GPIO0 GPIO1 GPIO3 SCLK MISO D AVDD DVDD2 IOVDD CS MOSI E VREF AGND IOGND DGND DVDD1 F VC1 IN1 IN3 IN5 IN7 G VC2 IN2 IN4 IN6 IN8 23297-005 BOTTOM VIEW, BALL SIDE UP (Not to Scale) Figure 4. ADPD4100 Pin Configuration Table 12. ADPD4100 Pin Function Descriptions Pin No. A5 A4 A3 A2 A1 B5 B4 B3 B2 B1 C5 C4 C3 C2 C1 D5 D4 D3 D2 D1 E5 E4 E3 E2 E1 F5 F4 F3 Mnemonic LED1A LED2A LED3A LED4A LED4B LGND LED1B LED2B LED3B GPIO2 GPIO0 GPIO1 GPIO3 SCLK MISO AVDD DVDD2 IOVDD CS MOSI VREF AGND IOGND DGND DVDD1 VC1 IN1 IN3 Type1 AO AO AO AO AO S AO AO AO DIO DIO DIO DIO DI DO S S S DI DI REF S S S S AO AI AI Description LED Driver 1A Current Sink. If not in use, leave this pin floating. LED Driver 2A Current Sink. If not in use, leave this pin floating. LED Driver 3A Current Sink. If not in use, leave this pin floating. LED Driver 4A Current Sink. If not in use, leave this pin floating. LED Driver 4B Current Sink. If not in use, leave this pin floating. LED Driver Ground. LED Driver 1B Current Sink. If not in use, leave this pin floating. LED Driver 2B Current Sink. If not in use, leave this pin floating. LED Driver 3B Current Sink. If not in use, leave this pin floating. General-Purpose I/O 2. This pin is used for interrupts and various clocking options. General-Purpose I/O 0. This pin is used for interrupts and various clocking options. General-Purpose I/O 1. This pin is used for interrupts and various clocking options. General-Purpose I/O 3. This pin is used for interrupts and various clocking options. SPI Clock Input. SPI Master Input/Slave Output. 1.8 V Analog Supply. 1.8 V Digital Supply. 1.8 V/3.3 V I/O Driver Supply. SPI Chip Select Input. SPI Master Output/Slave Input. Internally Generated ADC Voltage Reference. Buffer this pin with a 1 µF capacitor to AGND. Analog Ground. I/O Driver Ground. Digital Ground. 1.8 V Digital Supply. Output Voltage Source 1 for Photodiode Common Cathode Bias or Other Sensor Stimulus. Current Input 1. If not in use, leave this pin floating. Current Input 3. If not in use, leave this pin floating. Rev. 0 | Page 10 of 101 Data Sheet Pin No. F2 F1 G5 G4 G3 G2 G1 1 Mnemonic IN5 IN7 VC2 IN2 IN4 IN6 IN8 ADPD4100/ADPD4101 Type1 AI AI AO AI AI AI AI Description Current Input 5. If not in use, leave this pin floating. Current Input 7. If not in use, leave this pin floating. Output Voltage Source 2 for Photodiode Common Cathode Bias or Other Sensor Stimulus. Current Input 2. If not in use, leave this pin floating. Current Input 4. If not in use, leave this pin floating. Current Input 6. If not in use, leave this pin floating. Current Input 8. If not in use, leave this pin floating. AO means analog output, S means supply, DIO means digital input/output, DI means digital input, DO means digital output, REF means voltage reference, and AI means analog input. ADPD4101 5 4 3 2 1 A LED1A LED2A LED3A LED4A LED4B B LGND LED1B LED2B LED3B GPIO2 C GPIO0 GPIO1 GPIO3 SDA SCL D AVDD DVDD2 IOVDD E VREF AGND IOGND DGND DVDD1 F VC1 IN1 IN3 IN5 IN7 G VC2 IN2 IN4 IN6 IN8 23297-006 BOTTOM VIEW, BALL SIDE UP (Not to Scale) Figure 5. ADPD4101 Pin Configuration Table 13. ADPD4101 Pin Function Descriptions Pin No. A5 A4 A3 A2 A1 B5 B4 B3 B2 B1 C5 C4 C3 C2 C1 D5 D4 D3 E5 E4 Mnemonic LED1A LED2A LED3A LED4A LED4B LGND LED1B LED2B LED3B GPIO2 GPIO0 GPIO1 GPIO3 SDA SCL AVDD DVDD2 IOVDD VREF AGND Type1 AO AO AO AO AO S AO AO AO DIO DIO DIO DIO DIO DI S S S REF S Description LED Driver 1A Current Sink. If not in use, leave this pin floating. LED Driver 2A Current Sink. If not in use, leave this pin floating. LED Driver 3A Current Sink. If not in use, leave this pin floating. LED Driver 4A Current Sink. If not in use, leave this pin floating. LED Driver 4B Current Sink. If not in use, leave this pin floating. LED Driver Ground. LED Driver 1B Current Sink. If not in use, leave this pin floating. LED Driver 2B Current Sink. If not in use, leave this pin floating. LED Driver 3B Current Sink. If not in use, leave this pin floating. General-Purpose I/O 2. This pin is used for interrupts and various clocking options. General-Purpose I/O 0. This pin is used for interrupts and various clocking options. General-Purpose I/O 1. This pin is used for interrupts and various clocking options. General-Purpose I/O 3. This pin is used for interrupts and various clocking options. I2C Data Input/Output. I2C Clock Input. 1.8 V Analog Supply. 1.8 V Digital Supply. 1.8 V/3.3 V I/O Driver Supply. Internally Generated ADC Voltage Reference. Buffer this pin with a 1 µF capacitor to AGND. Analog Ground. Rev. 0 | Page 11 of 101 ADPD4100/ADPD4101 Pin No. E3 E2 E1 F5 F4 F3 F2 F1 G5 G4 G3 G2 G1 1 Mnemonic IOGND DGND DVDD1 VC1 IN1 IN3 IN5 IN7 VC2 IN2 IN4 IN6 IN8 Type1 S S S AO AI AI AI AI AO AI AI AI AI Data Sheet Description I/O Driver Ground. Digital Ground. 1.8 V Digital Supply. Output Voltage Source 1 for Photodiode Common Cathode Bias or Other Sensor Stimulus. Current Input 1. If not in use, leave this pin floating. Current Input 3. If not in use, leave this pin floating. Current Input 5. If not in use, leave this pin floating. Current Input 7. If not in use, leave this pin floating. Output Voltage Source 2 for Photodiode Common Cathode Bias or Other Sensor Stimulus. Current Input 2. If not in use, leave this pin floating. Current Input 4. If not in use, leave this pin floating. Current Input 6. If not in use, leave this pin floating. Current Input 8. If not in use, leave this pin floating. AO means analog output, S means supply, DIO means digital input/output, DI means digital input, DO means digital output, REF means voltage reference, and AI means analog input. Rev. 0 | Page 12 of 101 Data Sheet ADPD4100/ADPD4101 TYPICAL PERFORMANCE CHARACTERISTICS 0.20 9 0.18 8 0.12 0.10 0.08 0.06 0.04 6 5 4 3 2 1 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 LED1A DRIVER COMPLIANCE (V) 0 23297-007 0 12.5kΩ GAIN 25kΩ GAIN 50kΩ GAIN 100kΩ GAIN 200kΩ GAIN 7 0 100 200 300 400 500 600 700 800 900 1000 INPUT CAPACITANCE (pF) Figure 6. LED Driver Current vs. LED1A Driver Compliance at LED_CURRENT1_x = 0x7 (10 mA), 0x19 (40 mA), 0x4A (120 mA), and 0x7F (200 mA) 23297-010 LED DRIVER CURRENT (A) 0.14 INPUT REFERRED NOISE (nA rms) LED_CURRENT1_x 0x7 = 10mA LED_CURRENT1_x 0x19 = 40mA LED_CURRENT1_x 0x4A = 120mA LED_CURRENT1_x 0x7F = 200mA 0.16 Figure 9. Input Referred Noise vs. Input Capacitance, Integrator Input Resistor = 400 kΩ 0 96 94 –10 92 90 SNR (dB) AC PSRR (dB) –20 –30 88 86 84 –40 82 80 200kΩ GAIN 100kΩ GAIN 50kΩ GAIN 78 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) 76 23297-058 Figure 7. AC PSRR vs. Frequency 100 Figure 10. SNR vs. Number of LED Pulses in Continuous Connect Mode, CPD = 70 pF, Integrator Input Resistor = 400 kΩ, 90% Full Scale 10000 TOTAL POWER CONSUMPTION (µW) 8 INPUT REFERRED NOISE (nA rms) 10 NUMBER OF LED PULSES 9 7 6 5 4 3 2 0 20 40 60 80 100 120 TIA GAIN (kΩ) 140 160 180 200 Figure 8. Input Referred Noise vs. TIA Gain, CPD = 70 pF, Integrator Input Resistor = 400 kΩ 1000 100 10 76 23297-009 1 0 1 200kΩ GAIN 100kΩ GAIN 50kΩ GAIN 78 80 82 84 86 SNR (dB) 88 90 92 94 96 23297-012 –60 23297-011 –50 Figure 11. Total Power Consumption vs SNR in Continuous Connect Mode Including LED Power, CPD = 70 pF, Integrator Input Resistor = 400 kΩ, ODR = 25 Hz, CTR = 150 nA/mA, LED Supply Voltage = 4 V, 90% of Full Scale Rev. 0 | Page 13 of 101 Data Sheet 0 160 –10 140 –20 120 NUMBER OF DEVICES AMBIENT LIGHT REJECTION (dB) ADPD4100/ADPD4101 –30 –40 –50 100 80 60 40 –60 20 100 1k 10k 100k FREQUENCY (Hz) 0 FREQUENCY (MHz) Figure 14. 1 MHz Clock Frequency Distribution, Untrimmed Figure 12. Ambient Light Rejection vs. Frequency 90 200 80 180 160 50 40 30 140 120 100 80 60 20 0 0 FREQUENCY (kHz) 23297-014 40 10 30.0 30.5 31.0 31.5 32.0 32.5 33.0 33.5 34.0 34.5 35.0 35.5 36.0 36.5 37.0 37.5 38.0 38.5 39.0 39.5 40.0 MORE 20 Figure 13. 32 kHz Clock Frequency Distribution, Untrimmed FREQUENCY (MHz) Figure 15. 32 MHz Clock Frequency Distribution, Untrimmed Rev. 0 | Page 14 of 101 23297-016 60 BIN 28.0 28.5 29.0 29.5 30.0 30.5 31.0 31.5 32.0 32.5 33.0 33.5 34.0 34.5 35.0 35.5 36.0 36.5 37.0 37.5 38.0 MORE NUMBER OF DEVICES 70 NUMBER OF DEVICES 23297-015 10 23297-013 1 0.80 0.82 0.84 0.86 0.88 0.90 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 1.12 1.14 1.16 1.18 1.20 MORE –70 Data Sheet ADPD4100/ADPD4101 THEORY OF OPERATION RINT IN4 RF IN5 RF 6.3pF 6.3pF ADC RINT IN6 TIA IN7 BPF IN8 23297-017 RINT RF 6.3pF Figure 16. Analog Signal Path Block Diagram Analog Input Multiplexer VICM TIA_VREF The ADPD4100/ADPD4101 support eight analog input pins. Each input can be used as a single-ended input or as part of a differential pair. Figure 17 shows a single representation of the input switch matrix, which allows programmable connection to the two AFE channels. Each pair of inputs has an exact duplicate of this multiplexer: IN1 and IN2, IN3 and IN4, IN5 and IN6, and IN7 and IN8. The connections are programmable per time slot. IN1 VICM TIA IN2 ANALOG SIGNAL PATH The ADPD4100/ADPD4101 analog signal path consists of eight current inputs that can be configured as single-ended or differential pairs into one of two independent channels. The two channels can be sampled simultaneously for applications Rev. 0 | Page 15 of 103 TIA_VREF TIA THERE ARE FOUR COPIES OF SWITCH MATRIX. ONE COPY FOR EACH INPUT PAIR. TIA_VREF *ALL BIAS CONNECTIONS SHOWN ARE ONLY AVAILABLE DURING SLEEP AND PRECONDITIONING PERIODS. THE SWITCHES TO THESE BIAS LEVEL ARE OPEN DURING TIME SLOTS WITH THE RESPECTIVE INPUTS SELECTED. Figure 17. Analog Input Multiplexer 23297-018 The LED driver is a current sink and is independent from the LED supply voltage and the LED type. The inputs can be connected to any sensor that provides currents up to 200 μA. The ADPD4100/ADPD4101 can also interface with voltage output sensors with a series resistor placed between the sensor output and the ADPD4100/ADPD4101 inputs to convert the voltage to a current. The ADPD4100/ADPD4101 produce a high SNR for relatively low LED power while greatly reducing the effect of ambient light on the measured signal. BPF TIA IN3 VC2 When making optical measurements, the ADPD4100/ADPD4101 provide 60 dB of ac ambient light rejection using a synchronous modulation scheme with pulses as short as 1 μs combined with a BPF. Ambient light rejection is automatic without the need of external control loops, dc current subtraction, or digital algorithms. IN2 TIA_VREF The core circuitry provides stimulus to the sensors connected to the inputs of the device and measures the response, storing the results in discrete data locations. The eight inputs can drive two simultaneous input channels, either in a single-ended or differential configuration. Data is read directly by a register or through a FIFO method. This highly integrated system includes an analog signal processing block, digital signal processing block, an I2C communication interface on the ADPD4101 or an SPI port on the ADPD4100, programmable pulsed LED current sources, and pulsed voltage sources for sensors that require voltage excitation. RINT VC1* The AFE consists of a TIA, band-pass filter (BPF), integrator, and analog-to-digital converter (ADC). The digital block provides multiple operating modes, programmable timing, four general-purpose input/output (GPIO) pins, block averaging, and a selectable second- through fourth-order cascaded integrator comb (CIC) filter. Eight independent LED drivers are provided that can each drive up to 200 mA. Four LED drivers can be enabled in any time slot and can be programmed from 1.5 mA to 200 mA monotonically, with a 7-bit register setting. The LED drivers enabled in any time slot can provide a total combined maximum of 400 mA of LED current. 6.3pF RF IN1 VC2 The ADPD4100/ADPD4101 operate as a complete multimodal sensor front end, stimulating up to eight LEDs and measuring the return signal on up to eight separate current inputs. Twelve time slots are available, enabling 12 separate measurements per sampling period. The analog inputs can be driven single-ended or in differential pairs. The eight analog inputs are multiplexed into a single channel or two independent channels, enabling simultaneous sampling of two sensors. that require instantaneous sampling of two sensors. Each channel contains a TIA with programmable gain, a BPF with a high-pass corner at 100 kHz and a low-pass cutoff frequency of 390 kHz, and an integrator capable of integrating ±7.5 pC per sample. Each channel is time multiplexed into a 14-bit ADC. In Figure 16, RF is the TIA feedback resistor, and RINT is the series resistor to the input of the integrator. VC1* INTRODUCTION ADPD4100/ADPD4101 Data Sheet Preconditioning of the sensor connected to the input is provided to set the operating point at the input just prior to sampling. There are several different options for preconditioning determined by the PRECON_x bits. The PRECON_x bits are provided for each time slot to specify the precondition for enabled inputs or input pairs during the corresponding time slot. Preconditioning options include: float the input(s), VC1, VC2, input common-mode voltage (VICM), TIA_VREF, TIA input, and short the input pair. The preconditioning time at the start of each time slot is programmable using the PRE_WIDTH_x bits. The default preconditioning period is 8 µs. The block diagram in Figure 17 shows all the bias levels that can be switched into the input connections during sleep and preconditioning. These connections are not available during the sampling phase of a time slot in which the input is selected. Second AFE Channel The second AFE channel is disabled by default. When disabled, the three amplifiers (TIA, BPF, and integrator) are automatically powered down, and no ADC cycles occur for the second channel. Digital integration and impulse response mode do not use the second channel. The second AFE channel can be enabled with the CH2_EN_x bits on a per time slot basis. When the second channel is enabled, ADC conversions and the datapath bits of the second channel operate. When data is being written to the FIFO, the Channel 2 data is written after the Channel 1 data. Channel 2 TIA gain, integrator resistor, and buffer gain (when in digital integrate or TIA ADC mode) are set separately from Channel 1. VLED2 CVLED LEDxA CVLED LEDxB LED_CURRENTx_x 23297-019 LED_DRIVESIDEx_x NOTES CVLED IS THE BYPASS CAPACITOR. Figure 18. Block Diagram of LED Driver Output Pair The LED driver output pins (LED1A, LED1B, LED2A, LED2B, LED3A, LED3B, LED4A, and LED4B) have a maximum allowable pin voltage of 3.6 V. Any voltage exposure over this rating affects the reliability of the device operation and, in certain circumstances, causes the device to cease proper operation. The voltage of the LED driver output pins must not be confused with the supply voltages for the LED themselves. VLEDx is the voltage applied to the anode of the external LED whereas the LED output driver pin is connected to the cathode of the external LED. The compliance voltage is the amount of headroom voltage at the LED driver pin, measured with respect to ground, required to maintain the programmed LED current level and is a function of the current required. Figure 6 shows the typical compliance voltages required at various LED current settings for LED driver LED1A, and Figure 19 shows the typical compliance voltages for all the LED drivers at the maximum LED current setting. Due to internal layout of the LED driver circuitry, some drivers output more or less current than others at any given setting. Typically, the LED1A and LED1B drivers are ~3% higher than the LED4A and LED4B drivers, respectively, with the 2× and 3× drivers falling somewhere in between. Also, the LEDxA drivers are ~3% higher than the LEDxB driver of the same number. 0.20 0.18 0.16 0.14 0.12 0.10 0.08 LED4B LED4A LED3B LED3A LED2B LED2A LED1B LED1A 0.06 0.04 LED DRIVERS 0.02 The ADPD4100/ADPD4101 have four LED drivers, each of which is brought out to two LED driver outputs providing a total of eight LED output drivers. The device can drive up to four LEDs simultaneously, one from each driver pair. The LED output driver is a current sink. Figure 18 shows an example of a single LED driver output pair. 0 0 0.2 0.2 0.3 0.4 0.5 0.6 0.7 LED DRIVER VOLTAGE (V) 0.8 0.9 1.0 23297-020 The sleep conditions are used for any inputs that are not enabled. Sleep conditions are determined by the INP_SLEEP_12, INP_SLEEP_34, INP_SLEEP_56, and INP_SLEEP_78 bits, which specify the state for the input pairs during sleep and when the inputs are not active. Inputs are only considered active during the precondition and pulse regions for time slots where they are enabled. VLED1 LED DRIVER CURRENT (A) The PAIR12, PAIR34, PAIR56, and PAIR78 bits select whether the matching input pair is used as two single-ended inputs or as a differential pair. This selection is valid for all active time slots. The INP12_x, INP34_x, INP56_x, and INP78_x bits specify whether the input pair is enabled during the corresponding time slot and, if enabled, which input is connected to which AFE channel. Figure 19. LED Driver Current vs. LED Driver Voltage for LED Drivers (LEDxA, LEDxB) for LED_CURRENTx_x = 0x7F Rev. 0 | Page 16 of 101 Data Sheet ADPD4100/ADPD4101 Either side of each LED driver output pair, but not both, can be driven in any of the 12 available time slots. Up to four LED driver outputs can be enabled in any time slot using the LED_ DRIVESIDE1_x, LED_DRIVESIDE2_x, LED_DRIVESIDE3_x, and LED_DRIVESIDE4_x bits. The current is set on a per driver, per time slot basis using the LED_CURRENT1_x, LED_ CURRENT2_x, LED_CURRENT3_x, and LED_CURRENT4_x bits. Each driver can be programmed from 1.5 mA to 200 mA with a monotonic 7-bit setting, as shown in Figure 20. Each setting from 1 to 127 increases the LED drive current by ~1.5 mA. Setting LED_CURRENTx_x = 0 disables that particular driver. Although each driver can be programmed to 200 mA and up to four LED drivers can be enabled in any time slot, there is a limitation of a total of 400 mA of combined LED driver current that can be provided in any time slot. It is up to the user to program the LED drivers such that this 400 mA limit is not exceeded. If the 400 mA limit is exceeded by the user settings, priority is given, in the following order, to LED1x, LED2x, LED3x, and LED4x. For example, if the user settings have LED1A set to 150 mA, LED2B set to 150 mA, and LED3A set to 150 mA in a single time slot, LED1A and LED2B both provide 150 mA. However, LED3A is limited to 100 mA to maintain the 400 mA total LED drive current limit for the device. LED Driver Protection from LED Driver Pin Overvoltage In typical designs, no external components are needed on the LED driver. However, in some cases where the LED driver pin voltage has the possibility to be pulled above 3.6 V, an external NPN bipolar junction transistor (BJT) type transistor can be connected to the LED driver pin, as shown in Figure 21. This additional transistor serves as a protection of the LED driver pin from exceeding the maximum allowable LEDxx pin voltage of 3.6 V. Protecting the LED driver pins from overvoltage is required when (VLEDx − LED turn on voltage) > 3.6 V, or when the voltage source has a shunt resistance of less than 10 MΩ and the supply voltage is above 3.6 V. For example, VLEDx of 6 V can be used without pulling the LED driver pins up past 3.6 V for low leakage LEDs such as some green and blue LEDs. Typically, when VLEDx < 6 V, the protection transistor is not necessary. VLED1 CVLED VBASE LEDxx NOTES 1. CVLED IS THE BYPASS CAPACITOR. 2. VBASE IS THE BASE VOLTAGE. 150 23297-059 200 Figure 21. LED Driver Overvoltage Protection Circuit The NPN BJT selection must follow these guidelines: 100 • 50 0 0 16 32 48 64 80 96 112 LED_CURRENTx_x SETTING 23297-021 LED DRIVER CURRENT (mA) 250 Figure 20. LED Driver Current vs. LED_CURRENTx_x Setting LED Driver Protection from High Inductance • • • If the total inductance in the path between the LED and the ADPD4100/ADPD4101 LED driver pin (LEDxA or LEDxB) and in the path between the LED and the LED supply voltage (VLEDx) is significant due to the use of long wires and multiple connectors, connect a reverse biased protection diode to a suitable high supply voltage such as VLEDx at the LED driver pin used. That is, connect a reverse biased protection diode between the LED driver pin used and VLEDx. The current capacity must match the maximum LED driver current on the LED. The maximum LED driver current is 200 mA for one LED driver and 400 mA for multiple LED drivers connected to the same LED. The voltage rating of the transistor must exceed the supply being used on the load. The base emitter voltage must be ≤0.9 V at the maximum LED driver current on the LED. Lower collector emitter voltages at the maximum LED driver current on the LED provide more operating room for the load being driven. DETERMINING CVLED To determine the bypass capacitor (CVLED) value, determine the maximum forward-biased voltage, VFB_LED_MAX, of the LED in operation. The maximum LED current, ILED_MAX, converts to VFB_LED_MAX as shown in Figure 22. In this example, 125 mA of current through two green LEDs in parallel yields VFB_LED_MAX = 3.5 V. Any series resistance in the LED path must also be included in this voltage. When designing the LED path, keep in mind that small resistances can add up to large voltage drops due to the LED peak current being large. In addition, these resistances can be unnecessary constraints on the VLEDx supply. Rev. 0 | Page 17 of 101 ADPD4100/ADPD4101 Data Sheet voltage is the voltage of the anode of the LED such that the compliance of the LED driver and the forward-biased voltage of the LED operating at the maximum current is satisfied. At a 125 mA drive current, the compliance voltage of the driver is ~0.4 V. For a typical ADPD4100/ADPD4101 example, assume that the lowest value for the VLEDx supply is 4.5 V and that the peak current is 125 mA for two 528 nm LEDs in parallel. The minimum value for CVLED is then equal to 1 µF. TWO 528nm LEDs ONE 850nm LED 4.0 3.5 3.0 2.5 CVLED = (3 × 10−6 × 0.125)/(4.5 – (3.5 + 0.4)) = 0.625 nF (2) 2.0 1.5 1.0 0 50 100 150 200 LED DRIVER CURRENT SETTING (mA) 250 23297-022 LED FORWARD-BIASED VOLTAGE DROP (V) 4.5 Figure 22. Example of the Average LED Forward-Biased Voltage Drop as a Function of the LED Driver Current Setting To correctly size the CVLED capacitor, do not deplete it during the pulse of the LED to the point where the voltage on the capacitor is less than the forward bias on the LED. Calculate the minimum value for CVLED as follows: CVLED = (tLED_PW × ILED_MAX)/(VLED_MIN − (VFB_LED_MAX + VCOMP)) (1) where: tLED_PW is the LED pulse width. ILED_MAX is the maximum forward-biased current on the LED used in operating the devices. VLED_MIN is the lowest voltage from the VLEDx supply with no load. VFB_LED_MAX is the maximum forward-biased voltage required on the LED to achieve ILED_MAX. VCOMP is the compliance voltage of the LED driver at the programmed LED drive level. The numerator of Equation 1 sets up the total discharge amount in coulombs from the bypass capacitor to satisfy a single programmed LED pulse of the maximum current. The denominator represents the difference between the lowest voltage from the VLEDx supply and the LED required voltage. The LED required As shown in Equation 2, as the minimum supply voltage drops close to the maximum anode voltage, the demands on CVLED become more stringent, forcing the capacitor value higher. It is important to insert the correct values into Equation 2. For example, using an average value for VLED_MIN instead of the worst case value for VLED_MIN can cause a serious design deficiency, resulting in a CVLED value that is too small, causing insufficient optical power in the application. Additionally, multiple pulses can cause further droop on the VLEDx supply if the CVLED capacitor is not fully recharged between pulses. Therefore, adding a sufficient margin on CVLED is strongly recommended. Add additional margin to CVLED to account for multiple pulses and derating of the capacitor value over voltage, bias, temperature, and other factors over the life of the component. DATAPATH, DECIMATION, SUBSAMPLING, AND FIFO ADC samples are gathered for each pulse in each time slot and combine to create a running positive and negative sum for each time slot. These sums are each kept as a 32-bit unsigned value register and saturate if the values overflow 32 bits. Each ADC sample is added to either the positive or negative sum based on the SUBTRACT_x bits for the current pulse in standard sampling mode, or in the lit or dark acquisition regions for digital integration mode. Figure 23 shows the datapath structure. Rev. 0 | Page 18 of 101 Data Sheet ADPD4100/ADPD4101 ADC (14 BITS UNSIGNED) CHx_ADC_ADJUST_x + – 15 BITS SIGNED ACCORDING TO SUBTRACT OR DIGITAL INTEGRATION REGION POSITIVE ACCUMULATION 32 BITS SIGNED NEGATIVE ACCUMULATION 32 BITS SIGNED ADD 2048 IF ZERO_ADJUST_x = 1 CLIP CLIP LIT 32 BITS UNSIGNED PER CHANNEL AND PER TIME SLOT DARK 32 BITS UNSIGNED DECIMATION + – CLIP SIGNAL 32 BITS UNSIGNED CLIP PER CHANNEL AND PER TIME SLOT DARK 32 BITS UNSIGNED DATA REGISTERS Figure 23. Datapath Block Diagram Rev. 0 | Page 19 of 101 23297-023 SIGNAL 32 BITS UNSIGNED ADPD4100/ADPD4101 Data Sheet At the end of the pulse operations in each time slot, the lit and dark values are clipped to positive numbers and are sent to the decimation unit. At the end of time slot operations, if the decimated value is ready, the signal value is calculated by subtracting the dark value from the lit value. Then, the data registers that are ready are updated, and the selected values are written to the FIFO. The data interrupt for that time slot is also set at this time for each updated time slot. Decimation The DECIMATE_FACTOR_x bits determine the number of time slot values used to create a 32-bit final sample value at a rate of Sample Rate = (1/TIMESLOT_PERIOD_x)/(DECIMATE_FACTOR_x + 1) If DECIMATE_FACTOR_x is 0, the output sample rate equals the time slot rate. The final value is the sum of the decimated samples. There is no divide by (DECIMATE_FACTOR_x + 1) operation performed on the decimated data, but final data values can be bit shifted to the right before being written to the FIFO, creating a direct average when the number of samples is a power of 2. DECIMATE_TYPE_x selects the method of decimation used. A setting of 0 selects a simple block sum with other settings allowing higher order CIC filters up to fourth order. If using higher order CIC filters for the signal data, the dark data still uses the simple block sum at the same decimation rate. Each time slot maintains its own block sum or CIC filter state. The entire decimation path uses a 32-bit datapath. When using the CIC filter, the number of bits required for the result is dependent on the number of pulses, the decimation rate and the order of the CIC filter according to the following equation: NBITS = 14 + log2(Number of Pulses) + (log2(Decimation Rate))(CIC Order) It is up to the user to ensure that there is no undesired overflow. Final data results can be read from data registers or a 512-byte data FIFO. Data written to the FIFO is configurable to allow the different data registers, formats, and data sizes as required. Each time slot can use its own decimation rate. Data from each time slot is written to the FIFO at its respective ODR. Subsampling The ADPD4100/ADPD4101 support a subsampling mode that allows selected time slots to run at slower sampling rates than the programmed sampling rate. For example, in a multiparameter application where most of the measurements need to be taken at a sampling rate of 300 Hz but one of the measurements only needs to be taken at 25 Hz, the subsampling mode can be used on the time slot that only needs to operate at 25 Hz. To enable subsampling mode for a specific time slot, set the SUBSAMPLE_x bit to 1 and set the DECIMATE_FACTOR_x bits to the desired subsampling rate. The subsampled time slot then samples only once every (DECIMATE_FACTOR_x + 1) cycles, instead of operating every time slot sequence. If other time slots are decimating at the same rate, the subsampled cycles occur at the same time the decimated data is presented to the FIFO. For example, if Time Slot A is operating at 300 Hz but decimating to 25 Hz, and Time Slot B is set to subsample by 12, both time slots write the FIFO during the same time slot sequence and at the same rate. More complicated patterns can be made if the decimate and subsample rates for the enabled time slots are different. The user must manage the varying packet sizes by reading the data in multiples of the repeating packet size. For example, if Time Slot A is not decimating or subsampling, Time Slot B is subsampling every second cycle, and Time Slot C is subsampling every fourth cycle, the data pattern written to the FIFO is A, AB, A, ABC, and so on, as the repeating packet. Decimation and subsampling have the same effect on the output data rate. The only difference is that the decimated time slots operate every input cycle but produce data at the slower rate using the on-chip decimating filter. The subsampling time slots only occur at the slower rate. Status bytes are written to the FIFO every wake-up period, regardless of which time slots execute. Using the same example as the different decimate and subsample rates scenario, but with a status byte enabled, the pattern is AS, ABS, AS, ABCS, and so on, where S is a status byte. FIFO Data is written to the FIFO at the end of each sampling period. This packet can include 0, 8-, 16-, 24-, or 32-bit data for each of the dark data, lit data, and signal data values. The bit alignment of the data written to the FIFO is selectable with a shift of 0 bits to 31 bits, with saturation provided. Lower bits are ignored. The DARK_SHIFT_x, LIT_SHIFT_x, and SIGNAL_SHIFT_x bits select the number of bits to shift the output data to the right before writing to the FIFO. The DARK_SIZE_x, LIT_SIZE_x, and SIGNAL_SIZE_x bits select the number of bytes of each field to be written from 0 bytes to 4 bytes. When set to 0, no data is written for that data type. If there are any nonzero bits at more significant bit positions than those selected, the data written to the FIFO is saturated. If both channels are enabled, all selected Channel 1 data values are written to the FIFO first, followed by the Channel 2 data. For example, in modes that utilize dark data, the eight upper bits of the dark data can be stored with 24 appropriately selected bits from the signal data for each time slot to allow detection of whether the ambient light is becoming large, while limiting the size of the amount of data transferred. Data is written to the FIFO at the end of the sampling period only if there is enough FIFO space left to write data for each active time slot. For example, if one active time slot is running at an ODR of 100 Hz and a second time slot is decimating by 4 or subsampling at 1/4th the rate of the first time slot for an ODR of 25 Hz, data is only written to the FIFO at the end of the sampling period if there is enough room for both active time slots to write data, regardless of whether the time slot that is decimating or subsampling is supposed to write data during Rev. 0 | Page 20 of 101 Data Sheet ADPD4100/ADPD4101 that sampling period. It is up to the user to manage the data appropriately at the microprocessor end when using time slots with different decimation and/or subsampling rates. The FIFO is never written with partial packets of data. If there is not enough room for all of the data that is to be written to the FIFO for all enabled time slots and any selected status bytes, no data is written from any of the time slots during that period and the INT_FIFO_OFLOW status bit is set. The order of samples written to the FIFO (if selected) is dark data followed by signal data. The byte order for multibyte words is shown in Table 14. Table 14. Byte Order for FIFO Writes Size 8 16 24 32 Byte Order (After Shift) [7:0] [15:8], [7:0] [15:8], [7:0], [23:16] [15:8], [7:0], [31:24], [23:16] The FIFO size is 512 bytes. When the FIFO is empty, a read operation returns 0xFF, and the INT_FIFO_UFLOW status bit is set. In addition to the FIFO, the signal and dark 32-bit registers can be directly read. These registers are effectively two-stage registers where there is an internal data register that updates with every sample, and a latched output data register that is accessed by the host. The data interrupts can be used to align the access of these registers to just after the registers are written. If using the interrupt timing is troublesome, use the HOLD_REGS_x bits to prevent an update of the output registers during an access not aligned to the interrupt. Setting the HOLD_REGS_x bits blocks the update of the latched output data register and ensures that the dark and signal values read by the host are from the same sample point. If additional samples occur while the HOLD_REGS_x bit is set, the samples are written to the internal data register but not latched into the output data register that is accessed by the host. Setting the HOLD_REGS_x bit to 0 reenables the pass through of new data. After all time slots have completed, the optional status bytes are written to the FIFO. See the Optional Status Bytes section for more information. CLOCKING Low Frequency Oscillator A low frequency oscillator clocks the low speed state machine, which sets the time base used to control the sample timing, wake-up states, and overall operation. There are three options for low frequency oscillator generation. The first option is an internal, selectable 32 kHz or 1 MHz oscillator. The second option is for the host to provide a low frequency oscillator externally. Finally, the low frequency oscillator can be generated by a divide by 32 or divide by 1000 of an external high frequency clock source at 32 MHz. When powering up the device, it is expected that the low frequency oscillator be enabled and left running continuously. To operate with the on-chip low frequency oscillator, use the following writes. Set the LFOSC_SEL bit to 0 to select the 32 kHz clock or 1 if the 1 MHz clock is desired. Then, set either the OSC_1M_EN or OSC_32K_EN bit to 1 to turn on the desired internal oscillator. The internal 32 kHz clock frequency is set using the 6-bit OSC_32K_ADJUST bits. The internal 1 MHz clock frequency is set using the 10-bit OSC_1M_FREQ_ ADJ bits. If higher timing precision is required than can be provided by the on-chip low frequency oscillator, the low frequency oscillator can be driven directly from an external source provided on a GPIOx input. To enable an external low frequency clock, use the following writes. Enable one of the GPIOx inputs using the GPIO_PIN_CFGx bits. Next, use the ALT_CLK_GPIO bits to choose the enabled GPIOx input to be used for the external low frequency oscillator. Set the ALT_CLOCKS bits to 0x1 to select an external low frequency oscillator. Finally, use the LFOSC_SEL bit to match whether a 32 kHz or 1 MHz clock is being provided. In a third method, an external 32 MHz clock is used for both the high frequency clock and to be divided down to generate the low frequency clock. To use this method, follow the previous instructions for an external low frequency clock but set the ALT_CLOCKS bits to 0x3, and use the LFOSC_SEL bit to determine if a divide by 32 or 1000 is used to generate the low frequency clock so that either a 32 kHz or 1 MHz clock is generated from the external 32 MHz clock. High Frequency Oscillator A 32 MHz high frequency oscillator is generated internally or can be provided externally. This high frequency clock clocks the high speed state machine, which controls the AFE operations during the time slots, such as LED timing and integration times. The high frequency oscillator can be internally generated by setting the ALT_CLOCKS bits to 0x0 or 0x1. When selected, the internal 32 MHz oscillator is enabled automatically by the low speed state machine during the appropriate wake-up time or during the 32 MHz oscillator calibration routine. The high frequency oscillator can also be driven from an external source. To provide an external 32 MHz high frequency oscillator, enable one of the GPIO inputs using the GPIO_PIN_CFGx bits. Then, use the ALT_CLK_GPIO bits to choose the enabled GPIOx input for the external high frequency oscillator. Finally, write 0x2 or 0x3 to the ALT_CLOCKS bits to select an external high frequency oscillator. Writing 0x2 provides only the high frequency oscillator from the external source, whereas writing 0x3 generates both the low frequency oscillator and high frequency oscillator from the external 32 MHz source. When using an external 32 MHz oscillator, it must be kept running continuously for proper device operation. Rev. 0 | Page 21 of 101 ADPD4100/ADPD4101 Data Sheet TIME STAMP OPERATION The time stamp feature is useful for calibration of the low frequency oscillator as well as providing the host with timing information during time slot operation. Timestamping is supported by the use of any GPIO as a time stamp request input, the CAPTURE_TIMESTAMP bit to enable capture of the time stamp trigger, a time counter running in the low frequency oscillator domain, and two output registers. The output bits include TIMESTAMP_COUNT_x, which holds the number of low frequency oscillator cycles between time stamp triggers, and TIMESTAMP_SLOT_DELTA, which holds the number of low frequency oscillator cycles remaining to the next time slot start. The setup for using the time stamp operation is as follows: 1. 2. 3. 4. Set CLK_CAL_ENA = 1 to enable the oscillator calibration circuitry. Configure a GPIO to support the time stamp input using the appropriate GPIO_PIN_CFGx bits. Select the matching GPIOx to provide the time stamp using the TIMESTAMP_ GPIO bits. Configure the ADPD4100/ADPD4101 for operation and enable the low frequency oscillator. If the TIMESTAMP_SLOT_DELTA function is desired, start the time slot operation by placing the device in go mode using the OP_MODE bit (see Table 15). For low frequency oscillator calibration, it is only required that the low frequency oscillator be enabled. The device does not have to be in go mode for low frequency oscillator calibration. Use the following procedure to capture the time stamp: 1. 2. 3. 4. 5. Set the CAPTURE_TIMESTAMP bit to 1 to enable the capture of the time stamp on the next rising edge of the selected GPIOx input. The host provides the initial time stamp trigger on the selected GPIOx at an appropriate time. The CAPTURE_TIMESTAMP bit is cleared when the time stamp signal is captured unless the TIMESTAMP_ ALWAYS_EN bit is set, in which case, the capture of the time stamp is always enabled. Reenable the capture if necessary. The host provides a subsequent time stamp trigger on the selected GPIO at an appropriate time. The number of low frequency oscillator cycles that occurred between time stamp triggers can be read from the TIMESTAMP_COUNT_x bits. The host must continue to handle the FIFO and/or data register data normally during time stamp processing. If using a dedicated pin for a time stamp that does not have transitions other than the time stamp, set the TIMESTAMP_ ALWAYS_EN bit to avoid automatic clearing of the CAPTURE_ TIMESTAMP bit. This setting removes the need to enable the time stamp capture each time. The time stamp can calibrate the low frequency oscillator as described in the Low Frequency Oscillator Calibration section. The host can also use TIMESTAMP_SLOT_DELTA to determine when the next time slot occurs. TIMESTAMP_SLOT_DELTA can determine the arrival time of the samples currently in the FIFO. TIMESTAMP_SLOT_DELTA does not account for the decimation factor. The time stamp trigger is edge sensitive and can be set to either trigger on the rising edge (default) or falling edge using TIMESTAMP_INV. LOW FREQUENCY OSCILLATOR CALIBRATION The time stamp circuitry can calibrate either the 32 kHz or 1 MHz low frequency oscillator circuit by adjusting the frequency to match the timing of the time stamp triggers. Simply compare the TIMESTAMP_COUNT_x value in low frequency oscillator cycles to the actual time stamp trigger period and adjust the OSC_32K_ADJUST or OSC_1M_FREQ_ ADJ value accordingly. HIGH FREQUENCY OSCILLATOR CALIBRATION The high frequency oscillator is calibrated by comparing multiples of its cycles with multiple cycles of the low frequency oscillator, which is calibrated to the system time. Calibration of the low frequency oscillator precedes calibration of the high frequency oscillator. The method for calibrating the high frequency oscillator is as follows: 1. 2. 3. 4. 5. 6. 7. 8. Set CLK_CAL_ENA = 1 to enable the oscillator calibration circuitry. Write 1 to the OSC_32M_CAL_START bit. The ADPD4100/ADPD4101 automatically power up the high frequency oscillator. The device automatically waits for the high frequency oscillator to be stable. An internal counter automatically counts the number of 32 MHz high frequency oscillations that occur during 128 cycles of the 1 MHz low frequency oscillator or 4 cycles of the 32 kHz low frequency oscillator, depending on which low frequency oscillator is enabled based on the setting of the LFOSC_SEL bit. The OSC_32M_CAL_COUNT bits are updated with the final count. The 32 MHz oscillator automatically powers down following calibration unless time slots are active. The device resets the OSC_32M_CAL_START bit indicating the count has been updated. The OSC_32M_FREQ_ADJ bits adjust the frequency of the 32 MHz oscillator to the desired frequency. When using an external low frequency oscillator, the 32 MHz oscillator calibration is performed with respect to the externally provided low frequency oscillator. Note that when the calibrations of the low frequency and high frequency oscillators are complete, set CLK_CAL_ENA = 0 to disable the clocking of the oscillator calibration circuitry to Rev. 0 | Page 22 of 101 Data Sheet ADPD4100/ADPD4101 Offset = 64 × (Number of 1 MHz Low Frequency Oscillator Cycles) × TIMESLOT_OFFSET_x reduce the power consumption. CLK_CAL_ENA defaults to 0 so that the calibration circuitry is disabled by default. TIME SLOT OPERATION If using the 32 kHz low frequency oscillator, Offset = 2 × (Number of 32 kHz Low Frequency Oscillator Cycles) × TIMESLOT_OFFSET_x Operation of the ADPD4100/ADPD4101 is controlled by an internal configurable controller that generates all the timing needed to generate sampling regions and sleep periods. Measurements of multiple sensors and control of synchronous stimulus sources are handled by multiple time slots. The device provides up to 12 time slots for multisensor applications. The enabled time slots are repeated at the sampling rate, which is configured by the 23-bit TIMESLOT_PERIOD_x bits in the TS_FREQ register. The following formula determines the sampling rate: For example, if TIMESLOT_OFFSET_C is set to 0x040 and the 1 MHz low frequency oscillator is used, the offset from the start of Time Slot A to the start of Time Slot C is Offset = (64 × 1 µs × 64) = 4.096 ms The sampling rate is controlled by the low frequency oscillator. The low frequency oscillator is driven by one of three sources as described in the Clocking section. Each time slot allows the creation of one or more LED and/or modulation pulses, and the acquisition of the photodiode or other sensor current based on that stimulus. The operating parameters for each time slot are highly configurable. Figure 24 shows the basic time slot operation sequence. Each time slot is repeated at the sampling rate, followed by an ultra low power sleep period. By default, subsequent time slots are initiated immediately following the end of the previous time slot. In addition, there is an option to add an offset to the start of the subsequent time slots using the TIMESLOT_OFFSET_x bits. Figure 25 shows the TIMESLOT_ OFFSET_B bits being used to offset the start of Time Slot B. In this case, each time slot still operates at the sampling rate, but there is a sleep period between Time Slot A and Time Slot B. The wake period shown in Figure 24 and Figure 25 is used to power up and stabilize the analog circuitry before data acquisition begins. If the TIMESLOT_OFFSET_B bits are set to 0, the time slot starts as soon as the previous time slot finishes. The time slot offset is always applied to the Time Slot A start time. For example, TIMESLOT_OFFSET_D is an offset added to the beginning of Time Slot A, not Time Slot C, which immediately precedes Time Slot D. The amount of offset applied is dependent on the low frequency oscillator used. If using the 1 MHz low frequency oscillator, WAKE TIME SLOT A TIME SLOT B If TIMESLOT_OFFSET_x is set too short to allow the previous time slot to finish, the time slot occurs immediately after the previous time slot. Time slots always occur in A through L order. Using External Synchronization for Sampling An external signal driven to a configured GPIO pin can be used to wake the device from sleep instead of the TIMESLOT_PERIOD_x counter, which allows external control of the sample rate and time. This mode of operation is enabled using the EXT_SYNC_EN bit and uses the GPIOx pin selected by the EXT_SYNC_GPIO bits. If using this feature, be sure to enable the selected GPIOx pin as an input using the appropriate GPIO_PIN_CFGx bits. When operating with external synchronization and set in go mode, the device enters sleep first and waits for the next external synchronization signal before waking up. This external synchronization signal is then synchronized to the low frequency oscillator and then starts the wake-up sequence. If an additional external synchronization is provided prior to completing time slot operations, it is ignored. TIME SLOT L SLEEP WAKE TIME SLOT A TIMESLOT_PERIOD_x/ LOW FREQUENCY OSCILLATOR(s) Figure 24. Basic Time Slot Operation Sequence SLEEP WAKE TIME SLOT A SLEEP WAKE TIME SLOT B SLEEP TIME SLOT_OFFSET_B TIMESLOT_PERIOD_x/ LOW FREQUENCY OSCILLATOR(s) Figure 25. Time Slot Operation with Offset Using TIMESLOT_OFFSET_B Rev. 0 | Page 23 of 101 WAKE TIME SLOT A 23297-025 SLEEP If the sampling period is set too short to allow the enabled time slots to complete, a full cycle of enabled time slot samples are skipped, effectively reducing the overall sample rate. For example, if the sampling rate is set to 100 Hz (10 ms period) and the total amount of time required to complete all enabled time slots is 11 ms, the next cycle of time slots does not begin until t = 20 ms, effectively reducing the sampling rate to 50 Hz. 23297-024 Sampling Rate = Low Frequency Oscillator Frequency (Hz) ÷ TIMESLOT_PERIOD_x ADPD4100/ADPD4101 Data Sheet EXECUTION MODES Level Interrupts A state machine in the low frequency oscillator clock domain controls sleep times, wake-up cycles, and the start of time slot operations. The low frequency oscillator serves as the time base for all time slot operations, controls the sample rates, and clocks the low frequency state machine. This state machine controls all operations and is controlled by the OP_MODE bit. Two level interrupt status bits, INT_LEV0_x and INT_LEV1_x, provide an interrupt when the dark data or signal data values cross above or below a programmed threshold level. Table 15. OP_MODE Bit Setting Descriptions OP_MODE Setting 0 Mode Standby 1 Go Description All operations stopped. Time slot actions reset. Low power standby state. Transitioning to this state from standby mode starts time slot operation. At power-up and following any subsequent reset operations, the ADPD4100/ADPD4101 are in standby mode. The user can write 0 to the OP_MODE bit to immediately stop operations and return to standby mode. Register writes that affect operating modes cannot occur during go mode. The user must enter standby mode before changing the control registers. Standby mode resets the digital portion of the ADC, all of the pulse generators, and the state machine. When OP_MODE is set to 1, the device immediately starts the first wake-up sequence and time slot operations unless using an external synchronization trigger. If using an external synchronization trigger, the device enters the sleep state before the first wake-up and time slot regions begin. HOST INTERFACE The ADPD4100/ADPD4101 provide two methods of communication with the host, a SPI port and I2C interface. The device also provides numerous FIFO, data register, error, and threshold status bits, each of which can be provided by an interrupt function from a GPIO, read from status registers, or appended as optional status bytes at the end of a FIFO packet. Interrupt Status Bits Data Register Interrupts The data interrupt status bits, INT_DATA_x for each time slot, are set every time the data registers for that time slot are updated. The state of the HOLD_REGS_x bit has no effect on the interrupt logic. FIFO Threshold Interrupt The FIFO threshold interrupt status bit, INT_FIFO_TH, is set when the number of bytes in the FIFO exceeds the value stored in the FIFO_TH register. The INT_FIFO_TH bit is cleared automatically when a FIFO read reduces the number of bytes below the value in the FIFO_TH register, which allows the user to set an appropriate data size for their host needs. Two comparison circuits are available per time slot. The INT_LEV0_x or INT_LEV1_x status bits are set when the data register update meets the criteria set by the associated THRESH0_TYPE_x, THRESH0_DIR_x, THRESH0_CHAN_x settings, or by the associated THRESH1_TYPE_x, THRESH1_DIR_x, and THRESH1_CHAN_x settings. The Level 0 interrupt operates as follows. The user sets an 8-bit threshold value in the THRESH0_VALUE_x bits for the corresponding time slot. This value is then shifted to the left by anywhere from 0 bits to 24 bits, specified by the setting of the THRESH0_SHIFT_x bits. A comparison is then made between the shifted threshold value and the register chosen by the THRESH0_TYPE_x bits and the THRESH0_CHAN_x bit. The INT_LEV0_x status bit is set if the selected data register meets the criteria set in the THRESH0_DIR_x bits. The Level 1 interrupt operates in the same fashion. TIA Ceiling Detection Interrupts When the TIA ceiling detection is enabled, the TIA ceiling detection information is latched onto the INT_TCLN1_x bits in Register 0x0004 for Channel 1 and the INT_TCLN2_x bits in Register 0x0005 for Channel 2 separately for each time slot. Therefore, the TIA ceiling detection information can be read for all enabled channels in all enabled time slots separately. The latched status bits remain set until they are cleared when the TIA is driven into the region above the threshold, and the associated status bits turn to 1. Note that these status bits remain set until they are cleared. These status bits can be driven to Interrupt X or Interrupt Y by setting the relevant registers in Table 31, or they can be monitored by optional status bytes. Clearing Interrupt Status Bits All status bits are set regardless of whether the status bit is routed to one of the interrupt outputs, Interrupt X or Interrupt Y. The status bits are independent of the interrupt enable bits. The status bits are always set by the corresponding event. The interrupt bits stay set until they are either manually or automatically cleared. The user can manually clear a given interrupt by writing a 1 to the matching interrupt status bit. In addition, the data interrupt status bits can be configured to clear automatically. When the INT_ACLEAR_DATA_x or INT_ACLEAR_FIFO bit is set, the appropriate interrupt status bit is automatically cleared when any matching data register or FIFO register is read. Automatic clearing of the interrupt status bits removes the need to manually clear these interrupts. Rev. 0 | Page 24 of 101 Data Sheet ADPD4100/ADPD4101 Optional Status Bytes There is an option to append each data packet with status bits. This option is useful for hosts that cannot spare an interrupt channel to service. The status bytes can each be individually selected in the FIFO_STATUS_BYTES register. Each bit in the FIFO_ STATUS_BYTES register enables a status byte that is appended to the data packet in the FIFO. If any bit in the FIFO_STATUS_ BYTES register is set to 1, the byte that is appended to the data packet contains the status bits, as shown in Table 16. Table 16 shows the order, enable bit, and contents of each status byte. The 4-bit sequence number cycles from 0 to 15 and is incremented with a wraparound every time the time slot sequence completes. This sequence number can also be made available bitwise on the GPIOx pins. Interrupt Outputs, Interrupt X and Interrupt Y The ADPD4100/ADPD4101 support two separate interrupt outputs, Interrupt X and Interrupt Y. Each interrupt has the option to be driven to any of the four GPIOx pins. The two different interrupt outputs can be generated for a host processor if desired. For example, the FIFO threshold interrupt, INT_FIFO_TH, can be routed to Interrupt X and used to drive the direct memory access (DMA) channel of the host, while the INT_FIFO_OFLOW and INT_FIFO_UFLOW interrupts can be routed to Interrupt Y and used to drive an additional host interrupt pin. Another example case includes routing the data interrupt from a single time slot to Interrupt X and the FIFO threshold interrupt to Interrupt Y. The host receives one interrupt when the interrupt of that particular channel occurs and the host can then read that register directly. Interrupt Y, in this case, is handled by the host with DMA or with an interrupt. Each of the different interrupt status bits can be routed to Interrupt X or Interrupt Y, or both. For each interrupt, there is an associated Interrupt X and Interrupt Y enable bit. See Table 31 for a full list of available interrupts that can be brought out on Interrupt X and Interrupt Y. The logic for the Interrupt X and Interrupt Y function is a logic AND of the status bit with its matching enable bit. All enabled status bits are then logically OR’ed to create the interrupt function. The enable bits do not affect the status bits. General-Purpose I/Os The ADPD4100/ADPD4101 provide four general-purpose I/O pins: GPIO0, GPIO1, GPIO2, and GPIO3. These GPIOs can be used as previously described in the Interrupt Outputs, Interrupt X and Interrupt Y section for interrupt outputs or for providing external clock signals to the device. The GPIOs can also be used for many different control signals, as synchronization controls to external devices, as well as test signals that are useful during system debugging. All of the available signals that can be brought out on a GPIOx pin are listed in Table 35. IOVDD Supply Voltage Consideration The ADPD4100/ADPD4101 can operate with IOVDD as low as 1.7 V and as high as 3.6 V. LOW_IOVDD_EN in Register 0x00B4 is set to 0x1 for IOVDD lower than 3 V. 0x1 is the default value for this bit because the typical IOVDD value is 1.8 V. If 3 V or higher is supplied for IOVDD, the LOW_IOVDD_EN bit must be set to 0x0 for proper operation. Table 16. FIFO Status Byte Order and Contents Contents1 Byte Order 0 1 2 3 4 5 6 7 8 Enable Bit ENA_STAT_SUM ENA_STAT_D1 ENA_STAT_D2 ENA_STAT_L0 ENA_STAT_L1 ENA_STAT_LX ENA_STAT_TC12 ENA_STAT_TC22 ENA_STAT_TCX2 Bit 7 0 DATA_H 0 LEV0_H LEV1_H LEV1_L TCLN1_H TCLN2_H TCLN2_L Bit 6 0 DATA_G 0 LEV0_G LEV1_G LEV1_K TCLN1_G TCLN2_G TCLN2_K Bit 5 Any LEV1_x DATA_F 0 LEV0_F LEV1_F LEV1_J TCLN1_F TCLN2_F TCLN2_J Bit 4 Any LEV0_x DATA_E 0 LEV0_E LEV1_E LEV1_I TCLN1_E TCLN2_E TCLN2_I Bit 3 DATA_D DATA_L LEV0_D LEV1_D LEV0_L TCLN1_D TCLN2_D TCLN1_L Bit 2 Bit 1 4-bit sequence DATA_C DATA_B DATA_K DATA_J LEV0_C LEV0_B LEV1_C LEV1_B LEV0_K LEV0_J TCLN1_C TCLN1_B TCLN2_C TCLN2_B TCLN1_K TCLN1_J Bit 0 DATA_A DATA_I LEV0_A LEV1_A LEV0_I TCLN1_A TCLN2_A TCLN1_I DATA_x refers to the data register interrupts for the corresponding time slot. LEV0_x and LEV1_x refer to Level 0 and Level 1 time slot interrupts, respectively, for Time Slot A through Time Slot L. 2 These status bytes are associated with TIA ceiling detection. See the Protecting Against TIA Saturation with TIA Ceiling Detection section for more information. 1 Rev. 0 | Page 25 of 101 ADPD4100/ADPD4101 Data Sheet SPI and I2C Interface starting with the MSB. In addition, multiple registers can be read if additional 16-bit data is shifted out prior to deassertion of the CS signal. The ADPD4100 contains a SPI port, and the ADPD4101 contains an I2C interface. The SPI and I2C interfaces operate synchronously with their respective input clocks and require no internal clocks to operate. It is recommended that reading from the FIFO is performed byte wise. There is no requirement to read multiples of 16 bits. The ADPD4100/ADPD4101 have an internal power-on reset circuit that sets the device into a known idle state during the initial power-up. After the power-on reset is released, approximately 2 μs to 6 μs after the DVDDx supply is active, the device can be read and written through the SPI or I2C interface. I2C Operations The ADPD4101 supports fast-mode plus (see the I2C specification from NXP for more information). The I2C operations require addressing the device as well as choosing the register that is being read or written. An I2C register write is shown in Figure 28 and Figure 29. The SDA pin is bidirectional and open drain, where different bit times are driven in a predetermined way by the master or the slave. The ADPD4101 acts as a slave on the I2C bus. Start and stop bit operations are shown as S and P in Figure 28 and Figure 29. The I2C port supports both 7-bit and 15-bit addresses. If accessing Address 0x007F or lower, a 7-bit address can be used. If the first address bit after the slave address acknowledge (ACK) is a 0, a 7-bit address is used, as shown in the short read and write operations (see Figure 28 to Figure 31). If the first bit after a slave address acknowledge is 1, a 15-bit address is used as shown in the long read and write operations (see Figure 32 and Figure 33). The registers are accessed using addresses within a 15-bit address space. Each address references a 15-bit register with one address reserved for the FIFO read accesses. For both the I2C and SPI interfaces, reads and writes auto-increment to the next register if additional words are accessed as part of the same access sequence. This automatic address increment occurs for all addresses except the FIFO address, one less than the FIFO address and the last used address, which is 0x277. Reads from the FIFO address continue to access the next byte from the FIFO. SPI Operations The SPI single register write operation is shown in Figure 26. The first two bytes contain the 15-bit register address and specifies that a write is requested. The remaining two bytes are the 16 data bits to write to the register. The register write occurs only when all 16 bits are shifted in prior to deassertion of the CS signal. Figure 28 shows the first half of the short register write operation. The first byte indicates that the ADPD4101 is being addressed with a write operation. The ADPD4101 indicates that it has been addressed by driving an acknowledge. The next byte operation is a write of the address of the register to be written. The MSB is the L/S bit (long/short). When this bit is low, a 7-bit address follows. If the L/S bit is high, a 15-bit address follows. The ADPD4101 sends an acknowledge following the register address. In addition, multiple registers can be written if additional 16-bit data is shifted in before deassertion of the CS signal. The register address automatically increments to the next register after each 16 bits of data. The SPI single register read operation is shown in Figure 27. The first two bytes contain the 15-bit register address and specifies that a read is requested. Register bits are shifted out D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 23297-026 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 23297-027 SCLK CS MOSI A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Wr D15 D14 D13 Figure 26. SPI Write Operation SCLK CS MOSI A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Rd MISO D15 D14 D13 Figure 27. SPI Read Operation SDA S SLVA6 SLVA5 SLVA4 SLVA3 SLVA2 SLVA1 SLVA WRITE ACK L/S A6 A5 A4 A3 A2 A1 A0 ACK D15 GRAY BACKGROUND MEANS DRIVEN BY ADPD4101 23297-028 SCL Figure 28. I2C Short Write First Half SDA D15 D14 D13 D12 D11 D10 D9 D8 ACK D7 D6 D5 Figure 29. I2C Short Write Second Half Rev. 0 | Page 26 of 101 D4 D3 D2 D1 D0 ACK P 23297-029 SCL Data Sheet ADPD4100/ADPD4101 The rest of the write operation is shown in Figure 29, which shows the two data bytes that are written to the 16-bit register. Registers are written only when all 16 bits are shifted in before a stop bit occurs. The ADPD4101 sends an acknowledge for each byte received. Additional pairs of byte operations can be repeated prior to the stop bit occurring. The address auto-increments after each complete write. Register writes occur only after each pair of bytes is written. register read data one byte at a time. The host acknowledges each byte after it is sent by the ADPD4101, if additional bytes are to be read. The same address incrementing is used for reads as well. To read multiple bytes from the FIFO or from sequential registers, simply repeat the middle byte operation as shown in Figure 31. The first portion of a long write operation is shown in Figure 32. The second half of the long write is the same as for the short write, as shown in Figure 29. The I2C short read operations are shown in Figure 30 and Figure 31. Like the write operation, the first byte pair selects the ADPD4101 and specifies the register address (with the L/S bit low) to read from. The first half of a long read operation is shown in Figure 33. The second half is the same as shown in Figure 31. Figure 31 shows the rest of the read operation. This sequence starts with a start bit, selects the ADPD4101, and indicates that a read operation follows. The ADPD4101 sends an acknowledge to indicate data to be sent. The ADPD4101 then shifts out the S SDA SLVA6 SLVA5 SLVA4 SLVA3 SLVA2 SLVA1 SLVA WRITE ACK L/S A6 A5 A4 A3 A2 A1 A0 23297-030 SCL ACK 23297-031 Figure 30. I2C Short Read First Half SCL S SLVA6 SLVA5 SLVA4 SLVA3 SLVA2 SLVA1 SLVA0 READ SDA ACK D15 D14 D13 D12 D11 D10 D9 ACK D8 D7 D6 D5 D4 D3 D2 D1 D0 NACK P SCL SDA S SLVA6 SLVA5 SLVA4 SLVA3 SLVA2 SLVA1 SLVA0 WRITE ACK L/S A14 A13 A12 A11 A10 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D15 23297-032 Figure 31. I2C Short Read Second Half 2 SCL SDA S SLVA6 SLVA5 SLVA4 SLVA3 SLVA2 SLVA1 SLVA0 WRITE ACK L/S A14 A13 A12 A11 A10 A9 A8 Figure 33. I2C Long Read First Half Rev. 0 | Page 27 of 101 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 23297-033 Figure 32. I C Long Write First Half ADPD4100/ADPD4101 Data Sheet APPLICATIONS INFORMATION OPERATING MODE OVERVIEW Continuous Connect Mode The ADPD4100/ADPD4101 are effectively charge measuring devices that can interface with many different sensors, enabling optical and electrical measurements in various healthcare, industrial and consumer applications, such as PPG, ECG, EDA, impedance, capacitance, and temperature measurements, and gas, smoke, and aerosol detection. A selection of operating modes are built into the device to optimize each of the different sensor measurements supported. Continuous connect mode is used for a single analog integration of incoming charge per ADC conversion and is the most common operating mode for the ADPD4100/ADPD4101. In continuous connect mode, most of the dynamic range of the integrator is used when integrating the charge from the sensor response to a single stimulus event, for example, an LED pulse. The TIA is continuously connected to the inputs after the precondition period by setting MOD_TYPE_x to 0. Therefore, the input connection is not modulated in continuous connect mode. Analog integration mode refers to the modes of operation where the incoming charge from the sensor response to a stimulus event is integrated by the integrator in the ADPD4100/ADPD4101. There are several different analog integration modes, including continuous connect mode, float mode, pulse connect modulation, modulation of stimulus source, multiple integration mode, and sleep float mode. There is also a digital integration mode, where the integrator is configured as a buffer and the ADC samples are digitally integrated (see the Digital Integration Mode section for more information). Connection Modulation Types The ADPD4100/ADPD4101 use three different types of modulation connections to a sensor, controlled by the MOD_TYPE_x bits. Table 17 shows the different functions controlled by MOD_ TYPE_x. The default mode of operation is MOD_TYPE_x = 0, where there is no modulation of the input connection, and is the mode used as described in the Continuous Connect Mode section. Table 17. Modulation Connections Based on MOD_TYPE_x MOD_TYPE_x (Decimal) 0 1 2 Connect Function TIA is continuously connected to INx after the precondition period. There is no modulation of the input connection. Float mode operation. The TIA is connected to INx only during the modulation pulse and disconnected (floated) between pulses. Nonfloat mode connection modulation. The TIA is connected to INx during the modulation pulse and connected to the precondition value between pulses. Continuous connect mode is the typical operating mode used for a PPG measurement, where an LED is pulsed into human tissue and the resultant charge from the photodiode response is integrated and subsequently converted by the ADC. Figure 34 shows an example of a typical PPG measurement circuit. VCx RF 6.3pF RINT INx TIA VLED1 CVLED RF TIA_VREF BPF ADC RINT SWITCH 6.3pF LEDx 23297-034 ANALOG INTEGRATION MODE Figure 34. Typical PPG Measurement Circuit Set the PRECON_x bits to 0x5 to set the anode of the photodiode to the TIA_VREF potential during the preconditioning period. The VCx pin is connected to the cathode of the photodiode and is set to TIA_VREF + 215 mV to apply a 215 mV reverse bias across the photodiode, which reduces the photodiode capacitance and reduces the noise of the signal path. Set TIA_VREF to 1.27 V using the AFE_TRIM_VREF_x bits for maximum dynamic range. The LED pulse is controlled with the LED_OFFSET_x and LED_ WIDTH_x bits. The default LED offset (LED_OFFSET_x = 0x10) is 16 μs from the end of the preconditioning period and is suitable for most use cases. Recommended LED pulse width is 2 μs when using the BPF. Short LED pulse widths provide the greatest amount of ambient light rejection and the lowest power dissipation. The period is automatically calculated by the ADPD4100/ADPD4101. The automatic calculation is based on the integration width selected and the number of ADC conversions. To use the automatic calculation, leave the MIN_PERIOD_x bits at its default value of 0. If a longer period is desired, for example, if a specific pulse frequency is desired, use the MIN_PERIOD_x bits to enable a longer period. Rev. 0 | Page 28 of 101 Data Sheet ADPD4100/ADPD4101 SNR. The ADC conversions can be set to 1, 2, 3, or 4, based on the ADC_COUNT_x bits. In continuous connect mode using 2 µs LED pulses, the automatic period calculation is Period = (2 + 2 × INTEG_WIDTH_x + (Number of Channels Enabled × (ADC_COUNT_x + 1))) If two channels are enabled, Channel 1 occurs first, followed by Channel 2. The integration pulses are controlled with the INTEG_ OFFSET_x and INTEG_WIDTH_x bits. It is recommended that an integration width of 1 μs greater than the LED width be used because the signal spreads due to the response of the BPF. By setting the integration width 1 μs wider than the LED width, a maximum amount of charge from the incoming signal is integrated. The total number of pulses is equal to NUM_INT_x × NUM_ REPEAT_x. In continuous connect mode, NUM_INT_x = 1 for a single integration sequence per ADC conversion. Therefore, the total number of pulses is controlled by NUM_REPEAT_x. Increasing the number of pulses reduces the noise floor of the measurement by a factor of √n, where n is the total number of pulses. The number of ADC conversions defaults to a single ADC conversion. However, oversampling is available for increased Figure 35 shows the timing operation where a single integration cycle is used per ADC conversion. Table 18 details the relevant registers using continuous connect mode for a PPG measurement. Table 18. Continuous Connect Mode Settings Group Signal Path Setup Timing LED Settings Integrator Chop Mode2 Time Slot A Register Address1 0x0100, Bits[13:12] 0x0101, Bits[8:0] 0x0102, Bits[15:0] 0x0103, Bits[14:12] 0x0103, Bits[7:6], Bits[1:0] 0x0104, Bits[5:0] 0x0104, Bits[9:8] 0x0108, Bits[13:12] Bit Field Name SAMPLE_TYPE_x AFE_PATH_CFG_x INPxx_x PRECON_x VCx_SEL_x TIA_GAIN_CHx_x AFE_TRIM_VREF_x MOD_TYPE_x 0x0109, Bits[7:0] LED_OFFSET_x 0x0109, Bits[15:8] 0x010A, Bits[4:0] 0x010B, Bits[12:0] LED_WIDTH_x INTEG_WIDTH_x INTEG_OFFSET_x 0x0107, Bits[15:8] 0x0107, Bits[7:0] NUM_INT_x NUM_REPEAT_x 0x0105, Bit 15 and Bit 7; 0x0106, Bit 15 and Bit 7 0x0105, Bits[14:8], Bits[6:0]; 0x0106, Bits[14:8], Bits[6:0] 0x010D, Bits[7:4] LED_DRIVESIDEx_x Description Leave at the default setting (0) for default sampling mode. Set to 0x0DA for TIA, BPF, integrator, and ADC. Enable desired inputs. Set to 0x5 to precondition anode of the photodiode to TIA_VREF. Set to 0x2 to set ~215 mV reverse bias across the photodiode. Select TIA gain. Set to 0x3 to set TIA_VREF = 1.27 V for maximum dynamic range. Set to 0 for continuous TIA connection to inputs following preconditioning. Sets start time of first LED pulse in 1 μs increments. 0x10 default (16 μs). Sets width of LED pulse in 1 μs increments. 2 μs recommended. Integration time in µs. Set to LED_WIDTH_x + 1. Integration sequence start time = INTEG_OFFSET_x. Optimize as described in the Optimizing Position of Integration Sequence section. Set to 1 for a single integration per group of ADC conversions. With NUM_INT_x = 1, NUM_REPEAT_x sets the total number of pulses. Select LED for time slot used. LED_CURRENTx_x Set LED current for selected LED. SUBTRACT_x 0x010D, Bits[3:0] REVERSE_INTEG_x Four-pulse subtract pattern. Set to 1 to negate the math operation in the matching position in a group of four pulses. The LSB maps to the first pulse. Four-pulse integration reverse pattern. Set to 1 to reverse the integrator positive and negative pulse order in the matching position in a group of four pulses. The LSB maps to the first pulse. This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location for SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120. For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at Address 0x0160, and so on. 2 See the Improving SNR Using Integrator Chopping section for more information about integrator chop mode. 1 Rev. 0 | Page 29 of 101 ADPD4100/ADPD4101 Data Sheet integrator timing for all TIA gain settings without reoptimizing for each TIA gain setting, 200 kΩ TIA gain optimal timing must be used for the other TIA gain settings. Optimizing Position of Integration Sequence It is critical that the zero crossing of the output response of the BPF be aligned with the integration sequence such that the positive integration is aligned with the positive portion of the BPF output response and the negative integration is aligned with the negative portion of the BPF output response (see Figure 35). Improving SNR Using Multiple Pulses The ADPD4100/ADPD4101 use short LED pulses, on the order of 2 μs or 3 μs. The SNR of a single pulse is approximately 72 dB to 76 dB, depending on the TIA gain. The SNR can be extended to ~100 dB by increasing the number of pulses per sample and filtering to a relevant signal bandwidth, for example, 0.5 Hz to 20 Hz for a heart rate signal. The SNR increases as the square root of the number of pulses. Thus, for every doubling of pulses, 3 dB of SNR increase is achieved. The number of pulses is increased with the NUM_REPEAT_x bits. The resulting data for a particular time slot is the summation of ADC conversions that are NUM_REPEAT_x times. If the number of bits required for the result is larger than the number of output bits desired by the user, the most significant bits of the accumulated values can be selected by DARK_SHIFT_x, LIT_SHIFT_x, and SIGNAL_SHIFT_x bits. DARK_SHIFT_x, LIT_SHIFT_x, and SIGNAL_SHIFT_x shift the output data to the right before writing to the FIFO. For example, an 18-bit accumulated value can be shifted to write only the upper 16 bits to the FIFO. Optionally, 24-bit or 32-bit output can be written to the FIFO. A simple test to find the zero crossing is to set up the circuit so that the LED is reflecting off a reflector at a fixed distance from the photodiode such that a steady dc level of photodiode current is provided to the ADPD4100/ADPD4101. Monitor the output while sweeping the integrator offset, INTEG_OFFSET_x, Bits[12:5], from a low value to a high value in 1 μs steps. The zero crossing is located when a relative maxima is seen at the output. The zero crossing can then be identified with much finer precision by sweeping the INTEG_OFFSET_x, Bits[4:0] in 31.25 ns increments. It is critical to identify the zero crossing in such a fine precision to achieve the highest SNR performance. The optimal timing point is a function of TIA bandwidth which varies with TIA gain. To achieve the maximum SNR at each TIA gain setting, it is recommended that the user find the optimal timing point at each TIA gain setting for a given use case. Because there is minimal device to device variation in this optimal timing point, that same integrator offset timing for each gain setting can be used for all devices. To use the same START OF TIME SLOT PRECONDITION PRE_WIDTH_x PERIOD (AUTOMATICALLY CALCULATED) LED_OFFSET_x LED_WIDTH_x LED TIA OUTPUT BPF OUTPUT INTEG_OFFSET_x ZERO CROSSING INTEG_WIDTH_x INTEGRATOR SEQUENCE + – + – INTEGRATOR OUTPUT ADC CONVERSION(S) ADC CHANNEL 2 (IF ENABLED) REPEAT NUM_REPEAT_x TIMES Figure 35. Single Analog Integration per ADC Conversion with Continuous Connect Mode Rev. 0 | Page 30 of 101 23297-035 ADC CHANNEL 1 Data Sheet ADPD4100/ADPD4101 bits = 0xA to reverse the integration sequence for the second and fourth pulses. To complete the operation, the math must be adjusted by setting the SUBTRACT_x bits = 0xA. An even number of pulses must be used with integrator chop mode. Improving SNR Using Integrator Chopping The last stage in the ADPD4100/ADPD4101 datapath is a charge integrator. The integrator uses an on and off integration sequence, synchronized to the emitted light pulse, which acts as an additional high-pass filter to remove offsets, drifts, and low frequency noise from the previous stages. However, the integrating amplifier can itself introduce low frequency signal content. The ADPD4100/ADPD4101 have a mode that enables additional chopping in the digital domain to remove this signal. Chopping is achieved by using an even number of pulses per sample and inverting the integration sequence for half of those sequences. When the calculation is performed to combine the digitized result of each of the pulses of the sample, the sequences with an inverted integrator sequence are subtracted and the sequences with a normal integrator sequence are added. An example diagram of the integrator chopping sequence is shown in Figure 36. Because integrator chopping eliminates the low frequency noise contribution from the integrator, it is recommended to always keep integrator chop mode enabled in continuous connect mode to achieve optimal SNR performance. When using integrator chopping, the ADC offset bits, CH1_ADC_ADJUST_x and CH2_ADC_ADJUST_x, must be set to 0, because when the math is adjusted to subtract inverted integration sequences while default integration sequences are added, any digital offsets at the output of the ADC are automatically eliminated. Integrator chop mode also eliminates the need to manually null the ADC offsets at startup in a typical application. Note that the elimination of the offset using integrator chop mode can clip at least half of the noise signal when no input signal is present, which makes it difficult to measure the noise floor during characterization of the system. There are three options for performing noise floor characterization of the system. The result of chopping is that any low frequency signal contribution from the integrator is eliminated, leaving only the integrated signal and resulting in higher SNR, especially at higher numbers of pulses and at lower TIA gains where the noise contribution of the integrator becomes more pronounced. • • Digital chopping is enabled using the registers and bits detailed in Table 19. The bits define the chopping operation for the first four pulses. This 4-bit sequence is then repeated for all subsequent sequence of four pulses. In Figure 36, a sequence is shown where the second and fourth pulses are inverted while the first and third pulses remain in the default polarity (noninverted). This configuration is achieved by setting the REVERSE_INTEG_x PULSE 1 Integrator chop mode disabled. Integrator chop mode enabled but with a minimal signal present at the input, which increases the noise floor enough such that it is no longer clipped. Setting the ZERO_ADJUST_x bit = 1, which adds 2048 codes to the end result. • PULSE 2 PULSE 3 PULSE 4 LED BPF OUTPUT + – – + + – – + ADC + – + – 23297-036 INTEGRATOR SEQUENCE Figure 36. Diagram of Integrator Chopping Sequence Table 19. Register Settings for Integrator Chop Mode Group Integrator Chop Mode 1 Time Slot A Register Address1 0x010D, Bits[7:4] Bit Field Name SUBTRACT_x 0x010D, Bits[3:0] REVERSE_INTEG_x Description Four-pulse subtract pattern. Set to 1 to negate the math operation in the matching position in a group of four pulses. The LSB maps to the first pulse. Four-pulse integration reverse pattern. Set to 1 to reverse the integrator positive and negative pulse order in the matching position in a group of four pulses. The LSB maps to the first pulse. This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x010D is the location for SUBTRACT_A. For Time Slot B, this register is at Address 0x012D, For Time Slot C, this register is at Address 0x014D. For Time Slot D, this register is at Address 0x016D, and so on. Rev. 0 | Page 31 of 101 ADPD4100/ADPD4101 Data Sheet Float Mode Operation The ADPD4100/ADPD4101 have a unique operating mode, float mode, that allows high SNR at low power in low light situations. In float mode, the photodiode is first preconditioned to a known state. Then, the photodiode anode is disconnected from the receive path of the device for a preset amount of float time. During the float time, light falls on the photodiode, either from ambient light, pulsed LED light, or a combination of the two depending on the operating mode. Charge from the sensor is stored directly on the capacitance of the sensor, CPD. At the end of the float time, the photodiode is switched into the receive path of the ADPD4100/ADPD4101 and an inrush of the accumulated charge occurs, which is then integrated, allowing the maximum amount of charge to be processed per pulse with the minimum amount of noise added by the signal path. The charge is integrated externally on the capacitance of the photodiode for as long as it takes to acquire maximum charge, independent of the amplifiers of the signal path, effectively integrating noise free charge. Float mode allows the user the flexibility to increase the amount of charge per measurement by either increasing the LED drive current or by increasing the float time. In float mode, the signal path bypasses the BPF and uses only the TIA and integrator. The BPF is bypassed because the shape of the signal produced when transferring the charge from the photodiode by modulating the connection to the TIA can differ across devices and conditions. A filtered signal from the BPF is not able to be reliably aligned with the integration sequence. Therefore, the BPF cannot be used. In float mode, the entire charge transfer is integrated in the negative cycle of the integrator, and the positive cycle cancels any offsets. Float LED Mode for Synchronous LED Measurements Float LED mode is desirable in low signal conditions where the CTR is below 5 nA/mA. In addition, float mode is an ideal option when limiting the LED drive current of the green LEDs in a heart rate measurement to keep the forward voltage drop of the green LED to a level that allows the elimination of a boost converter for the LED supply. For example, the LED current can be limited to 10 mA to ensure that the LED voltage drop is ~3 V so that it can operate directly from the battery without the need of a boost converter. Float mode accumulates the received charge during longer LED pulses without adding noise from the signal path, effectively yielding the highest SNR per photon attainable. In float LED mode, multiple pulses are used to cancel electrical offsets, drifts, and ambient light. To achieve this ambient light rejection, an even number of equal length pulses is used. For every pair of pulses, the LED flashes in one of the pulses and does not flash in the other. The return from the combination of the LED, ambient light, and offset is present in one of the pulses. In the other, only the ambient light and offset is present. A subtraction of the two pulses is made that eliminates ambient light as well as any offset and drift. It is recommended to use groups of four pulses for measurement where the LED is flashed on Pulse 2 and Pulse 3. The accumulator adds Pulse 2 and Pulse 3 and then subtracts Pulse 1 and Pulse 4. To gain additional SNR, use multiple groups of four pulses. For each group of four pulses, the settings of LED_DISABLE_x determine if the LED flashes in a specific pulse position. Which pulse positions are added or subtracted is configured in the SUBTRACT_x bits. These sequences are repeated in groups of four pulses. The value written to the FIFO or data registers is dependent on the total number of pulses per sample period. With NUM_INT_x set to 1, NUM_REPEAT_x determines the total number of pulses. For example, if the device is set up for 32 pulses, the four-pulse sequence, as defined in LED_DISABLE_x and SUBTRACT_x, repeats eight times and a single register or FIFO write of the final value based on 32 pulses executes. In float mode, the MIN_PERIOD_x bits must be set to control the pulse period. The automatic period calculation is not designed to work with float mode. Set the MIN_PERIOD_x bits, in 1 μs increments, to accommodate the amount of float time and connect time required. Placement of the integration sequence is such that the negative phase of the integration is centered on the charge transfer phase. The TIA is an inverting stage. Therefore, placing the negative phase of the integration during the transferring of the charge from the photodiode causes the integrator to increase with the negative going output signal from the TIA. In the example shown in Figure 37, the LED flashes in the second and third pulses of the four-pulse sequence. SUBTRACT_x is set up to add the second and third pulses while subtracting the first and fourth pulses, effectively cancelling out the ambient light, electrical offsets, and drift. Table 20 details the relevant registers for float LED mode. Rev. 0 | Page 32 of 101 Data Sheet ADPD4100/ADPD4101 START OF TIME SLOT PRECONDITION PRE_WIDTH_x (DEFAULT 8µs) MOD_OFFSET_x MIN_PERIOD_x MOD_WIDTH_x CONNECT/FLOAT LED PULSES MASK PULSE 1 AND PULSE 4 FLASH PULSE 2 AND PULSE 3 LED_OFFSET_x MASKED LED PULSE FLASH LED FLASH LED MASKED LED PULSE LED_WIDTH_x ACCUMULATED CHARGE ON PD INTEGRATOR OUTPUT INTEG_OFFSET_x INTEGRATOR SEQUENCE INTEG_WIDTH_x 23297-037 INTEGRATOR RESET ADC READ Figure 37. Four-Pulse Float Mode Operation Table 20. Float LED Mode Settings Group Signal Path Setup Float Mode Configuration Time Slot A Register Address1 0x0100, Bits[13:12] 0x0100, Bits[11:10] 0x0101, Bits[8:0] 0x0102, Bits[15:0] 0x0103, Bits[14:12] Bit Field Name SAMPLE_TYPE_x INPUT_R_SELECT_x AFE_PATH_CFG_x INPxx_x PRECON_x 0x0103, Bits[7:6], Bits[1:0] 0x0104, Bits[5:0] 0x0104, Bits[9:8] 0x0107, Bits[15:8] 0x0107, Bits[7:0] VCx_SEL_x TIA_GAIN_CHx_x AFE_TRIM_VREF_x NUM_INT_x NUM_REPEAT_x 0x0108, Bits[13:12] 0x0108, Bits[9:0] MOD_TYPE_x MIN_PERIOD_x 0x010A, Bits[4:0] 0x010A, Bits[10:8], Bits[14:12] 0x010B, Bits[12:0] INTEG_WIDTH_x CHx_AMP_DISABLE_x INTEG_OFFSET_x 0x010C, Bits[15:8] MOD_WIDTH_x 0x010C, Bits[7:0] 0x010D, Bits[7:4] MOD_OFFSET_x SUBTRACT_x Description Leave at the default setting (0) for default sampling mode. Set to 0x0 for 500 Ω series input resistor. Set to 0x0E6 for TIA, integrator, and ADC. Bypass BPF. Enable desired inputs. Set to 0x4 to precondition anode of photodiode to the input of the TIA. Set to 0x2 to set ~215 mV reverse bias across photodiode. Select TIA gain (100 kΩ or 200 kΩ for float mode). Set to 0x2 to set TIA_VREF = 0.9 V. Set to 1 for a single integration per group of ADC conversions. Number of sequence repeats. Must be set to a multiple of 2 for float mode. Set to 0x1 for float mode operation. Set the period to accommodate float time plus connect time, in 1 μs increments. Integration time in µs. Set to MOD_WIDTH_x + 1. Set 0x010A, Bit 9 to 1 to power down BPF for Channel 1, Bit 13 to 1 to power down BPF for Channel 2 if Channel 2 is enabled. Integration sequence start time. Set to (MOD_OFFSET_x − INTEG_WIDTH_x – 250 ns). Sets width of connect pulse in 1 μs increments. Typical values of 2 μs or 3 μs. Sets start time of first connect pulse in 1 μs increments. In any given sequence of four pulses, negate the math operation in the selected position. Selections are active high (that is, subtract if 1) and the LSB of this register maps to the first pulse. For a float mode sequence, add pulses when the LED flashes and subtract pulses when the LED is disabled, according to LED_DISABLE_x. Rev. 0 | Page 33 of 101 ADPD4100/ADPD4101 Group LED Settings 1 Time Slot A Register Address1 0x0105, Bit 15 and Bit 7; 0x0106, Bit 15 and Bit 7 0x0105, Bits[14:8], Bits[6:0]; 0x0106, Bits[14:8], Bits[6:0] 0x0109, Bits[7:0] 0x0109, Bits[15:8] 0x010D, Bits[15:12] Data Sheet Bit Field Name LED_DRIVESIDEx_x Description Select LED for time slot used. LED_CURRENTx_x Set LED current for selected LED. LED_OFFSET_x LED_WIDTH_x LED_DISABLE_x Sets start time of first LED pulse in 1 μs increments. Sets width of LED pulse in 1 μs increments. In any given sequence of four pulses, disable the LED pulse in the selected position. Selections are active high (that is, disable LED if 1) and the LSB of this register maps to the first pulse. For a sequence of four pulses, it is recommended to turn on the LED in the second and third pulses by writing 0x9 to this register. This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location for SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120. For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at Address 0x0160, and so on. The maximum amount of charge that can be stored on the photodiode capacitance and remain in the linear operating region of the sensor is estimated by Q = CPDV where: Q is the integrated charge. CPD is the capacitance of the photodiode. V is the amount of voltage change across the photodiode before the photodiode becomes nonlinear. For a typical discrete optical design using a 7 mm2 photodiode with 70 pF capacitance and 450 mV of headroom, the maximum amount of charge that can store on the photodiode capacitance is 31.5 pC. PD BEGINS TO FORWARD BIAS RECOMMENDED FLOAT MODE OPERATING REGION FLOAT TIME (µs) 23297-038 When using float mode, the limitations of the mode must be well understood. For example, a finite amount of charge can accumulate on the capacitance of the photodiode, and there is a maximum amount of charge that can be integrated by the integrator. Based on an initial reverse bias of 215 mV on the photodiode and assuming that the photodiode begins to become nonlinear at ~200 mV of forward bias, there is ~450 mV of headroom for the anode voltage to increase from its starting point at the beginning of the float time before the charge ceases to accumulate in a linear fashion. It is desirable to operate only in the linear region of the photodiode (see Figure 38). To verify that float mode is operating in the linear region of the photodiode, the user can perform a simple check. Record data at a desired float time and then record data at half the float time. The recommended ratio of the two received signals is 2:1. If this ratio does not hold true, the photodiode is likely beginning to forward bias at the longer float time and becomes nonlinear. INTEGRATED CHARGE ON PD (pC) Float Mode Limitations Figure 38. Integrated Charge on the Photodiode (PD) vs. Float Time In addition, consider the maximum amount of charge the integrator of the ADPD4100/ADPD4101 can integrate. The integrator can integrate up to 7.6 pC. When this charge is referred back to the input, consider the TIA gain. When the TIA gain is at 200 kΩ, the input referred charge is at a 1:1 ratio to the integrated charge on the integrator. For 100 kΩ gain, it is 2:1. For 50 kΩ gain, it is 4:1. For 25 kΩ gain, it is 8:1. For the previous example using a photodiode with 70 pF capacitance, use a 50 kΩ TIA gain and set the float timing such that, for a single pulse, the output of the ADC is at 70% of full scale, which is a typical operating condition. Under these operating conditions, the integrator integrates 5.3 pC per pulse for 21.2 pC of charge accumulated on the photodiode capacitance. The amount of time to accumulate charge on CPD is inversely proportional to CTR. TIA gain settings of 100 kΩ or 200 kΩ may be required based on the CTR of the measurement and how much charge can be accumulated in a given amount of time. Ultimately, the type of measurement being made (ambient or pulsed LED), the photodiode capacitance, and the CTR of the system determine the float times. Rev. 0 | Page 34 of 101 Data Sheet ADPD4100/ADPD4101 Pulse Connect Modulation The BPF is bypassed for this measurement. When a stimulus pulse is provided on the VCx pin, the capacitor response is a positive spike on the rising edge that then settles back toward TIA_VREF, followed by a negative spike on the falling edge of the stimulus pulse. The integration sequence is centered such that the positive and negative integration sequences completely integrate the charge from the positive and negative TIA responses, respectively (see Figure 41). Pulse connect modulation is useful for ambient light measurements or any other sensor measurements that do not require a synchronous stimulus. This mode works by preconditioning the sensor to some level selected by the PRECON_x bits and then only connecting the sensor to the input of the TIA during the modulation pulse. When not connected to the TIA, the sensor is connected to a low input impedance node at the TIA_VREF voltage. Any sensor current during this time is directed into the AFE. Therefore, no charge accumulates on the sensor. This lack of charge accumulation is in contrast to float mode, which fully disconnects the sensor between modulation pulses. The MOD_TYPE_x bits must be set to 0x2 for pulse connect mode. The advantage of using this mode for nonsynchronous sensor measurements is that it allows the user to take advantage of the noise performance benefits of the full signal path using the BPF and integrator. Figure 40 shows a timing diagram for pulse connect modulation type measurements. Pulsing of the VC1 and VC2 pins is controlled by the VCx_PULSE_x, VCx_ALT_x, and VCx_SEL_x bits while timing of the modulation is controlled by the MOD_OFFSET_x and MOD_WIDTH_x bits. Table 21 shows the relevant registers for modulating the stimulus to the sensor. Mutual Capacitance-Based Proximity Measurement One of the applications of the ADPD4100/ADPD4101 based on capacitance measurement is the proximity measurement. A mutual capacitance-based proximity measurement application, for example, is based on modulation of the stimulus source in principle, and is shown in Figure 39. However, this application requires two electrodes along with the circuit shown in Figure 39, one of which is connected to an input of the ADPD4100/ ADPD4101 and the other connected to VC1 or VC2. The capacitor between INx and VCx, in this case, is the representation of the capacitance formed between two electrodes, instead of a physical capacitor. Modulation of Stimulus Source The ADPD4100/ADPD4101 have operating modes that modulate the VC1 and VC2 signals. These modes are useful for providing a pulsed stimulus to the sensor being measured. For example, a bioimpedance measurement can be made where one electrode to the human is being pulsed by the VC1 or VC2 output and the response is measured on a second electrode connected to the TIA input. This mode is also useful for a capacitance measurement, as shown in Figure 39, where one of the VCx pins is connected to one side of the capacitor and the other side is connected to the TIA input. A proximity event represents the proximity of tissue to the two electrodes mentioned. At the proximity event, a capacitance of ΔC is formed between the electrodes and human tissue. ΔC varies due to the varying proximity of tissue to the electrodes. Therefore, total capacitance, which is the sum of the capacitance of the capacitance between two electrodes represented as C and the capacitance ΔC formed between human tissue and the electrode, changes. RF RINT INx TIA_VREF C INT TIA VCx 23297-040 RINT RF Figure 39. Modulate Stimulus for Capacitance Measurement START OF TIME SLOT PRECONDITION PRE_WIDTH_x SENSOR (DEFAULT 8µs) MOD_OFFSET_x PERIOD (AUTOMATICALLY CALCULATED) CONNECT TIA TO SENSOR MOD_WIDTH_x TIA OUTPUT BPF OUTPUT INTEGRATOR SEQUENCE INTEG_WIDTH_x INTEG_OFFSET_x + – + – INTEGRATOR OUTPUT CONVERSION(S) ADC CHANNEL 2 (IF ENABLED) REPEAT NUM_REPEAT_x TIMES Figure 40. Timing Diagram for Pulse Connect Modulation Rev. 0 | Page 35 of 101 23297-039 ADC CHANNEL 1 ADPD4100/ADPD4101 Data Sheet One can determine the changing proximity by reading the change in ADC output when ΔC is induced through the change in the proximity of the human tissue. To be able to determine proximity, baseline measurement without tissue in proximity must be taken either at the same input or at another input with an electrode attached and configured the same way. from the positive and negative TIA responses, which is essential to integrate the maximum ac charge. Then, ΔC is proportionate to the change in ADC output, which is a function of the charge integrated, read at the proximity event. For example, when VC2 is pulsed by 215 mV by setting VC2_PULSE_x to 2, VC2_ALT_x to 2, and VC2_SEL_x to 2, ΔC is calculated as follows: Integrator timing width must be long enough to allow the positive TIA response to fully settle before the negative edge of the TIA response occurs. Also, as shown in Figure 41, the integration timing must be centered so that the positive and negative integration sequences completely integrate the charge ΔC = (−Δ(ADC Output in LSB) × 0.92 fC/LSB × (RINT/2RF)/Number of Pulses)/(2 × 0.215 V) Table 21 shows the relevant registers for this measurement. START OF TIME SLOT PRECONDITION SENSOR PRE_WIDTH_x (DEFAULT 8µs) MOD_WIDTH_x PERIOD (AUTOMATICALLY CALCULATED) MOD_OFFSET_x MODULATE STIMULUS TIA OUTPUT INTEG_OFFSET_x INTEG_WIDTH_x INTEGRATION SEQUENCE + – + – 23297-041 INTEGRATOR OUTPUT ADC CHANNEL 1 Figure 41. Timing Diagram for Modulate Stimulus Operation Table 21. Modulate Stimulus Settings Group Modulate Stimulus Setup Modulate Stimulus Timing 1 Time Slot A Register Address1 0x0100, Bits[13:12] 0x0101, Bits[8:0] 0x0102, Bits[15:0] 0x0103, Bits[14:12] 0x0103, Bits[11:10], Bits[5:4] Bit Field Name SAMPLE_TYPE_x AFE_PATH_CFG_x INPxx_x PRECON_x VCx_PULSE_x 0x0103, Bits[9:8], Bits[3:2] 0x0103, Bits[7:6], Bits[1:0] 0x0104, Bits[5:0] 0x0104, Bits[9:8] 0x010C, Bits[7:0] 0x010C, Bits[15:8] VCx_ALT_x VCx_SEL_x TIA_GAIN_CHx_x AFE_TRIM_VREF_x MOD_OFFSET_x MOD_WIDTH_x 0x010A, Bits[4:0] 0x010A, Bits[10:8], Bits[14:12] INTEG_WIDTH_x CHx_AMP_DISABLE_x 0x010B, Bits[12:0] INTEG_OFFSET_x 0x0107, Bits[15:8] 0x0107, Bits[7:0] NUM_INT_x NUM_REPEAT_x 0x0108, Bits[13:12] MOD_TYPE_x Description Leave at the default setting (0) for default sampling mode. Set to 0x0E6 for TIA, integrator, and ADC. Bypass BPF. Enable desired inputs. Set to 0x5 to precondition sensor to TIA_VREF. VCx pulse control. Set to 0x2 to pulse to the alternate voltage during a modulation pulse. Select the alternate state for VCx during the modulation pulse. Set to 0x1 to set VCx to TIA_VREF as primary state. Select TIA gain. Set to 0x2 to set TIA_VREF = 0.9 V. Sets start time of first modulation pulse in 1 μs increments. Sets width of modulation pulse in 1 μs increments. Typical values of 6 μs to 12 μs. Integration time in μs. Set to MOD_WIDTH_x + 1 or MOD_WIDTH_x + 2. Set 0x010A, Bit 9 to 1 to power down BPF for Channel 1, Bit 13 to 1 to power down BPF for Channel 2 if Channel 2 is enabled. Integration sequence start time. Set to MOD_OFFSET_x − 1 (if INTEG_WIDTH = MOD_WIDTH − 1) or MOD_OFFSET_x – 2 (if INTEG_WIDTH = MOD_WIDTH − 2) and then sweep INTEG_OFFSET_x, Bits[4:0] in 31.25 ns steps to find optimal operating point. Set to 1 for a single integration per ADC conversion. Number of sequence repeats. SNR increases as √n, where n = NUM_REPEAT_x × NUM_INT_x. Set to 0x0 for continuous TIA connection. This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location for SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120. For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at Address 0x0160, and so on. Rev. 0 | Page 36 of 101 Data Sheet ADPD4100/ADPD4101 capacitance-based measurement. The integration sequence must be centered in such a way that all the dc shift is canceled and remaining small ac charge due to the change in proximity is integrated. Figure 43 shows integration sequence timing with respect to the TIA_VREF pulse to cancel dc shift and integrate ac charge. The constant part in the TIA output represents the dc charge, and it must be canceled by the integration sequence so that only the surge charge accumulation at the positive and the negative edges of the TIA_VREF pulse are integrated. Self Capacitance-Based Proximity Measurement Capacitive proximity measurements can be performed by measuring self capacitance. As in mutual capacitance-based proximity measurement, the BPF is bypassed by setting AFE_PATH_CFG_x to 0E6. Self capacitance based proximity measurement, however, requires only one electrode connected to one of the inputs of ADPD4100/ADPD4101. Capacitance measurement in this case is performed by creating the voltage difference. To create the voltage difference, pulse TIA_VREF while the input used is preconditioned to TIA_VREF, and read the change in the ADC output when ΔC is induced through the change in the proximity of the human tissue. However, the baseline measurement without tissue in proximity is needed to determine true ΔC, which is proportionate to the change in ADC output read at the proximity event. Calculate ΔC as follows. For example, when TIA_VREF is pulsed from 0.9 V to 1.14 V by setting VREF_PULSE_VAL_x to 0, AFE_TRIM_VREF_x to 2, and VREF_PULSE_x to 1, ΔC then becomes This measurement modality makes use of the capacitance of the human body to the earth, and ΔC formed due to tissue proximity. The human body capacitance allows the use of TIA_VREF pulsing at the input as a voltage difference needed to measure ΔC. Figure 42 shows a representation of this measurement. ΔC = (Δ(ADC Output in LSB) × 0.92 fC/LSB × (RINT/2RF)/Number of Pulses)/(2 × (1.14 V − 0.9 V)) Table 22 summarizes the relevant registers for this measurement. Integrator chop mode can be enabled for this measurement. Because TIA_VREF is pulsed at the input, all the extra voltage at pulsing shows up the same way at the TIA output. Therefore, TIA has only a positive response compared to the mutual CINT RF ELECTRODE C RINT INx TIA TIA_VREF INT RF 23297-042 RINT CINT Figure 42. Self Capacitance Measurement START OF TIME SLOT PRECONDITION SENSOR PRE_WIDTH_x (DEFAULT 8µs) MOD_WIDTH_x PERIOD (AUTOMATICALLY CALCULATED) MOD_OFFSET_x PULSE TIA_VREF INTEG_OFFSET_x INTEG_WIDTH_x INTEGRATION SEQUENCE + – + – 23297-043 TIA OUTPUT Figure 43. Timing Diagram for Self Capacitance-Based Proximity Measurement Table 22. Relevant Registers for Self Capacitance Based Proximity Measurement Group Self Capacitance-Based Proximity Setup Time Slot A Register Address1 0x0100, Bits[13:12] Bit Field Name SAMPLE_TYPE_x 0x0101, Bits[8:0] AFE_PATH_CFG_x 0x0102, Bits[15:0] 0x0103, Bits[14:12] 0x0104, Bits[5:0] 0x0104, Bits[7:6] 0x0104, Bits[9:8] 0x0104, Bits[10] INPxx_x PRECON_x TIA_GAIN_CHx_x VREF_PULSE_VAL_x AFE_TRIM_VREF_x VREF_PULSE_x Rev. 0 | Page 37 of 101 Description Leave at the default setting (0) for default sampling mode. Set to 0x0E6 for TIA, integrator, and ADC. Bypass BPF. Enable desired inputs. Set to 0x5 to precondition sensor to TIA_VREF. Select TIA gain. Select 0x0 to pulse TIA_VREF to 1.14 V. Set to 0x2 to set TIA_VREF = 0.9 V. Set to 0x1 to pulse TIA_VREF. ADPD4100/ADPD4101 Group Self Capacitance-Based Proximity Timing 1 Data Sheet Time Slot A Register Address1 0x010C, Bits[7:0] Bit Field Name MOD_OFFSET_x 0x010C, Bits[15:8] MOD_WIDTH_x 0x010A, Bits[4:0] 0x010A, Bits[10:8], Bits[14:12] INTEG_WIDTH_x CHx_AMP_DISABLE_x 0x010B, Bits[12:0] INTEG_OFFSET_x 0x0107, Bits[15:8] NUM_INT_x 0x0107, Bits[7:0] NUM_REPEAT_x 0x0108, Bits[13:12] MOD_TYPE_x Description Sets start time of first modulation pulse in 1 μs increments. Typical value of 16 μs. Sets width of modulation pulse in 1 μs increments. Typical value of 6 μs. Integration time in µs. Typical value of 10 μs . Set 0x010A, Bit 9 to 1 to power down BPF for Channel 1, Bit 13 to 1 to power down BPF for Channel 2 if Channel 2 is enabled. Integration sequence start time. Set to typical value of 9 μs and then sweep INTEG_OFFSET_x, Bits[4:0] in 31.25 ns steps to find optimal operating point. Set to 1 for a single integration per ADC conversion Number of sequence repeats. SNR increases as √n, where n = NUM_REPEAT_x × NUM_INT_x. Set to 0x0 for continuous TIA connection. This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location for SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120. For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at Address 0x0160, and so on. Multiple Integration Mode Multiple integration mode provides multiple analog integrations of incoming charge per ADC conversion. This mode is most useful when there is a small response that uses a small amount of the available dynamic range per stimuli event. Multiple integration mode allows multiple integrations of charge prior to an ADC conversion so that a larger amount of the available dynamic range of the integrator is utilized. Figure 44 shows multiple integration mode using the LED as the stimulus. The number of LED pulses and subsequent integrations of charge from the photodiode response is determined by the setting of the NUM_INT_x bits. Following the final integration, there is a single ADC conversion. This process is repeated NUM_REPEAT_x times. Prior to setting the number of integrations using the NUM_INT_x bits, set the TIA gain to 200 kΩ and determine the optimal LED current setting, which is close to the maximum current. When the TIA gain and LED current are set, measure how much of the integrator dynamic range is used to integrate the charge created by a single LED pulse. If the amount of integrator dynamic range used for a single pulse is less than half the available dynamic range, it may be desirable to use multiple integrations prior to an ADC conversion. For example, if the amount of integrator dynamic range used for a single pulse is 1/8 of the available dynamic range, set NUM_INT_x to 0x6 to use six pulses and integrations, using most of the available dynamic range (75%) per ADC conversion while leaving 25% of headroom for margin so that the integrator does not saturate as the input level varies. As each pulse is applied to the LED, the charge from the response is integrated and held. The charge from the response to each subsequent pulse is added to the previous total integrated charge, as shown in Figure 44, until NUM_INT_x integrations is reached. In multiple integration mode, the minimum period is automatically calculated. In the example shown, the minimum period is calculated at 2 × INTEG_WIDTH_x so that subsequent pulses occur immediately following the completion of the previous integration. Extra time is automatically added to accommodate the ADC conversions at the end of NUM_INT_x integrations. Use NUM_REPEAT_x to increase the iterations to improve the overall SNR. The entire multiple integration per ADC conversion process repeats NUM_REPEAT_x number of times. Increasing NUM_REPEAT_x serves the same purpose as multiple pulses in continuous connect mode, where n pulses improve the SNR by √n. In multiple integration mode, the SNR increases by √n, where n = NUM_REPEAT_x. The total number of LED pulses in this mode is equal to NUM_INT_x × NUM_REPEAT_x. Integrator chop mode is recommended for multiple integration mode for optimal SNR performance. Rev. 0 | Page 38 of 101 Data Sheet ADPD4100/ADPD4101 START OF TIME SLOT PRECONDITION PRE_WIDTH_x (DEFAULT 8µs) LED_OFFSET_x CALCULATED PERIOD LED_WIDTH_x LED TIA OUTPUT BPF OUTPUT INTEG_OFFSET_x INTEGRATOR SEQUENCE + – + – + – + – INTEG_WIDTH_x INTEGRATOR OUTPUT 23297-044 ADC CONVERT NUM_INT_x NUM_REPEAT_x TIMES Figure 44. Multiple Integration Mode with LED as Stimulus Table 23. Relevant Settings for Multiple Integration Mode Group Multiple Integration Mode Using LED as Stimulus Timing LED Settings Integrator Chop Mode 1 Time Slot A Register Address1 0x0100, Bits[13:12] 0x0101, Bits[8:0] 0x0102, Bits[15:0] 0x0103, Bits[14:12] Bit Field Name SAMPLE_TYPE_x AFE_PATH_CFG_x INPxx_x PRECON_x 0x0103, Bits[7:6], Bits[1:0] 0x0104, Bits[5:0] 0x0104, Bits[9:8] VCx_SEL_x TIA_GAIN_CHx_x AFE_TRIM_VREF_x 0x0108, Bits[13:12] MOD_TYPE_x 0x0107, Bits[15:8] NUM_INT_x 0x0107, Bits[7:0] NUM_REPEAT_x 0x010A, Bits[4:0] 0x010B, Bits[12:0] INTEG_WIDTH_x INTEG_OFFSET_x 0x0105, Bit 15 and Bit 7; 0x0106, Bit 15 and Bit 7 0x0105, Bits[14:8], Bits[6:0]; 0x0106, Bits[14:8], Bits[6:0] 0x010D, Bits[7:4] LED_DRIVESIDEx_x Description Leave at the default setting (0) for default sampling mode. Set to 0x0DA for TIA, BPF, integrator, and ADC. Enable desired inputs. Set to 0x5 to precondition anode of the photodiode to TIA_VREF. Set to 0x2 to set ~215 mV reverse bias across photodiode. Set the TIA gain to 200 kΩ. Set to 0x3 to set TIA_VREF = 1.27 V for maximum dynamic range. Set to 0 for continuous TIA connection to inputs following preconditioning. Set to a number that utilizes most of the dynamic range of integrator available, leaving some margin for fluctuations in input level. Set NUM_REPEAT_x to the number of times to repeat the multiple integration sequence. SNR increases by a factor of √(NUM_REPEAT_x). Total number of pulses is equal to NUM_REPEAT_x × NUM_INT_x. Integration time in µs. Set to LED_WIDTH_x + 1. Integration sequence start time = INTEG_OFFSET_x. Optimize as described in the Optimizing Position of Integration Sequence section. Select LED for time slot used. LED_CURRENTx_x Set LED current for selected LED. SUBTRACT_x 0x010D, Bits[3:0] REVERSE_INTEG_x Four-pulse subtract pattern. Set to 1 to negate the math operation in the matching position in a group of four pulses. The LSB maps to the first pulse. Four-pulse integration reverse pattern. Set to 1 to reverse the integrator positive and negative pulse order in the matching position in a group of four pulses. The LSB maps to the first pulse. This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location for SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120, For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at Address 0x0160, and so on. Rev. 0 | Page 39 of 101 ADPD4100/ADPD4101 Data Sheet DIGITAL INTEGRATION MODE The ADPD4100/ADPD4101 support a digital integration mode to accommodate sensors that require longer pulses than can be supported in the typical analog integration modes. Digital integration mode allows the system to use a larger LED duty cycle than the analog integration modes, which may result in the highest achievable levels of SNR, at the expense of lower ambient light rejection. RF INx BUF TIA ADC 23297-045 TIA_VREF RF VCx Figure 45. Signal Path for Digital Integration Mode In digital integration mode, the BPF is bypassed and the integrator is configured as a buffer, resulting in the signal path shown in Figure 45. Digital integration regions are configured by the user and separated into lit and dark regions. The LED is pulsed in the lit region, and the LED is off in the dark region. ADC samples are taken at 1 μs intervals within the lit and dark regions and are then digitally integrated. The integration of the ADC samples from the dark region is subtracted from the integration of the ADC samples from the lit region and the result is written into the relevant signal output data registers. The sum of the samples from just the dark region are available in the dark output data registers. Both signal and dark values can be written to the FIFO. The ADPD4100/ADPD4101 support one-region and tworegion digital integration modes. In one-region digital integration mode, an equal number of dark and lit samples are taken where all of the dark samples are taken in the dark region just prior to the lit region. One-region digital integration mode is illustrated in the timing diagram in Figure 46. In two-region digital integration mode, an equal number of dark and lit samples are taken. However, the dark region is split such that half of the samples are taken in the dark region prior to the lit region, and the other half is taken in the dark region following the lit region. The two-region digital integration mode results in higher ambient light rejection than the one-region digital integration mode in situations with a varying ambient light level. A timing diagram for two-region digital integration mode is shown in Figure 47. Table 24 shows the relevant register settings for the digital integration modes of operation. Note that only a single channel can be used in digital integration mode. Two channels are not supported for digital integration mode of operation. The MIN_ PERIOD_x bits must also be manually set with the correct period because the minimum period is not automatically calculated in digital integration mode. START OF TIME SLOT PRECONDITION LED PRECONDITION PRE_WIDTH_x MIN_PERIOD_x (MUST BE SET, NOT AUTOMATICALLY CALCULATED) LED_WIDTH_x LED_OFFSET_x NUM_INT_x DARK1_OFFSET_x LIT_OFFSET_x NUM_INT_x NUM_REPEAT_x 23297-046 ADC CONVERSIONS Figure 46. One-Region Digital Integration Mode Timing Diagram START OF TIME SLOT PRECONDITION LED PRECONDITION PRE_WIDTH_x LED_OFFSET_x MIN_PERIOD_x (MUST BE SET, NOT AUTOMATICALLY CALCULATED) LED_WIDTH_x ADC CONVERSIONS NUM_INT_x NUM_REPEAT_x Figure 47. Two-Region Digital Integration Mode Timing Diagram Rev. 0 | Page 40 of 101 2 × NUM_INT_x 23297-047 DARK1_OFFSET_x LIT_OFFSET_x DARK2_OFFSET_x Data Sheet ADPD4100/ADPD4101 Table 24. Relevant Settings for Digital Integration Modes Group Signal Path Setup Timing LED Settings 1 Time Slot A Register Address1 0x0100, Bits[13:12] Bit Field Name SAMPLE_TYPE_x 0x0101, Bits[8:0] AFE_PATH_CFG_x 0x0102, Bits[15:0] 0x0103, Bits[14:12] 0x0103, Bits[7:6], Bits[1:0] 0x0104, Bits[5:0] 0x0104, Bits[9:8] 0x0104, Bits[12:11] 0x010A, Bit 11 0x010A, Bits[10:8] 0x0107, Bits[15:8] INPxx_x PRECON_x VCx_SELECT_x TIA_GAIN_CHx_x AFE_TRIM_VREF_x CH1_TRIM_INT_x AFE_INT_C_BUF_x CH1_AMP_DISABLE_x NUM_INT_x 0x0107, Bits[7:0] 0x0108, Bits[9:0] NUM_REPEAT_x MIN_PERIOD_x 0x0113, Bits[8:0] 0x0114, Bits[6:0] 0x0114, Bits[15:7] LIT_OFFSET_x DARK1_OFFSET_x DARK2_OFFSET_x 0x0105, Bit 15 and Bit 7; 0x0106, Bit 15 and Bit 7 0x0105, Bits[14:8], Bits[6:0]; 0x0106, Bits[14:8], Bits[6:0] 0x0109, Bits[7:0] 0x0109, Bits[15:8] LED_DRIVESIDEx_x Description Set to 0x1 for one-region digital integration mode. Set to 0x2 for two-region digital integration mode. Set to 0x0E6 for TIA, integrator, and ADC. Bypass BPF. Integrator is automatically configured as a buffer when one-region or tworegion digital integration mode is selected. Enable desired inputs. Set to 0x5 to precondition anode of photodiode to TIA_VREF. Set to 0x2 to set ~215 mV reverse bias across photodiode. Select TIA gain. Set to 0x3 to set TIA_VREF = 1.265 V. Set to 0x0 or 0x1 to set buffer gain = 1. Set to 1 to convert integrator to buffer. Set 0x010A, Bit 9 to 1 to power down BPF. Set to the number of desired ADC conversions in the dark and lit regions. Number of sequence repeats. Set the period. Automatic period calculation is not supported in digital integration mode. Set to the time of the first ADC conversion in the lit region. Set to the time of the first ADC conversion in the Dark 1 region. Set to the time of the first ADC conversion in the Dark 2 region. Only used in two-region digital integration mode. Select LED for time slot used. LED_CURRENTx_x Set LED current for selected LED. LED_OFFSET_x LED_WIDTH_x Sets start time of first LED pulse in 1 μs increments. Sets width of LED pulse in 1 μs increments. This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location for SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120. For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at Address 0x0160, and so on. Timing Recommendations for Digital Integration Modes DARK2_OFFSET_x = (LED_OFFSET_x + LED_WIDTH_x + tD) When setting the timing for digital integration mode, it is important to place the ADC samples such that the signal being sampled is given time to settle prior to the sample being taken. Settling time of the input signal is affected by photodiode capacitance and TIA settling time. Figure 48 shows an example of proper placement of the ADC sampling edges. Calculations for the offset values are as follows: This setting only applies to two-region digital integration mode. LED_OFFSET_x LED OUTPUT TIA OUTPUT tD DARK1_OFFSET_x LIT_OFFSET_x DARK2_OFFSET_x tD 23297-048 ADC SAMPLES DARK1_OFFSET_x = (LED_OFFSET_x – (NUM_INT_x + 2)) Add a value of 2 to the number of ADC conversions such that there is 2 μs of margin added to placement of the Dark 1 region samples with respect to the beginning of the LED pulse. LED_WIDTH_x Figure 48. Proper Placement of ADC Sampling Edges in Digital Integration Mode LIT_OFFSET_x = (LED_OFFSET_x + tD) where tD is the delay built into the offset setting to allow settling time of the signal. This value must be characterized in the final application. A value in the range of 3 µs to 5 µs is typically recommended as the tD value. Rev. 0 | Page 41 of 101 ADPD4100/ADPD4101 Data Sheet TIA ADC MODE Figure 49 shows TIA ADC mode, which bypasses the BPF and routes the TIA output through a buffer, directly into the ADC. TIA ADC mode is useful in applications, such as ambient light sensing, and measuring other dc signals, such as leakage resistance. In photodiode measurement applications using the BPF, all background light is blocked from the signal chain and, therefore, cannot be measured. TIA ADC mode can measure the amount of background and ambient light. This mode can also measure currents from other dc sources, such as leakage resistance. RF BUF ADC RF 23297-049 TIA Equation 3 is an approximation and does not account for internal offsets and gain errors. The calculation also assumes that the ADC offset registers are set to 0. Configuring one time slot in TIA ADC mode is useful for monitoring ambient and pulsed signals at the same time. The ambient signal is monitored during the time slot configured for TIA ADC mode, while the pulsed signal, with the ambient signal rejected, is monitored in the time slot configured for measuring the desired LED pulsed signal. PROTECTING AGAINST TIA SATURATION IN NORMAL OPERATION INx TIA_VREF Buffer Gain is either 0.7 or 1 based on the setting of CHx_TRIM_INT_x. Figure 49. TIA ADC Mode Block Diagram When the devices are in TIA ADC mode, the BPF is bypassed and the integrator stage is reconfigured as a buffer. If both Channel 1 and Channel 2 are enabled in a single time slot, the ADC samples Channel 1 and then Channel 2 in sequential order in 1 µs intervals. The recommended TIA ADC mode is one in which the BPF is bypassed and the integrator is configured as an inverting buffer. This mode is enabled by writing 0x0E6 to AFE_PATH_CFG_x (Register 0x0101, Bits[8:0] for Time Slot A) to enable a signal path that includes the TIA, integrator, and ADC. Additionally, to configure the integrator as a buffer, set INTEG_SETUP_x (Register 0x010A, Bit 11 for Time Slot A). With the ADC offset bits, ADC_OFF1_x and ADC_OFF2_x, set to 0 and TIA_VREF set to 1.265 V, the output of the ADC is at ~3000 codes for a single pulse and a zero input current condition. As the input current from the photodiode increases, the ADC output increases toward 16,384 LSBs. When configuring the integrator as a buffer, there is the option of either using a gain of 1 or a gain of 0.7. Using the gain of 0.7 increases the usable dynamic range at the input to the TIA. However, it is possible to overrange the ADC in this configuration and care must be taken to not saturate the ADC. To set the buffer gain, use the CHx_TRIM_INT_x bits. Setting CHx_TRIM_ INT_x to 0x0 or 0x1 sets a gain of 1. Setting CHx_TRIM_INT_x to 0x2 or 0x3 configures the buffer with a gain of 0.7. Calculate the ADC output (ADCOUT) as follows: ADCOUT = 8192 − (((2 × TIA_VREF − 2 × IINPUT_TIA × RF − 1.8 V)/146 µV/LSB) × Buffer Gain) (3) where: TIA_VREF is the internal voltage reference signal for the TIA (the default value is 1.265 V). IINPUT_TIA is the input current to the TIA. RF is the TIA feedback resistor. One concern when operating in high light conditions, especially with larger photodiodes, is that the TIA stage may become saturated while the ADPD4100/ADPD4101 continue to communicate data. The resulting saturation is not typical. The TIA, based on its settings, can only handle a certain level of photodiode current. Based on the way the ADPD4100/ADPD4101 are configured, if there is a current level from the photodiode that is larger than the TIA can handle, the TIA output during the LED pulse effectively extends the current pulse, making it wider. The AFE timing is then violated because the positive portion of the BPF output extends into the negative section of the integration window. Thus, the photosignal is subtracted from itself, causing the output signal to decrease when the effective light signal increases. Protecting Against TIA Saturation in Normal Operation with TIA ADC Mode TIA ADC mode monitoring is one of the ways to protect against environments that may cause saturation. To measure the response from the TIA and verify that this stage is not saturating, place the device in TIA ADC mode and slightly modify the timing. Specifically, sweep INTEG_OFFSET_x until a maximum is achieved. This procedure aligns the ADC sampling time with the LED pulse to measure the total amount of light falling on the photodetector (for example, background light and LED pulse). If this minimum value is below 16,384 LSBs, the TIA is not saturated. However, take care, because even if the result is not 16,384 LSBs, operating the device near saturation can quickly result in saturation if light conditions change. A safe operating region is typically at ¾ full scale and lower. The ADC resolution when operating in TIA ADC mode with a buffer gain = 1 is shown in Table 25. These codes are not the same as in modes with the BPF and integrator enabled because the BPF and integrator are not unity-gain elements. Table 25. ADC Resolution in TIA ADC Mode TIA Gain (kΩ) 12.5 25 50 100 200 Rev. 0 | Page 42 of 101 ADC Resolution (nA/LSB) 5.84 2.92 1.46 0.73 0.37 Data Sheet ADPD4100/ADPD4101 While the TIA ADC mode monitoring helps to avoid saturation, there may be cases where the voltage at the output terminals of the TIA may exceed the typical operation levels that ensure no current saturation for some amount of time while the actual measurement is in the process. If the current fed into the inputs of the TIA is high enough, it could result in exceeding the typical operating points of TIA depending on the TIA gain and the TIA reference voltage settings. In this case, measurements can be distorted or may not be done. High levels of photodiode current or high levels of ambient current may cause the output voltages of the TIA to go above a limit that is close to saturation. The ADPD4100/ADPD4101 have a TIA ceiling detection feature that uses voltage comparators at the outputs of the TIA stage to detect whether the TIA output voltage exceeds a certain range. This range ensures the TIA output to be far enough from the ceiling of the total TIA range by some margin. Therefore, if the TIA output voltage exceeds the range even for a small amount of time, the user is informed about the status of voltage at the TIA outputs and can take action to avoid a possible saturation. Voltage comparators compare the positive and negative output terminals to a certain threshold voltage, which sets the effective TIA output voltage range, and send an output bit indicating whether the TIA output voltage is beyond the range. To enable this feature, TIA_CEIL_DETECT_EN_x must be set to 1. Each time slot has its own TIA_CEIL_DETECT_EN_x bit that can be controlled individually. The feature is turned on for Channel 1, and Channel 2 if Channel 2 is also enabled within the time slot. When the comparators are enabled, the TIA ceiling detection information is latched onto the INT_TCLN1_x bits in Register 0x0004 for Channel 1 and INT_TCLN2_x bits in Register 0x0005 for Channel 2 separately for each time slot. The interrupt output turns to 1 if either output exceeds the threshold voltage. Figure 50 illustrates the internal circuitry for TIA ceiling detection. VTIAO+ and VTIAO− represent the positive and negative outputs of the TIA, respectively, and VTH is the threshold voltage that the TIA output voltages are being compared to. TIA_CEIL_DETECT_EN_x VTH VTIAO+ INT_TCLN1_x (INT_TCLN2_x FOR CHANNEL 2) VTH 23297-050 Protecting Against TIA Saturation with TIA Ceiling Detection VTIAO– Figure 50. Schematic of TIA Ceiling Detection Circuit Due to different TIA reference voltage settings and different TIA gains, different amounts of input current can result in exceeding the threshold. Higher TIA reference voltage (TIA_VREF) and lower TIA gain increase the input current level at which the TIA output voltage exceeds the threshold voltage and, therefore, increase the range in terms of current. Table 26 shows the typical input current needed to trigger TIA ceiling detection for different TIA gain and different TIA_VREF while using 2 µs LED pulses in continuous connect mode. Table 26. Typical Input Currents to Trigger TIA Ceiling Detection TIA Gain (kΩ) 25 Input Current (µA) at TIA_VREF = 0.9 V 21.9 Input Current (µA) at TIA_VREF = 1.3 V 33.6 50 10.6 16.7 100 5.2 8.4 200 2.6 4.2 Figure 51 illustrates the trigger points for TIA ceiling detection with respect to different TIA_VREF values. Trigger points for different TIA gains can be found in Table 26. TIA OUTPUT VOLTAGE (V) 0,0 TIA _VREF = 0.9V TIA _VREF = 1.3V 23297-052 INPUT CURRENT (µA) Figure 51. Illustration of Trigger Points for TIA Ceiling Detection for TIA_VREF = 0.9 V and TIA_VREF = 1.3 V, Points Marked by Black Crosses Rev. 0 | Page 43 of 101 ADPD4100/ADPD4101 Data Sheet ECG MEASUREMENT WITH THE ADPD4100/ADPD4101 measurement regardless of whether low impedance wet electrodes or high impedance dry electrodes are used. The ADPD4100/ADPD4101 can be used for ECG applications with the simple addition of an external RC network consisting of two 500 kΩ resistors in series with the inputs and a 470 pF capacitor across the inputs, as shown in Figure 52. The electrical equivalent model for an electrode is shown together with the RC circuit, external to the ADPD4100/ADPD4101. In sleep float mode, the sensing capacitor floats all the time except the charge transfer, accumulating charge from the ECG signal. The accumulated charge is then transferred into the ADPD4100/ADPD4101 during a specified time slot for charge measurement. The device must be configured to float the inputs for the ECG during the preconditioning period and during sleep. The inputs are connected to the external capacitor only during the charge transfer. At all other times, the inputs for the ECG are floating, resulting in a float time of 1/tP, where tP is the sampling rate of the ADPD4100/ADPD4101. For example, the float time in sleep float mode is ~3.3 ms for the sampling rate of 300 Hz. The 500 kΩ resistors limit the current that can be injected into or pulled from the body in the case of shorted input pins. The 470 pF capacitor serves as the sensing capacitor for the ECG signal. The ECG signal is integrated onto the sensing capacitor. The value of this capacitor is chosen such that an acceptable SNR is achieved and the time constant of the RC network and the electrode skin contact allows sufficient charge accumulation on the sensing capacitor during the sampling period. The RC network of the 500 kΩ resistors and the 470 pF capacitor also acts as a low-pass filter, which helps reduce the high frequency noise due to electrode skin contact. For multilead ECG measurement, each lead requires a separate pair of inputs and the RC network of two 500 kΩ resistors and the 470 pF capacitor, as shown in Figure 52. RA SKIN/ELECTRODE INTERFACE RP VDC RS ADPD4100/ ADPD4101 500kΩ CP INx RIN INx RIN 470pF RP 500kΩ LA TIA RF VDC RS RF 23297-051 CP NOTES 1. RA is right arm. LA is left arm. Figure 52. Circuit for Measuring Single-Lead ECG with the ADPD4100/ADPD4101 Sleep Float Mode The ADPD4100/ADPD4101 ECG measurement operates in sleep float mode. Sleep float mode allows a robust ECG An advantage of using sleep float in ECG measurements is the longer charging time for the sensing capacitor. In sleep float mode, charge accumulation on the sensing capacitor happens during the sleep and during all other enabled time slots. The time slot associated with the sleep float mode is only used to transfer the charge from the sensing capacitor to the ADPD4100/ ADPD4101 amplifier. Sleep float mode also allows the use of other time slots for different sensor-based applications while ECG is being measured because the sensing capacitor floats regardless of the types of applications that the other time slots enable. Another advantage of using sleep float mode in ECG measurements is the reduced power consumption and noise. In sleep float mode, while the sensing capacitor is floating, it is disconnected from the amplifier and the amplifier is not powered. Therefore, sleep float mode reduces the power consumption by using the passive charging time to transfer the ECG signal from the body onto the sensing capacitor while the amplifier and all the later stages are powered down. The passive charging process of the sampling capacitor associated with sleep float mode also reduces the noise as the charging process is noise free. A timing diagram for sleep float mode is shown in Figure 53. The relevant register settings for sleep float mode are shown in Table 27. START OF TIME SLOT SEQUENCE TIMING WAKE TIME SLOT A (TS A) TS B TS X SLEEP WAKE MOD_WIDTH_x CONNECT/FLOAT MOD_OFFSET_x ACCUMULATED CHARGE ON CAPACITOR INTEGRATOR OUTPUT INTEG_OFFSET_x INTEG_WIDTH_x 23297-053 INTEGRATOR SEQUENCE ADC READ Figure 53. Sleep Float Mode Timing Diagram Rev. 0 | Page 44 of 101 Data Sheet ADPD4100/ADPD4101 Table 27. Relevant Configuration Registers for ECG Measurement Using Sleep Float Mode Group Signal Path Setup Float Mode Configuration 1 Time Slot A Register Address1 0x0100, Bits[13:12] 0x0100, Bits[11:10] 0x0101, Bits[8:0] 0x0101, Bits[15:12] 0x0102, Bits[15:0] Bit Field Name SAMPLE_TYPE_x INPUT_R_SELECT_x AFE_PATH_CFG_x PRE_WIDTH_x INPxx_x 0x0103, Bits[4:12] 0x0020, Bits[15:0] 0x0021, Bits[3:0] 0x0104, Bits[5:0] 0x0104, Bits[9:8] 0x0107, Bits[15:8] 0x0107, Bits[7:0] 0x0108, Bits[13:12] 0x0108, Bits[9:0] PRECON_x INP_SLEEP_xx PAIRxx TIA_GAIN_CHx_x AFE_TRIM_VREF_x NUM_INT_x NUM_REPEAT_x MOD_TYPE_x MIN_PERIOD_x 0x010A, Bits[4:0] 0x010A, Bits[10:8], Bits[14:12] 0x010B, Bits[12:0] INTEG_WIDTH_x CHx_AMP_DISABLE_x INTEG_OFFSET_x 0x010C, Bits[15:8] MOD_WIDTH_x 0x010C, Bits[7:0] MOD_OFFSET_x Description Leave at the default setting (0) for default sampling mode. Set to 0x0 for 500 Ω series input resistor. Set to 0x0E6 for TIA, integrator, and ADC. Bypass the BPF. Set to 0 to skip preconditioning period. Set to 0x7 to enable desired inputs connected to Channel 1 as defined in PAIRxx. Set to 0x0 to float the inputs during preconditioning. Set to 0x0 to float inputs during sleep. Set to 1 to configure selected inputs as a differential pair. Select TIA gain. Set to 0x2 to set TIA_VREF = 0.9 V. Set to 1 for a single integration per group of ADC conversions. Number of sequence repeats. Set to 0x1 for float type operation. Set to 0. Minimum period is not applicable to sleep float mode with a single integration. Integration time in µs. Set to MOD_WIDTH_x + 1. Set 0x010A, Bit 9 to 1 to power down BPF for Channel 1, Bit 13 to 1 to power down BPF for Channel 2 if Channel 2 is enabled. Integration sequence start time. Set to (MOD_OFFSET_x − INTEG_WIDTH_x – 250 ns). Sets width of connect pulse in 1 μs increments. MOD_WIDTH_x × NUM_REPEAT_x determines the time to transfer the charge from the external capacitor. Set MOD_WIDTH_x × NUM_REPEAT_x to approximately three time constants based on the time constant created between the external capacitor and the series input resistor (500 Ω or 6500 Ω based on setting of INPUT_R_SELECT_x). Sets start time of first connect pulse in 1 μs increments. Set to INTEG_WIDTH_x + 3. This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location for SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120. For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at Address 0x0160, and so on. Sleep Float Mode with Multiple Charge Transfers In ECG measurement, there can be a dc offset voltage on the order of tens or hundreds of millivolts or even greater when the electrode skin contact impedance is high and/or the electrodes are made of different materials with large half cell potential mismatch. The dc offset voltage uses a significant amount of the dynamic range available for the ECG measurement. The maximum amount of charge that the ADPD4100/ADPD4101 can accommodate for a single sample is ~7.5 pC with the 200 kΩ TIA gain setting. The maximum allowable charge per sample scales inversely with the gain of the TIA. The presence of a large dc offset voltage creates excess charge on the sensing capacitor, which can saturate the input to the ADC. For example, 100 mV of dc offset voltage adds an additional 47 pC of charge to the 470 pF capacitor. To accommodate the dc offset voltage without reducing the size of the sensing capacitor, the recommendation is to reduce the TIA gain to 50 kΩ or 100 kΩ, and to transfer the accumulated charge in multiple short pulses. For example, to transfer 47 pC of charge from the sensing capacitor to the integrator, the TIA gain of 50 kΩ can accommodate 30 pC of charge per sample. Setting RIN = 6.5 kΩ limits the rate of charge transfer into the TIA with an RC time constant of 2 × 6.5 kΩ × 470 pF = 6.1 μs. Using multiple short modulation pulses, which can be as short as 1 µs, allows a smaller percentage of the overall charge to be transferred and integrated per pulse to avoid saturating the TIA. Multiple transfer cycles are then used to fully discharge the sensing capacitor. The ADPD4100/ADPD4101 automatically sum the results of the transfer cycles and report the total charge. The timing for this mode is the same as shown in Figure 53 except the device is set up for multiple modulation pulses. Rev. 0 | Page 45 of 101 ADPD4100/ADPD4101 Data Sheet Recommended Configurations for ECG Measurement The following is one of the recommended configurations for ECG measurement if the dc offset voltage (VDC, see Figure 52) is negligible or low, less than ±30 mV. #ADPD4100 ECG Measurement with high DC offset 0009 0080 # 32MHz oscillator trim 000B 02B2 # 1MHz oscillator trim #ADPD4100 ECG Measurement with small DC offset 000D 0D05 # Sampling rate 300 Hz 000F 0006 # 1MHz low frequency oscillator 0009 0080 # 32MHz oscillator trim 0010 0000 # Timeslot A enabled 000B 02B2 # 1MHz oscillator trim 0020 2220 # Float inputs 1&2 during sleep 000D 0D05 # Sampling rate 300 Hz 000F 0006 # 1MHz low frequency oscillator 0021 0001 # IN1/IN2 configured as a differential pair 0010 0000 # Timeslot A enabled 0020 2220 # Float input 1&2 during sleep # Timeslot configuration # ### Timeslot A - Sleep float mode ECG with multiple charge transfers 0021 0001 # IN1/IN2 configured as a differential pair 0100 0400 # Timeslot configuration # ### Timeslot A - Sleep float mode ECG with multiple charge transfers 0100 0000 # Input resistor 500 Ω 0101 00E6 # skip preconditioning, bandpass filter bypassed # Input resistor 6500 Ω 0101 00E6 # skip preconditioning, bandpass filter bypassed 0102 0007 channel 1 # IN1&IN2 differential pair to 0103 0000 # float during preconditioning 0104 02C3 # TIA gain 25k, Vref = 0.88V 0105 0000 # LEDs off 0106 0000 # LEDs off 0102 0007 channel 1 # IN1&IN2 differential pair to 0103 0000 # float during preconditioning 0107 010C # 12 pulses 0104 02C1 # TIA gain 100k, Vref = 0.88V 0108 1000 # float mode, minimum period 0105 0000 # LEDs off 0106 0000 # LEDs off 010A 0203 # Integrator pulse width, bandpass filter powered down 0107 0102 # 2 pulses 0108 1000 # float mode, minimum period 010A 0203 # Integrator pulse width, bandpass filter powered down 010B 01A0 offset # Integrator pulse timing 010C 0210 offset # Modulation pulse width and 010D 0000 # Chopping mode disabled 010E 0000 # no ADC offset # no ADC offset 010B 01A0 offset # Integrator pulse timing 010C 0210 offset # Modulation pulse width and 010F 0000 010D 0000 # Chopping mode disabled 0110 0003 # Configure number of bytes written to the registers 010E 0000 # no ADC offset 010F 0000 # no ADC offset 0110 0003 # Configure number of bytes written to the registers If the dc offset voltage is large, use the following recommended configuration, which can handle up to ±450 mV of dc offset voltage. There are only three register setting changes, and the rest is the same as the previous configuration. The input resistor is changed to 6500 Ω by setting INPUT_R_SELECT_x to 1, TIA gain is reduced to 25 kΩ by setting TIA_GAIN_CH1_x to 3, and the number of modulation pulses is increased to 12 by setting NUM_REPEAT_x to 12. To account for the cases where dc offset voltage is moderate, different configurations can be utilized. In general, higher dc offset voltage cases require low TIA gain and 6500 Ω input resistor selection, whereas lower dc offset voltage cases can use higher TIA gain and 500 Ω input resistor selection to achieve the lowest noise performance. In addition, NUM_REPEAT_x can be increased to allow the full discharge of the sampling capacitor. Table 28 summarizes the relevant registers for handling different dc offset voltage levels. Rev. 0 | Page 46 of 101 Data Sheet ADPD4100/ADPD4101 Improving SNR with Integrator Chopping in ECG Measurements ECG and three-electrode lead off detection are measured as follows: Integrator chopping can also improve SNR in ECG measurements with the sleep float mode by eliminating low frequency noise content. The procedure to enable integrator chop mode is the same as explained previously in the Improving SNR Using Integrator Chopping section. However, ECG measurements with integrator chopping require additional considerations. The sign of the dc offset voltages in Figure 52 can be positive or negative. When the sign of the net dc offset voltage is negative, integrator chop mode can result in clipping of the ECG signal. To prevent clipping of the ECG signal, lit data must be used. Figure 23 shows the datapath. In Figure 23, lit and dark values can be optionally written to FIFO. This option allows the use of negative signal values by writing both lit and dark values to the FIFO, and the user can perform a signed subtract in external processing of the data to calculate the signal value. Therefore, integrator chopping can be used regardless of the sign of net dc offset voltage. 1. Lead Off Detection To perform a lead off detection measurement, the ADPD4100/ ADPD4101 measure the impedance of the electrode skin contacts to determine whether one or more of the electrodes are not making contact with the skin. Lead off measurement can be performed in two different ways based on the number of electrodes used. Three-Electrode Lead Off Measurement The three-electrode configuration requires a third electrode connected to an unused VCx pin to provide a stimulus to the body. The RC network of the ECG measurement is bypassed by wiring the electrodes directly to a separate set of inputs through 25 kΩ resistors. The response from the stimulus is measured from this separate set of inputs. Three-electrode lead off measurement is capable of determining which electrode is loose or has lost the contact with the skin. Figure 54 shows the circuit for the three-electrode lead off detection measurement. RBODY is the resistance of the body. ADPD4100/ ADPD4101 25kΩ E1 47pF 500kΩ IN3 IN1 CH1 RBODY RBODY CHANNEL 1 CHANNEL 2 470pF 500kΩ IN2 25kΩ IN4 CH2 47pF 47pF 25kΩ VC2 E3 Figure 55 illustrates a representation of ADC output changes in different cases for leadoff condition. In Figure 55, before Time tA, both ECG electrodes make contact with the skin. At Time tA, E1 is disconnected from the skin. The time between tA and tB shows the case where only E1 is disconnected from the skin. At Time tB, E1 starts to make contact with skin and output of the two channels go to their initial levels. At Time tC, only E2 is disconnected from the skin and it stays disconnected until Time tD. At Time tE, E2 starts making contact with the skin again. At Time tE, both E1 and E2 are disconnected from the skin, and they stay disconnected until Time tF. At Time tF, both E1 and E2 start making contact with the skin. Therefore, lead off condition is detected in all electrode connection cases, and three-electrode lead off measurement detects and distinguishes all the different cases. The level of actual ADC outputs associated with Channel 1 and Channel 2 may differ because the type and placement of the electrodes may be different in each case, and RBODY differs from person to person, which affects the amount of current that each channel receives. ADC OUTPUT E2 When both ECG electrodes, E1 and E2, are making contact with the skin during the measurement, an ECG signal is visible. The impedance measurements of the E1 and E2 electrodes have some readout indicating that contact is being made with the skin and current is flowing into the ADPD4100/ADPD4101 through the body of low impedance when the stimulus is applied. When either ECG electrode stops making contact with the skin or is loose, there is no ECG signal in the acquired trace. When contact between both electrodes and the skin is restored, the ECG signal appears immediately. Because two inputs and two channels are allocated to detect leadoff condition for two electrodes, this measurement method can determine if one electrode loses contact with skin or both electrodes lose contact. This measurement can also detect which one of the electrodes loses contact with skin if only one electrode loses contact. VC2 23297-054 RBODY 2. ECG is measured in Time Slot A as defined in the ECG Measurement with the ADPD4100/ADPD4101 section. Lead off detection of the ECG electrodes is taken in Time Slot B by making simultaneous single-ended impedance measurements of ECG Electrode 1 (E1) and Electrode 2 (E2) into Channel 1 and Channel 2, respectively. tA tB tC tD TIME tE tF 23297-055 Figure 54. Circuit Used for Three-Electrode Lead Off Detection Measurement Figure 55. Graph of Three-Electrode Lead Off Measurement Rev. 0 | Page 47 of 101 ADPD4100/ADPD4101 Data Sheet Table 28. Relevant Register Settings to Handle Different DC Offset Voltage Levels in ECG Measurements Time Slot A Register Address1 0x0100, Bits[11:10] Bit Field Name INPUT_R_SELECT_x 0x0104, Bits[5:0] 0x0107, Bits[7:0] TIA_GAIN_CHx_x NUM_REPEAT_x 1 Description Set to 0x0 for 500 Ω series input resistor. Set to 0x1 for 6500 Ω series input resistor. Select TIA gain. Number of sequence repeats. This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location for SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120. For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at Address 0x0160, and so on. The following configuration enables low dc offset ECG measurement in Time Slot A and three-electrode lead off detection in Time Slot B: 0110 0003 # Configure number of bytes written to the registers # ADPD4100 ECG Measurement with small DC offset in Timeslot A and Three-Electrode Lead-Off Measurement in Timeslot B # Timeslot B – Three-Electrode Lead-Off Detection on IN3/4 0120 4000 # CH2 active 0009 0080 # 32MHz oscillator trim # 1MHz oscillator trim 0121 40DA BPF-INT-ADC # 8 µs preconditioning, TIA- 000B 02B2 000D 0D05 # Sampling rate 300 Hz 0122 0050 # IN3 to CH1, IN4 to CH2 000F 0006 # 1MHz low frequency oscillator 0010 0100 # Timeslot A and B enabled 0123 5A45 # Precondition to TIA_VREF, pulse VC2_VREF by 215 mV 0020 2200 # Float input 1&2 and 3&4 during sleep 0124 E212 # 50k TIA GAIN both channels, TIA_VREF=0.88V 0021 0001 # IN1/IN2 configured as a differential pair 0125 0000 # LEDs off 0126 0000 # LEDs off # 16 pulses, single # Timeslot configuration # 0127 0110 integration # ADPD4100 ECG Measurement with small DC offset 0128 0000 # continuous TIA connection 012A 0003 # Integrator pulse width 0100 0000 012B 0216 offset # Integrator pulse timing # Modulation pulse width and # Input resistor 500 Ω 0101 00E6 # skip preconditioning, bandpass filter bypassed 0102 0007 channel 1 # IN1&IN2 differential pair to 012C 0210 offset 012D 0000 # Integrator chopping off 0103 0000 # float during preconditioning 012E 0000 # No ADC Offset 0104 02C1 0.88V # TIA gain 100k, TIA_VREF = 012F 0000 # No ADC Offset 0105 0000 # LEDs off 0130 0003 # Configure number of bytes written to the registers 0106 0000 # LEDs off Two-Electrode Lead Off Measurement 0107 0102 # 2 pulses 0108 1000 # float mode, minimum period This measurement method can detect the lead off condition without requiring a third electrode at the expense of not being able to differentiate if one electrode or both electrodes have lost contact with skin. Two-electrode lead off measurement is useful in cases where either a separate electrode is not available, a smaller form factor with less components is desired, or the power requirement is tighter because power consumption of two-electrode lead off measurement is lower. In two-electrode lead off measurement, the stimulus from an unused VCx pin to the body can be provided through one of the ECG electrodes. Only one separate input is used to detect the lead off condition through the impedance measurement. 010A 0203 # Integrator pulse width, bandpass filter powered down 010B 01A0 offset # Integrator pulse timing 010C 0210 offset # Modulation pulse width and 010D 0000 # Chopping mode disabled 010E 0000 # no ADC offset 010F 0000 # no ADC offset Rev. 0 | Page 48 of 101 Data Sheet ADPD4100/ADPD4101 ADPD4100/ ADPD4101 25kΩ E1 RBODY 47pF 500kΩ IN3 tC tD tE tF Figure 57. Graph of Two-Electrode Lead Off Measurement IN2 The following configuration enables low dc offset ECG measurement in Time Slot A and two-electrode lead off detection in Time Slot B: VC2 VC2 23297-056 E2 47pF 25kΩ tB TIME CH1 470pF 500kΩ tA IN1 23297-057 ADC OUTPUT Figure 56 shows a circuit that can be used for the two-electrode lead off detection measurement. RBODY is the resistance of the body. Figure 56. Circuit Used for Two-Electrode Lead Off Detection Measurement # ADPD4100 ECG Measurement with small DC offset in Timeslot A and Two-Electrode Lead-Off Measurement in Timeslot B ECG and two-electrode lead off detection are measured as follows: 0009 0080 # 32MHz oscillator trim 000B 02B2 # 1MHz oscillator trim 1. 000D 0D05 # Sampling rate 300 Hz 000F 0006 # 1MHz low frequency oscillator 0010 0100 # Timeslot A and B enabled 2. ECG is measured in Time Slot A as defined in the ECG Measurement with the ADPD4100/ADPD4101 section. Lead off detection of the ECG electrodes is taken in Time Slot B by making a single-ended measurement for impedance between the E1 and E2 ECG electrodes into Channel 1, as shown in Figure 56. When the ECG electrodes are making contact with the skin during the measurement, an ECG signal and a value for the impedance measurement indicating that some current is flowing through RBODY are visible. When either electrode stops making contact with the skin, there is no ECG signal, and a much smaller value at the ADC output is observed for the impedance measurement indicating that there is no current flowing through the low impedance RBODY. When both electrode skin contacts are restored, the ECG signal appears immediately. Because only one input and one channel are allocated to detect lead off condition for two electrodes, the impedance measurement shows a much smaller value when either electrode loses contact with skin and, thus, it is a common indicator for both electrodes. Figure 57 illustrates a representation of ADC output changes in different cases. Before Time tA, both ECG electrodes make contact with the skin. At Time tA, only E1 is disconnected from the skin. At Time tB, it starts to make contact with the skin again and both electrodes make contact until tC. At tC, only E2 is disconnected from the skin and it stays disconnected until tD. At tD, E2 starts making contact with the skin again, and they stay connected until tE. At tE, both electrodes are disconnected. At tF, both electrodes start making contact again. Therefore, lead off detection measurement can be achieved for all cases, and lead off condition is represented by lower ADC output for the impedance measurement. 0020 2200 # Float input 1&2 and 3&4 during sleep 0021 0001 # IN1/IN2 configured as a differential pair # Timeslot configuration # # ADPD4100 ECG Measurement with small DC offset 0100 0000 # Input resistor 500 Ω 0101 00E6 # skip preconditioning, bandpass filter bypassed 0102 0007 channel 1 # IN1&IN2 differential pair to 0103 0000 # float during preconditioning 0104 02C1 0.88V # TIA gain 100kΩ, TIA_VREF = 0105 0000 # LEDs off 0106 0000 # LEDs off 0107 0102 # 2 pulses 0108 1000 # float mode, minimum period 010A 0203 # Integrator pulse width, bandpass filter powered down 010B 01A0 offset # Integrator pulse timing 010C 0210 offset # Modulation pulse width and 010D 0000 # Chopping mode disabled 010E 0000 # no ADC offset 010F 0000 # no ADC offset Rev. 0 | Page 49 of 101 ADPD4100/ADPD4101 Data Sheet 0110 0003 # Configure number of bytes written to the registers 0126 0000 # LEDs off 0127 0110 integration # 16 pulses, single # Timeslot B – Two-Electrode Lead-Off Detection on IN3 0128 0000 # continuous TIA connection 012A 0003 # Integrator pulse width 0120 0000 # 1 channel enabled # 8us precondition, TIA-BPF- 012B 0216 offset # Integrator pulse timing 0121 40DA INT-ADC 012C 0210 offset # Modulation pulse width and 012D 0000 # Integrator chopping off 012E 0000 # No ADC Offset 012F 0000 # No ADC Offset 0122 0010 # IN3 to CH1, IN4 disconnected 0123 5A45 # Precondition to TIA_VREF, pulse VC2_VREF by 215 mV 0124 E212 # 50 kΩ TIA GAIN both channels, TIA_VREF=0.88V 0125 0000 0130 0003 # Configure number of bytes written to the registers # LEDs off Rev. 0 | Page 50 of 101 Data Sheet ADPD4100/ADPD4101 REGISTER MAP Table 29. ADPD4100 Register Map Summary Reg 0x0000 Name FIFO_ STATUS 0x0001 INT_ STATUS_ DATA 0x0002 0x0003 0x0004 0x0005 INT_ STATUS_ LEV0 INT_ STATUS_ LEV1 [15:8] Bit 13 Bit 12 Bit 11 Bit 5 Bit 4 Bit 3 INT_FIFO_ Reserved OFLOW FIFO_BYTE_COUNT[7:0] INT_FIFO_TH Reserved INT_ DATA_L INT_DATA_H INT_DATA_G INT_ INT_ INT_ DATA_F DATA_E DATA_D Reserved INT_LEV0_L [7:0] INT_LEV0_H Bits [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] INT_ [15:8] STATUS_TC1 [7:0] INT_ [15:8] STATUS_TC2 [7:0] 0x0006 FIFO_TH 0x0007 INT_ACLEAR [15:8] [7:0] [15:8] [7:0] 0x0008 CHIP_ID 0x0009 OSC32M 0x000A OSC32M_ CAL 0x000B OSC1M [7:0] [15:8] 0x000C OSC32K [7:0] [15:8] 0x000D TS_FREQ 0x000E TS_FREQH 0x000F SYS_CTL 0x0010 OPMODE 0x0011 STAMP_L Bit 15 Bit 7 CLEAR_FIFO [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] INT_LEV1_H INT_ TCLN1_H INT_ TCLN2_H Bit 14 Bit 6 INT_FIFO_ UFLOW INT_LEV0_G INT_ LEV0_F Reserved INT_LEV0_E INT_LEV0_D INT_LEV1_G INT_ LEV1_F Reserved INT_LEV1_E INT_LEV1_D INT_ INT_ TCLN1_F TCLN1_G Reserved INT_ TCLN1_E INT_ TCLN2_G INT_ACLEAR_ FIFO INT_ACLEAR_ INT_ DATA_H ACLEAR_ DATA_G OSC_32M_ CAL_START INT_LEV1_L INT_TCLN1_L INT_ TCLN1_D INT_TCLN2_L Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 FIFO_BYTE_COUNT[10:8] INT_ DATA_K INT_ DATA_C INT_ LEV0_K INT_ LEV0_C INT_ LEV1_K INT_ LEV1_C INT_ TCLN1_K INT_ TCLN1_C INT_ TCLN2_K INT_ TCLN2_C INT_ INT_ INT_ TCLN2_D TCLN2_F TCLN2_E Reserved FIFO_TH[7:0] Reserved INT_ INT_ ACLEAR_ ACLEAR_ DATA_L DATA_K INT_ INT_ INT_ INT_ ACLEAR_ ACLEAR_ ACLEAR_ ACLEAR_ DATA_F DATA_E DATA_D DATA_C Version CHIP_ID Reserved OSC_32M_FREQ_ADJ[7:0] OSC_32M_CAL_COUNT[14:8] OSC_32M_CAL_COUNT[7:0] Reserved CLK_CAL_ ENA INT_ INT_ DATA_J DATA_I INT_ INT_ DATA_B DATA_A INT_ INT_ LEV0_J LEV0_I INT_ INT_ LEV0_B LEV0_A INT_ INT_ LEV1_J LEV1_I INT_ INT_ LEV1_B LEV1_A INT_ INT_ TCLN1_J TCLN1_I INT_ INT_ TCLN1_B TCLN1_A INT_ INT_ TCLN2_J TCLN2_I INT_ INT_ TCLN2_B TCLN2_A FIFO_TH[9:8] INT_ ACLEAR_ DATA_J INT_ ACLEAR_ DATA_B INT_ ACLEAR_ DATA_I INT_ ACLEAR_ DATA_A OSC_1M_FREQ_ ADJ[9:8] OSC_1M_FREQ_ADJ[7:0] Reserved CAPTURE_ TIMESTAMP Reserved Reserved SW_RESET ALT_CLK_GPIO[1:0] Reserved OSC_32K_ADJUST[5:0] TIMESLOT_PERIOD_L[15:8] TIMESLOT_PERIOD_L[7:0] Reserved TIMESLOT_PERIOD_H[6:0] Reserved ALT_CLOCKS[1:0] Reserved LFOSC_ OSC_ OSC_ SEL 1M_EN 32K_EN TIMESLOT_EN[3:0] Reserved OP_MODE TIMESTAMP_COUNT_L[15:8] TIMESTAMP_COUNT_L[7:0] Rev. 0 | Page 51 of 101 Reset 0x0000 R/W R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x8FFF R/W 0x02C2 R 0x0080 R/W 0x0000 R/W 0x02B2 R/W 0x0012 R/W 0x2710 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R ADPD4100/ADPD4101 Reg 0x0012 0x0013 0x0014 Name STAMP_H Bits [15:8] [7:0] STAMPDELTA [15:8] [7:0] INT_ENABLE_ [15:8] XD [7:0] 0x0015 INT_ENABLE_ [15:8] YD [7:0] 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D 0x001E 0x0020 INT_ENABLE_ [15:8] XL0 [7:0] INT_ENABLE_ [15:8] XL1 [7:0] INT_ENABLE_ [15:8] XT1 [7:0] INT_ENABLE_ [15:8] XT2 [7:0] INT_ENABLE_ [15:8] YL0 [7:0] INT_ENABLE_ [15:8] YL1 [7:0] INT_ENABLE_ [15:8] YT1 [7:0] INT_ENABLE_ [15:8] YT2 [7:0] FIFO_ STATUS_ BYTES Bit 15 Bit 7 INTX_EN_ FIFO_TH INTX_EN_ DATA_H INTY_EN_ FIFO_TH INTY_EN_ DATA_H INTX_EN_ LEV0_H INTX_EN_ LEV1_H INTX_EN_ TCLN1_H INTX_EN_ TCLN2_H INTY_EN_ LEV0_H INTY_EN_ LEV1_H INTY _EN_ TCLN1_H INTY_EN_ TCLN2_H [15:8] [7:0] 0x0022 INPUT_SLEEP [15:8] [7:0] INPUT_CFG [15:8] [7:0] GPIO_CFG [15:8] 0x0023 GPIO01 0x0021 Data Sheet [7:0] [15:8] [7:0] ENA_ STAT_TC2 Bit 14 Bit 6 Bit 12 Bit 11 Bit 4 Bit 3 TIMESTAMP_COUNT_H[15:8] TIMESTAMP_COUNT_H[7:0] TIMESTAMP_SLOT_DELTA[15:8] TIMESTAMP_SLOT_DELTA[7:0] INTX_EN_ INTX_EN_ Reserved INTX_EN_ DATA_L FIFO_ FIFO_ UFLOW OFLOW INTX_EN_ INTX_EN_ INTX_EN_ INTX_EN_ DATA_G DATA_F DATA_E DATA_D INTY_EN_ INTY_EN_ Reserved INTY_EN_ FIFO_ DATA_L FIFO_ UFLOW OFLOW INTY_EN_ INTY_EN_ INTY_EN_ INTY_EN_ DATA_G DATA_F DATA_E DATA_D Reserved INTX_EN_ LEV0_L INTX_EN_ INTX_EN_ INTX_EN_ INTX_EN_ LEV0_G LEV0_F LEV0_E LEV0_D Reserved INTX_EN_ LEV1_L INTX_EN_ INTX_EN_ INTX_EN_ INTX_EN_ LEV1_G LEV1_F LEV1_E LEV1_D Reserved INTX_EN_ TCLN1_L INTX_EN_ INTX_EN_ INTX_EN_ INTX_EN_ TCLN1_G TCLN1_F TCLN1_E TCLN1_D Reserved INTX_EN_ TCLN2_L INTX_EN_ INTX_EN_ INTX_EN_ INTX_EN_ TCLN2_G TCLN2_F TCLN2_E TCLN2_D Reserved INTY_EN_ LEV0_L INTY_EN_ INTY_EN_ INTY_EN_ INTY_EN_ LEV0_G LEV0_F LEV0_E LEV0_D Reserved INTY_EN_ LEV1_L INTY_EN_ INTY_EN_ INTY_EN_ INTY_EN_ LEV1_G LEV1_F LEV1_E LEV1_D Reserved INTY_EN_ TCLN1_L INTY _EN_ INTY_EN_ INTY_EN_ INTY_EN_ TCLN1_G TCLN1_F TCLN1_E TCLN1_D Reserved INTY_EN_ TCLN2_L INTY_EN_ INTY_EN_ INTY_EN_ INTY_EN_ TCLN2_G TCLN2_F TCLN2_E TCLN2_D Reserved ENA_ STAT_TC1 Bit 13 Bit 5 ENA_ STAT_LX ENA_ STAT_L1 ENA_ STAT_L0 INP_SLEEP_78[3:0] INP_SLEEP_34[3:0] VC2_SLEEP[1:0] GPIO_SLEW[1:0] GPIO_PIN_CFG2[1:0] Reserved Reserved Bit 10 Bit 2 Bit 9 Bit 1 INTX_EN_ INTX_EN_ INTX_EN_ DATA_K DATA_J DATA_I R/W R 0x0000 R 0x0000 R/W INTX_EN_ DATA_B INTY_EN_ DATA_J INTX_EN_ DATA_A INTY_ EN_ 0x0000 DATA_I INTY_EN_ DATA_C INTX_EN_ LEV0_K INTX_EN_ LEV0_C INTX_EN_ LEV1_K INTX_EN_ LEV1_C INTX_EN_ TCLN1_K INTX_EN_ TCLN1_C INTX_EN_ TCLN2_K INTX_EN_ TCLN2_C INTY_EN_ LEV0_K INTY_EN_ LEV0_C INTY_EN_ LEV1_K INTY_EN_ LEV1_C INTY _EN_ TCLN1_K INTY_EN_ TCLN1_C INTY_EN_ TCLN2_K INTY_EN_ TCLN2_C INTY_EN_ DATA_B INTX_EN_ LEV0_J INTX_EN_ LEV0_B INTX_EN_ LEV1_J INTX_EN_ LEV1_B INTX_EN_ TCLN1_J INTX_EN_ TCLN1_B INTX_EN_ TCLN2_J INTX_EN_ TCLN2_B INTY_EN_ LEV0_J INTY_EN_ LEV0_B INTY_EN_ LEV1_J INTY_EN_ LEV1_B INTY _EN_ TCLN1_J INTY_EN_ TCLN1_B INTY_EN_ TCLN2_J INTY_EN_ TCLN2_B INTY_EN_ DATA_A INTX_EN_ LEV0_I INTX_EN_ LEV0_A INTX_EN_ LEV1_I INTX_EN_ LEV1_A INTX_EN_ TCLN1_I INTX_EN_ TCLN1_A INTX_EN_ TCLN2_I INTX_EN_ TCLN2_A INTY_EN_ LEV0_I INTY_EN_ LEV0_A INTY_EN_ LEV1_I INTY_EN_ LEV1_A INTY _EN_ TCLN1_I INTY_EN_ TCLN1_A INTY_EN_ TCLN2_I INTY_EN_ TCLN2_A ENA_ STAT_TCX ENA_ STAT_ SUM R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 PAIR12 GPIO_PIN_ 0x0000 CFG2[2] GPIO_PIN_CFG0[2:0] 0x0000 R/W ENA_ STAT_D2 ENA_ STAT_D1 Reserved VC1_SLEEP[1:0] PAIR78 PAIR56 PAIR34 GPIO_DRV[1:0] GPIO_PIN_CFG3[2:0] Rev. 0 | Page 52 of 101 Reset 0x0000 INTX_EN_ DATA_C INTY_EN_ DATA_K INP_SLEEP_56[3:0] INP_SLEEP_12[3:0] GPIO_PIN_CFG1[2:0] GPIOOUT1[6:0] GPIOOUT0[6:0] Bit 8 Bit 0 R/W R/W Data Sheet Reg 0x0024 Name GPIO23 0x0025 GPIO_IN 0x0026 GPIO_EXT ADPD4100/ADPD4101 Bits [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] 0x002E DATA_ HOLD_FLAG [15:8] [7:0] 0x002F FIFO_DATA [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] 0x0030 SIGNAL1_L_A 0x0031 SIGNAL1_H_A 0x0032 SIGNAL2_L_A 0x0033 SIGNAL2_H_A 0x0034 DARK1_L_A 0x0035 DARK1_H_A 0x0036 DARK2_L_A 0x0037 DARK2_H_A 0x0038 SIGNAL1_L_B 0x0039 SIGNAL1_H_B 0x003A SIGNAL2_L_B 0x003B SIGNAL2_H_B 0x003C DARK1_L_B 0x003D DARK1_H_B 0x003E DARK2_L_B 0x003F DARK2_H_B 0x0040 SIGNAL1_L_C 0x0041 SIGNAL1_H_C 0x0042 SIGNAL2_L_C 0x0043 [7:0] SIGNAL2_H_C [15:8] [7:0] Bit 15 Bit 7 Reserved Reserved Bit 14 Bit 6 Bit 13 Bit 5 Reserved Bit 12 Bit 4 Bit 11 Bit 10 Bit 9 Bit 3 Bit 2 Bit 1 GPIOOUT3[6:0] GPIOOUT2[6:0] Reserved GPIO_INPUT[3:0] Reserved TIMESTAMP_ TIMESTAMP TIMESTAMP_GPIO[1:0] Reserved INV _ALWAYS_ EN Reserved HOLD_ REGS_L HOLD_ HOLD_ HOLD_ HOLD_ HOLD_ REGS_H REGS_G REGS_F REGS_E REGS_D FIFO_DATA[15:8] FIFO_DATA[7:0] SIGNAL1_L_A[15:8] SIGNAL1_L_A[7:0] SIGNAL1_H_A[15:8] SIGNAL1_H_A[7:0] SIGNAL2_L_A[15:8] SIGNAL2_L_A[7:0] SIGNAL2_H_A[15:8] SIGNAL2_H_A[7:0] DARK1_L_A[15:8] DARK1_L_A[7:0] DARK1_H_A[15:8] DARK1_H_A[7:0] DARK2_L_A[15:8] DARK2_L_A[7:0] DARK2_H_A[15:8] DARK2_H_A[7:0] SIGNAL1_L_B[15:8] SIGNAL1_L_B[7:0] SIGNAL1_H_B[15:8] SIGNAL1_H_B[7:0] SIGNAL2_L_B[15:8] SIGNAL2_L_B[7:0] SIGNAL2_H_B[15:8] SIGNAL2_H_B[7:0] DARK1_L_B[15:8] DARK1_L_B[7:0] DARK1_H_B[15:8] DARK1_H_B[7:0] DARK2_L_B[15:8] DARK2_L_B[7:0] DARK2_H_B[15:8] DARK2_H_B[7:0] SIGNAL1_L_C[15:8] SIGNAL1_L_C[7:0] SIGNAL1_H_C[15:8] SIGNAL1_H_C[7:0] SIGNAL2_L_C[15:8] SIGNAL2_L_C[7:0] SIGNAL2_H_C[15:8] SIGNAL2_H_C[7:0] Rev. 0 | Page 53 of 101 EXT_ SYNC_EN HOLD_ REGS_K HOLD_ REGS_C Bit 8 Bit 0 Reset 0x0000 R/W R/W 0x0000 R TS_GPIO_ 0x0000 SLEEP EXT_SYNC_GPIO[1:0] HOLD_ REGS_J HOLD_ REGS_B HOLD_ REGS_I HOLD_ REGS_A R/W 0x0000 R/W 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R ADPD4100/ADPD4101 Reg 0x0044 Name DARK1_L_C 0x0045 DARK1_H_C 0x0046 DARK2_L_C 0x0047 DARK2_H_C 0x0048 SIGNAL1_L_D 0x0049 SIGNAL1_H_D 0x004A SIGNAL2_L_D 0x004B SIGNAL2_H_D 0x004C DARK1_L_D 0x004D DARK1_H_D 0x004E DARK2_L_D 0x004F DARK2_H_D 0x0050 SIGNAL1_L_E 0x0051 SIGNAL1_H_E 0x0052 SIGNAL2_L_E 0x0053 SIGNAL2_H_E 0x0054 DARK1_L_E 0x0055 DARK1_H_E 0x0056 DARK2_L_E 0x0057 DARK2_H_E 0x0058 SIGNAL1_L_F 0x0059 SIGNAL1_H_F 0x005A SIGNAL2_L_F 0x005B SIGNAL2_H_F 0x005C DARK1_L_F 0x005D DARK1_H_F 0x005E DARK2_L_F Bits [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] Bit 15 Bit 7 Data Sheet Bit 14 Bit 6 Bit 13 Bit 5 Bit 12 Bit 11 Bit 4 Bit 3 DARK1_L_C[15:8] DARK1_L_C[7:0] DARK1_H_C[15:8] DARK1_H_C[7:0] DARK2_L_C[15:8] DARK2_L_C[7:0] DARK2_H_C[15:8] DARK2_H_C[7:0] SIGNAL1_L_D[15:8] SIGNAL1_L_D[7:0] SIGNAL1_H_D[15:8] SIGNAL1_H_D[7:0] SIGNAL2_L_D[15:8] SIGNAL2_L_D[7:0] SIGNAL2_H_D[15:8] SIGNAL2_H_D[7:0] DARK1_L_D[15:8] DARK1_L_D[7:0] DARK1_H_D[15:8] DARK1_H_D[7:0] DARK2_L_D[15:8] DARK2_L_D[7:0] DARK2_H_D[15:8] DARK2_H_D[7:0] SIGNAL1_L_E[15:8] SIGNAL1_L_E[7:0] SIGNAL1_H_E[15:8] SIGNAL1_H_E[7:0] SIGNAL2_L_E[15:8] SIGNAL2_L_E[7:0] SIGNAL2_H_E[15:8] SIGNAL2_H_E[7:0] DARK1_L_E[15:8] DARK1_L_E[7:0] DARK1_H_E[15:8] DARK1_H_E[7:0] DARK2_L_E[15:8] DARK2_L_E[7:0] DARK2_H_E[15:8] DARK2_H_E[7:0] SIGNAL1_L_F[15:8] SIGNAL1_L_F[7:0] SIGNAL1_H_F[15:8] SIGNAL1_H_F[7:0] SIGNAL2_L_F[15:8] SIGNAL2_L_F[7:0] SIGNAL2_H_F[15:8] SIGNAL2_H_F[7:0] DARK1_L_F[15:8] DARK1_L_F[7:0] DARK1_H_F[15:8] DARK1_H_F[7:0] DARK2_L_F[15:8] DARK2_L_F[7:0] Rev. 0 | Page 54 of 101 Bit 10 Bit 2 Bit 9 Bit 1 Bit 8 Bit 0 Reset 0x0000 R/W R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R Data Sheet Reg 0x005F Name DARK2_H_F 0x0060 SIGNAL1_L_G 0x0061 SIGNAL1_H_G 0x0062 SIGNAL2_L_G 0x0063 SIGNAL2_H_G 0x0064 DARK1_L_G 0x0065 DARK1_H_G 0x0066 DARK2_L_G 0x0067 DARK2_H_G 0x0068 SIGNAL1_L_H 0x0069 SIGNAL1_H_H 0x006A SIGNAL2_L_H 0x006B SIGNAL2_H_H 0x006C DARK1_L_H 0x006D DARK1_H_H 0x006E DARK2_L_H 0x006F DARK2_H_H 0x0070 SIGNAL1_L_I 0x0071 SIGNAL1_H_I 0x0072 SIGNAL2_L_I 0x0073 SIGNAL2_H_I 0x0074 DARK1_L_I 0x0075 DARK1_H_I 0x0076 DARK2_L_I 0x0077 DARK2_H_I 0x0078 SIGNAL1_L_J 0x0079 SIGNAL1_H_J ADPD4100/ADPD4101 Bits [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] Bit 15 Bit 7 Bit 14 Bit 6 Bit 13 Bit 5 Bit 12 Bit 11 Bit 4 Bit 3 DARK2_H_F[15:8] DARK2_H_F[7:0] SIGNAL1_L_G[15:8] SIGNAL1_L_G[7:0] SIGNAL1_H_G[15:8] SIGNAL1_H_G[7:0] SIGNAL2_L_G[15:8] SIGNAL2_L_G[7:0] SIGNAL2_H_G[15:8] SIGNAL2_H_G[7:0] DARK1_L_G[15:8] DARK1_L_G[7:0] DARK1_H_G[15:8] DARK1_H_G[7:0] DARK2_L_G[15:8] DARK2_L_G[7:0] DARK2_H_G[15:8] DARK2_H_G[7:0] SIGNAL1_L_H[15:8] SIGNAL1_L_H[7:0] SIGNAL1_H_H[15:8] SIGNAL1_H_H[7:0] SIGNAL2_L_H[15:8] SIGNAL2_L_H[7:0] SIGNAL2_H_H[15:8] SIGNAL2_H_H[7:0] DARK1_L_H[15:8] DARK1_L_H[7:0] DARK1_H_H[15:8] DARK1_H_H[7:0] DARK2_L_H[15:8] DARK2_L_H[7:0] DARK2_H_H[15:8] DARK2_H_H[7:0] SIGNAL1_L_I[15:8] SIGNAL1_L_I[7:0] SIGNAL1_H_I[15:8] SIGNAL1_H_I[7:0] SIGNAL2_L_I[15:8] SIGNAL2_L_I[7:0] SIGNAL2_H_I[15:8] SIGNAL2_H_I[7:0] DARK1_L_I[15:8] DARK1_L_I[7:0] DARK1_H_I[15:8] DARK1_H_I[7:0] DARK2_L_I[15:8] DARK2_L_I[7:0] DARK2_H_I[15:8] DARK2_H_I[7:0] SIGNAL1_L_J[15:8] SIGNAL1_L_J[7:0] SIGNAL1_H_J[15:8] SIGNAL1_H_J[7:0] Rev. 0 | Page 55 of 101 Bit 10 Bit 2 Bit 9 Bit 1 Bit 8 Bit 0 Reset 0x0000 R/W R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R ADPD4100/ADPD4101 Reg 0x007A 0x007B 0x007C 0x007D 0x007E 0x007F 0x0080 0x0081 0x0082 0x0083 0x0084 0x0085 0x0086 0x0087 0x0088 0x0089 0x008A 0x008B 0x008C 0x008D 0x008E 0x008F 0x00B4 Name Bits SIGNAL2_L_J [15:8] [7:0] SIGNAL2_H_J [15:8] [7:0] DARK1_L_J [15:8] [7:0] DARK1_H_J [15:8] [7:0] DARK2_L_J [15:8] [7:0] DARK2_H_J [15:8] [7:0] SIGNAL1_L_K [15:8] [7:0] SIGNAL1_H_K [15:8] [7:0] SIGNAL2_L_K [15:8] [7:0] SIGNAL2_H_K [15:8] [7:0] DARK1_L_K [15:8] [7:0] DARK1_H_K [15:8] [7:0] DARK2_L_K [15:8] [7:0] DARK2_H_K [15:8] [7:0] SIGNAL1_L_L [15:8] [7:0] SIGNAL1_H_L [15:8] [7:0] SIGNAL2_L_L [15:8] [7:0] SIGNAL2_H_L [15:8] [7:0] DARK1_L_L [15:8] [7:0] DARK1_H_L [15:8] [7:0] DARK2_L_L [15:8] [7:0] DARK2_H_L [15:8] [7:0] IO_ADJUST [15:8] [7:0] 0x00B6 I2C_KEY 0x00B7 I2C_ADDR 0x0100 TS_CTRL_A [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] Bit 15 Bit 7 Data Sheet Bit 14 Bit 6 Bit 13 Bit 5 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIGNAL2_L_J[15:8] SIGNAL2_L_J[7:0] SIGNAL2_H_J[15:8] SIGNAL2_H_J[7:0] DARK1_L_J[15:8] DARK1_L_J[7:0] DARK1_H_J[15:8] DARK1_H_J[7:0] DARK2_L_J[15:8] DARK2_L_J[7:0] DARK2_H_J[15:8] DARK2_H_J[7:0] SIGNAL1_L_K[15:8] SIGNAL1_L_K[7:0] SIGNAL1_H_K[15:8] SIGNAL1_H_K[7:0] SIGNAL2_L_K[15:8] SIGNAL2_L_K[7:0] SIGNAL2_H_K[15:8] SIGNAL2_H_K[7:0] DARK1_L_K[15:8] DARK1_L_K[7:0] DARK1_H_K[15:8] DARK1_H_K[7:0] DARK2_L_K[15:8] DARK2_L_K[7:0] DARK2_H_K[15:8] DARK2_H_K[7:0] SIGNAL1_L_L[15:8] SIGNAL1_L_L[7:0] SIGNAL1_H_L[15:8] SIGNAL1_H_L[7:0] SIGNAL2_L_L[15:8] SIGNAL2_L_L[7:0] SIGNAL2_H_L[15:8] SIGNAL2_H_L[7:0] DARK1_L_L[15:8] DARK1_L_L[7:0] DARK1_H_L[15:8] DARK1_H_L[7:0] DARK2_L_L[15:8] DARK2_L_L[7:0] DARK2_H_L[15:8] DARK2_H_L[7:0] Reserved Reserved (set LOW_ Reserved Reserved SPI_SLEW[1:0] SPI_DRV[1:0] to 0x0) IOVDD_EN (set to 0x0) (set to 0x1) I2C_KEY_MATCH[3:0] I2C_KEY[11:8] I2C_KEY[7:0] I2C_SLAVE_KEY2[7:0] I2C_SLAVE_ADDR[6:0] Reserved SUBSAMPLE_A CH2_EN_A SAMPLE_TYPE_A[1:0] INPUT_R_SELECT_A[1:0] TIMESLOT_OFFSET_ A[9:8] TIMESLOT_OFFSET_A[7:0] Rev. 0 | Page 56 of 101 Reset 0x0000 R/W R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0050 R/W 0x0000 R/W 0x0048 R/W 0x0000 R/W Data Sheet Reg 0x0101 Name TS_PATH_A 0x0102 INPUTS_A 0x0103 0x0104 0x0105 ADPD4100/ADPD4101 Bits [15:8] [7:0] [15:8] [7:0] CATHODE_A [15:8] [7:0] AFE_TRIM_A [15:8] LED_ POW12_A [7:0] [15:8] [7:0] 0x0106 LED_ POW34_A [15:8] [7:0] 0x0107 COUNTS_A 0x0108 PERIOD_A 0x0109 LED_ PULSE_A 0x010A INTEG_ SETUP_A 0x010B 0x010C 0x010D 0x010E 0x010F 0x0110 0x0111 0x0112 0x0113 [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] INTEG_OS_A [15:8] [7:0] MOD_ [15:8] PULSE_A [7:0] PATTERN_A [15:8] [7:0] ADC_OFF1_A [15:8] [7:0] ADC_OFF2_A [15:8] [7:0] [15:8] [7:0] LIT_DATA_ [15:8] FORMAT_A [7:0] DECIMATE_A [15:8] [7:0] DIGINT_ [15:8] LIT_A DATA_ FORMAT_A 0x0114 DIGINT_ DARK_A [7:0] [15:8] [7:0] 0x0115 THRESH_ CFG_A [15:8] [7:0] 0x0116 THRESH0_A [15:8] [7:0] Bit 15 Bit 7 Bit 14 Bit 13 Bit 6 Bit 5 PRE_WIDTH_A[3:0] Bit 12 Bit 4 Bit 11 Bit 3 Bit 10 Bit 2 Reserved Bit 9 Bit 1 TS_ GPIO_A Bit 8 Bit 0 AFE_ PATH_ CFG_A[8] AFE_PATH_CFG_A[7:0] INP78_A[3:0] INP56_A[3:0] INP34_A[3:0] INP12_A[3:0] Reserved PRECON_A[2:0] VC2_PULSE_A[1:0] VC2_ALT_A[1:0] VC2_SEL_A[1:0] VC1_PULSE_A[1:0] VC1_ALT_A[1:0] VC1_SEL_A[1:0] TIA_CEIL_ CH2_TRIM_INT_A[1:0] CH1_TRIM_INT_A[1:0] VREF_ AFE_TRIM_VREF_ DETECT_EN_A PULSE_A A[1:0] VREF_PULSE_VAL_A[1:0] TIA_GAIN_CH2_A[2:0] TIA_GAIN_CH1_A[2:0] LED_ LED_CURRENT2_A[6:0] DRIVESIDE2_A LED_ LED_CURRENT1_A[6:0] DRIVESIDE1_A LED_ LED_CURRENT4_A[6:0] DRIVESIDE4_A LED_ LED_CURRENT3_A[6:0] DRIVESIDE3_A NUM_INT_A[7:0] NUM_REPEAT_A[7:0] Reserved MOD_TYPE_A[1:0] Reserved MIN_PERIOD_A[9:8] MIN_PERIOD_A[7:0] LED_WIDTH_A[7:0] LED_OFFSET_A[7:0] SINGLE_ CH2_AMP_DISABLE_A[2:0] AFE_INT_ CH1_AMP_DISABLE_A[2:0] INTEG_A C_BUF_A ADC_COUNT_A[1:0] Reserved INTEG_WIDTH_A[4:0] Reserved INTEG_OFFSET_A[12:8] INTEG_OFFSET_A[7:0] MOD_WIDTH_A[7:0] MOD_OFFSET_A[7:0] LED_DISABLE_A[3:0] MOD_DISABLE_A[3:0] SUBTRACT_A[3:0] REVERSE_INTEG_A[3:0] Reserved CH1_ADC_ADJUST_A[13:8] CH1_ADC_ADJUST_A[7:0] ZERO_ Reserved CH2_ADC_ADJUST_A[13:8] ADJUST_A CH2_ADC_ADJUST_A[7:0] DARK_SHIFT_A[4:0] DARK_SIZE_A[2:0] SIGNAL_SHIFT_A[4:0] SIGNAL_SIZE_A[2:0] Reserved LIT_SHIFT_A[4:0] LIT_SIZE_A[2:0] Reserved DECIMATE_FACTOR_A[6:4] DECIMATE_FACTOR_A[3:0] DECIMATE_TYPE_A[3:0] Reserved LIT_ OFFSET_ A[8] LIT_OFFSET_A[7:0] DARK2_OFFSET_A[8:1] DARK2_ DARK1_OFFSET_A[6:0] OFFSET_A[0] Reserved THRESH1_ THRESH1_ THRESH1_TYPE_A[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_A[1:0] CHAN_A DIR_A CHAN_A DIR_A Reserved THRESH0_SHIFT_A[4:0] THRESH0_VALUE_A[7:0] Rev. 0 | Page 57 of 101 Reset 0x40DA R/W R/W 0x0000 R/W 0x0000 R/W 0x03C0 R/W 0x0000 R/W 0x0000 R/W 0x0101 R/W 0x0000 R/W 0x0210 R/W 0x0003 R/W 0x0214 R/W 0x0001 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0003 R/W 0x0000 R/W 0x0000 R/W 0x0026 R/W 0x2306 R/W 0x0000 R/W 0x0000 R/W ADPD4100/ADPD4101 Reg 0x0117 Name THRESH1_A 0x0120 TS_CTRL_B Bits [15:8] [7:0] [15:8] 0x0121 TS_PATH_B [7:0] [15:8] 0x0122 INPUTS_B 0x0123 0x0124 0x0125 [7:0] [15:8] [7:0] CATHODE_B [15:8] [7:0] AFE_TRIM_B [15:8] LED_ POW12_B [7:0] [15:8] [7:0] 0x0126 LED_ POW34_B [15:8] [7:0] 0x0127 COUNTS_B 0x0128 PERIOD_B 0x0129 LED_ PULSE_B 0x012A INTEG_ SETUP_B 0x012B 0x012C 0x012D 0x012E 0x012F 0x0130 0x0131 0x0132 0x0133 0x0134 [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] INTEG_OS_B [15:8] [7:0] MOD_ [15:8] PULSE_B [7:0] PATTERN_B [15:8] [7:0] ADC_OFF1_B [15:8] [7:0] ADC_OFF2_B [15:8] [7:0] [15:8] [7:0] LIT_DATA_ [15:8] FORMAT_B [7:0] DECIMATE_B [15:8] [7:0] DIGINT_LIT_B [15:8] DATA_ FORMAT_B DIGINT_ DARK_B [7:0] [15:8] [7:0] Bit 15 Bit 7 Data Sheet Bit 14 Bit 6 Reserved Bit 13 Bit 5 Bit 12 Bit 4 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 THRESH1_SHIFT_A[4:0] THRESH1_VALUE_A[7:0] SUBSAMPLE_B CH2_EN_B SAMPLE_TYPE_B[1:0] INPUT_R_SELECT_B[1:0] TIMESLOT_ OFFSET_B[9:8] TIMESLOT_OFFSET_B[7:0] PRE_WIDTH_B[3:0] Reserved TS_GPIO_B AFE_ PATH_ CFG_B[8] AFE_PATH_CFG_B[7:0] INP78_B[3:0] INP56_B[3:0] INP34_B[3:0] INP12_B[3:0] Reserved PRECON_B[2:0] VC2_PULSE_B[1:0] VC2_ALT_B[1:0] VC2_SEL_B[1:0] VC1_PULSE_B[1:0] VC1_ALT_B[1:0] VC1_SEL_B[1:0] TIA_CEIL_ CH2_TRIM_INT_B[1:0] CH2_TRIM_INT_B[1:0] VREF_ AFE_TRIM_ DETECT_EN_B PULSE_B VREF_B[1:0] VREF_PULSE_VAL_B[1:0] TIA_GAIN_CH2_B[2:0] TIA_GAIN_CH1_B[2:0] LED_ LED_CURRENT2_B[6:0] DRIVESIDE2_B LED_ LED_CURRENT1_B[6:0] DRIVESIDE1_B LED_ LED_CURRENT4_B[6:0] DRIVESIDE4_B LED_ LED_CURRENT3_B[6:0] DRIVESIDE3_B NUM_INT_B[7:0] NUM_REPEAT_B[7:0] Reserved MOD_TYPE_B[1:0] Reserved MIN_PERIOD_B[9:8] MIN_PERIOD_B[7:0] LED_WIDTH_B[7:0] LED_OFFSET_B[7:0] SINGLE_ CH2_AMP_DISABLE_B[2:0] AFE_INT_C_ CH1_AMP_DISABLE_B[2:0] INTEG_B BUF_B ADC_COUNT_B[1:0] Reserved INTEG_WIDTH_B[4:0] Reserved INTEG_ OFFSET_B[12:8] INTEG_OFFSET_B[7:0] MOD_WIDTH_B[7:0] MOD_OFFSET_B[7:0] LED_DISABLE_B[3:0] MOD_DISABLE_B[3:0] SUBTRACT_B[3:0] REVERSE_INTEG_B[3:0] Reserved CH1_ADC_ADJUST_B[13:8] CH1_ADC_ADJUST_B[7:0] ZERO_ Reserved CH2_ADC_ADJUST_B[13:8] ADJUST_B CH2_ADC_ADJUST_B[7:0] DARK_SHIFT_B[4:0] DARK_SIZE_B[2:0] SIGNAL_SHIFT_B[4:0] SIGNAL_SIZE_B[2:0] Reserved LIT_SHIFT_B[4:0] LIT_SIZE_B[2:0] Reserved DECIMATE_FACTOR_B[6:4] DECIMATE_FACTOR_B[3:0] DECIMATE_TYPE_B[3:0] Reserved LIT_ OFFSET_ B[8] LIT_OFFSET_B[7:0] DARK2_OFFSET_B[8:1] DARK2_ DARK1_OFFSET_B[6:0] OFFSET_B[0] Rev. 0 | Page 58 of 101 Bit 11 Bit 3 Reset 0x0000 R/W R/W 0x0000 R/W 0x40DA R/W 0x0000 R/W 0x0000 R/W 0x03C0 R/W 0x0000 R/W 0x0000 R/W 0x0101 R/W 0x0000 R/W 0x0210 R/W 0x0003 R/W 0x0214 R/W 0x0001 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0003 R/W 0x0000 R/W 0x0000 R/W 0x0026 R/W 0x2306 R/W Data Sheet Reg 0x0135 Name THRESH_ CFG_B ADPD4100/ADPD4101 Bits [15:8] [7:0] 0x0136 THRESH0_B 0x0137 THRESH1_B 0x0140 TS_CTRL_C [15:8] [7:0] [15:8] [7:0] [15:8] 0x0141 TS_PATH_C [7:0] [15:8] 0x0142 INPUTS_C 0x0143 0x0144 0x0145 [7:0] [15:8] [7:0] CATHODE_C [15:8] [7:0] AFE_TRIM_C [15:8] LED_ POW12_C [7:0] [15:8] [7:0] 0x0146 LED_ POW34_C [15:8] [7:0] 0x0147 COUNTS_C 0x0148 PERIOD_C 0x0149 LED_ PULSE_C 0x014A INTEG_ SETUP_C 0x014B 0x014C 0x014D 0x014E 0x014F 0x0150 0x0151 0x0152 [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] INTEG_OS_C [15:8] [7:0] MOD_ [15:8] PULSE_C [7:0] PATTERN_C [15:8] [7:0] ADC_OFF1_C [15:8] [7:0] ADC_OFF2_C [15:8] [7:0] [15:8] [7:0] LIT_DATA_ [15:8] FORMAT_C [7:0] DECIMATE_C [15:8] [7:0] DATA_ FORMAT_C Bit 15 Bit 7 Bit 14 Bit 6 THRESH1_ CHAN_B THRESH1_ DIR_B Reserved Bit 13 Bit 5 Bit 12 Bit 4 Bit 11 Bit 3 Reserved Bit 10 Bit 2 Bit 9 Bit 1 Bit 8 Bit 0 THRESH0_ THRESH0_ THRESH0_TYPE_ B[1:0] CHAN_B DIR_B THRESH0_SHIFT_B[4:0] THRESH0_VALUE_B[7:0] Reserved THRESH1_SHIFT_B[4:0] THRESH1_VALUE_B[7:0] SUBSAMPLE_C CH2_EN_C SAMPLE_TYPE_C[1:0] INPUT_R_SELECT_C[1:0] TIMESLOT_OFFSET_ C[9:8] TIMESLOT_OFFSET_C[7:0] PRE_WIDTH_C[3:0] Reserved TS_ AFE_PATH GPIO_C _CFG_C[8] AFE_PATH_CFG_C[7:0] INP78_C[3:0] INP56_C[3:0] INP34_C[3:0] INP12_C[3:0] Reserved PRECON_C[2:0] VC2_PULSE_C[1:0] VC2_ALT_C[1:0] VC2_SEL_C[1:0] VC1_PULSE_C[1:0] VC1_ALT_C[1:0] VC1_SEL_C[1:0] TIA_CEIL_ CH2_TRIM_INT_C[1:0] CH1_TRIM_INT_C[1:0] VREF_ AFE_TRIM_ DETECT_EN_C PULSE_C VREF_C[1:0] VREF_PULSE_VAL_C[1:0] TIA_GAIN_CH2_C[2:0] TIA_GAIN_CH1_C[2:0] LED_ LED_CURRENT2_C[6:0] DRIVESIDE2_C LED_ LED_CURRENT1_C[6:0] DRIVESIDE1_C LED_ LED_CURRENT4_C[6:0] DRIVESIDE4_C LED_ LED_CURRENT3_C[6:0] DRIVESIDE3_C NUM_INT_C[7:0] NUM_REPEAT_C[7:0] Reserved MOD_TYPE_C[1:0] Reserved MIN_PERIOD_C[9:8] MIN_PERIOD_C[7:0] LED_WIDTH_C[7:0] LED_OFFSET_C[7:0] SINGLE_ CH2_AMP_DISABLE_C[2:0] AFE_INT_C_ CH1_AMP_DISABLE_C[2:0] INTEG_C BUF_C ADC_COUNT_C[1:0] Reserved INTEG_WIDTH_C[4:0] Reserved INTEG_OFFSET_C[12:8] INTEG_OFFSET_C[7:0] MOD_WIDTH_C[7:0] MOD_OFFSET_C[7:0] LED_DISABLE_C[3:0] MOD_DISABLE_C[3:0] SUBTRACT_C[3:0] REVERSE_INTEG_C[3:0] Reserved CH1_ADC_ADJUST_C[13:8] CH1_ADC_ADJUST_C[7:0] ZERO_ Reserved CH2_ADC_ADJUST_C[13:8] ADJUST_C CH2_ADC_ADJUST_C[7:0] DARK_SHIFT_C[4:0] DARK_SIZE_C[2:0] SIGNAL_SHIFT_C[4:0] SIGNAL_SIZE_C[2:0] Reserved LIT_SHIFT_C[4:0] LIT_SIZE_C[2:0] Reserved DECIMATE_FACTOR_C[6:4] DECIMATE_FACTOR_C[3:0] DECIMATE_TYPE_C[3:0] Reset 0x0000 R/W R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x40DA R/W 0x0000 R/W 0x0000 R/W 0x03C0 R/W 0x0000 R/W 0x0000 R/W 0x0101 R/W 0x0000 R/W 0x0210 R/W 0x0003 R/W 0x0214 R/W 0x0001 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0003 R/W 0x0000 R/W 0x0000 R/W THRESH1_TYPE_B[1:0] Rev. 0 | Page 59 of 101 ADPD4100/ADPD4101 Reg 0x0153 Name Bits DIGINT_LIT_C [15:8] 0x0154 DIGINT_ DARK_C Bit 15 Bit 7 Data Sheet Bit 14 Bit 6 [7:0] [15:8] Bit 13 Bit 5 Bit 12 Bit 4 Reserved Bit 11 Bit 3 Bit 10 Bit 2 Bit 9 Bit 1 Bit 8 Bit 0 LIT_ OFFSET_ C[8] LIT_OFFSET_C[7:0] DARK2_OFFSET_C[8:1] [7:0] DARK2_ OFFSET_C[0] THRESH_ CFG_C [15:8] [7:0] 0x0156 THRESH0_C 0x0157 THRESH1_C 0x0160 TS_CTRL_D [15:8] [7:0] [15:8] [7:0] [15:8] 0x0161 TS_PATH_D [7:0] [15:8] 0x0162 INPUTS_D Reserved THRESH1_TYPE_C[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_ C[1:0] CHAN_C DIR_C THRESH0_SHIFT_C[4:0] THRESH0_VALUE_C[7:0] Reserved THRESH1_SHIFT_C[4:0] THRESH1_VALUE_C[7:0] SUBSAMPLE_ CH2_EN_D SAMPLE_TYPE_D[1:0] INPUT_R_SELECT_D[1:0] TIMESLOT_OFFSET_ D D[9:8] TIMESLOT_OFFSET_D[7:0] PRE_WIDTH_D[3:0] Reserved TS_ AFE_ GPIO_D PATH_ CFG_D[8] AFE_PATH_CFG_D[7:0] INP78_D[3:0] INP56_D[3:0] INP34_D[3:0] INP12_D[3:0] Reserved PRECON_D[2:0] VC2_PULSE_D[1:0] VC2_ALT_D[1:0] VC2_SEL_D[1:0] VC1_PULSE_D[1:0] VC1_ALT_D[1:0] VC1_SEL_D[1:0] TIA_CEIL_ CH2_TRIM_INT_D[1:0] CH1_TRIM_INT_D[1:0] VREF_ AFE_TRIM_VREF_ DETECT_EN_D PULSE_D D[1:0] VREF_PULSE_VAL_D[1:0] TIA_GAIN_CH2_D[2:0] TIA_GAIN_CH1_D[2:0] LED_ LED_CURRENT2_D[6:0] DRIVESIDE2_D LED_ LED_CURRENT1_D[6:0] DRIVESIDE1_D LED_ LED_CURRENT4_D[6:0] DRIVESIDE4_D LED_ LED_CURRENT3_D[6:0] DRIVESIDE3_D NUM_INT_D[7:0] NUM_REPEAT_D[7:0] Reserved MOD_TYPE_D[1:0] Reserved MIN_PERIOD_D[9:8] MIN_PERIOD_D[7:0] LED_WIDTH_D[7:0] LED_OFFSET_D[7:0] SINGLE_ CH2_AMP_DISABLE_D[2:0] AFE_INT_C_ CH1_AMP_DISABLE_D[2:0] INTEG_D BUF_D ADC_COUNT_D[1:0] Reserved INTEG_WIDTH_D[4:0] Reserved INTEG_OFFSET_D[12:8] INTEG_OFFSET_D[7:0] MOD_WIDTH_D[7:0] MOD_OFFSET_D[7:0] LED_DISABLE_D[3:0] MOD_DISABLE_D[3:0] SUBTRACT_D[3:0] REVERSE_INTEG_D[3:0] Reserved CH1_ADC_ADJUST_D[13:8] CH1_ADC_ADJUST_D[7:0] ZERO_ Reserved CH2_ADC_ADJUST_D[13:8] ADJUST_D CH2_ADC_ADJUST_D[7:0] DARK_SHIFT_D[4:0] DARK_SIZE_D[2:0] SIGNAL_SHIFT_D[4:0] SIGNAL_SIZE_D[2:0] 0x0155 0x0163 0x0164 0x0165 [7:0] [15:8] [7:0] CATHODE_D [15:8] [7:0] AFE_TRIM_D [15:8] LED_ POW12_D [7:0] [15:8] [7:0] 0x0166 LED_ POW34_D [15:8] [7:0] 0x0167 COUNTS_D 0x0168 PERIOD_D 0x0169 LED_ PULSE_D 0x016A INTEG_ SETUP_D 0x016B 0x016C 0x016D 0x016E 0x016F 0x0170 [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] INTEG_OS_D [15:8] [7:0] MOD_ [15:8] PULSE_D [7:0] PATTERN_D [15:8] [7:0] ADC_OFF1_D [15:8] [7:0] ADC_OFF2_D [15:8] DATA_ FORMAT_D [7:0] [15:8] [7:0] THRESH1_ CHAN_C Reset 0x0026 R/W R/W 0x2306 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x40DA R/W 0x0000 R/W 0x0000 R/W 0x03C0 R/W 0x0000 R/W 0x0000 R/W 0x0101 R/W 0x0000 R/W 0x0210 R/W 0x0003 R/W 0x0214 R/W 0x0001 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0003 R/W DARK1_OFFSET_C[6:0] THRESH1_ DIR_C Reserved Rev. 0 | Page 60 of 101 Data Sheet Reg 0x0171 0x0172 0x0173 ADPD4100/ADPD4101 Name LIT_DATA_ FORMAT_D Bits [15:8] [7:0] DECIMATE_D [15:8] [7:0] DIGINT_LIT_D [15:8] DIGINT_ DARK_D [7:0] [15:8] [7:0] THRESH_ CFG_D [15:8] [7:0] 0x0176 THRESH0_D 0x0177 THRESH1_D 0x0180 TS_CTRL_E [15:8] [7:0] [15:8] [7:0] [15:8] 0x0181 TS_PATH_E [7:0] [15:8] 0x0182 INPUTS_E 0x0183 CATHODE_E 0x0184 AFE_TRIM_E 0x0185 LED_ POW12_E 0x0174 0x0175 [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] 0x0186 LED_ POW34_E [15:8] [7:0] 0x0187 0x0188 0x0189 0x018A 0x018B 0x018C 0x018D 0x018E COUNTS_E [15:8] [7:0] PERIOD_E [15:8] [7:0] LED_PULSE_E [15:8] [7:0] INTEG_ [15:8] SETUP_E [7:0] INTEG_OS_E [15:8] [7:0] MOD_ [15:8] PULSE_E [7:0] PATTERN_E [15:8] [7:0] ADC_OFF1_E [15:8] [7:0] Bit 15 Bit 7 Bit 14 Bit 6 Bit 13 Bit 5 Bit 12 Bit 4 Bit 11 Bit 3 Reserved LIT_SHIFT_D[4:0] Reserved DECIMATE_FACTOR_D[3:0] Reserved Bit 10 Bit 2 Bit 9 Bit 1 Bit 8 Bit 0 LIT_SIZE_D[2:0] DECIMATE_FACTOR_D[6:4] DECIMATE_TYPE_D[3:0] LIT_ OFFSET_ D[8] LIT_OFFSET_D[7:0] DARK2_OFFSET_D[8:1] DARK1_OFFSET_D[6:0] DARK2_ OFFSET_D[0] Reserved THRESH1_TYPE_D[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_D[1:0] CHAN_D DIR_D THRESH0_SHIFT_D[4:0] THRESH0_VALUE_D[7:0] Reserved THRESH1_SHIFT_D[4:0] THRESH1_VALUE_D[7:0] SUBSAMPLE_E CH2_EN_E SAMPLE_TYPE_E[1:0] INPUT_R_SELECT_E[1:0] TIMESLOT_OFFSET_ E[9:8] TIMESLOT_OFFSET_E[7:0] PRE_WIDTH_E[3:0] Reserved TS_GPIO_E AFE_PATH _CFG_E[8] AFE_PATH_CFG_E[7:0] INP78_E[3:0] INP56_E[3:0] INP34_E[3:0] INP12_E[3:0] Reserved PRECON_E[2:0] VC2_PULSE_E[1:0] VC2_ALT_E[1:0] VC2_SEL_E[1:0] VC1_PULSE_E[1:0] VC1_ALT_E[1:0] VC1_SEL_E[1:0] TIA_CEIL_ CH2_TRIM_INT_E[1:0] CH1_TRIM_INT_E[1:0] VREF_ AFE_TRIM_ DETECT_EN_E PULSE_E VREF_E[1:0] VREF_PULSE_VAL_E[1:0] TIA_GAIN_CH2_E[2:0] TIA_GAIN_CH1_E[2:0] LED_ LED_CURRENT2_E[6:0] DRIVESIDE2_E LED_ LED_CURRENT1_E[6:0] DRIVESIDE1_E LED_ LED_CURRENT4_E[6:0] DRIVESIDE4_E LED_ LED_CURRENT3_E[6:0] DRIVESIDE3_E NUM_INT_E[7:0] NUM_REPEAT_E[7:0] Reserved MOD_TYPE_E[1:0] Reserved MIN_PERIOD_E[9:8] MIN_PERIOD_E[7:0] LED_WIDTH_E[7:0] LED_OFFSET_E[7:0] SINGLE_ CH2_AMP_DISABLE_E[2:0] AFE_INT_ CH1_AMP_DISABLE_E[2:0] INTEG_E C_BUF_E ADC_COUNT_E[1:0] Reserved INTEG_WIDTH_E[4:0] Reserved INTEG_OFFSET_E[12:8] INTEG_OFFSET_E[7:0] MOD_WIDTH_E[7:0] MOD_OFFSET_E[7:0] LED_DISABLE_E[3:0] MOD_DISABLE_E[3:0] SUBTRACT_E[3:0] REVERSE_INTEG_E[3:0] Reserved CH1_ADC_ADJUST_E[13:8] CH1_ADC_ADJUST_E[7:0] THRESH1_ CHAN_D THRESH1_ DIR_D Reserved Rev. 0 | Page 61 of 101 Reset 0x0000 R/W R/W 0x0000 R/W 0x0026 R/W 0x2306 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x40DA R/W 0x0000 R/W 0x0000 R/W 0x03C0 R/W 0x0000 R/W 0x0000 R/W 0x0101 R/W 0x0000 R/W 0x0210 R/W 0x0003 R/W 0x0214 R/W 0x0001 R/W 0x0000 R/W 0x0000 R/W ADPD4100/ADPD4101 Reg 0x018F Name Bits ADC_OFF2_E [15:8] 0x0190 DATA_ FORMAT_E 0x0191 0x0192 0x0193 [7:0] [15:8] [7:0] LIT_DATA_ [15:8] FORMAT_E [7:0] DECIMATE_E [15:8] [7:0] DIGINT_LIT_E [15:8] DIGINT_ DARK_E [7:0] [15:8] [7:0] THRESH_ CFG_E [15:8] [7:0] 0x0196 THRESH0_E 0x0197 THRESH1_E 0x01A0 TS_CTRL_F [15:8] [7:0] [15:8] [7:0] [15:8] 0x01A1 TS_PATH_F [7:0] [15:8] 0x01A2 INPUTS_F 0x01A3 CATHODE_F 0x01A4 AFE_TRIM_F 0x01A5 LED_ POW12_F 0x0194 0x0195 [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] 0x01A6 LED_ POW34_F [15:8] [7:0] 0x01A7 0x01A8 0x01A9 0x01AA 0x01AB 0x01AC Bit 15 Bit 7 ZERO_ ADJUST_E COUNTS_F [15:8] [7:0] PERIOD_F [15:8] [7:0] LED_PULSE_F [15:8] [7:0] INTEG_ [15:8] SETUP_F [7:0] INTEG_OS_F [15:8] [7:0] MOD_ [15:8] PULSE_F [7:0] Data Sheet Bit 14 Bit 6 Reserved Bit 13 Bit 5 Bit 12 Bit 4 Bit 11 Bit 10 Bit 9 Bit 3 Bit 2 Bit 1 CH2_ADC_ADJUST_E[13:8] CH2_ADC_ADJUST_E[7:0] DARK_SHIFT_E[4:0] SIGNAL_SHIFT_E[4:0] Reserved LIT_SHIFT_E[4:0] Reserved DECIMATE_FACTOR_E[3:0] Reserved Bit 8 Bit 0 DARK_SIZE_E[2:0] SIGNAL_SIZE_E[2:0] LIT_SIZE_E[2:0] DECIMATE_FACTOR_E[6:4] DECIMATE_TYPE_E[3:0] LIT_ OFFSET_ E[8] LIT_OFFSET_E[7:0] DARK2_OFFSET_E[8:1] DARK1_OFFSET_E[6:0] DARK2_ OFFSET_E[0] Reserved THRESH1_TYPE_E[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_E[1:0] CHAN_E DIR_E THRESH0_SHIFT_E[4:0] THRESH0_VALUE_E[7:0] Reserved THRESH1_SHIFT_E[4:0] THRESH1_VALUE_E[7:0] SUBSAMPLE_F CH2_EN_F SAMPLE_TYPE_F[1:0] INPUT_R_SELECT_F[1:0] TIMESLOT_OFFSET_ F[9:8] TIMESLOT_OFFSET_F[7:0] PRE_WIDTH_F[3:0] Reserved TS_GPIO_F AFE_PATH _CFG_F[8] AFE_PATH_CFG_F[7:0] INP78_F[3:0] INP56_F[3:0] INP34_F[3:0] INP12_F[3:0] Reserved PRECON_F[2:0] VC2_PULSE_F[1:0] VC2_ALT_F[1:0] VC2_SEL_F[1:0] VC1_PULSE_F[1:0] VC1_ALT_F[1:0] VC1_SEL_F[1:0] TIA_CEIL_ CH2_TRIM_INT_F[1:0] CH1_TRIM_INT_F[1:0] VREF_ AFE_TRIM_VREF_ DETECT_EN_F PULSE_F F[1:0] VREF_PULSE_VAL_F[1:0] TIA_GAIN_CH2_F[2:0] TIA_GAIN_CH1_F[2:0] LED_ LED_CURRENT2_F[6:0] DRIVESIDE2_F LED_ LED_CURRENT1_F[6:0] DRIVESIDE1_F LED_ LED_CURRENT4_F[6:0] DRIVESIDE4_F LED_ LED_CURRENT3_F[6:0] DRIVESIDE3_F NUM_INT_F[7:0] NUM_REPEAT_F[7:0] Reserved MOD_TYPE_F[1:0] Reserved MIN_PERIOD_F[9:8] MIN_PERIOD_F[7:0] LED_WIDTH_F[7:0] LED_OFFSET_F[7:0] SINGLE_ CH2_AMP_DISABLE_F[2:0] AFE_INT_C_ CH1_AMP_DISABLE_F[2:0] INTEG_F BUF_F ADC_COUNT_F[1:0] Reserved INTEG_WIDTH_F[4:0] Reserved INTEG_OFFSET_F[12:8] INTEG_OFFSET_F[7:0] MOD_WIDTH_F[7:0] MOD_OFFSET_F[7:0] THRESH1_ CHAN_E THRESH1_ DIR_E Reserved Rev. 0 | Page 62 of 101 Reset 0x0000 R/W R/W 0x0003 R/W 0x0000 R/W 0x0000 R/W 0x0026 R/W 0x2306 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x40DA R/W 0x0000 R/W 0x0000 R/W 0x03C0 R/W 0x0000 R/W 0x0000 R/W 0x0101 R/W 0x0000 R/W 0x0210 R/W 0x0003 R/W 0x0214 R/W 0x0001 R/W Data Sheet Reg 0x01AD 0x01AE 0x01AF 0x01B0 0x01B1 0x01B2 0x01B3 ADPD4100/ADPD4101 Name PATTERN_F Bits [15:8] [7:0] ADC_OFF1_F [15:8] [7:0] ADC_OFF2_F [15:8] THRESH_ CFG_F [15:8] [7:0] 0x01B6 THRESH0_F 0x01B7 THRESH1_F 0x01C0 TS_CTRL_G [15:8] [7:0] [15:8] [7:0] [15:8] 0x01C1 TS_PATH_G [7:0] [15:8] 0x01C2 INPUTS_G 0x01C3 0x01C4 0x01C5 [7:0] [15:8] [7:0] CATHODE_G [15:8] [7:0] AFE_TRIM_G [15:8] LED_ POW12_G [7:0] [15:8] [7:0] 0x01C6 LED_ POW34_G [15:8] [7:0] 0x01C7 0x01C8 0x01C9 0x01CA ZERO_ ADJUST_F [7:0] [15:8] [7:0] LIT_DATA_ [15:8] FORMAT_F [7:0] DECIMATE_F [15:8] [7:0] DIGINT_LIT_F [15:8] [7:0] [15:8] [7:0] 0x01B5 Bit 14 Bit 13 Bit 6 Bit 5 LED_DISABLE_F[3:0] SUBTRACT_F[3:0] Reserved COUNTS_G [15:8] [7:0] PERIOD_G [15:8] [7:0] LED_PULSE_G [15:8] [7:0] INTEG_ [15:8] SETUP_G [7:0] Reserved Bit 12 Bit 4 Bit 11 Bit 3 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 MOD_DISABLE_F[3:0] REVERSE_INTEG_F[3:0] CH1_ADC_ADJUST_F[13:8] CH1_ADC_ADJUST_F[7:0] CH2_ADC_ADJUST_F[13:8] CH2_ADC_ADJUST_F[7:0] DARK_SHIFT_F[4:0] SIGNAL_SHIFT_F[4:0] Reserved LIT_SHIFT_F[4:0] Reserved DECIMATE_FACTOR_F[3:0] Reserved DATA_ FORMAT_F DIGINT_ DARK_F 0x01B4 Bit 15 Bit 7 DARK_SIZE_F[2:0] SIGNAL_SIZE_F[2:0] LIT_SIZE_F[2:0] DECIMATE_FACTOR_F[6:4] DECIMATE_TYPE_F[3:0] LIT_ OFFSET_ F[8] LIT_OFFSET_F[7:0] DARK2_OFFSET_F[8:1] DARK1_OFFSET_F[6:0] DARK2_ OFFSET_F[0] Reserved THRESH1_TYPE_F[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_F[1:0] CHAN_F DIR_F THRESH0_SHIFT_F[4:0] THRESH0_VALUE_F[7:0] Reserved THRESH1_SHIFT_F[4:0] THRESH1_VALUE_F[7:0] SUBSAMPLE_ CH2_EN_G SAMPLE_TYPE_G[1:0] INPUT_R_SELECT_G[1:0] TIMESLOT_OFFSET_ G G[9:8] TIMESLOT_OFFSET_G[7:0] PRE_WIDTH_G[3:0] Reserved TS_ AFE_PATH_ GPIO_G CFG_G[8] AFE_PATH_CFG_G[7:0] INP78_G[3:0] INP56_G[3:0] INP34_G[3:0] INP12_G[3:0] Reserved PRECON_G[2:0] VC2_PULSE_G[1:0] VC2_ALT_G[1:0] VC2_SEL_G[1:0] VC1_PULSE_G[1:0] VC1_ALT_G[1:0] VC1_SEL_G[1:0] TIA_CEIL_ CH2_TRIM_INT_G[1:0] CH1_TRIM_INT_G[1:0] VREF_ AFE_TRIM_VREF_G[1:0] DETECT_EN_G PULSE_G VREF_PULSE_VAL_G[1:0] TIA_GAIN_CH2_G[2:0] TIA_GAIN_CH1_G[2:0] LED_ LED_CURRENT2_G[6:0] DRIVESIDE2_G LED_ LED_CURRENT1_G[6:0] DRIVESIDE1_G LED_ LED_CURRENT4_G[6:0] DRIVESIDE4_G LED_ LED_CURRENT3_G[6:0] DRIVESIDE3_G NUM_INT_G[7:0] NUM_REPEAT_G[7:0] Reserved MOD_TYPE_G[1:0] Reserved MIN_PERIOD_G[9:8] MIN_PERIOD_G[7:0] LED_WIDTH_G[7:0] LED_OFFSET_G[7:0] SINGLE_ CH2_AMP_DISABLE_G[2:0] AFE_INT_C_ CH1_AMP_DISABLE_G[2:0] INTEG_G BUF_G ADC_COUNT_G[1:0] Reserved INTEG_WIDTH_G[4:0] THRESH1_ CHAN_F THRESH1_ DIR_F Reserved Rev. 0 | Page 63 of 101 Reset 0x0000 R/W R/W 0x0000 R/W 0x0000 R/W 0x0003 R/W 0x0000 R/W 0x0000 R/W 0x0026 R/W 0x2306 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x40DA R/W 0x0000 R/W 0x0000 R/W 0x03C0 R/W 0x0000 R/W 0x0000 R/W 0x0101 R/W 0x0000 R/W 0x0210 R/W 0x0003 R/W ADPD4100/ADPD4101 Reg 0x01CB 0x01CC 0x01CD 0x01CE 0x01CF 0x01D0 0x01D1 0x01D2 0x01D3 Name Bits INTEG_OS_G [15:8] [7:0] MOD_ [15:8] PULSE_G [7:0] PATTERN_G [15:8] [7:0] ADC_OFF1_G [15:8] [7:0] ADC_OFF2_G [15:8] [7:0] [15:8] [7:0] LIT_DATA_ [15:8] FORMAT_G [7:0] DECIMATE_G [15:8] [7:0] DIGINT_LIT_G [15:8] DATA_ FORMAT_G 0x01D4 DIGINT_ DARK_G [7:0] [15:8] [7:0] 0x01D5 THRESH_ CFG_G [15:8] [7:0] 0x01D6 THRESH0_G 0x01D7 THRESH1_G 0x01E0 TS_CTRL_H [15:8] [7:0] [15:8] [7:0] [15:8] 0x01E1 TS_PATH_H [7:0] [15:8] 0x01E2 INPUTS_H 0x01E3 0x01E4 0x01E5 [7:0] [15:8] [7:0] CATHODE_H [15:8] [7:0] AFE_TRIM_H [15:8] LED_ POW12_H [7:0] [15:8] [7:0] 0x01E6 LED_ POW34_H [15:8] [7:0] 0x01E7 0x01E8 0x01E9 COUNTS_H [15:8] [7:0] PERIOD_H [15:8] [7:0] LED_PULSE_H [15:8] [7:0] Bit 15 Bit 7 Data Sheet Bit 14 Bit 6 Reserved Bit 13 Bit 5 Bit 12 Bit 4 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 INTEG_OFFSET_G[12:8] INTEG_OFFSET_G[7:0] MOD_WIDTH_G[7:0] MOD_OFFSET_G[7:0] LED_DISABLE_G[3:0] MOD_DISABLE_G[3:0] SUBTRACT_G[3:0] REVERSE_INTEG_G[3:0] Reserved CH1_ADC_ADJUST_G[13:8] CH1_ADC_ADJUST_G[7:0] ZERO_ Reserved CH2_ADC_ADJUST_G[13:8] ADJUST_G CH2_ADC_ADJUST_G[7:0] DARK_SHIFT_G[4:0] DARK_SIZE_G[2:0] SIGNAL_SHIFT_G[4:0] SIGNAL_SIZE_G[2:0] Reserved LIT_SHIFT_G[4:0] LIT_SIZE_G[2:0] Reserved DECIMATE_FACTOR_G[6:4] DECIMATE_FACTOR_G[3:0] DECIMATE_TYPE_G[3:0] Reserved LIT_ OFFSET_ G[8] LIT_OFFSET_G[7:0] DARK2_OFFSET_G[8:1] DARK2_ DARK1_OFFSET_G[6:0] OFFSET_G[0] Reserved THRESH1_ THRESH1_ THRESH1_TYPE_G[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_ CHAN_G DIR_G CHAN_G DIR_G G[1:0] Reserved THRESH0_SHIFT_G[4:0] THRESH0_VALUE_G[7:0] Reserved THRESH1_SHIFT_G[4:0] THRESH1_VALUE_G[7:0] SUBSAMPLE_ CH2_EN_H SAMPLE_TYPE_H[1:0] INPUT_R_SELECT_H[1:0] TIMESLOT_OFFSET_ H H[9:8] TIMESLOT_OFFSET_H[7:0] PRE_WIDTH_H[3:0] Reserved TS_GPIO_ AFE_PATH_ H CFG_H[8] AFE_PATH_CFG_H[7:0] INP78_H[3:0] INP56_H[3:0] INP34_H[3:0] INP12_H[3:0] Reserved PRECON_H[2:0] VC2_PULSE_H[1:0] VC2_ALT_H[1:0] VC2_SEL_H[1:0] VC1_PULSE_H[1:0] VC1_ALT_H[1:0] VC1_SEL_H[1:0] TIA_CEIL_ CH2_TRIM_INT_H[1:0] CH1_TRIM_INT_H[1:0] VREF_ AFE_TRIM_ DETECT_EN_H PULSE_H VREF_H[1:0] VREF_PULSE_VAL_H[1:0] TIA_GAIN_CH2_H[2:0] TIA_GAIN_CH1_H[2:0] LED_ LED_CURRENT2_H[6:0] DRIVESIDE2_H LED_ LED_CURRENT1_H[6:0] DRIVESIDE1_H LED_ LED_CURRENT4_H[6:0] DRIVESIDE4_H LED_ LED_CURRENT3_H[6:0] DRIVESIDE3_H NUM_INT_H[7:0] NUM_REPEAT_H[7:0] Reserved MOD_TYPE_H[1:0] Reserved MIN_PERIOD_H[9:8] MIN_PERIOD_H[7:0] LED_WIDTH_H[7:0] LED_OFFSET_H[7:0] Rev. 0 | Page 64 of 101 Bit 11 Bit 3 Reset 0x0214 R/W R/W 0x0001 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0003 R/W 0x0000 R/W 0x0000 R/W 0x0026 R/W 0x2306 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x40DA R/W 0x0000 R/W 0x0000 R/W 0x03C0 R/W 0x0000 R/W 0x0000 R/W 0x0101 R/W 0x0000 R/W 0x0210 R/W Data Sheet Reg 0x01EA 0x01EB 0x01EC 0x01ED 0x01EE 0x01EF 0x01F0 0x01F1 0x01F2 0x01F3 Name INTEG_ SETUP_H ADPD4100/ADPD4101 Bits [15:8] [7:0] INTEG_OS_H [15:8] [7:0] MOD_ [15:8] PULSE_H [7:0] PATTERN_H [15:8] [7:0] ADC_OFF1_H [15:8] [7:0] ADC_OFF2_H [15:8] [7:0] [15:8] [7:0] LIT_DATA_ [15:8] FORMAT_H [7:0] DECIMATE_H [15:8] [7:0] DIGINT_LIT_H [15:8] DATA_ FORMAT_H 0x01F4 DIGINT_ DARK_H [7:0] [15:8] [7:0] 0x01F5 THRESH_ CFG_H [15:8] [7:0] 0x01F6 THRESH0_H 0x01F7 THRESH1_H 0x0200 TS_CTRL_I [15:8] [7:0] [15:8] [7:0] [15:8] 0x0201 TS_PATH_I [7:0] [15:8] 0x0202 INPUTS_I 0x0203 CATHODE_I 0x0204 AFE_TRIM_I 0x0205 LED_ POW12_I [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] 0x0206 LED_ POW34_I [15:8] [7:0] 0x0207 COUNTS_I [15:8] [7:0] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SINGLE_ CH2_AMP_DISABLE_H[2:0] AFE_INT_C_ CH1_AMP_DISABLE_H[2:0] INTEG_H BUF_H ADC_COUNT_H[1:0] Reserved INTEG_WIDTH_H[4:0] Reserved INTEG_ OFFSET_H[12:8] INTEG_OFFSET_H[7:0] MOD_WIDTH_H[7:0] MOD_OFFSET_H[7:0] LED_DISABLE_H[3:0] MOD_DISABLE_H[3:0] SUBTRACT_H[3:0] REVERSE_INTEG_H[3:0] Reserved CH1_ADC_ADJUST_H[13:8] CH1_ADC_ADJUST_H[7:0] ZERO_ Reserved CH2_ADC_ADJUST_H[13:8] ADJUST_H CH2_ADC_ADJUST_H[7:0] DARK_SHIFT_H[4:0] DARK_SIZE_H[2:0] SIGNAL_SHIFT_H[4:0] SIGNAL_SIZE_H[2:0] Reserved LIT_SHIFT_H[4:0] LIT_SIZE_H[2:0] Reserved DECIMATE_FACTOR_H[6:4] DECIMATE_FACTOR_H[3:0] DECIMATE_TYPE_H[3:0] Reserved LIT_ OFFSET_ H[8] LIT_OFFSET_H[7:0] DARK2_OFFSET_H[8:1] DARK2_ DARK1_OFFSET_H[6:0] OFFSET_H[0] Reserved THRESH1_ THRESH1_ THRESH1_TYPE_H[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_H[1:0] CHAN_H DIR_H CHAN_H DIR_H Reserved THRESH0_SHIFT_H[4:0] THRESH0_VALUE_H[7:0] Reserved THRESH1_SHIFT_H[4:0] THRESH1_VALUE_H[7:0] SUBSAMPLE_I CH2_EN_I SAMPLE_TYPE_I[1:0] INPUT_R_SELECT_I[1:0] TIMESLOT_ OFFSET_I[9:8] TIMESLOT_OFFSET_I[7:0] PRE_WIDTH_I[3:0] Reserved TS_GPIO_I AFE_PATH _CFG_I[8] AFE_PATH_CFG_I[7:0] INP78_I[3:0] INP56_I[3:0] INP34_I[3:0] INP12_I[3:0] Reserved PRECON_I[2:0] VC2_PULSE_I[1:0] VC2_ALT_I[1:0] VC2_SEL_I[1:0] VC1_PULSE_I[1:0] VC1_ALT_I[1:0] VC1_SEL_I[1:0] TIA_CEIL_ CH2_TRIM_INT_I[1:0] CH1_TRIM_INT_I[1:0] VREF_ AFE_TRIM_ VREF_I[1:0] DETECT_EN_I PULSE_I VREF_PULSE_VAL_I[1:0] TIA_GAIN_CH2_I[2:0] TIA_GAIN_CH1_I[2:0] LED_ LED_CURRENT2_I[6:0] DRIVESIDE2_I LED_ LED_CURRENT1_I[6:0] DRIVESIDE1_I LED_ LED_CURRENT4_I[6:0] DRIVESIDE4_I LED_ LED_CURRENT3_I[6:0] DRIVESIDE3_I NUM_INT_I[7:0] NUM_REPEAT_I[7:0] Rev. 0 | Page 65 of 101 Reset 0x0003 R/W R/W 0x0214 R/W 0x0001 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0003 R/W 0x0000 R/W 0x0000 R/W 0x0026 R/W 0x2306 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x40DA R/W 0x0000 R/W 0x0000 R/W 0x03C0 R/W 0x0000 R/W 0x0000 R/W 0x0101 R/W ADPD4100/ADPD4101 Reg 0x0208 0x0209 0x020A 0x020B 0x020C 0x020D 0x020E 0x020F 0x0210 0x0211 0x0212 0x0213 Name PERIOD_I Bits [15:8] [7:0] LED_PULSE_I [15:8] [7:0] INTEG_ [15:8] SETUP_I [7:0] INTEG_OS_I [15:8] [7:0] MOD_ [15:8] PULSE_I [7:0] PATTERN_I [15:8] [7:0] ADC_OFF1_I [15:8] [7:0] ADC_OFF2_I [15:8] [7:0] [15:8] [7:0] LIT_DATA_ [15:8] FORMAT_I [7:0] DECIMATE_I [15:8] [7:0] DIGINT_LIT_I [15:8] DATA_ FORMAT_I 0x0214 DIGINT_ DARK_I [7:0] [15:8] [7:0] 0x0215 THRESH_ CFG_I [15:8] [7:0] 0x0216 THRESH0_I 0x0217 THRESH1_I 0x0220 TS_CTRL_J [15:8] [7:0] [15:8] [7:0] [15:8] 0x0221 TS_PATH_J [7:0] [15:8] 0x0222 INPUTS_J 0x0223 CATHODE_J 0x0224 AFE_TRIM_J 0x0225 LED_ POW12_J [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] Bit 15 Bit 7 Data Sheet Bit 14 Bit 6 Reserved Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MOD_TYPE_I[1:0] Reserved MIN_PERIOD_I[9:8] MIN_PERIOD_I[7:0] LED_WIDTH_I[7:0] LED_OFFSET_I[7:0] SINGLE_ CH2_AMP_DISABLE_I[2:0] AFE_INT_ CH1_AMP_DISABLE_I[2:0] INTEG_I C_BUF_I ADC_COUNT_I[1:0] Reserved INTEG_WIDTH_I[4:0] Reserved INTEG_OFFSET_I[12:8] INTEG_OFFSET_I[7:0] MOD_WIDTH_I[7:0] MOD_OFFSET_I[7:0] LED_DISABLE_I[3:0] MOD_DISABLE_I[3:0] SUBTRACT_I[3:0] REVERSE_INTEG_I[3:0] Reserved CH1_ADC_ADJUST_I[13:8] CH1_ADC_ADJUST_I[7:0] ZERO_ Reserved CH2_ADC_ADJUST_I[13:8] ADJUST_I CH2_ADC_ADJUST_I[7:0] DARK_SHIFT_I[4:0] DARK_SIZE_I[2:0] SIGNAL_SHIFT_I[4:0] SIGNAL_SIZE_I[2:0] Reserved LIT_SHIFT_I[4:0] LIT_SIZE_I[2:0] Reserved DECIMATE_FACTOR_I[6:4] DECIMATE_FACTOR_I[3:0] DECIMATE_TYPE_I[3:0] Reserved LIT_ OFFSET_ I[8] LIT_OFFSET_I[7:0] DARK2_OFFSET_I[8:1] DARK2_ DARK1_OFFSET_I[6:0] OFFSET_I[0] Reserved THRESH1_ THRESH1_ THRESH1_TYPE_I[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_I[1:0] CHAN_I DIR_I CHAN_I DIR_I Reserved THRESH0_SHIFT_I[4:0] THRESH0_VALUE_I[7:0] Reserved THRESH1_SHIFT_I[4:0] THRESH1_VALUE_I[7:0] SUBSAMPLE_J CH2_EN_J SAMPLE_TYPE_J[1:0] INPUT_R_SELECT_J[1:0] TIMESLOT_ OFFSET_J[9:8] TIMESLOT_OFFSET_J[7:0] PRE_WIDTH_J[3:0] Reserved TS_GPIO_J AFE_PATH _CFG_J[8] AFE_PATH_CFG_J[7:0] INP78_J[3:0] INP56_J[3:0] INP34_J[3:0] INP12_J[3:0] Reserved PRECON_J[2:0] VC2_PULSE_J[1:0] VC2_ALT_J[1:0] VC2_SEL_J[1:0] VC1_PULSE_J[1:0] VC1_ALT_J[1:0] VC1_SEL_J[1:0] TIA_CEIL_ CH2_TRIM_INT_J[1:0] CH1_TRIM_INT_J[1:0] VREF_ AFE_TRIM_ DETECT_EN_J PULSE_J VREF_J[1:0] VREF_PULSE_VAL_J[1:0] TIA_GAIN_CH2_J[2:0] TIA_GAIN_CH1_J[2:0] LED_ LED_CURRENT2_J[6:0] DRIVESIDE2_J LED_ LED_CURRENT1_J[6:0] DRIVESIDE1_J Rev. 0 | Page 66 of 101 Reset 0x0000 R/W R/W 0x0210 R/W 0x0003 R/W 0x0214 R/W 0x0001 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0003 R/W 0x0000 R/W 0x0000 R/W 0x0026 R/W 0x2306 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x40DA R/W 0x0000 R/W 0x0000 R/W 0x03C0 R/W 0x0000 R/W Data Sheet Reg 0x0226 Name LED_ POW34_J ADPD4100/ADPD4101 Bits [15:8] [7:0] 0x0227 0x0228 0x0229 0x022A 0x022B 0x022C 0x022D 0x022E 0x022F 0x0230 0x0231 0x0232 0x0233 COUNTS_J [15:8] [7:0] PERIOD_J [15:8] [7:0] LED_PULSE_J [15:8] [7:0] INTEG_ [15:8] SETUP_J [7:0] INTEG_OS_J [15:8] [7:0] MOD_ [15:8] PULSE_J [7:0] PATTERN_J [15:8] [7:0] ADC_OFF1_J [15:8] [7:0] ADC_OFF2_J [15:8] [7:0] [15:8] [7:0] LIT_DATA_ [15:8] FORMAT_J [7:0] DECIMATE_J [15:8] [7:0] DIGINT_LIT_J [15:8] DATA_ FORMAT_J 0x0234 DIGINT_ DARK_J [7:0] [15:8] [7:0] 0x0235 THRESH_ CFG_J [15:8] [7:0] 0x0236 THRESH0_J 0x0237 THRESH1_J 0x0240 TS_CTRL_K [15:8] [7:0] [15:8] [7:0] [15:8] 0x0241 TS_PATH_K [7:0] [15:8] 0x0242 INPUTS_K 0x0243 0x0244 [7:0] [15:8] [7:0] CATHODE_K [15:8] [7:0] AFE_TRIM_K [15:8] [7:0] Bit 15 Bit 14 Bit 7 Bit 6 LED_ DRIVESIDE4_J LED_ DRIVESIDE3_J Bit 13 Bit 5 Bit 12 Bit 4 Bit 11 Bit 10 Bit 3 Bit 2 LED_CURRENT4_J[6:0] Bit 9 Bit 1 Bit 8 Bit 0 Reset 0x0000 R/W R/W 0x0101 R/W 0x0000 R/W 0x0210 R/W 0x0003 R/W 0x0214 R/W 0x0001 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0003 R/W 0x0000 R/W 0x0000 R/W 0x0026 R/W 0x2306 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x40DA R/W 0x0000 R/W 0x0000 R/W 0x03C0 R/W LED_CURRENT3_J[6:0] NUM_INT_J[7:0] NUM_REPEAT_J[7:0] Reserved MOD_TYPE_J[1:0] Reserved MIN_PERIOD_J[9:8] MIN_PERIOD_J[7:0] LED_WIDTH_J[7:0] LED_OFFSET_J[7:0] SINGLE_ CH2_AMP_DISABLE_J[2:0] AFE_INT_ CH1_AMP_DISABLE_J[2:0] INTEG_J C_BUF_J ADC_COUNT_J[1:0] Reserved INTEG_WIDTH_J[4:0] Reserved INTEG_ OFFSET_J[12:8] INTEG_OFFSET_J[7:0] MOD_WIDTH_J[7:0] MOD_OFFSET_J[7:0] LED_DISABLE_J[3:0] MOD_DISABLE_J[3:0] SUBTRACT_J[3:0] REVERSE_INTEG_J[3:0] Reserved CH1_ADC_ADJUST_J[13:8] CH1_ADC_ADJUST_J[7:0] ZERO_ Reserved CH2_ADC_ADJUST_J[13:8] ADJUST_J CH2_ADC_ADJUST_J[7:0] DARK_SHIFT_J[4:0] DARK_SIZE_J[2:0] SIGNAL_SHIFT_J[4:0] SIGNAL_SIZE_J[2:0] Reserved LIT_SHIFT_J[4:0] LIT_SIZE_J[2:0] Reserved DECIMATE_FACTOR_J[6:4] DECIMATE_FACTOR_J[3:0] DECIMATE_TYPE_J[3:0] Reserved LIT_ OFFSET_ J[8] LIT_OFFSET_J[7:0] DARK2_OFFSET_J[8:1] DARK2_ DARK1_OFFSET_J[6:0] OFFSET_J[0] Reserved THRESH1_ THRESH1_ THRESH1_TYPE_J[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_J[1:0] CHAN_J DIR_J CHAN_J DIR_J Reserved THRESH0_SHIFT_J[4:0] THRESH0_VALUE_J[7:0] Reserved THRESH1_SHIFT_J[4:0] THRESH1_VALUE_J[7:0] SUBSAMPLE_K CH2_EN_K SAMPLE_TYPE_K[1:0] INPUT_R_SELECT_K[1:0] TIMESLOT_ OFFSET_K[9:8] TIMESLOT_OFFSET_K[7:0] PRE_WIDTH_K[3:0] Reserved TS_GPIO_K AFE_PATH _CFG_K[8] AFE_PATH_CFG_K[7:0] INP78_K[3:0] INP56_K[3:0] INP34_K[3:0] INP12_K[3:0] Reserved PRECON_K[2:0] VC2_PULSE_K[1:0] VC2_ALT_K[1:0] VC2_SEL_K[1:0] VC1_PULSE_K[1:0] VC1_ALT_K[1:0] VC1_SEL_K[1:0] TIA_CEIL_ CH2_TRIM_INT_K[1:0] CH1_TRIM_INT_K[1:0] VREF_ AFE_TRIM_ DETECT_EN_K PULSE_K VREF_K[1:0] VREF_PULSE_VAL_K[1:0] TIA_GAIN_CH2_K[2:0] TIA_GAIN_CH1_K[2:0] Rev. 0 | Page 67 of 101 ADPD4100/ADPD4101 Reg 0x0245 Name LED_ POW12_K Bits [15:8] [7:0] 0x0246 LED_ POW34_K [15:8] [7:0] 0x0247 0x0248 0x0249 0x024A 0x024B 0x024C 0x024D 0x024E 0x024F 0x0250 0x0251 0x0252 0x0253 COUNTS_K [15:8] [7:0] PERIOD_K [15:8] [7:0] LED_PULSE_K [15:8] [7:0] INTEG_ [15:8] SETUP_K [7:0] INTEG_OS_K [15:8] [7:0] MOD_ [15:8] PULSE_K [7:0] PATTERN_K [15:8] [7:0] ADC_OFF1_K [15:8] [7:0] ADC_OFF2_K [15:8] [7:0] [15:8] [7:0] LIT_DATA_ [15:8] FORMAT_K [7:0] DECIMATE_K [15:8] [7:0] DIGINT_LIT_K [15:8] DATA_ FORMAT_K 0x0254 DIGINT_ DARK_K [7:0] [15:8] [7:0] 0x0255 THRESH_ CFG_K [15:8] [7:0] 0x0256 THRESH0_K 0x0257 THRESH1_K 0x0260 TS_CTRL_L [15:8] [7:0] [15:8] [7:0] [15:8] 0x0261 TS_PATH_L [7:0] [15:8] 0x0262 INPUTS_L 0x0263 CATHODE_L [7:0] [15:8] [7:0] [15:8] [7:0] Bit 15 Bit 14 Bit 7 Bit 6 LED_ DRIVESIDE2_K LED_ DRIVESIDE1_K LED_ DRIVESIDE4_K LED_ DRIVESIDE3_K Data Sheet Bit 13 Bit 5 Bit 12 Bit 4 Bit 11 Bit 10 Bit 3 Bit 2 LED_CURRENT2_K[6:0] Bit 9 Bit 1 Bit 8 Bit 0 Reset 0x0000 R/W R/W 0x0000 R/W 0x0101 R/W 0x0000 R/W 0x0210 R/W 0x0003 R/W 0x0214 R/W 0x0001 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0003 R/W 0x0000 R/W 0x0000 R/W 0x0026 R/W 0x2306 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x40DA R/W 0x0000 R/W 0x0000 R/W LED_CURRENT1_K[6:0] LED_CURRENT4_K[6:0] LED_CURRENT3_K[6:0] NUM_INT_K[7:0] NUM_REPEAT_K[7:0] Reserved MOD_TYPE_K[1:0] Reserved MIN_PERIOD_K[9:8] MIN_PERIOD_K[7:0] LED_WIDTH_K[7:0] LED_OFFSET_K[7:0] SINGLE_ CH2_AMP_DISABLE_K[2:0] AFE_INT_C_ CH1_AMP_DISABLE_K[2:0] INTEG_K BUF_K ADC_COUNT_K[1:0] Reserved INTEG_WIDTH_K[4:0] Reserved INTEG_ OFFSET_K[12:8] INTEG_OFFSET_K[7:0] MOD_WIDTH_K[7:0] MOD_OFFSET_K[7:0] LED_DISABLE_K[3:0] MOD_DISABLE_K[3:0] SUBTRACT_K[3:0] REVERSE_INTEG_K[3:0] Reserved CH1_ADC_ADJUST_K[13:8] CH1_ADC_ADJUST_K[7:0] ZERO_ Reserved CH2_ADC_ADJUST_K[13:8] ADJUST_K CH2_ADC_ADJUST_K[7:0] DARK_SHIFT_K[4:0] DARK_SIZE_K[2:0] SIGNAL_SHIFT_K[4:0] SIGNAL_SIZE_K[2:0] Reserved LIT_SHIFT_K[4:0] LIT_SIZE_K[2:0] Reserved DECIMATE_FACTOR_K[6:4] DECIMATE_FACTOR_K[3:0] DECIMATE_TYPE_K[3:0] Reserved LIT_ OFFSET_ K[8] LIT_OFFSET_K[7:0] DARK2_OFFSET_K[8:1] DARK2_ DARK1_OFFSET_K[6:0] OFFSET_K[0] Reserved THRESH1_ THRESH1_ THRESH1_TYPE_K[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_ K[1:0] CHAN_K DIR_K CHAN_K DIR_K Reserved THRESH0_SHIFT_K[4:0] THRESH0_VALUE_K[7:0] Reserved THRESH1_SHIFT_K[4:0] THRESH1_VALUE_K[7:0] SUBSAMPLE_L CH2_EN_L SAMPLE_TYPE_L[1:0] INPUT_R_SELECT_L[1:0] TIMESLOT_ OFFSET_L[9:8] TIMESLOT_OFFSET_L[7:0] PRE_WIDTH_L[3:0] Reserved TS_GPIO_L AFE_PATH _CFG_L[8] AFE_PATH_CFG_L[7:0] INP78_L[3:0] INP56_L[3:0] INP34_L[3:0] INP12_L[3:0] Reserved PRECON_L[2:0] VC2_PULSE_L[1:0] VC2_ALT_L[1:0] VC2_SEL_L[1:0] VC1_PULSE_L[1:0] VC1_ALT_L[1:0] VC1_SEL_L[1:0] Rev. 0 | Page 68 of 101 Data Sheet Reg 0x0264 Name AFE_TRIM_L 0x0265 LED_ POW12_L ADPD4100/ADPD4101 Bits [15:8] [7:0] [15:8] [7:0] 0x0266 LED_ POW34_L [15:8] [7:0] 0x0267 0x0268 0x0269 0x026A 0x026B 0x026C 0x026D 0x026E 0x026F 0x0270 0x0271 0x0272 0x0273 COUNTS_L [15:8] [7:0] PERIOD_L [15:8] [7:0] LED_PULSE_L [15:8] [7:0] INTEG_ [15:8] SETUP_L [7:0] INTEG_OS_L [15:8] [7:0] MOD_ [15:8] PULSE_L [7:0] PATTERN_L [15:8] [7:0] ADC_OFF1_L [15:8] [7:0] ADC_OFF2_L [15:8] [7:0] [15:8] [7:0] LIT_DATA_ [15:8] FORMAT_L [7:0] DECIMATE_L [15:8] [7:0] DIGINT_LIT_L [15:8] DATA_ FORMAT_L 0x0274 DIGINT_ DARK_L [7:0] [15:8] [7:0] 0x0275 THRESH_ CFG_L [15:8] [7:0] 0x0276 THRESH0_L 0x0277 THRESH1_L [15:8] [7:0] [15:8] [7:0] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TIA_CEIL_ CH2_TRIM_INT_L[1:0] CH1_TRIM_INT_L[1:0] VREF_ AFE_TRIM_ DETECT_EN_L PULSE_L VREF_L[1:0] VREF_PULSE_VAL_L[1:0] TIA_GAIN_CH2_L[2:0] TIA_GAIN_CH1_L[2:0] LED_ LED_CURRENT2_L[6:0] DRIVESIDE2_L LED_ LED_CURRENT1_L[6:0] DRIVESIDE1_L LED_ LED_CURRENT4_L[6:0] DRIVESIDE4_L LED_ LED_CURRENT3_L[6:0] DRIVESIDE3_L NUM_INT_L[7:0] NUM_REPEAT_L[7:0] Reserved MOD_TYPE_L[1:0] Reserved MIN_PERIOD_L[9:8] MIN_PERIOD_L[7:0] LED_WIDTH_L[7:0] LED_OFFSET_L[7:0] SINGLE_ CH2_AMP_DISABLE_L[2:0] AFE_INT_C_ CH1_AMP_DISABLE_L[2:0] INTEG_L BUF_L ADC_COUNT_L[1:0] Reserved INTEG_WIDTH_L[4:0] Reserved INTEG_ OFFSET_L[12:8] INTEG_OFFSET_L[7:0] MOD_WIDTH_L[7:0] MOD_OFFSET_L[7:0] LED_DISABLE_L[3:0] MOD_DISABLE_L[3:0] SUBTRACT_L[3:0] REVERSE_INTEG_L[3:0] Reserved CH1_ADC_ADJUST_L[13:8] CH1_ADC_ADJUST_L[7:0] ZERO_ Reserved CH2_ADC_ADJUST_L[13:8] ADJUST_L CH2_ADC_ADJUST_L[7:0] DARK_SHIFT_L[4:0] DARK_SIZE_L[2:0] SIGNAL_SHIFT_L[4:0] SIGNAL_SIZE_L[2:0] Reserved LIT_SHIFT_L[4:0] LIT_SIZE_L[2:0] Reserved DECIMATE_FACTOR_L[6:4] DECIMATE_FACTOR_L[3:0] DECIMATE_TYPE_L[3:0] Reserved LIT_ OFFSET_ L[8] LIT_OFFSET_L[7:0] DARK2_OFFSET_L[8:1] DARK2_ DARK1_OFFSET_L[6:0] OFFSET_L[0] Reserved THRESH1_ THRESH1_ THRESH1_TYPE_L[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_L[1:0] CHAN_L DIR_L CHAN_L DIR_L Reserved THRESH0_SHIFT_L[4:0] THRESH0_VALUE_L[7:0] Reserved THRESH1_SHIFT_L[4:0] THRESH1_VALUE_L[7:0] Rev. 0 | Page 69 of 101 Reset 0x03C0 R/W R/W 0x0000 R/W 0x0000 R/W 0x0101 R/W 0x0000 R/W 0x0210 R/W 0x0003 R/W 0x0214 R/W 0x0001 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0003 R/W 0x0000 R/W 0x0000 R/W 0x0026 R/W 0x2306 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W ADPD4100/ADPD4101 Data Sheet REGISTER DETAILS GLOBAL CONFIGURATION REGISTERS Table 30. Global Configuration Register Details Addr Name 0x000D TS_FREQ 0x000E TS_FREQH 0x000F SYS_CTL 0x0010 OPMODE Bits [15:0] Bit Name Description TIMESLOT_PERIOD_L Lower 16 bits of time slot period in low frequency oscillator cycles. The time slot rate is (low frequency oscillator frequency) ÷ (TIMESLOT_PERIOD_x). The default value operates at 100 Hz when using the 1 MHz low frequency oscillator. [15:7] Reserved Reserved. [6:0] TIMESLOT_PERIOD_H Upper seven bits of time slot period in low frequency oscillator cycles. The time slot rate is (low frequency oscillator frequency) ÷ (TIMESLOT_PERIOD_x). The default value operates at 100 Hz when using the 1 MHz low frequency oscillator. Software reset. Write 1 to this bit to assert a software reset, which 15 SW_RESET stops all AFE operations and resets the device to its default values. Software reset does not reset the SPI or I2C port. [14:10] Reserved Reserved. [9:8] ALT_CLOCKS External clock select. 00: use internal low frequency oscillator and high frequency oscillator. 01: use external low frequency oscillator. 02: use external high frequency oscillator and internal low frequency oscillator. 03: use external high frequency oscillator and generate low frequency oscillator from high frequency oscillator. [7:6] ALT_CLK_GPIO Alternate clock GPIO select. 00: use GPIO0 for alternate clock. 01: use GPIO1 for alternate clock. 10: use GPIO2 for alternate clock. 11: use GPIO3 for alternate clock. [5:3] Reserved Write 0x0. Selects low frequency oscillator. This bit selects between the 2 LFOSC_SEL 32 kHz and 1 MHz low speed oscillator. 0: use the 32 kHz oscillator as the low frequency clock. 1: use the 1 MHz oscillator as the low frequency clock. Enable 1 MHz low frequency oscillator. This bit turns on the 1 MHz 1 OSC_1M_EN low frequency oscillator, which must be left running during all operations while using this oscillator. Enable 32 kHz low frequency oscillator. This bit turns on the 32 kHz 0 OSC_32K_EN low frequency oscillator, which must be left running during all operations while using this oscillator. [15:12] Reserved Reserved. [11:8] TIMESLOT_EN Time slot enable control. 0000: Time Slot Sequence A only. 0001: Time Slot Sequence AB. 0010: Time Slot Sequence ABC. 0011: Time Slot Sequence ABCD. 0100: Time Slot Sequence ABCDE. 0101: Time Slot Sequence ABCDEF. 0110: Time Slot Sequence ABCDEFG. 0111: Time Slot Sequence ABCDEFGH. 1000: Time Slot Sequence ABCDEFGHI. 1001: Time Slot Sequence ABCDEFGHIJ. 1010: Time Slot Sequence ABCDEFGHIJK. 1011: Time Slot Sequence ABCDEFGHIJKL. Rev. 0 | Page 70 of 101 Reset Access 0x2710 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R/W R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W Data Sheet Addr Name ADPD4100/ADPD4101 Bits [7:1] 0 Bit Name Reserved OP_MODE 0x0020 INPUT_SLEEP [15:12] INP_SLEEP_78 [11:8] INP_SLEEP_56 [7:4] INP_SLEEP_34 [3:0] INP_SLEEP_12 Description Reserved. Operating mode selection. 0: standby. 1: go mode. Operate selected time slots. Input pair sleep state for IN7 and IN8 inputs. 0x0: both inputs float. 0x1: floating short of IN7 to IN8. Only if PAIR78 is set to 1. 0x2: IN7 and IN8 connected to VC1. Also shorted together if PAIR78 is set to 1. 0x3: IN7 and IN8 connected to VC2. Also shorted together if PAIR78 is set to 1. 0x4: IN7 connected to VC1. IN8 floating. 0x5: IN7 connected to VC1. IN8 connected to VC2. 0x6: IN7 connected to VC2. IN8 floating. 0x7: IN7 connected to VC2. IN8 connected to VC1. 0x8: IN7 floating. IN8 connected to VC1. 0x9: IN7 floating. IN8 connected to VC2. Input pair sleep state for IN5 and IN6 inputs. 0x0: both inputs float. 0x1: floating short of IN5 to IN6. Only if PAIR56 is set to 1. 0x2: IN5 and IN6 connected to VC1. Also shorted together if PAIR56 is set to 1. 0x3: IN5 and IN6 connected to VC2. Also shorted together if PAIR56 is set to 1. 0x4: IN5 connected to VC1. IN6 floating. 0x5: IN5 connected to VC1. IN6 connected to VC2. 0x6: IN5 connected to VC2. IN6 floating. 0x7: IN5 connected to VC2. IN6 connected to VC1. 0x8: IN5 floating. IN6 connected to VC1. 0x9: IN5 floating. IN6 connected to VC2. Input pair sleep state for IN3 and IN4 inputs. 0x0: both inputs float. 0x1: floating short of IN3 to IN4. Only if PAIR34 is set to 1. 0x2: IN3 and IN4 connected to VC1. Also shorted together if PAIR34 is set to 1. 0x3: IN3 and IN4 connected to VC2. Also shorted together if PAIR34 is set to 1. 0x4: IN3 connected to VC1. IN4 floating. 0x5: IN3 connected to VC1. IN4 connected to VC2. 0x6: IN3 connected to VC2. IN4 floating. 0x7: IN3 connected to VC2. IN4 connected to VC1. 0x8: IN3 floating. IN4 connected to VC1. 0x9: IN3 floating. IN4 connected to VC2. Input pair sleep state for IN1 and IN2 inputs. 0x0: both inputs float. 0x1: floating short of IN1 to IN2. Only if PAIR12 is set to 1. 0x2: IN1 and IN2 connected to VC1. Also shorted together if PAIR12 is set to 1. 0x3: IN1 and IN2 connected to VC2. Also shorted together if PAIR12 is set to 1. 0x4: IN1 connected to VC1. IN2 floating. 0x5: IN1 connected to VC1. IN2 connected to VC2. 0x6: IN1 connected to VC2. IN2 floating. Rev. 0 | Page 71 of 101 Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W ADPD4100/ADPD4101 Addr Name 0x0021 INPUT_CFG Data Sheet Bits Bit Name [15:8] [7:6] Reserved VC2_SLEEP [5:4] VC1_SLEEP 3 PAIR78 2 PAIR56 1 PAIR34 0 PAIR12 Description 0x7: IN1 connected to VC2. IN2 connected to VC1. 0x8: IN1 floating. IN2 connected to VC1. 0x9: IN1 floating. IN2 connected to VC2. Reserved. VC2 sleep state. 0: VC2 set to AVDD during sleep. 1: VC2 set to ground during sleep. 10: VC2 floating during sleep. VC1 sleep state. 0: VC1 set to AVDD during sleep. 1: VC1 set to ground during sleep. 10: VC1 floating during sleep. Input pair configuration. 0: IN7 and IN8 configured as two single-ended inputs. 1: IN7 and IN8 configured as a differential pair. Input pair configuration. 0: IN5 and IN6 configured as two single-ended inputs. 1: IN5 and IN6 configured as a differential pair. Input pair configuration. 0: IN3 and IN4 configured as two single-ended inputs. 1: IN3 and IN4 configured as a differential pair. Input pair configuration. 0: IN1 and IN2 configured as two single-ended inputs. 1: IN1 and IN2 configured as a differential pair. Reset Access 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W INTERRUPT STATUS AND CONTROL REGISTERS Table 31. Interrupt Status and Control Register Details Addr Name 0x0000 FIFO_STATUS 0x0001 INT_STATUS_DATA Bits 15 Bit Name CLEAR_FIFO 14 INT_FIFO_UFLOW 13 INT_FIFO_OFLOW [12:11] Reserved [10:0] FIFO_BYTE_COUNT 15 INT_FIFO_TH [14:12] Reserved 11 INT_DATA_L Description Clear FIFO. Write a 1 to empty the FIFO while the FIFO is not being accessed. This resets FIFO_BYTE_COUNT and clears the INT_FIFO_OFLOW, INT_FIFO_UFLOW, and INT_FIFO_TH status bits. FIFO underflow error. This bit is set when the FIFO is read while empty. Write 1 to this bit to clear the interrupt. This bit is also cleared if the FIFO is cleared using the CLEAR_FIFO bit. FIFO overflow error. This bit is set when data was not written to the FIFO due to lack of space. Write 1 to this bit to clear the interrupt. This bit is also cleared if the FIFO is cleared with the CLEAR_FIFO bit. Reserved. This field indicates the number of bytes in the FIFO. FIFO_TH interrupt status. This bit is set during a FIFO write when the number of bytes in the FIFO exceeds the FIFO_TH register value. Write 1 to this bit to clear this interrupt. This bit can also be automatically cleared when the FIFO_DATA register is read if the INT_ACLEAR_FIFO bit is set. Reserved. Time Slot L data register interrupt status. This bit is set every time the Time Slot L data registers are updated. Write 1 to this bit to clear the interrupt. The interrupt is cleared automatically when the Time Slot L data registers are read if the INT_ACLEAR_DATA_L bit is set. Rev. 0 | Page 72 of 101 Reset Access1 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 0x0 0x0 R R R/W1C 0x0 0x0 R R/W1C Data Sheet Addr Name ADPD4100/ADPD4101 Bits 10 Bit Name INT_DATA_K 9 INT_DATA_J 8 INT_DATA_I 7 INT_DATA_H 6 INT_DATA_G 5 INT_DATA_F 4 INT_DATA_E 3 INT_DATA_D 2 INT_DATA_C 1 INT_DATA_B 0 INT_DATA_A Description Time Slot K data register interrupt status. This bit is set every time the Time Slot K data registers get updated. Write 1 to this bit to clear the interrupt. The interrupt is cleared automatically when the Time Slot K data registers are read if the INT_ACLEAR_DATA_K bit is set. Time Slot J data register interrupt status. This bit is set every time the Time Slot J data registers are updated. Write 1 to this bit to clear the interrupt. The interrupt is cleared automatically when the Time Slot J data registers are read if the INT_ACLEAR_DATA_J bit is set. Time Slot I data register interrupt status. This bit is set every time the Time Slot I data registers are updated. Write 1 to this bit to clear the interrupt. The interrupt is cleared automatically when the Time Slot I data registers are read if the INT_ACLEAR_DATA_I bit is set. Time Slot H data register interrupt status. This bit is set every time the Time Slot H data registers are updated. Write 1 to this bit to clear the interrupt. The interrupt is cleared automatically when the Time Slot H data registers are read if the INT_ACLEAR_DATA_H bit is set. Time Slot G data register interrupt status. This bit is set every time the Time Slot G data registers are updated. Write 1 to this bit to clear the interrupt. The interrupt is cleared automatically when the Time Slot G data registers are read if the INT_ACLEAR_DATA_G bit is set. Time Slot F data register interrupt status. This bit is set every time the Time Slot F data registers are updated. Write 1 to this bit to clear the interrupt. The interrupt is cleared automatically when the Time Slot F data registers are read if the INT_ACLEAR_DATA_F bit is set. Time Slot E data register interrupt status. This bit is set every time the Time Slot E data registers are updated. Write 1 to this bit to clear the interrupt. The interrupt is cleared automatically when the Time Slot E data registers are read if the INT_ACLEAR_DATA_E bit is set. Time Slot D data register interrupt status. This bit is set every time the Time Slot D data registers are updated. Write 1 to this bit to clear the interrupt. The interrupt is cleared automatically when the Time Slot D data registers are read if the INT_ACLEAR_DATA_D bit is set. Time Slot C data register interrupt status. This bit is set every time the Time Slot C data registers are updated. Write 1 to this bit to clear the interrupt. The interrupt is cleared automatically when the Time Slot C data registers are read if the INT_ACLEAR_DATA_C bit is set. Time Slot B data register interrupt status. This bit is set every time the Time Slot B data registers are updated. Write 1 to this bit to clear the interrupt. The interrupt is cleared automatically when the Time Slot B data registers are read if the INT_ACLEAR_DATA_B bit is set. Time Slot A data register interrupt status. This bit is set every time the Time Slot A data registers are updated. Write 1 to this bit to clear the interrupt. The interrupt is cleared automatically when the Time Slot A data registers are read if the INT_ACLEAR_DATA_A bit is set. Rev. 0 | Page 73 of 101 Reset Access1 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C ADPD4100/ADPD4101 Addr Name 0x0002 INT_STATUS_LEV0 0x0003 INT_STATUS_LEV1 0x0004 INT_STATUS_TC1 Data Sheet Bits Bit Name [15:12] Reserved 11 INT_LEV0_L 10 INT_LEV0_K 9 INT_LEV0_J 8 INT_LEV0_I 7 INT_LEV0_H 6 INT_LEV0_G 5 INT_LEV0_F 4 INT_LEV0_E 3 INT_LEV0_D 2 INT_LEV0_C 1 INT_LEV0_B 0 INT_LEV0_A [15:12] Reserved 11 INT_LEV1_L 10 INT_LEV1_K 9 INT_LEV1_J 8 INT_LEV1_I 7 INT_LEV1_H 6 INT_LEV1_G 5 INT_LEV1_F 4 INT_LEV1_E 3 INT_LEV1_D 2 INT_LEV1_C 1 INT_LEV1_B 0 INT_LEV1_A [15:12] Reserved 11 INT_TCLN1_L 10 INT_TCLN1_K Description Reserved. Time Slot L Level 0 interrupt status. This bit is set during a data register update when the configured criteria is met. Time Slot K Level 0 interrupt status. This bit is set during a data register update when the configured criteria is met. Time Slot J Level 0 interrupt status. This bit is set during a data register update when the configured criteria is met. Time Slot I Level 0 interrupt status. This bit is set during a data register update when the configured criteria is met. Time Slot H Level 0 interrupt status. This bit is set during a data register update when the configured criteria is met. Time Slot G Level 0 interrupt status. This bit is set during a data register update when the configured criteria is met. Time Slot F Level 0 interrupt status. This bit is set during a data register update when the configured criteria is met. Time Slot E Level 0 interrupt status. This bit is set during a data register update when the configured criteria is met. Time Slot D Level 0 interrupt status. This bit is set during a data register update when the configured criteria is met. Time Slot C Level 0 interrupt status. This bit is set during a data register update when the configured criteria is met. Time Slot B Level 0 interrupt status. This bit is set during a data register update when the configured criteria is met. Time Slot A Level 0 interrupt status. This bit is set during a data register update when the configured criteria is met. Reserved. Time Slot L Level 1 interrupt status. This bit is set during a data register update when the configured criteria is met. Time Slot K Level 1 interrupt status. This bit is set during a data register update when the configured criteria is met. Time Slot J Level 1 interrupt status. This bit is set during a data register update when the configured criteria is met. Time Slot I Level 1 interrupt status. This bit is set during a data register update when the configured criteria is met. Time Slot H Level 1 interrupt status. This bit is set during a data register update when the configured criteria is met. Time Slot G Level 1 interrupt status. This bit is set during a data register update when the configured criteria is met. Time Slot F Level 1 interrupt status. This bit is set during a data register update when the configured criteria is met. Time Slot E Level 1 interrupt status. This bit is set during a data register update when the configured criteria is met. Time Slot D Level 1 interrupt status. This bit is set during a data register update when the configured criteria is met. Time Slot C Level 1 interrupt status. This bit is set during a data register update when the configured criteria is met. Time Slot B Level 1 interrupt status. This bit is set during a data register update when the configured criteria is met. Time Slot A Level 1 interrupt status. This bit is set during a data register update when the configured criteria is met. Reserved. Time Slot L Channel 1 ceiling detection interrupt status. This bit is set during a data register update when Channel 1 exceeds the threshold level during Time Slot L. Time Slot K Channel 1 ceiling detection interrupt status. This bit is set during a data register update when Channel 1 exceeds the threshold level during Time Slot K. Rev. 0 | Page 74 of 101 Reset Access1 0x0 R 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 0x0 R R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 0x0 R R/W1C 0x0 R/W1C Data Sheet Addr Name 0x0005 INT_STATUS_TC2 ADPD4100/ADPD4101 Bits 9 Bit Name INT_TCLN1_J 8 INT_TCLN1_I 7 INT_TCLN1_H 6 INT_TCLN1_G 5 INT_TCLN1_F 4 INT_TCLN1_E 3 INT_TCLN1_D 2 INT_TCLN1_C 1 INT_TCLN1_B 0 INT_TCLN1_A [15:12] Reserved 11 INT_TCLN2_L 10 INT_TCLN2_K 9 INT_TCLN2_J 8 INT_TCLN2_I 7 INT_TCLN2_H 6 INT_TCLN2_G 5 INT_TCLN2_F 4 INT_TCLN2_E 3 INT_TCLN2_D Description Time Slot J Channel 1 ceiling detection interrupt status. This bit is set during a data register update when Channel 1 exceeds the threshold level during Time Slot J. Time Slot I Channel 1 ceiling detection interrupt status. This bit is set during a data register update when Channel 1 exceeds the threshold level during Time Slot I. Time Slot H Channel 1 ceiling detection interrupt status. This bit is set during a data register update when Channel 1 exceeds the threshold level during Time Slot H. Time Slot G Channel 1 ceiling detection interrupt status. This bit is set during a data register update when Channel 1 exceeds the threshold level during Time Slot G. Time Slot F Channel 1 ceiling detection interrupt status. This bit is set during a data register update when Channel 1 exceeds the threshold level during Time Slot F. Time Slot E Channel 1 ceiling detection interrupt status. This bit is set during a data register update when Channel 1 exceeds the threshold level during Time Slot E. Time Slot D Channel 1 ceiling detection interrupt status. This bit is set during a data register update when Channel 1 exceeds the threshold level during Time Slot D. Time Slot C Channel 1 ceiling detection interrupt status. This bit is set during a data register update when Channel 1 exceeds the threshold level during Time Slot C. Time Slot B Channel 1 ceiling detection interrupt status. This bit is set during a data register update when Channel 1 exceeds the threshold level during Time Slot B. Time Slot A Channel 1 ceiling detection interrupt status. This bit is set during a data register update when Channel 1 exceeds the threshold level during Time Slot A. Reserved. Time Slot L Channel 2 ceiling detection interrupt status. This bit is set during a data register update when Channel 2 exceeds the threshold level during Time Slot L. Time Slot K Channel 2 ceiling detection interrupt status. This bit is set during a data register update when Channel 2 exceeds the threshold level during Time Slot K. Time Slot J Channel 2 ceiling detection interrupt status. This bit is set during a data register update when Channel 2 exceeds the threshold level during Time Slot J. Time Slot I Channel 2 ceiling detection interrupt status. This bit is set during a data register update when Channel 2 exceeds the threshold level during Time Slot I. Time Slot H Channel 2 ceiling detection interrupt status. This bit is set during a data register update when Channel 2 exceeds the threshold level during Time Slot H. Time Slot G Channel 2 ceiling detection interrupt status. This bit is set during a data register update when Channel 2 exceeds the threshold level during Time Slot G. Time Slot F Channel 2 ceiling detection interrupt status. This bit is set during a data register update when Channel 2 exceeds the threshold level during Time Slot F. Time Slot E Channel 2 ceiling detection interrupt status. This bit is set during a data register update when Channel 2 exceeds the threshold level during Time Slot E. Time Slot D Channel 2 ceiling detection interrupt status. This bit is set during a data register update when Channel 2 exceeds the threshold level during Time Slot D. Rev. 0 | Page 75 of 101 Reset Access1 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 0x0 R R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C ADPD4100/ADPD4101 Addr Name 0x0007 INT_ACLEAR Data Sheet Bits 2 Bit Name INT_TCLN2_C 1 INT_TCLN2_B 0 INT_TCLN2_A 15 INT_ACLEAR_FIFO [14:12] Reserved 11 INT_ACLEAR_DATA_L 10 INT_ACLEAR_DATA_K 9 INT_ACLEAR_DATA_J 8 INT_ACLEAR_DATA_I 7 INT_ACLEAR_DATA_H 6 INT_ACLEAR_DATA_G 5 INT_ACLEAR_DATA_F 4 INT_ACLEAR_DATA_E 3 INT_ACLEAR_DATA_D 2 INT_ACLEAR_DATA_C 1 INT_ACLEAR_DATA_B 0 INT_ACLEAR_DATA_A Description Time Slot C Channel 2 ceiling detection interrupt status. This bit is set during a data register update when Channel 2 exceeds the threshold level during Time Slot C. Time Slot B Channel 2 ceiling detection interrupt status. This bit is set during a data register update when Channel 2 exceeds the threshold level during Time Slot B. Time Slot A Channel 2 ceiling detection interrupt status. This bit is set during a data register update when Channel 2 exceeds the threshold level during Time Slot A. FIFO threshold interrupt autoclear enable. Set this bit to enable automatic clearing of the FIFO_TH interrupt each time the FIFO is read. Reserved. Time Slot L interrupt autoclear enable. Set this bit to enable automatic clearing of the INT_DATA_L interrupt each time the Time Slot L data registers are read. Time Slot K interrupt autoclear enable. Set this bit to enable automatic clearing of the INT_DATA_K interrupt each time the Time Slot K data registers are read. Time Slot J interrupt autoclear enable. Set this bit to enable automatic clearing of the INT_DATA_J interrupt each time the Time Slot J data registers are read. Time Slot I interrupt autoclear enable. Set this bit to enable automatic clearing of the INT_DATA_I interrupt each time the Time Slot I data registers are read. Time Slot H interrupt autoclear enable. Set this bit to enable automatic clearing of the INT_DATA_H interrupt each time the Time Slot H data registers are read. Time Slot G interrupt autoclear enable. Set this bit to enable automatic clearing of the INT_DATA_G interrupt each time the Time Slot G data registers are read. Time Slot F interrupt autoclear enable. Set this bit to enable automatic clearing of the INT_DATA_F interrupt each time the Time Slot F data registers are read. Time Slot E interrupt autoclear enable. Set this bit to enable automatic clearing of the INT_DATA_E interrupt each time the Time Slot E data register is read. Time Slot D interrupt autoclear enable. Set this bit to enable automatic clearing of the INT_DATA_D interrupt each time the Time Slot D data registers are read. Time Slot C interrupt autoclear enable. Set this bit to enable automatic clearing of the INT_DATA_C interrupt each time the Time Slot C data registers are read. Time Slot B interrupt autoclear enable. Set this bit to enable automatic clearing of the INT_DATA_B interrupt each time the Time Slot B data registers are read. Time Slot A interrupt autoclear enable. Set this bit to enable automatic clearing of the INT_DATA_A interrupt each time the Time Slot A data registers are read. Rev. 0 | Page 76 of 101 Reset Access1 0x0 R/W1C 0x0 R/W1C 0x0 R/W1C 0x1 R/W 0x0 0x1 R R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x1 R/W Data Sheet Addr Name 0x0014 INT_ENABLE_XD 0x0015 INT_ENABLE_YD ADPD4100/ADPD4101 Bits 15 Bit Name INTX_EN_FIFO_TH 14 INTX_EN_FIFO_UFLOW 13 INTX_EN_FIFO_OFLOW 12 11 Reserved INTX_EN_DATA_L 10 INTX_EN_DATA_K 9 INTX_EN_DATA_J 8 INTX_EN_DATA_I 7 INTX_EN_DATA_H 6 INTX_EN_DATA_G 5 INTX_EN_DATA_F 4 INTX_EN_DATA_E 3 INTX_EN_DATA_D 2 INTX_EN_DATA_C 1 INTX_EN_DATA_B 0 INTX_EN_DATA_A 15 INTY_EN_FIFO_TH 14 INTY_EN_FIFO_UFLOW 13 INTY_EN_FIFO_OFLOW 12 11 Reserved INTY_EN_DATA_L 10 INTY_EN_DATA_K 9 INTY_EN_DATA_J 8 INTY_EN_DATA_I 7 INTY_EN_DATA_H 6 INTY_EN_DATA_G 5 INTY_EN_DATA_F 4 INTY_EN_DATA_E Description INT_FIFO_TH interrupt enable. Write a 1 to this bit to enable drive of the FIFO threshold status on Interrupt X. INT_FIFO_UFLOW interrupt enable for Interrupt X. Write a 1 to this bit to enable drive of the FIFO underflow status on Interrupt X. INT_FIFO_OFLOW interrupt enable for Interrupt X. Write a 1 to this bit to enable drive of the FIFO overflow status on Interrupt X. Reserved. INT_DATA_L interrupt enable. Write a 1 to this bit to enable drive of INT_DATA_L status on Interrupt X. INT_DATA_K interrupt enable. Write a 1 to this bit to enable drive of INT_DATA_K status on Interrupt X. INT_DATA_J interrupt enable. Write a 1 to this bit to enable drive of INT_DATA_J status on Interrupt X. INT_DATA_I interrupt enable. Write a 1 to this bit to enable drive of INT_DATA_I status on Interrupt X. INT_DATA_H interrupt enable. Write a 1 to this bit to enable drive of INT_DATA_H status on Interrupt X. INT_DATA_G interrupt enable. Write a 1 to this bit to enable drive of INT_DATA_G status on Interrupt X. INT_DATA_F interrupt enable. Write a 1 to this bit to enable drive of INT_DATA_F status on Interrupt X. INT_DATA_E interrupt enable. Write a 1 to this bit to enable drive of INT_DATA_E status on Interrupt X. INT_DATA_D interrupt enable. Write a 1 to this bit to enable drive of INT_DATA_D status on Interrupt X. INT_DATA_C interrupt enable. Write a 1 to this bit to enable drive of INT_DATA_C status on Interrupt X. INT_DATA_B interrupt enable. Write a 1 to this bit to enable drive of INT_DATA_B status on Interrupt X. INT_DATA_A interrupt enable. Write a 1 to this bit to enable drive of INT_DATA_A status on Interrupt X. INT_FIFO_TH interrupt enable. Write a 1 to this bit to enable drive of the FIFO threshold status on Interrupt Y. INT_FIFO_UFLOW interrupt enable for Interrupt Y. Write a 1 to this bit to enable drive of the FIFO underflow status on Interrupt Y. INT_FIFO_OFLOW interrupt enable for Interrupt Y. Write a 1 to this bit to enable drive of the FIFO overflow status on Interrupt Y. Reserved. INT_DATA_L interrupt enable. Write a 1 to this bit to enable drive of INT_DATA_L status on Interrupt Y. INT_DATA_K interrupt enable. Write a 1 to this bit to enable drive of INT_DATA_K status on Interrupt Y. INT_DATA_J interrupt enable. Write a 1 to this bit to enable drive of INT_DATA_J status on Interrupt Y. INT_DATA_I interrupt enable. Write a 1 to this bit to enable drive of INT_DATA_I status on Interrupt Y. INT_DATA_H interrupt enable. Write a 1 to this bit to enable drive of INT_DATA_H status on Interrupt Y. INT_DATA_G interrupt enable. Write a 1 to this bit to enable drive of INT_DATA_G status on Interrupt Y. INT_DATA_F interrupt enable. Write a 1 to this bit to enable drive of INT_DATA_F status on Interrupt Y. INT_DATA_E interrupt enable. Write a 1 to this bit to enable drive of INT_DATA_E status on Interrupt Y. Rev. 0 | Page 77 of 101 Reset Access1 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W ADPD4100/ADPD4101 Addr Name 0x0016 INT_ENABLE_XL0 0x0017 INT_ENABLE_XL1 Data Sheet Bits 3 Bit Name INTY_EN_DATA_D 2 INTY_EN_DATA_C 1 INTY_EN_DATA_B 0 INTY_EN_DATA_A [15:12] Reserved 11 INTX_EN_LEV0_L 10 INTX_EN_LEV0_K 9 INTX_EN_LEV0_J 8 INTX_EN_LEV0_I 7 INTX_EN_LEV0_H 6 INTX_EN_LEV0_G 5 INTX_EN_LEV0_F 4 INTX_EN_LEV0_E 3 INTX_EN_LEV0_D 2 INTX_EN_LEV0_C 1 INTX_EN_LEV0_B 0 INTX_EN_LEV0_A [15:12] Reserved 11 INTX_EN_LEV1_L 10 INTX_EN_LEV1_K 9 INTX_EN_LEV1_J 8 INTX_EN_LEV1_I 7 INTX_EN_LEV1_H 6 INTX_EN_LEV1_G 5 INTX_EN_LEV1_F 4 INTX_EN_LEV1_E 3 INTX_EN_LEV1_D 2 INTX_EN_LEV1_C Description INT_DATA_D interrupt enable. Write a 1 to this bit to enable drive of INT_DATA_D status on Interrupt Y. INT_DATA_C interrupt enable. Write a 1 to this bit to enable drive of INT_DATA_C status on Interrupt Y. INT_DATA_B interrupt enable. Write a 1 to this bit to enable drive of INT_DATA_B status on Interrupt Y. INT_DATA_A interrupt enable. Write a 1 to this bit to enable drive of INT_DATA_A status on Interrupt Y. Reserved. INT_LEV0_L interrupt enable. Write a 1 to this bit to enable drive of INT_LEV0_L status on Interrupt X. INT_LEV0_K interrupt enable. Write a 1 to this bit to enable drive of INT_LEV0_K status on Interrupt X. INT_LEV0_J interrupt enable. Write a 1 to this bit to enable drive of INT_LEV0_J status on Interrupt X. INT_LEV0_I interrupt enable. Write a 1 to this bit to enable drive of INT_LEV0_I status on Interrupt X. INT_LEV0_H interrupt enable. Write a 1 to this bit to enable drive of INT_LEV0_H status on Interrupt X. INT_LEV0_G interrupt enable. Write a 1 to this bit to enable drive of INT_LEV0_G status on Interrupt X. INT_LEV0_F interrupt enable. Write a 1 to this bit to enable drive of INT_LEV0_F status on Interrupt X. INT_LEV0_E interrupt enable. Write a 1 to this bit to enable drive of INT_LEV0_E status on Interrupt X. INT_LEV0_D interrupt enable. Write a 1 to this bit to enable drive of INT_LEV0_D status on Interrupt X. INT_LEV0_C interrupt enable. Write a 1 to this bit to enable drive of INT_LEV0_C status on Interrupt X. INT_LEV0_B interrupt enable. Write a 1 to this bit to enable drive of INT_LEV0_B status on Interrupt X. INT_LEV0_A interrupt enable. Write a 1 to this bit to enable drive of INT_LEV0_A status on Interrupt X. Reserved. INT_LEV1_L interrupt enable. Write a 1 to this bit to enable drive of INT_LEV1_L status on Interrupt X. INT_LEV1_K interrupt enable. Write a 1 to this bit to enable drive of INT_LEV1_K status on Interrupt X. INT_LEV1_J interrupt enable. Write a 1 to this bit to enable drive of INT_LEV1_J status on Interrupt X. INT_LEV1_I interrupt enable. Write a 1 to this bit to enable drive of INT_LEV1_I status on Interrupt X. INT_LEV1_H interrupt enable. Write a 1 to this bit to enable drive of INT_LEV1_H status on Interrupt X. INT_LEV1_G interrupt enable. Write a 1 to this bit to enable drive of INT_LEV1_G status on Interrupt X. INT_LEV1_F interrupt enable. Write a 1 to this bit to enable drive of INT_LEV1_F status on Interrupt X. INT_LEV1_E interrupt enable. Write a 1 to this bit to enable drive of INT_LEV1_E status on Interrupt X. INT_LEV1_D interrupt enable. Write a 1 to this bit to enable drive of INT_LEV1_D status on Interrupt X. INT_LEV1_C interrupt enable. Write a 1 to this bit to enable drive of INT_LEV1_C status on Interrupt X. Rev. 0 | Page 78 of 101 Reset Access1 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet Addr Name 0x0018 INT_ENABLE_XT1 0x0019 INT_ENABLE_XT2 ADPD4100/ADPD4101 Bits 1 Bit Name INTX_EN_LEV1_B 0 INTX_EN_LEV1_A [15:12] Reserved 11 INTX_EN_TCLN1_L 10 INTX_EN_TCLN1_K 9 INTX_EN_TCLN1_J 8 INTX_EN_TCLN1_I 7 INTX_EN_TCLN1_H 6 INTX_EN_TCLN1_G 5 INTX_EN_TCLN1_F 4 INTX_EN_TCLN1_E 3 INTX_EN_TCLN1_D 2 INTX_EN_TCLN1_C 1 INTX_EN_TCLN1_B 0 INTX_EN_TCLN1_A [15:12] Reserved 11 INTX_EN_TCLN2_L 10 INTX_EN_TCLN2_K 9 INTX_EN_TCLN2_J 8 INTX_EN_TCLN2_I 7 INTX_EN_TCLN2_H 6 INTX_EN_TCLN2_G 5 INTX_EN_TCLN2_F 4 INTX_EN_TCLN2_E 3 INTX_EN_TCLN2_D 2 INTX_EN_TCLN2_C 1 INTX_EN_TCLN2_B 0 INTX_EN_TCLN2_A Description INT_LEV1_B interrupt enable. Write a 1 to this bit to enable drive of INT_LEV1_B status on Interrupt X. INT_LEV1_A interrupt enable. Write a 1 to this bit to enable drive of INT_LEV1_A status on Interrupt X. Reserved. INT_TCLN1_L interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN1_L status on Interrupt X. INT_TCLN1_K interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN1_K status on Interrupt X. INT_TCLN1_J interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN1_J status on Interrupt X. INT_TCLN1_I interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN1_I status on Interrupt X. INT_TCLN1_H interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN1_H status on Interrupt X. INT_TCLN1_G interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN1_G status on Interrupt X. INT_TCLN1_F interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN1_F status on Interrupt X. INT_TCLN1_E interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN1_E status on Interrupt X. INT_TCLN1_D interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN1_D status on Interrupt X. INT_TCLN1_C interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN1_C status on Interrupt X. INT_TCLN1_B interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN1_B status on Interrupt X. INT_TCLN1_A interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN1_A status on Interrupt X. Reserved. INT_TCLN2_L interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN2_L status on Interrupt X. INT_TCLN2_K interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN2_K status on Interrupt X. INT_TCLN2_J interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN2_J status on Interrupt X. INT_TCLN2_I interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN2_I status on Interrupt X. INT_TCLN2_H interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN2_H status on Interrupt X. INT_TCLN2_G interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN2_G status on Interrupt X. INT_TCLN2_F interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN2_F status on Interrupt X. INT_TCLN2_E interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN2_E status on Interrupt X. INT_TCLN2_D interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN2_D status on Interrupt X. INT_TCLN2_C interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN2_C status on Interrupt X. INT_TCLN2_B interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN2_B status on Interrupt X. INT_TCLN2_A interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN2_A status on Interrupt X. Rev. 0 | Page 79 of 101 Reset Access1 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W ADPD4100/ADPD4101 Addr Name 0x001A INT_ENABLE_YL0 0x001B INT_ENABLE_YL1 Data Sheet Bits Bit Name [15:12] Reserved 11 INTY_EN_LEV0_L 10 INTY_EN_LEV0_K 9 INTY_EN_LEV0_J 8 INTY_EN_LEV0_I 7 INTY_EN_LEV0_H 6 INTY_EN_LEV0_G 5 INTY_EN_LEV0_F 4 INTY_EN_LEV0_E 3 INTY_EN_LEV0_D 2 INTY_EN_LEV0_C 1 INTY_EN_LEV0_B 0 INTY_EN_LEV0_A [15:12] Reserved 11 INTY_EN_LEV1_L 10 INTY_EN_LEV1_K 9 INTY_EN_LEV1_J 8 INTY_EN_LEV1_I 7 INTY_EN_LEV1_H 6 INTY_EN_LEV1_G 5 INTY_EN_LEV1_F 4 INTY_EN_LEV1_E 3 INTY_EN_LEV1_D 2 INTY_EN_LEV1_C 1 INTY_EN_LEV1_B 0 INTY_EN_LEV1_A Description Reserved. INT_LEV0_L interrupt enable. Write a 1 to this bit to enable drive of INT_LEV0_L status on Interrupt Y. INT_LEV0_K interrupt enable. Write a 1 to this bit to enable drive of INT_LEV0_K status on Interrupt Y. INT_LEV0_J interrupt enable. Write a 1 to this bit to enable drive of INT_LEV0_J status on Interrupt Y. INT_LEV0_I interrupt enable. Write a 1 to this bit to enable drive of INT_LEV0_I status on Interrupt Y. INT_LEV0_H interrupt enable. Write a 1 to this bit to enable drive of INT_LEV0_H status on Interrupt Y. INT_LEV0_G interrupt enable. Write a 1 to this bit to enable drive of INT_LEV0_G status on Interrupt Y. INT_LEV0_F interrupt enable. Write a 1 to this bit to enable drive of INT_LEV0_F status on Interrupt Y. INT_LEV0_E interrupt enable. Write a 1 to this bit to enable drive of INT_LEV0_E status on Interrupt Y. INT_LEV0_D interrupt enable. Write a 1 to this bit to enable drive of INT_LEV0_D status on Interrupt Y. INT_LEV0_C interrupt enable. Write a 1 to this bit to enable drive of INT_LEV0_C status on Interrupt Y. INT_LEV0_B interrupt enable. Write a 1 to this bit to enable drive of INT_LEV0_B status on Interrupt Y. INT_LEV0_A interrupt enable. Write a 1 to this bit to enable drive of INT_LEV0_A status on Interrupt Y. Reserved. INT_LEV1_L interrupt enable. Write a 1 to this bit to enable drive of INT_LEV1_L status on Interrupt Y. INT_LEV1_K interrupt enable. Write a 1 to this bit to enable drive of INT_LEV1_K status on Interrupt Y. INT_LEV1_J interrupt enable. Write a 1 to this bit to enable drive of INT_LEV1_J status on Interrupt Y. INT_LEV1_I interrupt enable. Write a 1 to this bit to enable drive of INT_LEV1_I status on Interrupt Y. INT_LEV1_H interrupt enable. Write a 1 to this bit to enable drive of INT_LEV1_H status on Interrupt Y. INT_LEV1_G interrupt enable. Write a 1 to this bit to enable drive of INT_LEV1_G status on Interrupt Y. INT_LEV1_F interrupt enable. Write a 1 to this bit to enable drive of INT_LEV1_F status on Interrupt Y. INT_LEV1_E interrupt enable. Write a 1 to this bit to enable drive of INT_LEV1_E status on Interrupt Y. INT_LEV1_D interrupt enable. Write a 1 to this bit to enable drive of INT_LEV1_D status on Interrupt Y. INT_LEV1_C interrupt enable. Write a 1 to this bit to enable drive of INT_LEV1_C status on Interrupt Y. INT_LEV1_B interrupt enable. Write a 1 to this bit to enable drive of INT_LEV1_B status on Interrupt Y. INT_LEV1_A interrupt enable. Write a 1 to this bit to enable drive of INT_LEV1_A status on Interrupt Y. Rev. 0 | Page 80 of 101 Reset Access1 0x0 R 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet Addr Name 0x001C INT_ENABLE_YT1 0x001D INT_ENABLE_YT2 ADPD4100/ADPD4101 Bits Bit Name [15:12] Reserved 11 INTY_EN_TCLN1_L 10 INTY_EN_TCLN1_K 9 INTY_EN_TCLN1_J 8 INTY_EN_TCLN1_I 7 INTY_EN_TCLN1_H 6 INTY_EN_TCLN1_G 5 INTY_EN_TCLN1_F 4 INTY_EN_TCLN1_E 3 INTY_EN_TCLN1_D 2 INTY_EN_TCLN1_C 1 INTY_EN_TCLN1_B 0 INTY_EN_TCLN1_A [15:12] Reserved 11 INTY_EN_TCLN2_L 10 INTY_EN_TCLN2_K 9 INTY_EN_TCLN2_J 8 INTY_EN_TCLN2_I 7 INTY_EN_TCLN2_H 6 INTY_EN_TCLN2_G 5 INTY_EN_TCLN2_F 4 INTY_EN_TCLN2_E 3 INTY_EN_TCLN2_D 2 INTY_EN_TCLN2_C 1 INTY_EN_TCLN2_B 0 INTY_EN_TCLN2_A Description Reserved. INT_TCLN1_L interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN1_L status on Interrupt Y. INT_TCLN1_K interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN1_K status on Interrupt Y. INT_TCLN1_J interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN1_J status on Interrupt Y. INT_TCLN1_I interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN1_I status on Interrupt Y. INT_TCLN1_H interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN1_H status on Interrupt Y. INT_TCLN1_G interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN1_G status on Interrupt Y. INT_TCLN1_F interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN1_F status on Interrupt Y. INT_TCLN1_E interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN1_E status on Interrupt Y. INT_TCLN1_D interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN1_D status on Interrupt Y. INT_TCLN1_C interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN1_C status on Interrupt Y. INT_TCLN1_B interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN1_B status on Interrupt Y. INT_TCLN1_A interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN1_A status on Interrupt Y. Reserved. INT_TCLN2_L interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN2_L status on Interrupt Y. INT_TCLN2_K interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN2_K status on Interrupt Y. INT_TCLN2_J interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN2_J status on Interrupt Y. INT_TCLN2_I interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN2_I status on Interrupt Y. INT_TCLN2_H interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN2_H status on Interrupt Y. INT_TCLN2_G interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN2_G status on Interrupt Y. INT_TCLN2_F interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN2_F status on Interrupt Y. INT_TCLN2_E interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN2_E status on Interrupt Y. INT_TCLN2_D interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN2_D status on Interrupt Y. INT_TCLN2_C interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN2_C status on Interrupt Y. INT_TCLN2_B interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN2_B status on Interrupt Y. INT_TCLN2_A interrupt enable. Write a 1 to this bit to enable drive of INT_TCLN2_A status on Interrupt . Rev. 0 | Page 81 of 101 Reset Access1 0x0 R 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W ADPD4100/ADPD4101 Data Sheet Addr Name Bits 0x001E FIFO_STATUS_BYTES [15:9] 8 1 Bit Name Reserved ENA_STAT_TCX 7 ENA_STAT_TC2 6 ENA_STAT_TC1 5 ENA_STAT_LX 4 ENA_STAT_L1 3 ENA_STAT_L0 2 ENA_STAT_D2 1 ENA_STAT_D1 0 ENA_STAT_SUM Description Reserved. Enable Channel 1 and Channel 2 TIA ceiling detection interrupt status byte for Time Slot I through Time Slot L. This byte contains the interrupt status for the Channel 1 and Channel 2 interrupts for Time Slot I through Time Slot L. Enable Channel 2 TIA ceiling detection interrupt status byte for Time Slot A through Time Slot H. This byte contains the interrupt status for the Channel 2 and Channel 2 interrupts for Time Slot A through Time Slot H. Enable Channel 1 TIA ceiling detection interrupt status byte for Time Slot A through Time Slot H. This byte contains the interrupt status for the Channel 1 and Channel 2 interrupts for Time Slot A through Time Slot H. Enable Level 0 and Level 1 interrupt status byte for Time Slot I through Time Slot L. This byte contains the interrupt status for the Level 0 and Level 1 interrupts for Time Slot I through Time Slot L. Enable Level 1 interrupt status byte for Time Slot A through Time Slot H. This byte contains the interrupt status for the Level 1 interrupts for Time Slot A through Time Slot H. Enable Level 0 interrupt status byte for Time Slot A through Time Slot H. This byte contains the interrupt status for Level Interrupt 0 for Time Slot A through Time Slot H. Enable data interrupt status byte for Time Slot I through Time Slot L. This byte contains the data interrupt status for Time Slot I through Time Slot L. Enable data interrupt status byte for Time Slot A through Time Slot H. This byte is the data interrupt status for Time Slot A through Time Slot H. Enable status summary byte. When enabled, write a status byte containing the summary pattern to the FIFO following the last enabled time slot data. Reset Access1 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W R/W1C means write 1 to clear. THRESHOLD SETUP AND CONTROL REGISTERS Table 32. Threshold Setup and Control Register Details Addr Name 0x0006 FIFO_TH Bits Bit Name [15:10] Reserved [9:0] FIFO_TH Reset Access 0x00 R 0x000 R/W 0x0115 0x0135 0x0155 0x0175 0x0195 0x01B5 0x01D5 0x01F5 0x0215 0x0235 0x0255 0x0275 [15:8] 7 0x0 0x0 R R/W 0x0 R/W 0x0 R/W THRESH_CFG_A THRESH_CFG_B THRESH_CFG_C THRESH_CFG_D THRESH_CFG_E THRESH_CFG_F THRESH_CFG_G THRESH_CFG_H THRESH_CFG_I THRESH_CFG_J THRESH_CFG_K THRESH_CFG_L 6 [5:4] Description Reserved. FIFO interrupt generation threshold. Generate FIFO interrupt during a FIFO write when the number of bytes in the FIFO exceeds this value. The FIFO is 512 bytes. Therefore, the maximum value for FIFO_TH is 0x1FF. Reserved Reserved. THRESH1_CHAN_x Select channel for Level 1 interrupt. 0: use Channel 1. 1: use Channel 2. THRESH1_DIR_x Direction of comparison for Level 1 interrupt. 0: set when below Level 1 interrupt threshold. 1: set when above Level 1 interrupt threshold. THRESH1_TYPE_x Type of comparison for Level 1 interrupt. 0: off (no comparison). 1: compare to signal. 10: compare to dark. 11: reserved. Rev. 0 | Page 82 of 101 Data Sheet Addr 0x0116 0x0136 0x0156 0x0176 0x0196 0x01B6 0x01D6 0x01F6 0x0216 0x0236 0x0256 0x0276 0x0117 0x0137 0x0157 0x0177 0x0197 0x01B7 0x01D7 0x01F7 0x0217 0x0237 0x0257 0x0277 Name THRESH0_A THRESH0_B THRESH0_C THRESH0_D THRESH0_E THRESH0_F THRESH0_G THRESH0_H THRESH0_I THRESH0_J THRESH0_K THRESH0_L THRESH1_A THRESH1_B THRESH1_C THRESH1_D THRESH1_E THRESH1_F THRESH1_G THRESH1_H THRESH1_I THRESH1_J THRESH1_K THRESH1_L ADPD4100/ADPD4101 Bits 3 Bit Name Description THRESH0_CHAN_x Select channel for Level 0 interrupt. 0: use Channel 1. 1: use Channel 2. 2 THRESH0_DIR_x Direction of comparison for Level 0 interrupt. 0: set when below Level 0 interrupt threshold. 1: set when above Level 0 interrupt threshold. [1:0] THRESH0_TYPE_x Type of comparison for Level 0 interrupt. 0: off (no comparison). 1: compare to signal. 10: compare to dark. 11: reserved. [15:13] Reserved Reserved. [12:8] THRESH0_SHIFT_x Shift for Level 0 interrupt comparison threshold. Shift THRESH0_VALUE_x by this amount before comparing. [7:0] THRESH0_VALUE_x Value for Level 0 interrupt comparison threshold. [15:13] Reserved [12:8] THRESH1_SHIFT_x [7:0] Reserved. Shift for Level 1 interrupt comparison threshold. Shift THRESH1_VALUE_x by this amount before comparing. THRESH1_VALUE_x Value for Level 1 interrupt comparison threshold. Rev. 0 | Page 83 of 101 Reset Access 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W ADPD4100/ADPD4101 Data Sheet CLOCK AND TIMESTAMP SETUP AND CONTROL REGISTERS Table 33. Clock and Timestamp Setup and Control Register Details Addr Name 0x0009 OSC32M Bits [15:8] [7:0] Bit Name Reserved OSC_32M_FREQ_ADJ Description Reserved. High frequency oscillator frequency control. 0x00 is the lowest frequency, and 0xFF is maximum frequency. Start high frequency oscillator calibration cycle. Writing a 1 to 0x000A OSC32M_CAL 15 OSC_32M_CAL_START this bit causes the high frequency oscillator calibration cycle to occur. 32 MHz oscillator cycles are counted during 128 low frequency oscillator cycles if using the 1 MHz low frequency oscillator, or 32 low frequency oscillator cycles if using the 32 kHz low frequency oscillator. The OSC_32M_CAL_COUNT bits are updated with the count. The calibration circuit clears the OSC_32M_CAL_START bit when the calibration cycle is completed. [14:0] OSC_32M_CAL_COUNT High frequency oscillator calibration count. These bits contain the total number of 32 MHz cycles that occurred during the last high frequency oscillator calibration cycle. 0x000B OSC1M [15:11] Reserved Reserved. Enables clock for oscillator calibration. When set to 0 (default), 10 CLK_CAL_ENA the oscillator calibration circuitry is disabled. Set this bit to 1 to turn on the oscillator calibration circuitry. Low frequency oscillator frequency control. 0x000 is the lowest [9:0] OSC_1M_FREQ_ADJ frequency, and 0x3FF is maximum frequency. Enable time stamp capture. This bit is used to activate the time 0x000C OSC32K 15 CAPTURE_TIMESTAMP stamp capture function. When set, the next rising edge on the time stamp input (defaults to GPIO0) causes a time stamp capture. This bit is cleared when the time stamp occurs. [14:6] Reserved Reserved. [5:0] OSC_32K_ADJUST 32 kHz oscillator trim. 00 0000: maximum frequency. 01 0010: default frequency. 11 1111: minimum frequency. 0x0011 STAMP_L [15:0] TIMESTAMP_COUNT_L Count at last time stamp. Lower 16 bits. 0x0012 STAMP_H [15:0] TIMESTAMP_COUNT_H Count at last time stamp. Upper 16 bits. 0x0013 STAMPDELTA [15:0] TIMESTAMP_SLOT_DELTA Count remaining until next time slot start. Reset Access 0x0 R 0x80 R/W 0x0 R/W 0x0 R 0x0 0x0 R R/W 0x2B2 R/W 0x0 R/W 0x0 0x12 R R/W 0x0 0x0 0x0 R R R Reset 0x2 0xC2 0x0 0x0 Access R R R R/W 0x0 R/W 0x0 R/W 0x0 R/W SYSTEM REGISTERS Table 34. System Register Details Addr Name 0x0008 CHIP_ID Bits [15:8] [7:0] 0x002E DATA_HOLD_FLAG [15:12] 11 Bit Name Version CHIP_ID Reserved HOLD_REGS_L 10 HOLD_REGS_K 9 HOLD_REGS_J 8 HOLD_REGS_I Description Mask version. Chip ID. Reserved. Prevent update of Time Slot L data registers. 0: allow data register update. 1: hold current contents of data register. Prevent update of time Slot K data registers. 0: allow data register update. 1: hold current contents of data register. Prevent update of Time Slot J data registers. 0: allow data register update. 1: hold current contents of data register. Prevent update of Time Slot I data registers. 0: allow data register update. 1: hold current contents of data register. Rev. 0 | Page 84 of 101 Data Sheet Addr Name 0x00B6 I2C_KEY 0x00B7 I2C_ADDR ADPD4100/ADPD4101 Bits 7 Bit Name HOLD_REGS_H Description Prevent Update of Time Slot H data registers. 0: allow data register update. 1: hold current contents of data register. 6 HOLD_REGS_G Prevent update of Time Slot G data registers. 0: allow data register update. 1: hold current contents of data register. 5 HOLD_REGS_F Prevent update of Time Slot F data registers. 0: allow data register update. 1: hold current contents of data register. 4 HOLD_REGS_E Prevent update of Time Slot E data registers. 0: allow data register update. 1: hold current contents of data register. 3 HOLD_REGS_D Prevent update of Time Slot D data registers. 0: allow data register update. 1: hold current contents of data register. 2 HOLD_REGS_C Prevent update of Time Slot C data registers. 0: allow data register update. 1: hold current contents of data register. 1 HOLD_REGS_B Prevent update of Time Slot B data registers. 0: allow data register update. 1: hold current contents of data register. 0 HOLD_REGS_A Prevent update of Time Slot A data registers. 0: allow data register update. 1: hold current contents of data register. [15:12] I2C_KEY_MATCH Write the I2C_KEY_MATCH bits to specify which GPIOx pins must be high to change the slave address. A 0 ignores that specific GPIO input. A 1 selects which GPIOx must be high to change the address. Any combination is allowed. Use Bit 12 for GPIO0, Bit 13 for GPIO1, Bit 14 for GPIO2, and Bit 15 for GPIO3. I2C address change key. Must write these bits to 0x4AD to change [11:0] I2C_KEY address. Write these bits at the same time that the I2C_KEY_MATCH bits are written. [15:8] I2C_SLAVE_KEY2 I2C key, Part 2. Must be written to 0xAD immediately following the write of the I2C_KEY bits. The GPIOx pins as selected in the I2C_KEY_MATCH bits must also be set high at this time. [7:1] I2C_SLAVE_ADDR I2C slave address update field. Write the desired 7-bit slave address along with proper keys to change the I2C slave address. 0 Reserved Reserved. Rev. 0 | Page 85 of 101 Reset Access 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R0/W 0x0 R/W 0x24 R/W 0x0 R ADPD4100/ADPD4101 Data Sheet I/O SETUP AND CONTROL REGISTERS Table 35. I/O Setup and Control Register Details Addr Name 0x0022 GPIO_CFG Bits Bit Name [15:14] GPIO_SLEW [13:12] GPIO_DRV [11:9] GPIO_PIN_CFG3 [8:6] GPIO_PIN_CFG2 [5:3] GPIO_PIN_CFG1 [2:0] GPIO_PIN_CFG0 Description Slew control for GPIOx pins. 0: slowest. 1: slow. 10: fastest. 11: fast. Drive control for GPIOx pins. 0: medium. 1: weak. 10: strong. 11: strong. GPIO3 pin configuration. 000: disabled (tristate, input buffer off ). 001: enabled input. 010: output—normal. 011: output—inverted. 100: pull-down only—normal. 101: pull-down only—inverted. 110: pull-up only—normal. 111: pull-up only—inverted. GPIO2 pin configuration. 000: disabled (tristate, input buffer off ). 001: enabled input. 010: output—normal. 011: output—inverted. 100: pulldown only—normal. 101: pull-down only—inverted. 110: pull-up only—normal. 111: pull-up only—inverted. GPIO1 pin configuration. 000: disabled (tristate, input buffer off ). 001: enabled input. 010: output—normal. 011: output—inverted. 100: pull-down only—normal. 101: pull-down only—inverted. 110: pull-up only—normal. 111: pull-up only—inverted. GPIO0 pin configuration. 000: disabled (tristate, input buffer off ). 001: enabled input. 010: output—normal. 011: output—inverted. 100: pull-down only—normal. 101: pull-down only—inverted. 110: pull-up only—normal. 111: pull-up only—inverted. Rev. 0 | Page 86 of 101 Reset Access 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet Addr Name 0x0023 GPIO01 ADPD4100/ADPD4101 Bits 15 [14:8] Bit Name Reserved GPIOOUT1 Description Reset Access Reserved. 0x0 R GPIO1 output signal select. 0x0 R/W 0x00: Output Logic 0. 0x01: Output Logic 1. 0x02: Interrupt X. 0x03: Interrupt Y. 0x08: LED1x amplifier enable 0x09: LED2x amplifier enable 0x0A: LED3x amplifier enable 0x0B: LED4x amplifier enable 0x0C: Any LED amplifier enable 0x0F: 32 MHz oscillator output divided by 64 (500 kHz). 0x10: time slot specific output pattern defined by TS_GPIO_x and TS_GPIO_SLEEP bits. 0x11: in sleep state. 0x16: low frequency oscillator output. 0x17: 32 MHz oscillator output. 0x18: 32 MHz oscillator output divided by 32 (1 MHz). 0x20: Time Slot A active. 0x21: Time Slot B active. 0x22: Time Slot C active. 0x23: Time Slot D active. 0x24: Time Slot E active. 0x25: Time Slot F active. 0x26: Time Slot G active. 0x27: Time Slot H active. 0x28: Time Slot I active. 0x29: Time Slot J active. 0x2A: Time Slot K active. 0x2B: Time Slot L active. 0x30: Time Slot A LED pulse. 0x31: Time Slot B LED pulse. 0x32: Time Slot C LED pulse. 0x33: Time Slot D LED pulse. 0x34: Time Slot E LED pulse. 0x35: Time Slot F LED pulse. 0x36: Time Slot G LED pulse. 0x37: Time Slot H LED pulse. 0x38: Time Slot I LED pulse. 0x39: Time Slot J LED pulse. 0x3A: Time Slot K LED pulse. 0x3B: Time Slot L LED pulse. 0x3F: any time slot LED pulse. 0x40: Time Slot A modulation pulse. 0x41: Time Slot B modulation pulse. 0x42: Time Slot C modulation pulse. 0x43: Time Slot D modulation pulse. 0x44: Time Slot E modulation pulse. 0x45: Time Slot F modulation pulse. 0x46: Time Slot G modulation pulse. 0x47: Time Slot H modulation pulse. 0x48: Time Slot I modulation pulse. 0x49: Time Slot J modulation pulse. Rev. 0 | Page 87 of 101 ADPD4100/ADPD4101 Addr Name Bits 7 [6:0] 0x0024 GPIO23 15 [14:8] 7 [6:0] 0x0025 GPIO_IN [15:4] [3:0] 0x0026 GPIO_EXT [15:9] 8 7 6 [5:4] 3 2 [1:0] Data Sheet Bit Name Description 0x4A: Time Slot K modulation pulse. 0x4B: Time Slot L modulation pulse. 0x4F: any time slot modulation pulse. 0x50: output data cycle occurred in Time Slot A, which is useful when synchronizing an external device to a decimated data rate from the ADPD4100/ADPD4101. 0x51: output data cycle occurred in Time Slot B. 0x52: output data cycle occurred in Time Slot C. 0x53: output data cycle occurred in Time Slot D. 0x54: output data cycle occurred in Time Slot E. 0x55: output data cycle occurred in Time Slot F. 0x56: output data cycle occurred in Time Slot G. 0x57: output data cycle occurred in Time Slot H. 0x58: output data cycle occurred in Time Slot I. 0x59: output data cycle occurred in Time Slot J. 0x5A: output data cycle occurred in Time Slot K. 0x5B: output data cycle occurred in Time Slot L. 0x5F: output data cycle occurred in any time slot. Reserved Reserved. GPIO0 output signal select. Options are identical to those GPIOOUT0 described in GPIOOUT1. Reserved Reserved. GPIO3 output signal select. Options are identical to those GPIOOUT3 described in GPIOOUT1. Reserved Reserved. GPIO2 output signal select. Options are identical to those GPIOOUT2 described in GPIOOUT1. Reserved Reserved. GPIO input value (if enabled). Read back the value present on any GPIO_INPUT GPIO enabled as an input. Bit 0 is GPIO1, Bit 1 is GPIO1, Bit 2 is GPIO2, and Bit 3 is GPIO3. Reserved Reserved. When GPIOOUTx is set to 0x10, the GPIO returns to the TS_GPIO_SLEEP TS_GPIO_SLEEP value at the end of the time slot and during sleep. TIMESTAMP_INV Time stamp trigger invert. 0: time stamp trigger is rising edge. 1: time stamp trigger is falling edge. TIMESTAMP_ALWAYS_EN Enable time stamp always on. When set, do not automatically clear CAPTURE_TIMESTAMP. This bit provides an always activated time stamp. TIMESTAMP_GPIO Time stamp GPIO select. 0x0: use GPIO0 for time stamp (default). 0x1: use GPIO1 for time stamp. 0x2: use GPIO2 for time stamp. 0x3: use GPIO3 for time stamp Reserved Reserved. External sync enable. When enabled, use the GPIO selected by EXT_SYNC_EN EXT_SYNC_GPIO to trigger samples rather than the period counter. EXT_SYNC_GPIO External synchronization GPIO select. 00: use GPIO0 for external synchronization 01: use GPIO1 for external synchronization. 10: use GPIO2 for external synchronization. 11: use GPIO3 for external synchronization. Rev. 0 | Page 88 of 101 Reset Access 0x0 0x0 R R/W 0x0 0x0 R R/W 0x0 0x0 R R/W 0x0 0x0 R R 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R/W R/W 0x0 R/W Data Sheet ADPD4100/ADPD4101 Addr Name Bits 0x00B4 IO_ADJUST [15:7] 6 Bit Name Reserved LOW_IOVDD_EN [5:4] [3:2] Reserved SPI_SLEW [1:0] SPI_DRV Description Reserved. Set to 0x0 if IOVDD of 3 V or higher is used. Default value of 0x1 used for IOVDD is lower than 3 V, because the typical value of IOVDD is 1.8 V. Set to 0x01. Slew control for SPI pins. 0: slowest. 1: slow. 10: fastest. 11: fast. Drive control for SPI pins. 0: medium. 1: weak. 10: strong. 11: strong. Reset Access 0x000 R 0x1 R/W Description Subsample using DECIMATE_FACTOR_x. When this bit is set, operate the selected time slot only once per (DECIMATE_FACTOR_x + 1) time slot sequences. Reset Access 0x0 R/W 0x01 0x0 R/W R/W 0x0 R/W TIME SLOT CONFIGURATION REGISTERS Table 36. Time Slot Configuration Register Details Addr 0x0100 0x0120 0x0140 0x0160 0x0180 0x01A0 0x01C0 0x01E0 0x0200 0x0220 0x0240 0x0260 0x0101 0x0121 0x0141 0x0161 0x0181 0x01A1 0x01C1 0x01E1 0x0201 Name TS_CTRL_A TS_CTRL_B TS_CTRL_C TS_CTRL_D TS_CTRL_E TS_CTRL_F TS_CTRL_G TS_CTRL_H TS_CTRL_I TS_CTRL_J TS_CTRL_K TS_CTRL_L TS_PATH_A TS_PATH_B TS_PATH_C TS_PATH_D TS_PATH_E TS_PATH_F TS_PATH_G TS_PATH_H TS_PATH_I Bits 15 Bit Name SUBSAMPLE_x 14 CH2_EN_x Channel 2 enable. 0: Channel 2 disabled. 1: Channel 2 enabled. [13:12] SAMPLE_TYPE_x Time Slot x sampling type. 00: standard sampling modes. 01: one-region digital integration mode. 10: two-region digital integration mode. 11: impulse response mode. [11:10] INPUT_R_SELECT_x Input resistor (RIN) select. 00: 500 Ω. 01: 6.5 kΩ. 10: reserved. 11: reserved. [9:0] TIMESLOT_OFFSET_x Time Slot x offset in 64 × the number of 1 MHz low frequency oscillator cycles or 2 × the number of 32 kHz low frequency oscillator cycles. Preconditioning duration for Time Slot x. This value is in [15:12] PRE_WIDTH_x 2 μs increments. A value of 0 skips the preconditioning state. Default is 8 μs. [11:10] Reserved 9 TS_GPIO_x 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x4 R/W Write 0x0. 0x0 Time slot specific value for Time Slot x. When GPIOOUTx is 0x0 set to 0x10 and TS_GPIO_x is set to 1, the GPIO selected by GPIOOUTx outputs a 1 while the time slot selected by TS_GPIO_x is active. The GPIO returns to the TS_GPIO_SLEEP value at the end of the time slot. R R/W Rev. 0 | Page 89 of 101 ADPD4100/ADPD4101 Data Sheet Addr 0x0221 0x0241 0x0261 Name TS_PATH_J TS_PATH_K TS_PATH_L Bits [8:0] Bit Name AFE_PATH_CFG_x 0x0102 0x0122 0x0142 0x0162 0x0182 0x01A2 0x01C2 0x01E2 0x0202 0x0222 0x0242 0x0262 INPUTS_A INPUTS_B INPUTS_C INPUTS_D INPUTS_E INPUTS_F INPUTS_G INPUTS_H INPUTS_I INPUTS_J INPUTS_K INPUTS_L [15:12] INP78_x [11:8] INP56_x [7:4] INP34_x Description Signal path selection. 0x0DA: TIA, BPF, integrator, and ADC. 0x0E6: TIA, integrator, and ADC. 0x106: TIA and ADC. 0x101: ADC. 0x0E1: buffer and ADC. 0x0E6: TIA, integrator, and ADC. IN7 and IN8 input pair enable. 0000: input pair disabled. IN7 and IN8 disconnected. 0001: IN7 connected to Channel 1. IN8 disconnected. 0010: IN7 connected to Channel 2. IN8 disconnected. 0011: IN7 disconnected. IN8 connected to Channel 1. 0100: IN7 disconnected. IN8 connected to Channel 2. 0101: IN7 connected to Channel 1. IN8 connected to Channel 2. 0110: IN7 connected to Channel 2. IN8 connected to Channel 1. 0111: IN7 and IN8 connected to Channel 1. Singleended or differential, based on PAIR78. 1000: IN7 and IN8 connected to Channel 2. Single-ended or differential, based on PAIR78. IN5 and IN6 input pair enable. 0000: input pair disabled. IN5 and IN6 disconnected. 0001: IN5 connected to Channel 1. IN6 disconnected. 0010: IN5 connected to Channel 2. IN6 disconnected. 0011: IN5 disconnected. IN6 connected to Channel 1. 0100: IN5 disconnected. IN6 connected to Channel 2. 0101: IN5 connected to Channel 1. IN6 connected to Channel 2. 0110: IN5 connected to Channel 2. IN6 connected to Channel 1. 0111: IN5 and IN6 connected to Channel 1. Single-ended or differential, based on PAIR56. 1000: IN5 and IN6 connected to Channel 2. Single-ended or differential, based on PAIR56. IN3 and IN4 input pair enable. 0000: input pair disabled. IN3 and IN4 disconnected. 0001: IN3 connected to Channel 1. IN4 disconnected. 0010: IN3 connected to Channel 2. IN4 disconnected. 0011: IN3 disconnected. IN4 connected to Channel 1. 0100: IN3 disconnected. IN4 connected to Channel 2. 0101: IN3 connected to Channel 1. IN4 connected to Channel 2. 0110: IN3 connected to Channel 2. IN4 connected to Channel 1. 0111: IN3 and IN4 connected to Channel 1. Single-ended or differential, based on PAIR34. 1000: IN3 and IN4 connected to Channel. Single-ended or differential, based on PAIR34. Rev. 0 | Page 90 of 101 Reset Access 0x0DA R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet ADPD4100/ADPD4101 Addr Name Bits [3:0] Bit Name INP12_x 0x0103 0x0123 0x0143 0x0163 0x0183 0x01A3 0x01C3 0x01E3 0x0203 0x0223 0x0243 0x0263 CATHODE_A CATHODE_B CATHODE_C CATHODE_D CATHODE_E CATHODE_F CATHODE_G CATHODE_H CATHODE_I CATHODE_J CATHODE_K CATHODE_L 15 Reserved [14:12] PRECON_x [11:10] VC2_PULSE_x [9:8] VC2_ALT_x [7:6] VC2_SEL_x [5:4] VC1_PULSE_x [3:2] VC1_ALT_x [1:0] VC1_SEL_x Description IN1 and IN2 input pair enable. 0000: input pair disabled. IN1 and IN2 disconnected. 0001: IN1 connected to Channel 1. IN2 disconnected. 0010: IN1 connected to Channel 2. IN2 disconnected. 0011: IN1 disconnected. IN2 connected to Channel 1. 0100: IN1 disconnected. IN2 connected to Channel 2. 0101: IN1 connected to Channel 1. IN2 connected to Channel 2. 0110: IN1 connected to Channel 2. IN2 connected to Channel 1. 0111: IN1 and IN2 connected to Channel 1. Single-ended or differential, based on PAIR12. 1000: IN1 and IN2 connected to Channel 2. Single-ended or differential, based on PAIR12. Reserved. Precondition value for enabled inputs during Time Slot x. 000: float input(s). 001: precondition to VC1. 010: precondition to VC2. 011: precondition to VICM. Used when inputs are configured differentially. 100: precondition with TIA input. 101: precondition with TIA_VREF. 110: precondition by shorting differential pair. VC2 pulse control for Time Slot x. 00: no pulsing. 01: alternate VC2 on each subsequent Time Slot x. 10: pulse to alternate value specified in VC2_ALT_x using modulation pulse. VC2 alternate pulsed state for Time Slot x. 00: VDD. 01: TIA_VREF. 10: TIA_VREF + 215 mV. 11: GND. VC2 active state for Time Slot x. 00: VDD. 01: TIA_VREF. 10: TIA_VREF + 215 mV. 11: GND. VC1 pulse control for Time Slot x. 00: no pulsing. 01: alternate VC1 on each subsequent Time Slot x. 10: pulse to alternate value specified in VC1_ALT_x using modulation pulse. VC1 alternate pulsed state for Time Slot x. 00: VDD. 01: TIA_VREF. 10: TIA_VREF + 215 mV. 11: GND. VC1 active state for Time Slot x. 00: VDD. 01: TIA_VREF. 10: TIA_VREF + 215 mV. 11: GND. Rev. 0 | Page 91 of 101 Reset Access 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W ADPD4100/ADPD4101 Addr 0x0104 0x0124 0x0144 0x0164 0x0184 0x01A4 0x01C4 0x01E4 0x0204 0x0224 0x0244 0x0264 0x010D 0x012D 0x014D 0x016D 0x018D 0x01AD 0x01CD 0x01ED 0x020D Name AFE_TRIM_A AFE_TRIM_B AFE_TRIM_C AFE_TRIM_D AFE_TRIM_E AFE_TRIM_F AFE_TRIM_G AFE_TRIM_H AFE_TRIM_I AFE_TRIM_J AFE_TRIM_K AFE_TRIM_L PATTERN_A PATTERN_B PATTERN_C PATTERN_D PATTERN_E PATTERN_F PATTERN_G PATTERN_H PATTERN_I Bits 15 Data Sheet Bit Name TIA_CEIL_DETECT_ EN_x Description Reset Access Set to 1 to enable TIA ceiling detection circuitry. Enables 0x0 R/W Channel 1 TIA ceiling detection circuitry and Channel 2 TIA ceiling detection circuitry if Channel 2 is also enabled. [14:13] CH2_TRIM_INT_x [12:11] CH1_TRIM_INT_x 10 VREF_PULSE_x [9:8] AFE_TRIM_VREF_x [7:6] VREF_PULSE_VAL_x [5:3] TIA_GAIN_CH2_x [2:0] TIA_GAIN_CH1_x [15:12] LED_DISABLE_x Set the integrator input resistor when AFE_INT_C_BUF_x = 0. Set the buffer gain when AFE_INT_C_BUF_x = 1 AFE_INT_C_BUF_x = 0 AFE_INT_C_BUF_x = 1 00: 400 kΩ. 00: gain = 1. 01: 200 kΩ. 01: gain = 1. 10: 100 kΩ. 10: gain = 0.7. 11: 100 kΩ. 11: gain = 0.7. Set the integrator input resistor when AFE_INT_C_BUF_x = 0. Set the buffer gain when AFE_INT_C_BUF_x = 1 or in digital integration mode. AFE_INT_C_BUF_x = 0 AFE_INT_C_BUF_x = 1 00: 400 kΩ. 00: gain = 1. 01: 200 kΩ. 01: gain = 1. 10: 100 kΩ. 10: gain = 0.7. 11: 100 kΩ. 11: gain = 0.7. TIA_VREF pulse control. 0: no pulsing. 1: pulse TIA_VREF based on modulation pulse. Voltage select for TIA_VREF. 00: TIA_VREF = 1.1385 V. 01: TIA_VREF = 1.012 V. 10: TIA_VREF = 0.8855 V. 11: TIA_VREF = 1.265 V. TIA_VREF pulse alternate value. 00: modulate TIA_VREF = 1.1385 V. 01: modulate TIA_VREF = 1.012 V. 10: modulate TIA_VREF = 0.8855 V. 11: modulate TIA_VREF = 1.265 V. TIA resistor gain setting for Channel 2. 000: 200 kΩ. 001: 100 kΩ. 010: 50 kΩ. 011: 25 kΩ. 100: 12.5 kΩ. TIA resistor gain setting for Channel 1. 000: 200 kΩ. 001: 100 kΩ. 010: 50 kΩ. 011: 25 kΩ. 100: 12.5 kΩ. Four-pulse LED disable pattern. Set to 1 to disable the LED pulse in the matching position in a group of four pulses. The LSB maps to the first pulse. 0x0 R/W 0x0 R/W 0x0 R/W 0x3 R/W 0x3 R/W 0x0 R/W 0x0 R/W 0x0 R/W [11:8] MOD_DISABLE_x Four-pulse modulation disable pattern. Set to 1 to disable 0x0 the modulation pulse in the matching position in a group of four pulses. The LSB maps to the first pulse. R/W [7:4] SUBTRACT_x Four-pulse subtract pattern. Set to 1 to negate the math operation in the matching position in a group of four pulses. The LSB maps to the first pulse. R/W Rev. 0 | Page 92 of 101 0x0 Data Sheet ADPD4100/ADPD4101 Addr 0x022D 0x024D 0x026D Name PATTERN_J PATTERN_K PATTERN_L Bits [3:0] Bit Name REVERSE_INTEG_x 0x0110 0x0130 0x0150 0x0170 0x0190 0x01B0 0x01D0 0x01F0 0x0210 0x0230 0x0250 0x0270 0x0111 0x0131 0x0151 0x0171 0x0191 0x01B1 0x01D1 0x01F1 0x0211 0x0231 0x0251 0x0271 0x0112 0x0132 0x0152 0x0172 0x0192 0x01B2 0x01D2 0x01F2 0x0212 0x0232 0x0252 0x0272 DATA_FORMAT_A DATA_FORMAT_B DATA_FORMAT_C DATA_FORMAT_D DATA_FORMAT_E DATA_FORMAT_F DATA_FORMAT_G DATA_FORMAT_H DATA_FORMAT_I DATA_FORMAT_J DATA_FORMAT_K DATA_FORMAT_L LIT_DATA_FORMAT_A LIT_DATA_FORMAT_B LIT_DATA_FORMAT_C LIT_DATA_FORMAT_D LIT_DATA_FORMAT_E LIT_DATA_FORMAT_F LIT_DATA_FORMAT_G LIT_DATA_FORMAT_H LIT_DATA_FORMAT_I LIT_DATA_FORMAT_J LIT_DATA_FORMAT_K LIT_DATA_FORMAT_L DECIMATE_A DECIMATE_B DECIMATE_C DECIMATE_D DECIMATE_E DECIMATE_F DECIMATE_G DECIMATE_H DECIMATE_I DECIMATE_J DECIMATE_K DECIMATE_L [15:11] DARK_SHIFT_x Description Reset Access Four-pulse integration reverse pattern. Set to 1 to reverse 0x0 R/W the integrator positive/negative pulse order in the matching position in a group of four pulses. The LSB maps to the first pulse. Number of bits to shift the dark data to the right before 0x0 R/W writing to the FIFO for Time Slot x. Selectable between 0 bits and 32 bits. [10:8] DARK_SIZE_x Number of bytes of dark data to be written to the FIFO for 0x0 Time Slot x. Selectable between 0 bytes and 4 bytes. R/W [7:3] SIGNAL_SHIFT_x Number of bits to shift the signal data to the right before writing to the FIFO for Time Slot x. Selectable between 0 bits and 32 bits. 0x0 R/W [2:0] SIGNAL_SIZE_x Number of bytes of signal data to be written to the FIFO for Time Slot x. Selectable between 0 bytes and 4 bytes. 0x3 R/W [15:8] [7:3] Reserved LIT_SHIFT_x Reserved Number of bits to shift the lit data to the right before writing to the FIFO for Time Slot x. Selectable between 0 bits and 32 bits. 0x0 0x0 R/W R/W [2:0] LIT_SIZE_x Number of bytes of lit data to be written to the FIFO for Time Slot x. Selectable between 0 bytes and 4 bytes. 0x3 R/W [15:11] Reserved Write 0x0. [10:4] DECIMATE_FACTOR_x Decimate sample divider. Output data rate is sample rate ÷ (DECIMATE_FACTOR_x + 1). Decimate by 1 to 128. 0x0 0x0 R R/W [3:0] 0x0 R/W DECIMATE_TYPE_x Decimation type select. 0: block sum, CIC first order. 1: signal uses CIC second order. 10: signal uses CIC third order. 11: signal uses CIC fourth order. 100: reserved. Rev. 0 | Page 93 of 101 ADPD4100/ADPD4101 Data Sheet AFE TIMING SETUP REGISTERS Table 37. AFE Timing Setup Register Details Addr 0x0107 0x0127 0x0147 0x0167 0x0187 0x01A7 0x01C7 0x01E7 0x0207 0x0227 0x0247 0x0267 0x0108 0x0128 0x0148 0x0168 0x0188 0x01A8 0x01C8 0x01E8 0x0208 0x0228 0x0248 0x0268 Name COUNTS_A COUNTS_B COUNTS_C COUNTS_D COUNTS_E COUNTS_F COUNTS_G COUNTS_H COUNTS_I COUNTS_J COUNTS_K COUNTS_L PERIOD_A PERIOD_B PERIOD_C PERIOD_D PERIOD_E PERIOD_F PERIOD_G PERIOD_H PERIOD_I PERIOD_J PERIOD_K PERIOD_L Bits [15:8] Bit Name NUM_INT_x Description Number of ADC cycles or acquisition width. Number of analog integration cycles per ADC conversion or the acquisition width for digital integration and impulse mode. A setting of 0 is not allowed. Reset Access 0x1 R/W [7:0] NUM_REPEAT_x Number of sequence repeats. Total number of pulses = NUM_INT_x × NUM_REPEAT_x. A setting of 0 is not allowed. 0x1 R/W Reserved. Modulation connection type. 00: TIA is continuously connected to input after precondition. No connection modulation. 0x0 0x0 R R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 0x0 R/W R/W 0x0 R/W 0x0 0x3 R R/W [15:14] Reserved [13:12] MOD_TYPE_x 01: float type operation. Pulse connection from input to TIA with modulation pulse, floating between pulses. 10: nonfloat type connection modulation. Pulse connection from input to TIA. Connect to precondition value between pulses. [11:10] Reserved [9:0] MIN_PERIOD_x Reserved. Minimum period for pulse repetition in μs. Override for the automatically calculated period. Used in float type operations to set the float time of second and subsequent floats using the formula: Float Time = MIN_PERIOD_x − MOD_WIDTH_x. 0x010A INTEG_SETUP_A 15 SINGLE_INTEG_x Use single integrator pulse. 0x012A INTEG_SETUP_B 0: use both generated integrator clocks. 0x014A INTEG_SETUP_C 1: skip the second integrator clock. 0x016A INTEG_SETUP_D [14:12] CH2_AMP_DISABLE_x Amplifier disables for power control. Set the appropriate bit to 0x018A INTEG_SETUP_E disable the Channel 2 amplifier in Time Slot x. 0x01AA INTEG_SETUP_F 0: TIA. 0x01CA INTEG_SETUP_G 1: BPF. 0x01EA INTEG_SETUP_H 2: integrator. 0x020A INTEG_SETUP_I 11 AFE_INT_C_BUF_x Set to 1 to configure the integrator as a buffer in Time Slot x. 0x022A INTEG_SETUP_J [10:8] CH1_AMP_DISABLE_x Amplifier disables for power control. Set the appropriate bit to disable the Channel 1 amplifier in Time Slot x. 0x024A INTEG_SETUP_K 0x026A INTEG_SETUP_L 0: TIA. 1: BPF. 2: integrator. ADC conversions per pulse. Number of conversions = [7:6] ADC_COUNT_x ADC_COUNT + 1. 5 Reserved Reserved. [4:0] INTEG_WIDTH_A Integrator clock width in μs. Must be >0. Rev. 0 | Page 94 of 101 Data Sheet Addr 0x010B 0x012B 0x014B 0x016B 0x018B 0x01AB 0x01CB 0x01EB 0x020B 0x022B 0x024B 0x026B 0x010C 0x012C 0x014C 0x016C 0x018C 0x01AC 0x01CC 0x01EC 0x020C 0x022C 0x024C 0x026C 0x0113 0x0133 0x0153 0x0173 0x0193 0x01B3 0x01D3 0x01F3 0x0213 0x0233 0x0253 0x0273 0x0114 0x0134 0x0154 0x0174 0x0194 0x01B4 0x01D4 0x01F4 0x0214 0x0234 0x0254 0x0274 Name INTEG_OS_A INTEG_OS_B INTEG_OS_C INTEG_OS_D INTEG_OS_E INTEG_OS_F INTEG_OS_G INTEG_OS_H INTEG_OS_I INTEG_OS_J INTEG_OS_K INTEG_OS_L MOD_PULSE_A MOD_PULSE_B MOD_PULSE_C MOD_PULSE_D MOD_PULSE_E MOD_PULSE_F MOD_PULSE_G MOD_PULSE_H MOD_PULSE_I MOD_PULSE_J MOD_PULSE_K MOD_PULSE_L DIGINT_LIT_A DIGINT_LIT_B DIGINT_LIT_C DIGINT_LIT_D DIGINT_LIT_E DIGINT_LIT_F DIGINT_LIT_G DIGINT_LIT_H DIGINT_LIT_I DIGINT_LIT_J DIGINT_LIT_K DIGINT_LIT_L DIGINT_DARK_A DIGINT_DARK_B DIGINT_DARK_C DIGINT_DARK_D DIGINT_DARK_E DIGINT_DARK_F DIGINT_DARK_G DIGINT_DARK_H DIGINT_DARK_I DIGINT_DARK_J DIGINT_DARK_K DIGINT_DARK_L ADPD4100/ADPD4101 Bits Bit Name [15:13] Reserved [12:5] INTEG_OFFSET_x Description Reserved. Integrator clock offset for Time Slot x in 1 µs increments per LSB. Must be >0. Integrator clock offset for Time Slot x in 31.25 ns increments per LSB. Reset Access 0x0 R 0x10 R/W 0x14 R/W [4:0] INTEG_OFFSET_x [15:8] [7:0] MOD_WIDTH_x MOD_OFFSET_x Modulation pulse width for Time Slot x in μs. 0 = disable. Modulation pulse offset for Time Slot x in μs. Must be >0. 0x0 0x1 R/W R/W [15:9] [8:0] Reserved LIT_OFFSET_x Reserved. Digital integration mode, acquisition window lit offset in μs for Time Slot x. Also, impulse response mode offset. Must be >0. 0x0 0x26 R R/W [15:7] DARK2_OFFSET_x Digital integration mode, acquisition window Dark Offset 2 for Time Slot x in μs. Must be >0. 0x046 R/W [6:0] DARK1_OFFSET_x Digital integration mode, acquisition window Dark Offset 1 for Time Slot x in μs. Must be >0. 0x6 Rev. 0 | Page 95 of 101 R/W ADPD4100/ADPD4101 Data Sheet LED CONTROL AND TIMING REGISTERS Table 38. LED Control and Timing Register Details Addr 0x0105 0x0125 0x0145 0x0165 0x0185 0x01A5 0x01C5 0x01E5 0x0205 0x0225 0x0245 0x0265 0x0106 0x0126 0x0146 0x0166 0x0186 0x01A6 0x01C6 0x01E6 0x0206 0x0226 0x0246 0x0266 0x0109 0x0129 0x0149 0x0169 0x0189 0x01A9 0x01C9 0x01E9 0x0209 0x0229 0x0249 0x0269 Name LED_POW12_A LED_POW12_B LED_POW12_C LED_POW12_D LED_POW12_E LED_POW12_F LED_POW12_G LED_POW12_H LED_POW12_I LED_POW12_J LED_POW12_K LED_POW12_L LED_POW34_A LED_POW34_B LED_POW34_C LED_POW34_D LED_POW34_E LED_POW34_F LED_POW34_G LED_POW34_H LED_POW34_I LED_POW34_J LED_POW34_K LED_POW34_L LED_PULSE_A LED_PULSE_B LED_PULSE_C LED_PULSE_D LED_PULSE_E LED_PULSE_F LED_PULSE_G LED_PULSE_H LED_PULSE_I LED_PULSE_J LED_PULSE_K LED_PULSE_L Bits 15 Bit Name Description LED_DRIVESIDE2_x LED output select for LED2x. 0: drive LED on Output LED2A. 1: drive LED on Output LED2B. [14:8] LED_CURRENT2_x LED current setting for LED2A or LED2B output. Set to 0 to disable. Output current varies monotonically from 1.5 mA to 200 mA for values between 0x01 and 0x7F. 7 [6:0] LED_DRIVESIDE1_x LED output select for LED1x. 0: drive LED on Output LED1A. 1: drive LED on Output LED1B. LED_CURRENT1_x LED current setting for LED1A or LED1B output. Set to 0 to disable. Output current varies monotonically from 1.5 mA to 200 mA for values between 0x01 and 0x7F. 15 LED_DRIVESIDE4_x LED output select for LED4x. 0: drive LED on Output LED4A. 1: drive LED on Output LED4B. [14:8] LED_CURRENT4_x LED current setting for LED4A or LED4B output. Set to 0 to disable. Output current varies monotonically from 1.5 mA to 200 mA for values between 0x01 and 0x7F. 7 [6:0] LED_DRIVESIDE3_x LED output select for LED3x. 0: drive LED on Output LED3A. 1: drive LED on Output LED3B. LED_CURRENT3_x LED current setting for LED3A or LED3B output. Set to 0 to disable. Output current varies monotonically from 1.5 mA to 200 mA for values between 0x01 and 0x7F. [15:8] LED_WIDTH_x [7:0] LED_OFFSET_x LED pulse width in μs. 0 = disable. LED pulse offset in μs. Set to a minimum of 16 μs (0x10). Must be >0. Rev. 0 | Page 96 of 101 Reset Access 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x2 0x10 R/W R/W Data Sheet ADPD4100/ADPD4101 ADC OFFSET REGISTERS Table 39. ADC Offset Register Details Addr 0x010E 0x012E 0x014E 0x016E 0x018E 0x01AE 0x01CE 0x01EE 0x020E 0x022E 0x024E 0x026E 0x010F 0x012F 0x014F 0x016F 0x018F 0x01AF 0x01CF 0x01EF 0x020F 0x022F 0x024F 0x026F Name ADC_OFF1_A ADC_OFF1_B ADC_OFF1_C ADC_OFF1_D ADC_OFF1_E ADC_OFF1_F ADC_OFF1_G ADC_OFF1_H ADC_OFF1_I ADC_OFF1_J ADC_OFF1_K ADC_OFF1_L ADC_OFF2_A ADC_OFF2_B ADC_OFF2_C ADC_OFF2_D ADC_OFF2_E ADC_OFF2_F ADC_OFF2_G ADC_OFF2_H ADC_OFF2_I ADC_OFF2_J ADC_OFF2_K ADC_OFF2_L Bits Bit Name Description [15:14] Reserved Reserved. [13:0] CH1_ADC_ADJUST_x Adjustment to ADC value. This value is subtracted from the ADC value for Channel 1 in Time Slot x. Set to 0 for chop and float modes. Reset Access 0x0 R 0x0 R/W 15 14 [13:0] 0x0 R/W 0x0 R/W ZERO_ADJUST_x Reserved Reserved. CH2_ADC_ADJUST_x Adjustment to ADC value. This value is subtracted from the ADC value for Channel 2 in Time Slot x. Set to 0 for chop and float modes. OUTPUT DATA REGISTERS Table 40. Output Data Register Details Addr 0x002F 0x0030 0x0031 0x0032 0x0033 0x0034 0x0035 0x0036 0x0037 0x0038 0x0039 0x003A 0x003B 0x003C 0x003D 0x003E 0x003F 0x0040 0x0041 0x0042 0x0043 Name FIFO_DATA SIGNAL1_L_A SIGNAL1_H_A SIGNAL2_L_A SIGNAL2_H_A DARK1_L_A DARK1_H_A DARK2_L_A DARK2_H_A SIGNAL1_L_B SIGNAL1_H_B SIGNAL2_L_B SIGNAL2_H_B DARK1_L_B DARK1_H_B DARK2_L_B DARK2_H_B SIGNAL1_L_C SIGNAL1_H_C SIGNAL2_L_C SIGNAL2_H_C Bits [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Bit Name FIFO_DATA SIGNAL1_L_A SIGNAL1_H_A SIGNAL2_L_A SIGNAL2_H_A DARK1_L_A DARK1_H_A DARK2_L_A DARK2_H_A SIGNAL1_L_B SIGNAL1_H_B SIGNAL2_L_B SIGNAL2_H_B DARK1_L_B DARK1_H_B DARK2_L_B DARK2_H_B SIGNAL1_L_C SIGNAL1_H_C SIGNAL2_L_C SIGNAL2_H_C Description FIFO data port Signal Channel 1 lower half, Time Slot A Signal Channel 1 upper half, Time Slot A Signal Channel 2 lower half, Time Slot A Signal Channel 2 upper half, Time Slot A Dark Channel 1 value lower half, Time Slot A Dark Channel 1 value upper half, Time Slot A Dark Channel 2 value lower half, Time Slot A Dark Channel 2 value upper half, Time Slot A Signal Channel 1 lower half, Time Slot B Signal Channel 1 upper half, Time Slot B Signal Channel 2 lower half, Time Slot B Signal Channel 2 upper half, Time Slot B Dark Channel 1 value lower half, Time Slot B Dark Channel 1 value upper half, Time Slot B Dark Channel 2 value lower half, Time Slot B Dark Channel 2 value upper half, Time Slot B Signal Channel 1 lower half, Time Slot C Signal Channel 1 upper half, Time Slot C Signal Channel 2 lower half, Time Slot C Signal Channel 2 upper half, Time Slot C Rev. 0 | Page 97 of 101 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R R R R R R R R R R R R R R R ADPD4100/ADPD4101 Addr 0x0044 0x0045 0x0046 0x0047 0x0048 0x0049 0x004A 0x004B 0x004C 0x004D 0x004E 0x004F 0x0050 0x0051 0x0052 0x0053 0x0054 0x0055 0x0056 0x0057 0x0058 0x0059 0x005A 0x005B 0x005C 0x005D 0x005E 0x005F 0x0060 0x0061 0x0062 0x0063 0x0064 0x0065 0x0066 0x0067 0x0068 0x0069 0x006A 0x006B 0x006C 0x006D 0x006E 0x006F 0x0070 0x0071 0x0072 0x0073 0x0074 0x0075 0x0076 0x0077 0x0078 Name DARK1_L_C DARK1_H_C DARK2_L_C DARK2_H_C SIGNAL1_L_D SIGNAL1_H_D SIGNAL2_L_D SIGNAL2_H_D DARK1_L_D DARK1_H_D DARK2_L_D DARK2_H_D SIGNAL1_L_E SIGNAL1_H_E SIGNAL2_L_E SIGNAL2_H_E DARK1_L_E DARK1_H_E DARK2_L_E DARK2_H_E SIGNAL1_L_F SIGNAL1_H_F SIGNAL2_L_F SIGNAL2_H_F DARK1_L_F DARK1_H_F DARK2_L_F DARK2_H_F SIGNAL1_L_G SIGNAL1_H_G SIGNAL2_L_G SIGNAL2_H_G DARK1_L_G DARK1_H_G DARK2_L_G DARK2_H_G SIGNAL1_L_H SIGNAL1_H_H SIGNAL2_L_H SIGNAL2_H_H DARK1_L_H DARK1_H_H DARK2_L_H DARK2_H_H SIGNAL1_L_I SIGNAL1_H_I SIGNAL2_L_I SIGNAL2_H_I DARK1_L_I DARK1_H_I DARK2_L_I DARK2_H_I SIGNAL1_L_J Bits [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Data Sheet Bit Name DARK1_L_C DARK1_H_C DARK2_L_C DARK2_H_C SIGNAL1_L_D SIGNAL1_H_D SIGNAL2_L_D SIGNAL2_H_D DARK1_L_D DARK1_H_D DARK2_L_D DARK2_H_D SIGNAL1_L_E SIGNAL1_H_E SIGNAL2_L_E SIGNAL2_H_E DARK1_L_E DARK1_H_E DARK2_L_E DARK2_H_E SIGNAL1_L_F SIGNAL1_H_F SIGNAL2_L_F SIGNAL2_H_F DARK1_L_F DARK1_H_F DARK2_L_F DARK2_H_F SIGNAL1_L_G SIGNAL1_H_G SIGNAL2_L_G SIGNAL2_H_G DARK1_L_G DARK1_H_G DARK2_L_G DARK2_H_G SIGNAL1_L_H SIGNAL1_H_H SIGNAL2_L_H SIGNAL2_H_H DARK1_L_H DARK1_H_H DARK2_L_H DARK2_H_H SIGNAL1_L_I SIGNAL1_H_I SIGNAL2_L_I SIGNAL2_H_I DARK1_L_I DARK1_H_I DARK2_L_I DARK2_H_I SIGNAL1_L_J Description Dark Channel 1 value lower half, Time Slot C Dark Channel 1 value upper half, Time Slot C Dark Channel 2 value lower half, Time Slot C Dark Channel 2 value upper half, Time Slot C Signal Channel 1 lower half, Time Slot D Signal Channel 1 upper half, Time Slot D Signal Channel 2 lower half, Time Slot D Signal Channel 2 upper half, Time Slot D Dark Channel 1 value lower half, Time Slot D Dark Channel 1 value upper half, Time Slot D Dark Channel 2 value lower half, Time Slot D Dark Channel 2 value upper half, Time Slot D Signal Channel 1 lower half, Time Slot E Signal Channel 1 upper half, Time Slot E Signal Channel 2 lower half, Time Slot E Signal Channel 2 upper half, Time Slot E Dark Channel 1 value lower half, Time Slot E Dark Channel 1 value upper half, Time Slot E Dark Channel 2 value lower half, Time Slot E Dark Channel 2 value upper half, Time Slot E Signal Channel 1 lower half, Time Slot F Signal Channel 1 upper half, Time Slot F Signal Channel 2 lower half, Time Slot F Signal Channel 2 upper half, Time Slot F Dark Channel 1 value lower half, Time Slot F Dark Channel 1 value upper half, Time Slot F Dark Channel 2 value lower half, Time Slot F Dark Channel 2 value upper half, Time Slot F Signal Channel 1 lower half, Time Slot G Signal Channel 1 upper half, Time Slot G Signal Channel 2 lower half, Time Slot G Signal Channel 2 upper half, Time Slot G Dark Channel 1 value lower half, Time Slot G Dark Channel 1 value upper half, Time Slot G Dark Channel 2 value lower half, Time Slot G Dark Channel 2 value upper half, Time Slot G Signal Channel 1 lower half, Time Slot H Signal Channel 1 upper half, Time Slot H Signal Channel 2 lower half, Time Slot H Signal Channel 2 upper half, Time Slot H Dark Channel 1 value lower half, Time Slot H Dark Channel 1 value upper half, Time Slot H Dark Channel 2 value lower half, Time Slot H Dark Channel 2 value upper half, Time Slot H Signal Channel 1 lower half, Time Slot I Signal Channel 1 upper half, Time Slot I Signal Channel 2 lower half, Time Slot I Signal Channel 2 upper half, Time Slot I Dark Channel 1 value lower half, Time Slot I Dark Channel 1 value upper half, Time Slot I Dark Channel 2 value lower half, Time Slot I Dark Channel 2 value upper half, Time Slot I Signal Channel 1 lower half, Time Slot J Rev. 0 | Page 98 of 101 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Data Sheet Addr 0x0079 0x007A 0x007B 0x007C 0x007D 0x007E 0x007F 0x0080 0x0081 0x0082 0x0083 0x0084 0x0085 0x0086 0x0087 0x0088 0x0089 0x008A 0x008B 0x008C 0x008D 0x008E 0x008F Name SIGNAL1_H_J SIGNAL2_L_J SIGNAL2_H_J DARK1_L_J DARK1_H_J DARK2_L_J DARK2_H_J SIGNAL1_L_K SIGNAL1_H_K SIGNAL2_L_K SIGNAL2_H_K DARK1_L_K DARK1_H_K DARK2_L_K DARK2_H_K SIGNAL1_L_L SIGNAL1_H_L SIGNAL2_L_L SIGNAL2_H_L DARK1_L_L DARK1_H_L DARK2_L_L DARK2_H_L ADPD4100/ADPD4101 Bits [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Bit Name SIGNAL1_H_J SIGNAL2_L_J SIGNAL2_H_J DARK1_L_J DARK1_H_J DARK2_L_J DARK2_H_J SIGNAL1_L_K SIGNAL1_H_K SIGNAL2_L_K SIGNAL2_H_K DARK1_L_K DARK1_H_K DARK2_L_K DARK2_H_K SIGNAL1_L_L SIGNAL1_H_L SIGNAL2_L_L SIGNAL2_H_L DARK1_L_L DARK1_H_L DARK2_L_L DARK2_H_L Description Signal Channel 1 upper half, Time Slot J Signal Channel 2 lower half, Time Slot J Signal Channel 2 upper half, Time Slot J Dark Channel 1 value lower half, Time Slot J Dark Channel 1 value upper half, Time Slot J Dark Channel 2 value lower half, Time Slot J Dark Channel 2 value upper half, Time Slot J Signal Channel 1 lower half, Time Slot K Signal Channel 1 upper half, Time Slot K Signal Channel 2 lower half, Time Slot K Signal Channel 2 upper half, Time Slot K Dark Channel 1 value lower half, Time Slot K Dark Channel 1 value upper half, Time Slot K Dark Channel 2 value lower half, Time Slot K Dark Channel 2 value upper half, Time Slot K Signal Channel 1 lower half, Time Slot L Signal Channel 1 upper half, Time Slot L Signal Channel 2 lower half, Time Slot L Signal Channel 2 upper half, Time Slot L Dark Channel 1 value lower half, Time Slot L Dark Channel 1 value upper half, Time Slot L Dark Channel 2 value lower half, Time Slot L Dark Channel 2 value upper half, Time Slot L Rev. 0 | Page 99 of 101 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R R R R R R R R R R R R R R R R R ADPD4100/ADPD4101 Data Sheet OUTLINE DIMENSIONS 2.180 2.140 2.100 0.225 BSC 5 4 3 2 1 A BALL A1 IDENTIFIER B 3.150 3.110 3.070 C 2.40 REF D E 0.40 BSC F G TOP VIEW SIDE VIEW 0.330 0.300 0.270 0.315 BSC (BALL SIDE UP) COPLANARITY 0.05 SEATING PLANE 0.230 0.200 0.170 PKG-005711 0.300 0.260 0.220 06-03-2019-B 0.560 0.500 0.440 BOTTOM VIEW 0.225 BSC 1.60 REF (BALL SIDE DOWN) 0.485 BSC Figure 58. 35-Ball Wafer Level Chip Scale Package [WLCSP] (CB-35-2) Dimensions shown in millimeters 2.180 2.140 2.100 0.225 BSC 5 4 3 2 1 A BALL A1 IDENTIFIER B 3.150 3.110 3.070 C 2.40 REF D E 0.40 BSC F G TOP VIEW 0.225 BSC 1.60 REF (BALL SIDE DOWN) PKG-005914 SEATING PLANE SIDE VIEW 0.330 0.300 0.270 (BALL SIDE UP) 0.315 BSC COPLANARITY 0.05 0.300 0.260 0.220 0.230 0.200 0.170 Figure 59. 33-Ball Wafer Level Chip Scale Package [WLCSP] (CB-33-1) Dimensions shown in millimeters Rev. 0 | Page 100 of 101 06-03-2019-B 0.560 0.500 0.440 BOTTOM VIEW 0.485 BSC Data Sheet ADPD4100/ADPD4101 ORDERING GUIDE Model1, 2 ADPD4100BCBZR7 ADPD4101BCBZR7 EVAL-ADPD4100Z-PPG 1 2 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 35-Ball Wafer Level Chip Scale Package [WLCSP] 33-Ball Wafer Level Chip Scale Package [WLCSP] Evaluation Board Package Option CB-35-2 CB-33-1 Z = RoHS Compliant Part. EVAL-ADPDUCZ is the microcontroller board, ordered separately, which is required to interface with the EVAL-ADPD4100Z-PPG evaluation board. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D23297-6/20(0) Rev. 0 | Page 101 of 101