ADRF5720BCCZN

0.5 dB LSB, 6-Bit, Silicon Digital Attenuator, 9 kHz to 40 GHz ADRF5720 Data Sheet FUNCTIONAL BLOCK DIAGRAM D5/CLK D4/SERIN D3/SEROUT D2 D1 D0 ADRF5720 24 23 22 21 20 19 LE 1 18 VDD PS 2 17 VSS GND 3 16 GND GND 4 15 GND ATTIN 5 14 ATTOUT GND 6 13 GND SERIAL/ PARALLEL INTERFACE 6-BIT DIGITAL ATTENUATOR 12 PACKAGE BASE GND 15959-001 11 GND 10 GND 9 GND 8 GND 7 GND Ultrawideband frequency range: 9 kHz to 40 GHz Attenuation range: 0.5 dB steps to 31.5 dB Low insertion loss with impedance match 2.0 dB up to 18 GHz 2.8 dB up to 26 GHz 4.5 dB up to 40 GHz Attenuation accuracy with impedance match ±(0.20 + 1.0% of attenuation state) up to 18 GHz ±(0.20 + 1.5% of attenuation state) up to 26 GHz ±(0.40+ 3.0% of attenuation state) up to 40 GHz Typical step error with impedance match ±0.25 dB up to 26 GHz ±0.65 dB up to 40 GHz High input linearity P0.1dB insertion loss state: 30 dBm P0.1dB other attenuation states: 27 dBm IP3: 50 dBm typical High RF input power handling: 27 dBm average, 30 dBm peak Tight distribution in relative phase No low frequency spurious signals SPI and parallel mode control, CMOS/LVTTL compatible RF amplitude settling time (0.1 dB of final RF output): 8 µs 24-terminal, 4 mm × 4 mm LGA package Pin-compatible with ADRF5730, fast switching version GND FEATURES Figure 1. APPLICATIONS Industrial scanners Test and instrumentation Cellular infrastructure: 5G millimeter wave Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs) GENERAL DESCRIPTION The ADRF5720 is a silicon, 6-bit digital attenuator with 31.5 dB attenuation control range in 0.5 dB steps. The ADRF5720 is pin-compatible with the ADRF5730, the fast switching version, which operates from 100 MHz to 40 GHz. This device operates from 9 kHz to 40 GHz with better than 4.5 dB of insertion loss and excellent attenuation accuracy. The ATTIN port of the ADRF5720 has a radio frequency (RF) input power handling capability of 27 dBm average and 30 dBm peak for all states. The ADRF5720 RF ports are designed to match a characteristic impedance of 50 Ω. For wideband applications, impedance matching on the RF transmission lines can further optimize high frequency insertion loss, return loss, and attenuation accuracy characteristics. Refer to the Electrical Specifications section, the Typical Performance Characteristics section, and the Applications Information section for more details. The ADRF5720 requires a dual supply voltage of +3.3 V and −3.3 V. The device features serial peripheral interface (SPI), parallel mode control, and complementary metal-oxide semiconductor (CMOS)-/low voltage transistor to transistor logic (LVTTL)-compatible controls. Rev. B The ADRF5720 comes in a 24-terminal, 4 mm × 4 mm, RoHS compliant, land grid array (LGA) package and operates from −40°C to +105°C. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2018–2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADRF5720 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Insertion Loss, Return Loss, State Error, Step Error, and Relative Phase ................................................................................8 Functional Block Diagram .............................................................. 1 Input Power Compression and Third-Order Intercept ......... 12 General Description ......................................................................... 1 Theory of Operation ...................................................................... 13 Revision History ............................................................................... 2 Power Sequence .......................................................................... 13 Specifications..................................................................................... 3 RF Input and Output ................................................................. 13 Electrical Specifications ............................................................... 3 Serial or Parallel Mode Selection ............................................. 14 Timing Specifications .................................................................. 5 Serial Mode Interface ................................................................. 14 Absolute Maximum Ratings............................................................ 6 Parallel Mode Interface.............................................................. 15 Power Derating Curves ................................................................ 6 Applications Information .............................................................. 16 ESD Caution .................................................................................. 6 Evaluation Board ........................................................................ 16 Pin Configuration and Function Descriptions ............................. 7 Probe Matrix Board ................................................................... 18 Interface Schematics..................................................................... 7 Outline Dimensions ....................................................................... 19 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 19 REVISION HISTORY 11/2020—Rev. A to Rev. B Changes to tCH Parameter and tCO Parameter, Table 2 ................. 5 Changes to Figure 26 and Figure 27............................................. 11 Changes to Serial Mode Interface Section, Using SEROUT Section, and Figure 34 ................................................................................... 14 Deleted Figure 33; Renumbered Sequentially ............................ 14 3/2020—Rev. 0 to Rev. A Changes to RF Power Parameter, Table 1 .......................................5 Changes to Table 3.............................................................................6 Changes to Power Supply Section ................................................ 13 Added Power-Up State Section..................................................... 13 Moved Serial or Parallel Mode Selection Section and Table 7; Renumbered Sequentially ......................................................................14 7/2018—Revision 0: Initial Version Rev. B | Page 2 of 19 Data Sheet ADRF5720 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VDD = 3.3 V, VSS = −3.3 V, digital voltages = 0 V or VDD, case temperature (TCASE) = 25°C, and 50 Ω system, unless otherwise noted. Table 1. Parameter FREQUENCY RANGE INSERTION LOSS (IL) With Impedance Match Without Impedance Match RETURN LOSS With Impedance Match Without Impedance Match ATTENUATION Range Step Size Accuracy With Impedance Match Without Impedance Match Test Conditions/Comments See Figure 43 9 kHz to 10 GHz 10 GHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz See Figure 42 9 kHz to 10 GHz 10 GHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz ATTIN and ATTOUT, all attenuation states See Figure 43 9 kHz to 10 GHz 10 GHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz See Figure 42 9 kHz to 10 GHz 10 GHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz Between minimum and maximum attenuation states Between any successive attenuation states Referenced to insertion loss See Figure 43 9 kHz to 10 GHz 10 GHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz See Figure 42 9 kHz to 10 GHz 10 GHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz Rev. B | Page 3 of 19 Min 0.009 Typ Max 40,000 Unit MHz 1.5 2.0 2.8 3.7 4.5 dB dB dB dB dB 1.6 2.1 2.7 3.6 4.6 dB dB dB dB dB 18 17 17 15 15 dB dB dB dB dB 18 15 15 14 11 dB dB dB dB dB 31.5 dB 0.5 dB ±(0.15 + 1.0% of state) ±(0.20 + 1.0% of state) ±(0.20 + 1.5% of state) ±(0.25 + 2.5% of state) ±(0.40 + 3.0% of state) dB dB dB dB dB ±(0.15 + 1.0% of state) ±(0.25 + 1.0% of state) ±(0.20 + 1.5% of state) ±(0.25 + 2.0% of state) ±(0.40 + 5.0% of state) dB dB dB dB dB ADRF5720 Parameter Step Error With Impedance Match Without Impedance Match RELATIVE PHASE With Impedance Match Without Impedance Match SWITCHING CHARACTERISTICS Rise and Fall Time (tRISE and tFALL) On and Off Time (tON and tOFF) RF Amplitude Settling Time 0.1 dB 0.05 dB Overshoot Undershoot RF Phase Settling Time 5° 1° INPUT LINEARITY 1 Data Sheet Test Conditions/Comments Between any successive state See Figure 43 9 kHz to 10 GHz 10 GHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz See Figure 42 9 kHz to 10 GHz 10 GHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz Referenced to insertion loss See Figure 43 10 GHz 18 GHz 26 GHz 35 GHz 40 GHz See Figure 42 10 GHz 18 GHz 26 GHz 35 GHz 40 GHz All attenuation states at input power = 10 dBm 10% to 90% of RF output 50% triggered control (CTL) to 90% of RF output Min 50% triggered CTL to 0.1 dB of final RF output 50% triggered CTL to 0.05 dB of final RF output f = 5 GHz 50% triggered CTL to 5° of final RF output 50% triggered CTL to 1° of final RF output 1 MHz to 30 GHz Typ Max Unit ±0.15 ±0.23 ±0.25 ±0.50 ±0.65 dB dB dB dB dB ±0.15 ±0.23 ±0.25 ±0.40 ±0.70 dB dB dB dB dB 15 30 50 75 100 Degrees Degrees Degrees Degrees Degrees 15 30 50 80 105 Degrees Degrees Degrees Degrees Degrees 1.3 3.9 µs µs 8 10 2 −1.5 µs µs dB dB 3 4 µs µs 30 27 50 dBm dBm dBm 0.1 dB Power Compression (P0.1dB) Insertion Loss State Other Attenuation States Third-Order Intercept (IP3) DIGITAL CONTROL INPUTS Voltage Low (VINL) High (VINH) Current Low (IINL) High (IINH) Two-tone input power = 14 dBm per tone, Δf = 1 MHz, all attenuation states LE, PS, D0, D1, D2, D3/SEROUT 2, D4/SERIN, D5/CLK pins 0 1.2 D0, D1, D2 LE, PS, D3/SEROUT2, D4/SERIN, D5/CLK pins Rev. B | Page 4 of 19 0.8 3.3