ADRF6520ACPZ

Dual Programmable Filters and VGAs for 2 GHz Channel Spacing for µW Radios ADRF6520 Data Sheet APPLICATIONS 25 ENBL 26 CHP1 27 COM 28 VPS 29 VPS 30 COMD 31 VPSD 32 CS FUNCTIONAL BLOCK DIAGRAM INP1 1 24 OPP1 INM1 2 23 OPM1 COM 3 22 COM ADRF6520 CFLT1 4 21 VGN1 CFLT2 5 20 VGN2 DETECTOR 19 COM VRMS 16 CHP2 15 COM 14 VPS 13 VPS 12 17 OPP2 SDIO 11 18 OPM2 INP2 8 9 INM2 7 14830-001 COM 6 RST Matched VGAs and programmable filters Maximum gain: 53 dB Continuous gain control range: 60 dB Filter bypass mode I/Q bandwidth ±1 dB gain flatness: >1250 MHz 4-pole Butterworth filter I/Q bandwidth: 36 MHz to 720 MHz RMS detector IMD3: 55 dBc, RLOAD = 100 Ω Gain = 53 dB Min Typ 3.5 4.5 1.5 14 Max Unit Inputs shorted, dc offset correction loop enabled AC coupling recommended 2 V. Analog Positive Supply Voltage: 3.15 V to 3.45 V. DC Offset Correction Loop Capacitors. Connect the capacitors to a circuit common. RMS Detector Output. The output transfer function is 1 V/V rms × (CH1_RMS + CH2_RMS), where CH1_RMS is the differential rms voltage of the input of the Channel 1 filter, and CH2_RMS is the differential rms voltage of the input of the Channel 2 filter. The user can leave the pin open if not using the rms detector; there is no need to terminate this pin. Load this pin with at least 1 kΩ to ground; values lower than this prevent the detector output from reaching its full-scale value. Channel 2 Differential Outputs. These outputs have a 20 Ω differential output impedance. VGA2 and VGA1 Analog Gain Control. These pins operate from 0 V to 1.5 V with 30 mV/dB gain scaling. Channel 2 Differential Outputs. These outputs have a 20 Ω differential output impedance. Chip Enable. Pull this pin high to enable the chip. Voltages on ENBL of less than 1.6 V disable the device. Digital Common. Connect this pin to an external circuit common using the lowest possible impedance. Digital Positive Supply Voltage: 3.15 V to 3.45 V. Chip Select Bar to Enable SPI Programming. CS is an SPI programming pin and is active low. The TTL levels are VLOW < 0.8 V and VHIGH > 2 V. Exposed Ground Pad. Connect the exposed pad to a low impedance ground pad. Rev. 0 | Page 7 of 29 ADRF6520 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VPS, VPSD = 3.3 V, TA = 25°C, ZLOAD = 100 Ω, dc offset correction loop disable bit (B5) = 1 (enabled), noise spectral density (NSD) measured at fC/2 and at 500 MHz in bypass mode, unless otherwise noted. Noise figure measured with 100 Ω differential input termination. Worst case IMD3 tone is reported for all IMD3/IP3 plots. 25 3 +85°C +25°C –40°C 20 +85°C +25°C –40°C 2 GAIN ERROR (dB) GAIN (dB) 15 10 5 1 0 –1 0 0 0.25 0.50 0.75 1.00 1.25 1.50 VGN1 (V) Figure 3. Gain at 500 MHz vs. VGN1 over Temperature; Bypass Mode, VGN2 = 0 V 60 –3 14830-003 –10 0 0.25 0.50 0.75 1.00 1.25 1.50 VGN1 (V) 14830-006 –2 –5 Figure 6. Gain Error at 500 MHz vs. VGN1 over Temperature; Bypass Mode, VGN2 = 0 V 5 +85°C +25°C –40°C +85°C +25°C –40°C 4 3 GAIN ERROR (dB) GAIN (dB) 50 40 2 1 0 –1 –2 30 –3 0 0.25 0.50 0.75 1.00 1.25 1.50 VGN2 (V) –5 14830-004 20 0 0.75 1.00 1.25 1.50 Figure 7. Gain Error at 500 MHz vs. VGN2 over Temperature; Bypass Mode, VGN1 = 1.5 V 60 3.15V 3.45V 3.3V 3.15V 3.45V 3.3V 20 0.50 VGN2 (V) Figure 4. Gain at 500 MHz vs. VGN2 over Supply; Bypass Mode, VGN1 = 1.5 V 25 0.25 14830-007 –4 50 GAIN (dB) 10 5 0 40 30 –10 0 0.25 0.50 0.75 1.00 1.25 1.50 VGN1 (V) Figure 5. Gain at 500 MHz vs. VGN1 over Supply; Bypass Mode, VGN2 = 0 V 20 0 0.25 0.50 0.75 1.00 1.25 1.50 VGN2 (V) Figure 8. Gain at 500 MHz vs. VGN2 over Supply; Bypass Mode, VGN1 = 1.5 V Rev. 0 | Page 8 of 29 14830-104 –5 14830-103 GAIN (dB) 15 Data Sheet ADRF6520 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.5 0 0.25 0.50 0.75 1.00 1.25 1.50 VGN1 (V) 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 14830-005 –0.4 0.4 0 0.25 0.75 0.50 1.25 1.00 1.50 VGN2 (V) 14830-008 CHANNEL TO CHANNEL GAIN MISMATCH (dB) CHANNEL TO CHANNEL GAIN MISMATCH (dB) 0.5 Figure 12. Channel to Channel Gain Mismatch vs. VGN2; VGN1 = 1.5 V, Bypass Mode at 500 MHz Figure 9. Channel to Chanel Gain Mismatch vs. VGN1; VGN2 = 0 V, Bypass Mode at 500 MHz 60 60 VPS = 3.3V VPS = 3.15V VPS = 3.45V TA = +85°C TA = +25°C TA = –40°C 50 50 40 BYPASS 720MHz 40 30 576MHz 20 GAIN (dB) GAIN (dB) 30 10 0 –10 432MHz 20 288MHz 10 –20 –30 0 –40 36MHz 72MHz 144MHz –10 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (GHz) –20 Figure 10. Gain vs. Frequency over VGN1/VGN2, 3 dB Gain Steps 0 1.5 2.0 2.5 3.0 4.5 5.0 54.5 54.0 GAIN (dB) 53.5 53 53.0 52.5 52.0 36MHz FILTER 72MHz FILTER 144MHz FILTER 288MHz FILTER 432MHz FILTER 576MHz FILTER 720MHz FILTER FILTER BYPASS 51.5 52 51.0 50.5 51 10 4.0 55.0 36MHz FILTER 72MHz FILTER 144MHz FILTER 288MHz FILTER 432MHz FILTER 576MHz FILTER 720MHz FILTER FILTER BYPASS 1 3.5 Figure 13. Frequency Response over Supply and Temperature for 36 MHz, 144 MHz, 288 MHz, 432 MHz, 576 MHz, and 720 MHz Filter Corners and Bypass 100 1000 FREQUENCY (MHz) 14830-011 GAIN (dB) 1.0 FREQUENCY (MHz) 55 54 0.5 Figure 11. Gain vs. Frequency over all Bandwidth Settings; VGN1 = VGN2 = 1.5 V (Logarithmic) 50.0 100 300 500 700 900 1100 1300 1500 FREQUENCY (MHz) Figure 14. Gain vs. Frequency over all Bandwidth Settings; VGN1 = VGN2 = 1.5 V (Linear) Rev. 0 | Page 9 of 29 14830-014 0 14830-009 –60 14830-013 –50 ADRF6520 Data Sheet 16 1.00 36MHz FILTER 144MHz FILTER 720MHz FILTER BYPASS MODE 10 8 6 4 2 0.50 0.25 0 –0.25 –0.50 –0.75 5 50 –1.00 14830-015 0 500 FREQUENCY (MHz) Figure 15. Group Delay vs. Frequency for 36 MHz, 144 MHz, 720 MHz, and Bypass Mode 10 1 100 14830-018 GROUP DELAY (ns) 12 1000 FREQUENCY (MHz) Figure 18. IQ Amplitude Mismatch vs. Frequency for 36 MHz, 144 MHz, 720 MHz, and Bypass Mode 100 300 BYPASS MODE 720MHz FILTER 36MHz FILTER 144MHz FILTER 250 200 GROUP DELAY MISMATCH (ps) GROUP DELAY MISMATCH (ps) 36MHz FILTER 144MHz FILTER 720MHz FILTER BYPASS MODE 0.75 I/Q AMPLITUDE MISMATCH (dB) 14 150 100 50 0 –50 –100 –150 50 0 –50 –200 13 23 33 43 53 63 73 83 93 103 113 123 133 143 153 FREQUENCY (MHz) –100 0 15 55 430 14 50 13 45 12 40 11 35 10 30 0 Figure 17. OP1dB vs. Gain at a Fundamental of 500 MHz GAIN (dB) 25 20 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VGN2 (V) CURRENT CONSUMPTION (mA) 440 500 625 750 875 1000 1125 1250 420 410 400 390 380 370 360 350 –40 –30 –20 –10 14830-317 OP1dB (dBm) 60 8 375 Figure 19. IQ Group Delay Mismatch vs. Frequency for 720 MHz and Bypass Mode 16 OP1dB GAIN 250 FREQUENCY (MHz) Figure 16. IQ Group Delay Mismatch vs. Frequency for 36 MHz and 144 MHz 9 125 3.15V, 144MHz 3.3V, 144MHz 3.45V, 144MHz 3.15V, 720MHz 3.3V, 720MHz 3.45V, 720MHz 3.15V, 36MHz 3.3V, 36MHz 3.45V, 36MHz 3.15V, BYPASS 3.3V, BYPASS 3.45V, BYPASS 0 10 20 30 40 TEMPERATURE (°C) 50 60 70 80 14830-035 3 14830-016 –300 14830-119 –250 Figure 20. Current Consumption vs. Temperature for 36 MHz, 144 MHz, 720 MHz, and Bypass Mode Rev. 0 | Page 10 of 29 Data Sheet ADRF6520 –115 FILTER BYPASS 720MHz 144MHz 36MHz 40 –120 OUTPUT NSD (dBV/Hz) NOISE FIGURE (dB) 35 30 25 20 15 10 –125 –130 –135 FILTER BYPASS 720MHz 144MHz 36MHz 5 0 0.25 0.50 0.75 1.00 1.25 1.50 VGN1 (V) –140 14830-019 0 Figure 21. Noise Figure vs. VGN1 for 36 MHz, 144 MHz, 720 MHz, and Bypass; VGN2 = 1.5 V 0 0.50 0.75 1.00 1.25 1.50 VGN1 (V) Figure 24. Output NSD vs. VGN1 for 36 MHz, 144 MHz, 720 MHz, and Bypass; VGN2 = 1.5 V 30 –115 36MHz FILTER 144MHz FILTER 720MHz FILTER 25 0.25 14830-017 45 OUTPUT NSD (dBV/Hz) 20 15 10 –125 –130 –135 5 0 0.25 0.50 0.75 1.00 1.25 1.50 VGN2 (V) 14830-122 0 720MHz 144MHz 36MHz –140 0 0.25 0.50 0.75 1.00 1.25 1.50 VGN2 (V) Figure 22. Noise Figure vs. VGN2 for 36 MHz, 144 MHz, 720 MHz; VGN1 = 1.5 V 14830-023 NOISE FIGURE (dB) –120 Figure 25. Output NSD vs. VGN2 for 36 MHz, 144 MHz, 720 MHz; VGN1 = 1.5 V 30 –115 100MHz BYPASS 500MHz BYPASS 25 OUTPUT NSD (dBV/Hz) 20 15 10 –125 –130 –135 0 0 0.25 0.50 0.75 VGN2 (V) 1.00 1.25 1.50 14830-200 5 Figure 23. Noise Figure vs. VGN2 for Bypass Mode; NSD at 100 MHz and 500 MHz; VGN1 = 1.5 V NSD AT 100MHz NSD AT 500MHz –140 0 0.25 0.50 0.75 VGN2 (V) 1.00 1.25 1.50 14830-123 NOISE FIGURE (dB) –120 Figure 26. Output NSD vs. VGN2 for Bypass Mode; NSD at 100 MHz and 500 MHz; VGN1 = 1.5 V Rev. 0 | Page 11 of 29 ADRF6520 Data Sheet 60 40 –120 OUTPUT NSD (dBV/Hz) 50 30 20 VGN2 = 0.4V VGN2 = 1.0V VGN2 = 1.6V –130 0.50 0.75 1.00 1.25 1.50 –140 VGN1 (V) 0 –110 –130 –45 –40 –35 –30 –25 –20 –15 –10 15 10 INPUT BLOCKER LEVEL (dBV) 0 –50 –40 –30 –20 –10 14830-125 –50 –55 –55 –60 –60 –65 –65 –70 –70 HD3 (dBc) –50 –75 –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V –90 –95 –100 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VGN1 (V) 10 20 30 40 50 60 70 80 90 –75 –80 –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V –85 –90 –95 14830-205 –85 0 Figure 31. Noise Figure vs. Temperature over Bandwidth and Gain –50 –80 36MHz fC; VGN1/VGN2 = 1.5V/0V 720MHz fC; VGN1/VGN2 = 1.5V/0V FILTER BYPASS; VGN1/VGN2 = 1.5V/0V 36MHz fC; VGN1/VGN2 = 1.5V/1.5V 720MHz fC; VGN1/VGN2 = 1.5V/1.5V FILTER BYPASS; VGN1/VGN2 = 1.5V/1.5V TEMPERATURE (°C) Figure 28. Output NSD vs. Input Blocker Level over VGA2 Gain and Filter Corners; VGN1 = 1.5 V 0 1.50 20 5 –140 –55 1.25 25 –120 –150 –60 1.00 30 NOISE FIGURE (dB) –100 0.75 Figure 30. Output NSD vs. VGN1 over VGN2; Bypass Mode 36MHz fC, GAIN = 54dB 144MHz fC, GAIN = 54dB 720MHz fC, GAIN = 54dB 36MHz fC, GAIN = 39dB 144MHz fC, GAIN = 39dB 720MHz fC, GAIN = 39dB 36MHz fC, GAIN = 24dB 144MHz fC, GAIN = 24dB 720MHz fC, GAIN = 24dB –90 0.50 VGN1 (V) Figure 27. Noise Figure vs. VGN1 over VGN2, Bypass Mode –80 0.25 14830-025 0.25 14830-022 0 14830-021 0 OUTPUT NSD (dBV/Hz) VGN2 = 0.2V VGN2 = 0.8V VGN2 = 1.4V –135 10 HD2 (dBc) VGN2 = 0V VGN2 = 0.6V VGN2 = 1.2V –125 Figure 29. HD2 vs. VGN1 over Supply and Temperature, VGN2 = 0 V, 1.5 V p-p at Output, Bypass Mode –100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VGN1 (V) 14830-206 NOISE FIGURE (dB) –115 VGN2 = 0V VGN2 = 0.2V VGN2 = 0.4V VGN2 = 0.6V VGN2 = 0.8V VGN2 = 1V VGN2 = 1.2V VGN2 = 1.4V VGN2 = 1.6V Figure 32. HD3 vs. VGN1 over Supply and Temperature, VGN2 = 0 V, 1.5 V p-p at Output, Bypass Mode Rev. 0 | Page 12 of 29 Data Sheet ADRF6520 –55 –60 –65 –55 –60 –65 HD3 (dBc) –70 –75 –80 –70 –75 –80 –85 –85 –90 –90 –95 –95 –100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VGN2 (V) Figure 33. HD2 vs. VGN2 over Supply and Temperature, VGN1 = 1.5 V, 1.5 V p-p at Output, Bypass Mode –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V –100 14830-207 HD2 (dBc) –50 –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VGN2 (V) 14830-208 –50 Figure 36. HD3 vs. VGN2 over Supply and Temperature, VGN1 = 1.5 V, 1.5 V p-p at Output, Bypass Mode –50 –50 –55 –55 –65 –65 –70 –70 –75 –80 –90 –95 –100 0 –90 UPPER TONE –95 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 Figure 34. IMD2 vs. VGN1 over Supply and Temperature, VGN2 = 0 V, 1.5 V p-p Composite at Output, 36 MHz Filter Corner –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V –55 –60 –100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VGN1 (V) Figure 37. IMD3 vs. VGN1 over Supply and Temperature, VGN2 = 0 V, 1.5 V p-p Composite at Output, 36 MHz Filter Corner –50 –55 –60 UPPER TONE –65 –70 IMD3 (dBc) IMD2 (dBc) –65 –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V –85 VGN1 (V) –50 –80 –75 –80 –85 –70 –75 –80 –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V –85 LOWER TONE –90 –90 –95 –95 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VGN1 (V) –100 14830-335 –100 Figure 35. IMD2 vs. VGN1 over Supply and Temperature, VGN2 = 0 V, 1.5 V p-p Composite at Output, 144 MHz Filter Corner 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VGN1 (V) 14830-338 –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V –85 –75 14830-337 IMD3 (dBc) –60 14830-334 IMD2 (dBc) LOWER TONE –60 Figure 38. IMD3 vs. VGN1 over Supply and Temperature, VGN2 = 0 V, 1.5 V p-p Composite at Output, 144 MHz Filter Corner Rev. 0 | Page 13 of 29 ADRF6520 Data Sheet –50 –50 UPPER TONE –55 –60 –65 –65 –70 –70 –75 –80 –85 –90 –95 LOWER TONE –100 0 –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VGN1 (V) –55 LOWER TONE –60 –95 –100 0 VGN1 (V) –50 –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V –55 –60 –65 –70 –75 –80 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 Figure 42. IMD3 vs. VGN1 over Supply and Temperature, VGN2 = 0 V, 1.5 V p-p Composite at Output, 720 MHz Filter Corner –70 –75 –80 –85 –85 –90 –90 UPPER TONE –100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VGN2 (V) Figure 40. IMD2 vs. VGN2 over Supply and Temperature, VGN1 = 1.5 V, 1.5 V p-p Composite at Output, 36 MHz Filter Corner –50 –55 –60 UPPER TONE –65 –100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VGN2 (V) Figure 43. IMD3 vs. VGN2 over Supply and Temperature, VGN1 = 1.5 V, 1.5 V p-p Composite at Output, 36 MHz Filter Corner –50 –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V –55 –60 –65 IMD3 (dBc) –70 –75 –80 14830-343 –95 14830-340 –95 –85 –70 –75 –80 –85 LOWER TONE –90 –90 –95 –95 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VGN2 (V) –100 14830-341 –100 Figure 41. IMD2 vs. VGN2 over Supply and Temperature, VGN1 = 1.5 V, 1.5 V p-p Composite at Output, 144 MHz Filter Corner 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VGN2 (V) 14830-344 IMD2 (dBc) –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V –90 IMD3 (dBc) IMD2 (dBc) –65 –80 –85 Figure 39. IMD2 vs. VGN1 over Supply and Temperature, VGN2 = 0 V, 1.5 V p-p Composite at Output, 720 MHz Filter Corner –50 –75 14830-342 IMD3 (dBc) –60 14830-339 IMD2 (dBc) –55 Figure 44. IMD3 vs. VGN2 over Supply and Temperature, VGN1 = 1.5 V, 1.5 V p-p Composite at Output, 144 MHz Filter Corner Rev. 0 | Page 14 of 29 Data Sheet –60 –60 –65 IMD3 (dBc) –70 –75 –80 –80 –90 –90 –95 –95 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VGN2 (V) Figure 45. IMD2 vs. VGN2 over Supply and Temperature, VGN1 = 1.5 V, 1.5 V p-p Composite at Output, 720 MHz Filter Corner –50 –100 0 VGN2 (V) –50 UPPER TONE –55 –60 –60 –65 –65 –70 –70 IMD3 (dBc) –55 –75 –80 –85 –90 LOWER TONE –95 –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V –100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VGN1 (V) –75 –80 –90 –95 –100 0 VGN1 (V) –55 –55 –60 –60 –65 –65 –70 –70 IMD3 (dBc) –50 –75 –80 –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V –100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VGN1 (V) –75 –80 –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V –85 –90 –95 –100 14830-347 –95 Figure 47. IMD2 vs. VGN1 over Supply and Temperature, VGN2 = 0 V, 1.5 V p-p Composite at Output, Bypass Mode, 1 GHz Tones, Low Tone Measured 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 Figure 49. IMD3 vs. VGN1 over Supply and Temperature, VGN2 = 0 V, 1.5 V p-p Composite at Output, Bypass Mode, 500 MHz Tones –50 –90 –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V –85 Figure 46. IMD2 vs. VGN1 over Supply and Temperature, VGN2 = 0 V, 1.5 V p-p Composite at Output, Bypass Mode, 500 MHz Tones –85 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 Figure 48. IMD3 vs. VGN2 over Supply and Temperature, VGN1 = 1.5 V, 1.5 V p-p Composite at Output, 720 MHz Filter Corner 14830-346 IMD2 (dBc) –75 –85 –100 IMD2 (dBc) –70 –85 14830-345 IMD2 (dBc) –65 –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V –55 14830-348 –55 –50 –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V 14830-349 UPPER TONE LOWER TONE 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VGN1 (V) 14830-350 –50 ADRF6520 Figure 50. IMD3 vs. VGN1 over Supply and Temperature, VGN2 = 0 V, 1.5 V p-p Composite at Output, Bypass Mode, 1 GHz Tones Rev. 0 | Page 15 of 29 ADRF6520 Data Sheet –50 –50 –55 –60 –60 –65 –65 –70 –70 IMD3 (dBc) –55 –75 –80 –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V –95 –85 –90 –95 –100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VGN2 (V) –100 0 VGN2 (V) –50 –55 –55 –60 –60 –65 –65 –70 –70 IMD3 (dBc) –50 –75 –80 –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V –85 –90 –95 –75 –80 –90 –95 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VGN2 (V) Figure 52. IMD2 vs. VGN2 over Supply and Temperature, VGN1 = 1.5 V, 1.5 V p-p Composite at Output, Bypass Mode, 1 GHz Tones, Low Tone Measured –100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VGN2 (V) Figure 55. IMD3 vs. VGN2 over Supply and Temperature, VGN1 = 1.5 V, 1.5 V p-p Composite at Output, Bypass Mode, 1 GHz Tones 75 75 –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V 65 60 55 50 65 60 40 35 30 IIP3 50 45 40 35 30 20 15 15 10 10 0.6 0.7 0.8 0.9 1.0 VGN1 (V) 1.1 1.2 1.3 1.4 1.5 5 0.3 14830-353 0.5 IIP3 25 20 0.4 IIP2 55 45 25 –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V 70 IIP2, IIP3 (dBm) IIP2 70 5 0.3 –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V –85 –100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 Figure 54. IMD3 vs. VGN2 over Supply and Temperature, VGN1 = 1.5 V, 1.5 V p-p Composite at Output, Bypass Mode, 500 MHz Tones 14830-352 IMD2 (dBc) Figure 51. IMD2 vs. VGN2 over Supply and Temperature, VGN1 = 1.5 V, 1.5 V p-p Composite at Output, Bypass Mode, 500 MHz Tones IIP2, IIP3 (dBm) –80 Figure 53. Input IP2 (IIP2), Input IP3 (IIP3) vs. VGN1, VGN2 = 0 V, Bypass Mode, 500 MHz Tones 14830-354 –90 –75 14830-355 LOWER TONE –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VGN1 (V) 1.1 1.2 1.3 1.4 1.5 14830-356 –85 14830-351 IMD2 (dBc) UPPER TONE Figure 56. IIP2, IIP3 vs. VGN1, VGN2 = 0 V, Bypass Mode, 1 GHz Tones Rev. 0 | Page 16 of 29 Data Sheet ADRF6520 100 90 36MHz FILTER IIP3 720MHz FILTER IIP3 45 80 OUT OF BAND INPUT IP3 (dBm) 70 60 50 40 30 20 40 35 30 25 20 15 10 10 5 –5 0 5 10 15 20 25 ABSOLUTE GAIN (dB) 30 35 40 0 –10 14830-357 0 –10 Figure 57. Out of Band IIP2, IMD2 for 36 MHz and 720 MHz –5 0 5 10 15 20 25 ABSOLUTE GAIN (dB) 30 35 40 14830-360 OUT OF BAND INPUT IP2 (dBm) 50 36MHz FILTER IIP2 720MHz FILTER IIP2 Figure 60. Out of Band IIP3, IMD3 for 36 MHz and 720 MHz 70 0 –10 60 –20 50 –40 CMRR (dB) –50 –60 –70 40 30 20 –100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 DIFFERENITAL OUTPUT (V p-p COMPOSITE) 10 4.5 0 14830-358 –90 Figure 58. In Band IMD3 vs. Differential Output Voltage (V p-p Composite) over Gain, Bypass Mode at 500 MHz 1 VGN1 = 1.5V, VGN2 = 0V VGN1 = 0V, VGN2 = 0V VGN1 = 1.5V, VGN2 = 1.5V 0 100 200 300 400 500 600 700 800 900 1000 1100 FREQUENCY (MHz) Figure 61. Common-Mode Rejection Ratio (CMRR) vs. Frequency, Bypass Mode CH2 500mV CH4 500mV M2.00µs 14830-202 1 CH2 500mV Figure 59. VGA1 Gain Step Response CH4 500mV M2.00µs Figure 62. VGA2 Gain Step Response; C9 and C16 = Open Rev. 0 | Page 17 of 29 14830-201 GAIN = +53dB GAIN = +40dB GAIN = +25dB GAIN = +10dB GAIN = –7dB –80 14830-203 IMD3 (dBc) –30 ADRF6520 1.0 +85°C +25°C –40°C +85°C, 3.15V +85°C, 3.3V +85°C, 3.45V +25°C, 3.15V +25°C, 3.3V +25°C, 3.45V –40°C, 3.15V –40°C, 3.3V –40°C, 3.45V 0.9 VRMS DETECTOR OUTPUT (V) VRMS DETECTOR OUTPUT (V) 10 Data Sheet 1 0.1 0.8 0.7 0.6 0.5 0.4 0.3 0.2 –45 –40 –35 –30 –25 –20 –15 INPUT POWER (dBm) –10 –5 0 5 0 14830-042 0.01 –50 Figure 63. Detector Output vs. Input Power (PIN) over Temperature, VGN1 = 1.5 V, VGN2 = 0 V, Both Inputs Driven to Same Amplitude 0 0.5 1.0 1.5 OUTPUT SIGNAL LEVEL (V p-p) 2.0 2.5 14830-032 0.1 Figure 64. Detector Output Voltage vs. Output Signal Level (V p-p) over Supply and Temperature, VGN1 = 1.5 V, VGN2 = 0 V, Both Inputs Driven to Same Amplitude Rev. 0 | Page 18 of 29 Data Sheet ADRF6520 THEORY OF OPERATION 30dB VVA BASEBAND INPUTS 36MHz TO 720MHz PROGRAMMABLE FILTERS 30dB VVA 6dB 18dB 12dB 18dB BASEBAND OUTPUTS ANALOG GAIN CONTROL 30mV/dB SPI INTERFACE 14830-050 FILTER, CHIP ENABLE, AND DC OFFSET LOOP PROGRAMMING SPI BUS Figure 65. Signal Path Block Diagram for a Single Channel of the ADRF6520 The ADRF6520 consists of a matched pair of input VGAs followed by programmable filters, 6 dB fixed gain amplifiers, and finally another matched pair of variable gain amplifiers and output ADC drivers. The filters can be bypassed and powered down through the SPI interface for operation beyond the maximum filter bandwidth. The block diagram of a single channel is shown in Figure 65. The programmability of the filter bandwidth through the SPI offers great flexibility when coping with signals in the presence of noise and large, undesired signals near the desired band. The entire differential signal chain is dc-coupled. The bandwidth and gain setting controls for the two channels are shared, ensuring close matching of their magnitude and phase responses. The ADRF6520 can be fully disabled through the ENBL pin or the enable bit in the SPI register. Filtering and amplification are fundamental operations in any signal processing system. Filtering is necessary to select the intended signal while rejecting out of band noise and interferers. Amplification increases the level of the desired signal to overcome noise added by the system. When used together, filtering and amplification can extract a low level signal of interest in the presence of noise and out of band interferers. Such analog signal processing alleviates the requirements on the analog, mixed signal, and digital components that follow. RMS DETECTOR To measure the signal level at the critical interface of the VGA1 output and the programmable filter input, an rms detector was implemented. The rms detector simultaneously measures both channels at the VGA1 output and reports the sum of the two at the VRMS pin. On-chip averaging capacitors set the minimum settling time for the VRMS voltage to roughly 50 ns for most of the signal measurement range. The on-chip capacitors can be augmented by placing capacitors between the CFLT1 and CFLT2 pins and VPS. Off-chip capacitors are needed in most cases to obtain an accurate rms measurement of the input signal, as well as to reduce the modulation ripple in the VRMS output voltage. The rms detector responds in a linear in volts manner, with the VRMS voltage representing the rms value of the input signal with the following relationship at maximum VGA1 gain: VRMS = k × [RMS(ch1 input) + RMS(ch2 input)] where RMS(x) is the root mean square value, and it is assumed that sufficiently large filtering capacitors are chosen to allow averaging of the modulation content. The previous relationship applies at maximum VGA1 gain only. When VGA1 gain is reduced, the VRMS output voltage also decreases proportionately. Relating VRMS, the gain of VGA1 and the summation of the rms values of the channel inputs is VRMS = 1(V/VRMS)(VGA1 Linear Voltage Gain)(RMS(ch1 input) + RMS(ch2 input)) INPUT VGAs The input VGAs are designed to have low noise and high linearity. The VGAs have a differential input impedance of 100 Ω, maximum gain of 18 dB, and minimum gain of −12 dB, providing a 30 dB gain range. They are designed to drive the filters with up to 1.5 V p-p of undesired signal or 0.75 V p-p of desired signal, or a combination of both. The input to the ADRF6520 must be ac-coupled. The topology of the input VGA is such that its noise figure (NF) degrades dB for dB as its gain is reduced, although its high linearity is maintained across its full input range. The input VGA can drive up to 3 V p-p at its output; however, it is recommended that the VGA be kept to the aforementioned limits to avoid overdriving the filter or 6 dB fixed gain amplifier. For example, if VGA1 is at its maximum gain of 18 dB, the equation reduces down to VRMS = 8(V/VRMS)(RMS(ch1 input) + RMS(ch2 input)) And at the VGA1 minimum gain of −12 dB, the equation reduces down to Rev. 0 | Page 19 of 29 VRMS = 0.25(V/VRMS) × (RMS(ch1 input) + RMS(ch2 input)) ADRF6520 Data Sheet Therefore, for the example of CFLTx = 0 (no external capacitor), the settling time is 50 ns; and if CFLTx = 1 nF, the settling time is 550 ns. Note that this is the 90% settling time of the rms detector. There is a slight dependency on input power level, wherein larger input signals to the rms detector cause it to settle more quickly. Also, the settling time varies with temperature. The simple equation, shown previously, is given for guidance so that the user can set the settling times within an order of magnitude of where they want it to be. If settling time is important, some experimentation by the user is necessary to optimize the CFLTx value for their system. –20 –40 –60 –80 –100 –120 –140 –160 1M 10M 100M 1G 10G Figure 66. Ideal Fourth-Order Butterworth Magnitude Response for All 1 dB Bandwidths Programmed 18 36MHz 72MHz 144MHz 288MHz 432MHz 576MHz 720MHz 16 PROGRAMMABLE FILTERS The filters are designed so that the gain and phase responses vs. frequency are retained for any bandwidth setting. Figure 66 and Figure 67 illustrate the ideal four-pole Butterworth response. The group delay, τG, is defined as τG = −∂φ/∂ω where: φ is the phase in radians. ω = 2πf is the frequency in radians per second. Note that for a frequency scaled filter prototype, the absolute magnitude of the group delay scales inversely with the bandwidth; however, the shape is retained. For example, the peak group delay for a 36 MHz bandwidth setting is 20× more than for a 720 MHz setting. The corner frequency of the filters is defined by the on-chip RC product, which can vary by ±20% over manufacturing variations. Therefore, all the devices are factory calibrated for corner frequency, resulting in a residual ±8% corner frequency variation over the −40°C to +85°C temperature range. Although absolute accuracy requires calibration, the matching of RC products between the pair of channels is better than 1% by observing careful design and layout practices. Calibration and excellent matching ensure that the magnitude and group delay responses of both channels track together, a critical requirement for digital IQ-based communication systems. GROUP DELAY (ns) 14 The integrated programmable filter is the key signal processing function in the ADRF6520. The filters follow a four-pole Butterworth type response that provides minimum in-band ripple and group delay variation, and good out of band rejection. The −1 dB bandwidth is programmed from 36 MHz to 720 MHz in six steps via the SPI, as described in the Programming the ADRF6520 section. The quoted corner frequency is the −1 dB point; the ADRF6520 has filter corners at 36 MHz, 72 MHz, 144 MHz, 288 MHz, 432 MHz, 576 MHz, and 720 MHz. 100G FREQUENCY (Hz) 14830-051 where CFLTx is either the external CFLT1 value or CFLT2 value. 36MHz 72MHz 144MHz 288MHz 432MHz 576MHz 720MHz 0 12 10 8 6 4 2 0 1M 10M 100M 1G FREQUENCY (Hz) 10G 100G 14830-052 τ (sec) = 500 Ω × (100 pF + CFLTx) 20 RELATIVE MAGNITUDE (dB) The RC time constant that, to a first order, dictates the rise and fall times of the rms output is expressed with the following equation: Figure 67. Ideal Fourth-Order Butterworth Group Delay Response for All 1 dB Bandwidths Programmed Bypassing the Filters For bandwidth applications greater than 720 MHz, the filters of the ADRF6520 can be bypassed via the SPI. In filter bypass mode, filters are disabled and power consumption is significantly reduced. The bandwidth of cascaded VGAs is fully realized in the filter bypass mode. VARIABLE GAIN AMPLIFIERS The second VGA, VGA2, is based on the same architecture as the input VGA, with 12 dB maximum gain and minimum gain of −18 dB, providing a 30 dB gain range controlled with a separate high impedance gain control input, the VGN2 pin. The basic VGA structure of the second VGA is identical to that of the first VGA. However, the VGA2 details vary slightly from VGA1 to produce a higher noise figure. OUTPUT BUFFERS/ADC DRIVERS The low impedance (50 dBc IMD3. The output common-mode of the ADC driver is set internally to mid supply and cannot be Rev. 0 | Page 20 of 29 Data Sheet ADRF6520 adjusted. If the circuit must be dc-coupled, it must be coupled to a subsequent stage with matching common mode. However, if common-mode matching is not possible, take care to limit the dc common-mode current that is used to shift the common mode, or else poor linearity results are observed. DC OFFSET COMPENSATION LOOP In many signal processing applications, no information is carried in the dc level. In fact, dc voltages and other low frequency disturbances can often dominate the intended signal and consume precious dynamic range in the analog path and bits in the data converters. These dc voltages can be present with the desired input signal or can be generated inside the signal path by inherent dc offsets or other unintended signaldependent processes such as self mixing or rectification. It is recommended to use ac coupling capacitors at the input and output terminals of the ADRF6520. The ac coupling capacitors at the input block any dc offset from the input getting into the device. The coupling capacitors must be sufficiently large, because they form a high pass filter with the100 Ω differential input impedance plus any source impedance of the driving circuit. The high-pass corners may need to be