300 MHz to 2500 MHz Rx Mixer with
Integrated Fractional-N PLL and VCO
ADRF6601
Data Sheet
FEATURES
The PLL can support input reference frequencies from 12 MHz
to 160 MHz. The PFD output controls a charge pump whose
output drives an off-chip loop filter.
Rx mixer with integrated fractional-N PLL
RF input frequency range: 300 MHz to 2500 MHz
Internal LO frequency range: 750 MHz to 1160 MHz
Input P1dB: 14.5 dBm
Input IP3: 31 dBm
IIP3 optimization via external pin
SSB noise figure
IP3SET pin open: 13.5 dB
IP3SET pin at 3.3 V: 14.6 dB
Voltage conversion gain: 6.7 dB
Matched 200 Ω IF output impedance
IF 3 dB bandwidth: 500 MHz
Programmable via 3-wire SPI interface
40-lead, 6 mm × 6 mm LFCSP
The loop filter output is then applied to an integrated VCO. The
VCO output at 2 × fLO is applied to an LO divider, as well as to a
programmable PLL divider. The programmable PLL divider is
controlled by a sigma-delta (Σ-Δ) modulator (SDM). The modulus
of the SDM can be programmed from 1 to 2047.
The active mixer converts the single-ended 50 Ω RF input to
a 200 Ω differential IF output. The IF output can operate up
to 500 MHz.
The ADRF6601 is fabricated using an advanced silicon-germanium
BiCMOS process. It is available in a 40-lead, RoHS-compliant,
6 mm × 6 mm LFCSP with an exposed paddle. Performance is
specified over the −40°C to +85°C temperature range.
APPLICATIONS
Table 1.
Cellular base stations
GENERAL DESCRIPTION
Part No.
ADRF6601
The ADRF6601 is a high dynamic range active mixer with an
integrated phase-locked loop (PLL) and a voltage controlled
oscillator (VCO). The PLL/synthesizer uses a fractional-N
PLL to generate a fLO input to the mixer. The reference input
can be divided or multiplied and then applied to the PLL phase
frequency detector (PFD).
ADRF6602
ADRF6603
ADRF6604
Internal LO
Range
750 MHz
1160 MHz
1550 MHz
2150 MHz
2100 MHz
2600 MHz
2500 MHz
2900 MHz
±3 dB RFIN
Balun Range
300 MHz
2500 MHz
1000 MHz
3100 MHz
1100 MHz
3200 MHz
1200 MHz
3600 MHz
±1 dB RFIN
Balun Range
450 MHz
1600 MHz
1350 MHz
2750 MHz
1450 MHz
2850 MHz
1600 MHz
3200 MHz
FUNCTIONAL BLOCK DIAGRAM
VCC1
VCC2
VCC_LO
VCC_MIX
VCC_V2I
VCC_LO
1
10
17
22
27
34
NC NC
32
33
ADRF6601
INTERNAL LO RANGE
750MHz TO 1160MHz
LODRV_EN 36
LON 37
BUFFER
LOP 38
BUFFER
PLL_EN 16
CLK 13
SPI
INTERFACE
LE 14
2:1
MUX
INTEGER
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
×2
REF_IN 6
÷2
÷4
N COUNTER
21 TO 123
MUX
TEMP
SENSOR
7
VCO
CORE
PRESCALER
÷2
DECL3P3
9
DECL2P5
VCO
LDO
40
DECLVCO
26
RFIN
29
IP3SET
CHARGE PUMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
–
PHASE
+ FREQUENCY
DETECTOR
MUXOUT 8
4
DIV
BY
4, 2, 1
2
2.5V
LDO
11 15 20 21 23 24 25 28 30 31 35
5
RSET
GND
3
39
CP VTUNE
18 19
IFP IFN
08546-001
FRACTION MODULUS
REG
DATA 12
3.3V
LDO
Figure 1.
Rev. B
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ADRF6601
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
RF Specifications .......................................................................... 3
Synthesizer/PLL Specifications ................................................... 4
Register 3—Σ-Δ Modulator Dither Control (Default:
0x10000B) .................................................................................... 17
Register 4—PLL Charge Pump, PFD, and Reference Path
Control (Default: 0x0AA7E4)................................................... 18
Register 5—PLL Enable and LO Path Control (Default:
0x0000E5) .................................................................................... 19
Register 6—VCO Control and VCO Enable (Default:
0x1E2106) .................................................................................... 19
Logic Input and Power Specifications ....................................... 4
Register 7—Mixer Bias Enable and External VCO Enable
(Default: 0x000007).................................................................... 19
Timing Characteristics ................................................................ 5
Theory of Operation ...................................................................... 20
Absolute Maximum Ratings ............................................................ 6
Programming the ADRF6601................................................... 20
ESD Caution .................................................................................. 6
Initialization Sequence .............................................................. 20
Pin Configuration and Function Descriptions ............................. 7
LO Selection Logic ..................................................................... 21
Typical Performance Characteristics ............................................. 9
Applications Information .............................................................. 22
RF Frequency Sweep .................................................................... 9
Basic Connections for Operation ............................................. 22
IF Frequency Sweep ................................................................... 10
AC Test Fixture ............................................................................... 23
Spurious Performance................................................................ 15
Evaluation Board ............................................................................ 24
Register Structure ........................................................................... 16
Evaluation Board Control Software ......................................... 24
Register 0—Integer Divide Control (Default: 0x0001C0) .... 16
Schematic and Artwork ............................................................. 26
Register 1—Modulus Divide Control (Default: 0x003001) ........ 16
Evaluation Board Configuration Options ............................... 28
Register 2—Fractional Divide Control (Default: 0x001802) ...... 17
Outline Dimensions ....................................................................... 29
Ordering Guide .......................................................................... 29
REVISION HISTORY
1/14—Rev. A to Rev. B
Replaced LO Range with RF Range in Data Sheet Title .............. 1
Updated Outline Dimensions ....................................................... 29
3/11—Rev. 0 to Rev. A
Changes to Features Section, General Description Section, and
Table 1 ............................................................................................ 1
Changes to Table 2 ............................................................................ 3
Changes to Conditions Statement and the Figure of Merit,
Reference Spurs, and Phase Noise Parameters, Table 3;
Changes to Conditions Statement and the Supply Current
Parameter, Table 4 ........................................................................ 4
Changes to Table 6 ............................................................................ 6
Changes to Table 7 ............................................................................ 7
Replaced Typical Performance Characteristics Section .............. 9
Added Spurious Performance Section ......................................... 15
Changes to Figure 44 and Figure 45............................................. 19
Changes to Theory of Operation Section .................................... 20
Added AC Test Fixture Section and Figure 47;
Renumbered Sequentially ......................................................... 23
Changes to Evaluation Board Control Software Section........... 24
Changes to Table 10 ........................................................................ 28
1/10—Revision 0: Initial Version
Rev. B | Page 2 of 32
Data Sheet
ADRF6601
SPECIFICATIONS
RF SPECIFICATIONS
VS = 5 V, ambient temperature (TA) = 25°C, fREF = 153.6 MHz, fPFD = 38.4 MHz, high-side LO injection, fIF = 140 MHz, IIP3 optimized
using CDAC = 0x0 and IP3SET = 3.3 V, unless otherwise noted.
Table 2.
Parameter
INTERNAL LO FREQUENCY RANGE
RF INPUT FREQUENCY RANGE
RF INPUT AT 610 MHz
Input Return Loss
Input P1dB
Second-Order Intercept (IIP2)
Third-Order Intercept (IIP3)
Single-Side Band Noise Figure
LO-to-IF Leakage
RF INPUT AT 910 MHz
Input Return Loss
Input P1dB
Second-Order Intercept (IIP2)
Third-Order Intercept (IIP3)
Single-Side Band Noise Figure
LO-to-IF Leakage
RF INPUT AT 1020 MHz
Input Return Loss
Input P1dB
Second-Order Intercept (IIP2)
Third-Order Intercept (IIP3)
Single-Side Band Noise Figure
LO-to-IF Leakage
IF OUTPUT
Voltage Conversion Gain
IF Bandwidth
Output Common-Mode Voltage
Gain Flatness
Gain Variation
Output Swing
Differential Output Return Loss
LO INPUT/OUTPUT (LOP, LON)
Frequency Range
Output Level (LO as Output)
Input Level (LO as Input)
Input Impedance
Test Conditions/Comments
±3 dB RF input range
Min
750
300
Relative to 50 Ω (can be improved with external match)
−5 dBm each tone (10 MHz spacing between tones)
−5 dBm each tone (10 MHz spacing between tones)
IP3SET = 3.3 V
IP3SET = open
At 1× LO frequency, 50 Ω termination at the RF port
Relative to 50 Ω (can be improved with external match)
−5 dBm each tone (10 MHz spacing between tones)
−5 dBm each tone (10 MHz spacing between tones)
IP3SET = 3.3 V
IP3SET = open
At 1× LO frequency, 50 Ω termination at the RF port
Relative to 50 Ω (can be improved with external match)
−5 dBm each tone (10 MHz spacing between tones)
−5 dBm each tone (10 MHz spacing between tones)
IP3SET = 3.3 V
IP3SET = open
At 1× LO frequency, 50 Ω termination at the RF port
Differential 200 Ω load
Small signal 3 dB bandwidth
External pull-up balun or inductors required
Over frequency range, any 5 MHz/50 MHz
Over full temperature range
Differential 200 Ω load
Measured through 4:1 balun
Externally applied 1× LO input, internal PLL disabled
Typ
−6
Rev. B | Page 3 of 32
Unit
MHz
MHz
−11.1
14.8
67.4
33.4
13.3
12.5
−55.5
dB
dBm
dBm
dBm
dB
dB
dBm
−16.7
14.5
55.3
30.9
14.6
13.5
−48
dB
dBm
dBm
dBm
dB
dB
dBm
−16.8
14.8
60.9
32.2
14.8
13.5
−49
dB
dBm
dBm
dBm
dB
dB
dBm
6.7
500
5
0.2/0.5
1.2
2
−15.5
dB
MHz
V
dB
dB
V p-p
dB
250
1× LO into a 50 Ω load, LO output buffer enabled
Max
1160
2500
6000
−6
0
50
+6
MHz
dBm
dBm
Ω
ADRF6601
Data Sheet
SYNTHESIZER/PLL SPECIFICATIONS
VS = 5 V, ambient temperature (TA) = 25°C, fREF = 153.6 MHz, fREF power = 4 dBm, fPFD = 38.4 MHz, high-side LO injection,
fIF = 140 MHz, IIP3 optimized using CDAC = 0x0 and IP3SET = 3.3 V, unless otherwise noted.
Table 3.
Parameter
SYNTHESIZER SPECIFICATIONS
Frequency Range
Figure of Merit 1
Reference Spurs
PHASE NOISE
Integrated Phase Noise
PFD Frequency
REFERENCE CHARACTERISTICS
REF_IN Input Frequency
REF_IN Input Capacitance
MUXOUT Output Level
MUXOUT Duty Cycle
CHARGE PUMP
Pump Current
Output Compliance Range
1
Test Conditions/Comments
Synthesizer specifications referenced to 1× LO
Internally generated LO
PREF_IN = 0 dBm
fPFD = 38.4 MHz
fPFD/4
fPFD
>fPFD
fLO = 750 MHz to 1160 MHz, fPFD = 38.4 MHz
1 kHz to 10 kHz offset
100 kHz offset
500 kHz offset
1 MHz offset
5 MHz offset
10 MHz offset
20 MHz offset
1 kHz to 40 MHz integration bandwidth
Min
Typ
Max
Unit
1160
−222
MHz
dBc/Hz/Hz
−107
−83
−88
dBc
dBc
dBc
−99
−108
−127
−135
−147
−151
−153
0.14
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
MHz
750
20
40
REF_IN, MUXOUT pins
12
160
4
VOL (lock detect output selected)
VOH (lock detect output selected)
0.25
2.7
50
Programmable to 250 µA, 500 µA, 750 µA, 1 mA
500
1
MHz
pF
V
V
%
µA
V
2.8
The figure of merit (FOM) is computed as phase noise (dBc/Hz) – 10 log 10(fPFD) – 20 log 10(fLO/fPFD). The FOM was measured across the full LO range with fREF = 80 MHz,
and fREF power = 10 dBm (500 V/µs slew rate) with a 40 MHz fPFD. The FOM was computed at 50 kHz offset.
LOGIC INPUT AND POWER SPECIFICATIONS
VS = 5 V, ambient temperature (TA) = 25°C, fREF = 153.6 MHz, fPFD = 38.4 MHz, high-side LO injection, fIF = 140 MHz, IIP3 optimized
using CDAC = 0x0 and IP3SET = 3.3 V, unless otherwise noted.
Table 4.
Parameter
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
POWER SUPPLIES
Voltage Range
Supply Current
Test Conditions/Comments
CLK, DATA, LE
Min
Typ
1.4
0
Max
Unit
3.3
0.7
V
V
µA
pF
5.25
V
mA
mA
mA
mA
mA
0.1
5
VCC1, VCC2, VCC_LO, VCC_MIX, and VCC_V2I pins
4.75
PLL only
External LO mode (internal PLL disabled, IP3SET pin = 3.3 V, LO output buffer off)
Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V, LO output buffer on)
Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V, LO output buffer off)
Power-down mode
Rev. B | Page 4 of 32
5
97
184
294
281
30
Data Sheet
ADRF6601
TIMING CHARACTERISTICS
VS = 5 V ± 5%.
Table 5.
Parameter
t1
t2
t3
t4
t5
t6
t7
Limit
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Description
LE setup time
DATA-to-CLK setup time
DATA-to-CLK hold time
CLK high duration
CLK low duration
CLK-to-LE setup time
LE pulse width
Timing Diagram
t4
t5
CLK
t2
DATA
DB23 (MSB)
t3
DB22
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
t1
DB0 (LSB)
(CONTROL BIT C1)
t7
08546-002
t6
LE
Figure 2. Timing Diagram
Rev. B | Page 5 of 32
ADRF6601
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Supply Voltage, VCC1, VCC2, VCC_LO,
VCC_MIX, VCC_V2I
Digital I/O, CLK, DATA, LE, LODRV_EN,
PLL_EN
VTUNE
IFP, IFN
RFIN
LOP, LON, REF_IN
θJA (Exposed Paddle Soldered Down)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Rating
−0.5 V to +5.5 V
−0.3 V to +3.6 V
0 V to 3.3 V
−0.3 V to VCC_V2I + 0.3 V
16 dBm
13 dBm
35°C/W
150°C
−40°C to +85°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. B | Page 6 of 32
Data Sheet
ADRF6601
40
39
38
37
36
35
34
33
32
31
DECLVCO
VTUNE
LOP
LON
LODRV_EN
GND
VCC_LO
NC
NC
GND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
ADRF6601
TOP VIEW
(Not to Scale)
30
29
28
27
26
25
24
23
22
21
GND
IP3SET
GND
VCC_V2I
RFIN
GND
GND
GND
VCC_MIX
GND
NOTES
1. NC = NO CONNECT. DO NOT CONNECT THIS PIN.
2. THE EXPOSED PADDLE SHOULD BE SOLDERED TO A
LOW IMPEDANCE GROUND PLANE.
08546-003
GND
DATA
CLK
LE
GND
PLL_EN
VCC_LO
IFP
IFN
GND
11
12
13
14
15
16
17
18
19
20
VCC1 1
DECL3P3 2
CP 3
GND 4
RSET 5
REF_IN 6
GND 7
MUXOUT 8
DECL2P5 9
VCC2 10
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1
Mnemonic
VCC1
2
3
4, 7, 11, 15, 20,
21, 23, 24, 25,
28, 30, 31, 35
5
DECL3P3
CP
GND
RSET
Description
Power Supply for the 3.3 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin
should be decoupled with a 100 pF capacitor and a 0.1 µF capacitor located close to the pin.
Decoupling Node for the 3.3 V LDO. Connect a 0.1 µF capacitor between this pin and ground.
Charge Pump Output Pin. Connect to VTUNE through the loop filter.
Ground. Connect these pins to a low impedance ground plane.
Charge Pump Current. The nominal charge pump current can be set to 250 µA, 500 µA, 750 µA, or 1 mA using
Bit DB11 and Bit DB10 in Register 4 and by setting Bit DB18 in Register 4 to 0 (internal reference current). In
this mode, no external RSET is required. If Bit DB18 is set to 1, the four nominal charge pump currents (INOMINAL)
can be externally adjusted according to the following equation:
217.4 × I CP
R SET =
I NOMINAL
6
REF_IN
8
MUXOUT
9
10
DECL2P5
VCC2
12
13
DATA
CLK
14
LE
16
PLL_EN
17, 34
VCC_LO
18, 19
IFP, IFN
− 37.8 Ω
Reference Input. Nominal input level is 1 V p-p. Input range is 12 MHz to 160 MHz. This pin is internally dcbiased and should be ac-coupled.
Multiplexer Output. This output can be programmed to provide the reference output signal or the lock detect
signal. The output is selected by programming the appropriate register.
Decoupling Node for the 2.5 V LDO. Connect a 0.1 µF capacitor between this pin and ground.
Power Supply for the 2.5 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin
should be decoupled with a 100 pF capacitor and a 0.1 µF capacitor located close to the pin.
Serial Data Input. The serial data input is loaded MSB first; the three LSBs are the control bits.
Serial Clock Input. The serial clock input is used to clock in the serial data to the registers. The data is latched
into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz.
Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one of the
eight registers. The relevant latch is selected by the three control bits of the 24-bit word.
PLL Enable. Switch between internal PLL and external LO input. When this pin is logic high, the mixer LO is
automatically switched to the internal PLL and the internal PLL is powered up. When this pin is logic low, the
internal PLL is powered down and the external LO input is routed to the mixer LO inputs. The SPI can also be
used to switch modes.
Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled
with a 100 pF capacitor and a 0.1 µF capacitor located close to the pin.
Mixer IF Outputs. These outputs should be pulled to VCC with RF chokes.
Rev. B | Page 7 of 32
ADRF6601
Data Sheet
Pin No.
22
Mnemonic
VCC_MIX
26
27
RFIN
VCC_V2I
29
32, 33
36
IP3SET
NC
LODRV_EN
37, 38
LON, LOP
39
VTUNE
40
DECLVCO
EPAD
Description
Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled
with a 100 pF capacitor and a 0.1 µF capacitor located close to the pin.
RF Input (single-ended, 50 Ω).
Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled
with a 100 pF capacitor and a 0.1 µF capacitor located close to the pin.
Connect a resistor from this pin to a 5 V supply to adjust IIP3. Normally leave open.
No Connection.
LO Driver Enable. Together with Pin 16 (PLL_EN), this digital input pin determines whether the LOP and LON
pins operate as inputs or outputs. LOP and LON become inputs if the PLL_EN pin is low or if the PLL_EN pin
is set high if the PLEN bit (DB6 in Register 5) is set to 0. LOP and LON become outputs if either the LODRV_EN pin
or the LDRV bit (DB3 in Register 5) is set to 1 while the PLL_EN pin is set high. The external LO drive frequency
must be 1× LO. This pin has an internal 100 kΩ pull-down resistor.
Local Oscillator Input/Output. The internally generated 1× LO is available on these pins. When internal LO
generation is disabled, an external 1× LO can be applied to these pins.
VCO Control Voltage Input. This pin is driven by the output of the loop filter. The nominal input voltage
range on this pin is 1.5 V to 2.5 V.
Decoupling Node for the VCO LDO. Connect a 100 pF capacitor and a 10 µF capacitor between this pin and
ground.
Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane.
Rev. B | Page 8 of 32
Data Sheet
ADRF6601
TYPICAL PERFORMANCE CHARACTERISTICS
RF FREQUENCY SWEEP
CDAC = 0x0, internally generated high-side LO, RFIN = −5 dBm, fIF = 140 MHz, unless otherwise noted.
5
4
45
IP3SET = OPEN
IP3SET = 3.3V
TA = +85°C
TA = +25°C
TA = –40°C
40
IP3SET = OPEN
IP3SET = 3.3V
3
35
INPUT IP3 (dBm)
1
0
–1
30
25
20
TA = +85°C
TA = +25°C
TA = –40°C
–2
15
–3
10
–4
660
710
760
810
860
910
960
1010
RF FREQUENCY (MHz)
5
610
08546-004
–5
610
660
760
810
860
910
960
1010
RF FREQUENCY (MHz)
Figure 7. Input IP3 vs. RF Frequency
Figure 4. Gain vs. RF Frequency
20
90
TA = +85°C
TA = +25°C
TA = –40°C
IP3SET = OPEN
IP3SET = 3.3V
80
18
IP3SET = OPEN
IP3SET = 3.3V
16
INPUT P1dB (dBm)
INPUT IP2 (dBm)
710
08546-007
GAIN (dB)
2
70
60
50
14
12
10
TA = +85°C
TA = +25°C
TA = –40°C
8
6
4
40
710
760
810
860
910
960
1010
RF FREQUENCY (MHz)
0
610
08546-005
660
IP3SET = OPEN
IP3SET = 3.3V
14
12
10
8
TA = +85°C
TA = +25°C
TA = –40°C
4
2
660
710
760
810
860
910
RF FREQUENCY (MHz)
960
1010
08546-006
NOISE FIGURE (dB)
16
0
610
760
810
860
910
Figure 8. Input P1dB vs. RF Frequency
20
6
710
RF FREQUENCY (MHz)
Figure 5. Input IP2 vs. RF Frequency
18
660
Figure 6. Noise Figure vs. RF Frequency
Rev. B | Page 9 of 32
960
1010
08546-008
2
30
610
ADRF6601
Data Sheet
IF FREQUENCY SWEEP
CDAC = 0x0, internally generated swept low-side LO, fRF = 1960 MHz, RFIN = −5 dBm, unless otherwise noted.
5
4
45
IP3SET = OPEN
IP3SET = 3.3V
TA = +85°C
TA = +25°C
TA = –40°C
40
IP3SET = OPEN
IP3SET = 3.3V
3
35
INPUT IP3 (dBm)
1
0
–1
30
25
20
TA = +85°C
TA = +25°C
TA = –40°C
–2
15
–3
10
–4
IF FREQUENCY (MHz)
5
25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400
08546-009
–5
25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400
IF FREQUENCY (MHz)
Figure 9. Gain vs. IF Frequency
Figure 12. Input IP3 vs. IF Frequency, RFIN = −5 dBm
90
20
IP3SET = OPEN
IP3SET = 3.3V
80
TA = +85°C
TA = +25°C
TA = –40°C
18
IP3SET = OPEN
IP3SET = 3.3V
16
70
INPUT P1dB (dBm)
INPUT IP2 (dBm)
08546-012
GAIN (dB)
2
60
50
14
12
10
8
TA = +85°C
TA = +25°C
TA = –40°C
6
4
40
IF FREQUENCY (MHz)
0
25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400
08546-010
30
25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400
IF FREQUENCY (MHz)
Figure 10. Input IP2 vs. IF Frequency, RFIN = −5 dBm
Figure 13. Input P1dB vs. IF Frequency
20
18
IP3SET = OPEN
IP3SET = 3.3V
14
12
10
8
TA = +85°C
TA = +25°C
TA = –40°C
6
4
2
0
25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400
IF FREQUENCY (MHz)
08546-011
NOISE FIGURE (dB)
16
Figure 11. Noise Figure vs. IF Frequency
Rev. B | Page 10 of 32
08546-013
2
Data Sheet
ADRF6601
0
0
–10
–5
–15
–10
–20
RETURN LOSS (dB)
LO-TO-IF FEEDTHROUGH (dBm)
TA = +85°C
TA = +25°C
TA = –40°C
IP3SET = OPEN
IP3SET = 3.3V
–5
–25
–30
–35
–40
–45
–50
–15
–20
–25
–30
–55
–60
–35
800
850
900
950
1000
1050
1100
1150
LO FREQUENCY (MHz)
–40
500
08546-014
–70
750
600
700
800
900
1000
1100
1200
1300
LO FREQUENCY (MHz)
Figure 14. LO-to-IF Feedthrough vs. LO Frequency,
LO Output Turned Off, CDAC = 0x0
Figure 17. LO Input Return Loss vs. LO Frequency (Including TC1-1-13 Balun)
–30
350
IP3SET = OPEN
IP3SET = 3.3V
TA = +85°C
TA = +25°C
TA = –40°C
–40
08546-017
–65
3.5
300
3.0
–70
2.5
200
2.0
150
100
1.0
50
0.5
–80
800
850
900
950
1000
1050
1100
1150
LO FREQUENCY (MHz)
0
50
08546-015
–90
750
1.5
CAPACITANCE
150
200
250
300
350
400
450
0
500
IF FREQUENCY (MHz)
Figure 15. LO-to-RF Leakage vs. LO Frequency, LO Output Turned Off
Figure 18. IF Differential Output Impedance (R Parallel C Equivalent)
0
35
IP3SET = OPEN
IP3SET = 3.3V
–5
30
NOISE FIGURE (dB)
–10
–15
–20
–25
25
20
–30
15
–40
500
600
700
800
900
1000
1100
1200
RF FREQUENCY (MHz)
1300
Figure 16. RF Input Return Loss vs. RF Frequency
10
–60
–50
–40
–30
–20
–10
CW BLOCKER LEVEL (dBm)
Figure 19. SSB Noise Figure vs. 5 MHz Offset Blocker Level,
LO Frequency = 1055 MHz, RF Frequency = 915 MHz
Rev. B | Page 11 of 32
0
08546-019
–35
08546-016
RETURN LOSS (dB)
100
CAPACITANCE (pF)
–60
250
08546-018
–50
RESISTANCE (Ω)
LO-RF LEAKAGE (dBm)
RESISTANCE
ADRF6601
Data Sheet
0
5.0
–10
TA = +85°C
TA = +25°C
TA = –40°C
4.5
–15
4.0
–20
3.5
VTUNE VOLTAGE (V)
–25
–30
–35
–40
–45
–50
–55
3.0
2.5
2.0
1.5
1.0
–60
0.5
–65
650
750
850
950
1050
1150
1250
1350
RF FREQUENCY (MHz)
0
750
08546-020
–70
550
800
900
950
1000
1050
1100
1150
LO FREQUENCY (MHz)
Figure 20. RF-to-IF Isolation vs. RF Frequency, High-Side LO, IF = 140 MHz,
LO Output Turned Off
Figure 23. VTUNE vs. LO Frequency
0
350
IP3SET = OPEN
IP3SET = 3.3V
–1
IP3SET = OPEN
IP3SET = 3.3V
TA = +85°C
TA = +25°C
TA = –40°C
–2
300
SUPPLY CURRENT (mA)
LO OUTPUT AMPLITUDE (dBm)
850
08546-023
RF-TO-IF ISOLATION (dBc)
TA = +85°C
TA = +25°C
TA = –40°C
IP3SET = OPEN
IP3SET = 3.3V
–5
–3
–4
–5
–6
–7
–8
250
200
TA = +85°C
TA = +25°C
TA = –40°C
150
850
900
950
1000
1050
1100
1150
LO FREQUENCY (MHz)
100
750
08546-021
800
850
900
950
1000
1050
1100
1150
LO FREQUENCY (MHz)
Figure 21. LO Output Amplitude vs. LO Frequency
Figure 24. Supply Current vs. LO Frequency
20
2.0
1.9
15
IP3SET = OPEN
IP3SET = 3.3V
1.8
VPTAT VOLTAGE (V)
10
5
0
–5
–10
1.6
1.5
1.4
1.3
1.1
0
50
100
150
TIME (µs)
200
250
1.0
–55
Figure 22. Frequency Deviation from 910 MHz vs. Time
(Demonstrates LO Frequency Settling Time from 920 MHz to 910 MHz)
–35
–15
5
25
45
TEMPERATURE (°C)
65
85
105
08546-025
–20
1.7
1.2
–15
08546-022
FREQUENCY DEVIATION FROM 920MHz (MHz)
800
08546-024
–9
–10
750
Figure 25. VPTAT Voltage vs. Temperature (IP3SET = Optimized, Open)
Rev. B | Page 12 of 32
Data Sheet
ADRF6601
Complementary cumulative distribution function (CCDF), fRF = 2140 MHz, fIF = 140 MHz.
100
IP3SET = OPEN
IP3SET = 3.3V
80
70
60
TA = +85°C
TA = +25°C
TA = –40°C
50
40
IP3SET = OPEN
IP3SET = 3.3V
90
DISTRIBUTION PERCENTAGE (%)
30
20
10
80
70
60
50
40
30
20
TA = +85°C
TA = +25°C
TA = –40°C
10
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
GAIN (dB)
0
24
08546-026
0
–2.0
26
28
36
38
40
100
DISTRIBUTION PERCENTAGE (%)
80
70
60
TA = +85°C
TA = +25°C
TA = –40°C
50
40
IP3SET = OPEN
IP3SET = 3.3V
90
30
20
10
80
70
60
50
40
30
20
TA = +85°C
TA = +25°C
TA = –40°C
10
55
60
65
70
75
80
INPUT IP2 (dBm)
0
10
08546-027
0
50
11
12
Figure 27. Input IP2
100
16
17
18
IP3SET = OPEN
IP3SET = 3.3V
DISTRIBUTION PERCENTAGE (%)
90
80
70
60
50
40
30
20
TA = +85°C
TA = +25°C
TA = –40°C
12
13
14
NOISE FIGURE (dB)
15
16
80
70
TA = +85°C
TA = +25°C
TA = –40°C
60
50
40
30
20
10
17
0
–90
08546-028
10
11
15
100
90
10
14
Figure 30. Input P1dB
IP3SET = OPEN
9
13
INPUT P1dB (dBm)
08546-030
IP3SET = OPEN
IP3SET = 3.3V
90
DISTRIBUTION PERCENTAGE (%)
34
Figure 29. Input IP3
100
DISTRIBUTION PERCENTAGE (%)
32
INPUT IP3 (dBm)
Figure 26. Gain
0
30
–80
–70
–60
–50
–40
LO FEEDTHROUGH (dBm)
Figure 28. Noise Figure
Figure 31. LO Feedthrough to IF, LO Output Turned Off
Rev. B | Page 13 of 32
–30
08546-031
DISTRIBUTION PERCENTAGE (%)
90
08546-029
100
ADRF6601
Data Sheet
Measured at IF output, CDAC = 0x0, IP3SET = open, internally generated high-side LO, fREF = 153.6 MHz, fPFD = 38.4 MHz,
RFIN = −5 dBm, fIF = 140 MHz, unless otherwise noted. Phase noise measurements made at LO output, unless otherwise noted.
–80
0.50
TA = +85°C
TA = +25°C
TA = –40°C
–100
–110
–120
LO FREQUENCY = 752MHz
–140
–150
0.35
0.30
0.25
0.20
0.15
0.10
100k
1M
10M
100M
OFFSET FREQUENCY (Hz)
0
750
08546-032
10k
TA = +85°C
TA = +25°C
TA = –40°C
PHASE NOISE (dBc/Hz)
SPURS LEVEL (dBc)
1000
–90
–95
–100
1100
1150
–110
–120
OFFSET = 100kHz
TA = +85°C
TA = +25°C
TA = –40°C
–130
–140
OFFSET = 5MHz
–150
850
900
950
1000
1050
1100
1150
–160
750
08546-033
800
LO FREQUENCY (MHz)
Figure 33. PLL Reference Spurs vs. LO Frequency (2× PFD and 4× PFD)
800
850
900
950
1000
OFFSET = 10kHz
PHASE NOISE (dBc/Hz)
–110
–95
–100
–115
–120
–125
–130
OFFSET = 1MHz
–135
–140
0.25× PFD
FREQUENCY
900
950
TA = +85°C
TA = +25°C
TA = –40°C
–145
1000
LO FREQUENCY (MHz)
1050
1100
1150
08546-034
850
1150
–105
–90
800
1100
Figure 36. Phase Noise vs. LO Frequency (1 kHz, 100 kHz, and 5 MHz Steps)
TA = +85°C
TA = +25°C
TA = –40°C
–85
–105
1050
LO FREQUENCY (MHz)
–100
OFFSET AT 3× PFD FREQUENCY
OFFSET AT 1× PFD FREQUENCY
–80
–110
750
1050
OFFSET = 1kHz
–100
–105
SPURS LEVEL (dBc)
950
–90
OFFSET AT 2× PFD FREQUENCY
OFFSET AT 4× PFD FREQUENCY
–85
–75
900
Figure 35. Integrated Phase Noise vs. LO Frequency
–80
–110
750
850
LO FREQUENCY (MHz)
Figure 32. Phase Noise vs. Offset Frequency
–75
800
08546-035
0.05
–160
1k
08546-036
–130
0.40
Figure 34. PLL Reference Spurs vs. LO Frequency (0.25× PFD, 1× PFD, and 3× PFD)
Rev. B | Page 14 of 32
–150
750
800
850
900
950
1000
1050
1100
1150
LO FREQUENCY (MHz)
Figure 37. Phase Noise vs. LO Frequency (10 kHz, 1 MHz Steps)
08546-037
PHASE NOISE (dBc/Hz)
LO FREQUENCY = 1155.2MHz
TA = +85°C
TA = +25°C
TA = –40°C
0.45
INTEGRATED PHASE NOISE (°rms)
–90
Data Sheet
ADRF6601
SPURIOUS PERFORMANCE
(N × fRF) − (M × fLO) spur measurements were made using the standard evaluation board (see the Evaluation Board section). Mixer spurious
products were measured in dB relative to the carrier (dBc) from the IF output power level. All spurious components greater than −125 dBc
are shown.
LO = 750 MHz, RF = 610 MHz (horizontal axis is m, vertical axis is n), and RFIN power = 0 dBm.
N
0
1
2
3
4
5
6
7
0
−115.74
−49.49
−48.77
−81.30
−83.02
−103.16
−110.88
−110.87
1
−63.28
0.0
−42.49
−71.27
−91.24
−111.19
−112.83
−108.26
M
2
−31.83
−64.58
−75.23
−103.32
−105.20
−114.25
−112.85
−112.91
3
−54.52
−24.09
−60.35
−73.13
−88.27
−108.4
−113.85
−111.93
4
−33.54
−71.52
−67.88
−110.05
−113.66
−115.31
−113.55
−113.64
LO = 1050 MHz, RF = 910 MHz (horizontal axis is m, vertical axis is n), and RFIN power = 0 dBm.
N
0
1
2
3
4
5
6
7
0
−113.23
−34.12
−49.76
−73.54
−102.66
−108.79
−110.79
1
−57.96
0.0
−47.19
−74.12
−110.29
−107.57
−108.34
−109.87
M
2
−27.78
−58.72
−57.30
−102.24
−100.07
−110.94
−107.38
−109.71
Rev. B | Page 15 of 32
3
−58.01
−27.14
−68.48
−72.99
−99.75
−110.16
−112.44
−108.58
4
−40.34
−84.94
−65.03
−108.62
−112.69
−115.35
−113.78
−110.01
ADRF6601
Data Sheet
REGISTER STRUCTURE
This section provides the register maps for the ADRF6601. The three LSBs determine the register that is programmed.
REGISTER 0—INTEGER DIVIDE CONTROL (DEFAULT: 0x0001C0)
DIVIDE
MODE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11
0
0
0
0
0
0
0
0
0
0
0
INTEGER DIVIDE RATIO
CONTROL BITS
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DM
ID6
ID5
ID4
ID3
ID2
ID1
ID0
C3(0) C2(0) C1(0)
0
0
DM
DIVIDE MODE
0
FRACTIONAL (DEFAULT)
1
INTEGER
DB1
ID6
ID5
ID4
ID3
ID2
ID1
ID0
INTEGER DIVIDE RATIO
0
0
1
0
1
0
1
21 (INTEGER MODE ONLY)
0
0
1
0
1
1
0
22 (INTEGER MODE ONLY)
0
0
1
0
1
1
1
23 (INTEGER MODE ONLY)
0
0
1
1
0
0
0
24
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
0
1
1
1
0
0
0
56 (DEFAULT)
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
1
1
1
0
1
1
1
119
1
1
1
1
0
0
0
120 (INTEGER MODE ONLY)
1
1
1
1
0
0
1
121 (INTEGER MODE ONLY)
1
1
1
1
0
1
0
122 (INTEGER MODE ONLY)
1
1
1
1
0
1
1
123 (INTEGER MODE ONLY)
DB0
08546-038
RESERVED
Figure 38. Register 0—Integer Divide Control Register Map
REGISTER 1—MODULUS DIVIDE CONTROL (DEFAULT: 0x003001)
MODULUS VALUE
0
0
0
0
0
0
0
0
0
0
CONTROL BITS
DB13
DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
MD10
MD9
MD6
MD5
MD4
MD3
MD2
MD1
MD0
C3(0) C2(0) C1(1)
MD8
MD7
DB1
DB0
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MODULUS VALUE
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
2
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
1
1
0
0
0
0
0
0
0
0
0
1536 (DEFAULT)
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
1
1
1
1
1
1
1
1
1
1
1
2047
Figure 39. Register 1—Modulus Divide Control Register Map
Rev. B | Page 16 of 32
08546-039
RESERVED
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14
Data Sheet
ADRF6601
REGISTER 2—FRACTIONAL DIVIDE CONTROL (DEFAULT: 0x001802)
RESERVED
0
0
0
0
0
FD10
FD9
FD8
FD7
DB9
DB8
DB7
DB6
DB5
DB4
DB3
FD6
FD5
FD4
FD3
FD2
FD1
FD0
DB2
DB1
DB0
C3(0) C2(1) C1(0)
0
0
FD10
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
FRACTIONAL VALUE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
0
1
1
0
0
0
0
0
0
0
0
768 (DEFAULT)
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
0
0
DB12 DB11 DB10
08546-040
0
CONTROL BITS
FRACTIONAL VALUE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13
...
100 ms, set the PLEN bit to 1 (Register 5,
Bit DB6).
After this procedure is complete, the other registers should
be programmed in the following order: Register 7, Register 6,
Register 4, Register 3, Register 2, Register 1. Then, after a delay
of >100 ms, Register 0 should be programmed.
Rev. B | Page 20 of 32
Data Sheet
ADRF6601
LO SELECTION LOGIC
The downconverting mixer in the ADRF6601 can be used
without the internal PLL by applying an external differential
LO to Pin 37 and Pin 38 (LON and LOP). In addition, when
using an LO generated by the internal PLL, the LO signal can
be accessed directly at these same pins. This function can be
used for debugging purposes, or the internally generated LO
can be used as the LO for a separate mixer.
The operation of the LO generation and whether LOP and LON
are inputs or outputs are determined by the logic levels applied
at Pin 16 (PLL_EN) and Pin 36 (LODRV_EN), as well as Bit DB3
(LDRV) and Bit DB6 (PLEN) in Register 5. The combination of
externally applied logic and internal bits required for particular
LO functions is given in Table 9.
Table 9. LO Selection Logic
Pin 16 (PLL_EN)
0
0
1
1
1
1
1
Pins 1
Pin 36 (LODRV_EN)
X
X
X
0
X
1
Register 5 Bits1
Bit DB6 (PLEN)
Bit DB3 (LDRV)
0
X
1
X
0
X
1
0
1
1
1
X
X = don’t care.
Rev. B | Page 21 of 32
Output Buffer
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Outputs
LO
External
External
External
Internal
Internal
Internal
ADRF6601
Data Sheet
APPLICATIONS INFORMATION
BASIC CONNECTIONS FOR OPERATION
be ac-coupled and terminated with a 50 Ω resistor as shown in
Figure 46. The reference signal, or a divided-down version of
the reference signal, can be brought back off chip at the multiplexer
output pin (MUXOUT). A lock detect signal and a voltage
proportional to the ambient temperature can also be selected
on the multiplexer output pin.
Figure 46 shows the schematic for the ADRF6601 evaluation
board. The six power supply pins should be individually decoupled
using 100 pF and 0.1 µF capacitors located as close as possible
to the device. In addition, the internal decoupling nodes
(DECL3P3, DECL2P5, and DECLVCO) should be decoupled
with the capacitor values shown in Figure 46.
The loop filter is connected between the CP and VTUNE pins.
When connected in this way, the internal VCO is operational.
For information about the loop filter components, see the
Evaluation Board Configuration Options section.
The RF input is internally ac-coupled and needs no external
bias. The IF outputs are open collector, and a bias inductor is
required from these outputs to VCC.
Operation with an external VCO is also possible. In this case,
the loop filter components should be referred to ground. The
output of the loop filter is connected to the input voltage pin of
the external VCO. The output of the VCO is brought back into
the device on the LOP and LON pins, using a balun if necessary.
The reference frequency for the PLL should be from 12 MHz to
160 MHz and should be applied to the REF_IN pin, which should
1
2
3
4
5
VCC
R19
0Ω
R20 (0402)
0Ω
(0402)
R54
10kΩ
(0402)
S2
LO IN/OUT
LON
4
3
C19
0.1µF
(0402)
C9
0.1µF
(0402)
C33
OPEN
(0402)
R51
OPEN
(0402)
R6
0Ω
(0402)
C8
100pF
(0402)
R26
0Ω
(0402)
C24
100pF
(0402)
R25
0Ω
(0402)
C22
100pF
(0402)
R24
0Ω
(0402)
C21
100pF
(0402)
R17
0Ω
(0402)
C18
100pF
(0402)
R7
0Ω
(0402)
C10
100pF
(0402)
C32
OPEN
(0402)
R50
OPEN
(0402)
VCC_MIX
VCC_LO
22
27
VCC2
17
VCC1
10
1
T8
TC1-1-13+
REF_IN
R70
49.9Ω
(0402)
R16
0Ω
(0402)
12
14
DECL2P5
9
37
DIVIDER
÷2
BUFFER
BUFFER
FRACTION
REG
MODULUS
INTEGER
REG
2
DIV
BY
4, 2, 1
2:1
MUX
ADRF6601
26
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
×2
N COUNTER
21 TO 123
6
÷2
MUXOUT
13
C16
R18
100pF 0Ω
(0402) (0402)
C17
0.1µF
(0402)
C42
10µF
(0603)
DECL3P3
C12
R8
100pF 0Ω
(0402) (0402)
C11
0.1µF
(0402)
C41
OPEN
(0603)
SPI
INTERFACE
TEMP
SENSOR
8
4
7
11 15 20 21 23 24 25 38 30 31 35
RSET
R2
R37 OPEN
0Ω (0402)
(0402)
CP
TEST
POINT
(ORANGE)
R38
0Ω
(0402)
C14
22pF
(0603)
29
3
5
39
CP
R10
3.0kΩ
(0603)
C15
2.7nF
(1206)
C2
OPEN
(0402)
40
18
C13
6.8pF
(0603)
R1
0Ω
(0402)
VTUNE
C40
22pF
(0603)
1
2
R59
0Ω 3
(0402)
4
RFOUT
R43
0Ω
5 (0402)
C29
0.1µF
(0402)
R12
0Ω
(0402)
C1
100pF
(0402)
Figure 46. Basic Connections for Operation of the ADRF6601
Rev. B | Page 22 of 32
IFN
VCC
+5V
R63
OPEN
(0402)
C27
0.1µF
(0402)
19
VTUNE DECLVCO IFP
R62
0Ω
(0402)
RFIN
IP3SET
R27
0Ω
(0402)
R9 10kΩ R65 10kΩ
(0402)
(0402)
R11
OPEN
(0402)
C43
10µF
(0603)
R28
0Ω
(0402)
CHARGE PUMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
–
PHASE
+ FREQUENCY
DETECTOR
RFIN
VCO
CORE
PRESCALER
÷2
MUX
÷4
REFOUT
16
36
C6
1nF
(0402)
C31
1nF
(0402) REF_IN
CLK
VCC_V2I
LE
C20
0.1µF
(0402)
DATA
C23
0.1µF
(0402)
C5
1nF LOP 38
1 (0402)
5
R52
OPEN
(0402)
C25
0.1µF
(0402)
34
LODRV_EN
C34
OPEN
(0402)
C7
0.1µF
(0402)
PLL_EN
VCC_LO
R56
0Ω
(0402)
R36
0Ω
R30
(0402)
0Ω
(0402) R57
0Ω
(0402)
R35
0Ω
(0402)
R53
10kΩ
(0402)
VCC
RED
+5V
VCC1
RED
R55
OPEN
(0402)
S1
OPEN
P1
9-PIN
DSUB
9
8
7
6
08546-046
A peak-to-peak differential swing on RFIN of 1 V (0.353 V rms
for a sine wave input) results in an IF output power of 4.7 dBm.
Data Sheet
ADRF6601
AC TEST FIXTURE
the signal generation and measurement equipment. Figure 47
shows the typical ac test setup used in the characterization of
the ADRF6601.
Characterization data for the ADRF6601 was taken under very
strict test conditions. All possible techniques were used to
achieve optimum accuracy and to remove degrading effects of
ADRF6601 CHARACTERIZATION RACK DIAGRAM.
ALL INSTRUMENTS ARE CONTROLLED BY A LAB
COMPUTER VIA A USB TO GPIB CONTROLLER, DAISY
CHAINED TO EACH INDIVIDUAL INSTRUMENT.
RF1 AGILENT N5181A
HP 11636A
POWER DIVIDER
RF2 AGILENT N5181A
REF_IN AGILENT N5181A
RFIN
REF_IN
ADRF6601
EVALUATION BOARD
9-PIN CONTROLLER DSUB AND
10-PIN DC HEADER
IF_OUT
ROHDE & SCHWARTZ
FSEA30
AGILENT 34401A SET TO IDC
(SET FOR SUPPLY CURRENT)
GND VIA
10-PIN DC HEADER
5V dc VIA
10-PIN DC HEADER
3.3V dc VIA
10-PIN DC HEADER
AGILENT 34980A WITH THREE 34921 MODULES
AND ONE 34950 MODULE
AGILENT E3631A 25V SET TO
3.3V, 6V SET TO 5V.
RETURNS ARE
JUMPERED TOGETHER
Figure 47. ADRF6601 AC Test Setup
Rev. B | Page 23 of 32
08546-047
5V dc MEASURED FOR SUPPLY CURRENT
ADRF6601
Data Sheet
EVALUATION BOARD
Figure 50 shows the schematic of the RoHS-compliant evaluation
board for the ADRF6601. This board has four layers and was
designed using Rogers 4350 hybrid material to minimize high
frequency losses. FR4 material is also adequate if the design can
accept the slightly higher trace loss of this material.
This board connects to the PC using a standard USB cable with a
USB mini-connector at one end. An additional 25-pin male to 9-pin
female adapter is required to mate the EVAL-ADF4XXXZ-USB
board to the 9-pin D-Sub connector on the ADRF6601 evaluation
board.
The evaluation board is designed to operate using the internal
VCO of the device (the default configuration) or with an external
VCO. To use an external VCO, R62 and R12 should be removed.
Place 0 Ω resistors in R63 and R11. The input of the external
VCO should be connected to the VTUNE SMA connector, and
the external VCO output should be connected to the LO IN/OUT
SMA connector. In addition to these hardware changes, internal
register settings must also be changed to enable operation with
an external VCO (see the Register 6—VCO Control and VCO
Enable (Default: 0x1E2106) section).
Additional configuration options for the evaluation board are
described in Table 10.
EVALUATION BOARD CONTROL SOFTWARE
The evaluation board can be connected to the PC using a PC
USB port.
To connect the evaluation board to a USB port, a USB adapter board
(EVAL-ADF4XXXZ-USB) must be purchased from Analog Devices.
08546-053
Software to program the ADRF6601 is available for download
from the ADRF6601 product page under the Evaluation Boards
& Kits section. To install the software
1. Download and extract the zip file:
ADRF6x0x_3p0p0_XP_install.exe file.
2. Follow the instructions in the read me file.
Figure 48. Control Software Opening Menu
Figure 49 shows the main window of the control software with
the default settings displayed.
Rev. B | Page 24 of 32
ADRF6601
08546-049
Data Sheet
Figure 49. Main Window of the ADRF6601 Evaluation Board Software
Rev. B | Page 25 of 32
3P3V_LDO
100PF
AGND
0.1UF
AGND
AGND
AGND
REFIN
R70
49.9
AGND
AGND
OSC_3P3V
1000PF
C31
10PF
22000PF
C3
C4
0
OSC_3P3V
1
R15
C12
C11
10UF
0
R8
AGND
C41
3P3V1
1
AGND
C10
100PF
C9
0
R7
0.1UF
VCC4
1
VCC
0
C14
22PF
DNI
R11
0
R37
0
R16
AGND
2P5V_LDO
REFOUT
DNI
R49
VCO_LDO
1
VCC
AGND
C42
10UF
P1-1
C13
6.8PF
C18
100PF
AGND
C19
0.1UF
AGND
0
R17
AGND
AGND
VCC2
1
100PF
0.1UF
R2
1
R50
1K DNI
CLK
DNI
R72
R62
R63
100K
0
40
39
37
36
DATA
1
LE
34
R54
10K
32
31
26
AGND
C20
0.1UF
VCC_LO
VCC_LO1
1
C21
AGND
IP3SET
AGND
AGND
100PF
0
R24
E-PAD PAD
GNDRF 21
VCCBB 22
GNDRF 23
NC 24
RFRTN 25
RFIN
VCCRF 27
AGND
20
19
29
GNDRF 28
IP3SET
GNDRF 30
AGND
AGND
C7
VCC_LO
1
P1-T7
0.1UF
0
R6
4
2
AGND
C8
NC
5
100PF
T8
OUTPUT_EN
18
VCC
AGND
1
VCC5
R53
10K
33
17
3
2
AGND
100PF DNI
C34
AGND
100PF DNI
16
AGND
R56
10K
AGND
AGND
15
14
Z1
35
3
LO_EXTERN
P3-T7
1
P4-T7
P4-T7
AGND
AGND
LO
VCC
R58
DNI
VCC
AGND
L2
TBD
AGND
C23
DNI
C36
DNI
C35
0
0
R48
0
R47
VCC_BB1
1
VCC_BB
0.1UF
L1
TBD
0
VCC_LO
0
R32
IFP
AGND
IFN
AGND
VCC_BB
VCC
1
VCC
R68
AGND
0
R67
0 DNI
AGND
RFIN
VCC_RF
IP3SET
R28
AGND
C25
C22
VCC_RF
VCC_RF
1
0.1UF
R25
R29
VCC_BB
C24
AGND
0
R31
OUTPUT_EN
100PF
0
R26
AGND
100PF
AGND
TBD
R60
C27
TBD
0.1UF
R27
VCC_LO
IP3SET
1
0
R69
0
10UF
P3-T7
P3-T7
6
6A
5
5A
4
4A
SNS1
SNS
0
T7
R43
AGND
P4-T7
1
S2
R52
1K DNI
R51
1K DNI
13
C33
12
11
100PF DNI
C32
10 VCC
9 2P5_LDO
38
R55
10K
VCC1
1
VCC
C5
1NF
C6
1NF
8 REFOUT/LOCK
7 REFGND
6 REF_IN
5 RSET
4 GNDCP
3 CPOUT
2 3P3_LDO
1 VCC
0
P1
AGND
P1-1
1
R19
2
0
3
4
R30
5
0
P1-6
6
R57
7
0
R36
8
0
9
1
AMP745781-4
DIG_GND
22PF
C40
AGND
C16
0
R18
10K
R65
C17
2P5V
1
AGND
AGND
AGND
10UF
100PF
C1
AGND
C43
0
R1
R12
0.1UF
C2
R9
10K
2.7NF
C15
AGND
VCO_LDO
R10
R71
R38
DNI
0
3K
TBD
3
2
CP 1
Y1
R14
VCO_LDO
GNDDIG
AGND
VCO_IN
DATA
VCC_LO
VTUNE
OUTPUTEN
0
INBB
C28
R66
P1-6
LOP
R35
LON
0
CLK
1
GNDBB
S1
LE
VCO_LDO
VCC_SENSE
T3
AGND
OUT
VCC
AGND
VCC_SENSE
AGND
3P3V_LDO
2P5V_LDO
LO_EXTERN
4
1
1
LOEXTEN
GNDDIG
GND
R20
VCC_LO
0
R34
DNI
R44
AGND
0.1UF
C29
2
R33
IPBB
IFP
0
Rev. B | Page 26 of 32
GNDBB
Figure 50. Evaluation Board Schematic
IFN
GND
1
R59
0
J1 1
J1 2
J1 3
J1 4
J1 5
J1 6
J1 7
J1 8
J1 9
J1 10
GND1 GND2
1
1
AGND
AGND
VCC
6
TC4-1W
3
1
1A
2
2A
3
3A
08546-050
P1-T7
P1-T7
ADRF6601
Data Sheet
SCHEMATIC AND ARTWORK
0
ADRF6601
Figure 51. Evaluation Board Layout (Bottom)
08546-052
08546-051
Data Sheet
Figure 52. Evaluation Board Layout (Top)
Rev. B | Page 27 of 32
ADRF6601
Data Sheet
EVALUATION BOARD CONFIGURATION OPTIONS
Table 10.
Component
S1, R55, R56, R33
Description
LO select. Switch and resistors to ground the LODRV_EN pin. The LODRV_EN pin setting, in
combination with internal register settings, determines whether the LOP and LON pins
function as inputs or outputs (see the LO Selection Logic section for more information).
LO IN/OUT
SMA Connector
REFIN
SMA Connector
REFOUT
SMA Connector
LO input/output. An external 1× LO or 2× LO signal can be applied to this single-ended
input connector.
Reference input. The input reference frequency for the PLL is applied to this connector.
Input impedance is 50 Ω.
Multiplexer output. The REFOUT connector connects directly to the MUXOUT pin. The
on-board multiplexer can be programmed to bring out the following signals: REF_IN,
2× REF_IN, REF_IN/2, and REF_IN/4; temperature sensor output voltage; and lock detect
indicator.
Charge pump test point. The unfiltered charge pump signal can be probed at this test
point. Note that the CP pin should not be probed during critical measurements such as
phase noise.
Loop filter. Loop filter components.
CP Test Point
R37, C14, R9, R10,
C15, C13, R65, C40
R11, R12
R62, R63, VTUNE
SMA Connector
R2
RFIN SMA Connector
T3
Loop filter return. When the internal VCO is used, the loop filter components should be
returned to Pin 40 (DECLVCO) by installing a 0 Ω resistor in R12. When an external VCO is used,
the loop filter components can be returned to ground by installing a 0 Ω resistor in R11.
Internal vs. external VCO. When the internal VCO is enabled, the loop filter components are
connected directly to the VTUNE pin (Pin 39) by installing a 0 Ω resistor in R62. To use an
external VCO, R62 should be left open. A 0 Ω resistor should be installed in R63, and the
voltage input of the VCO should be connected to the VTUNE SMA connector. The output of
the VCO is brought back into the PLL via the LO IN/OUT SMA connector.
RSET pin. This pin is unused and should be left open.
RF input. The RF input signal should be applied to the RFIN SMA connector. The RF input of
the ADRF6601 is ac-coupled; therefore, no bias is necessary.
IF output. The differential IF output signals from the ADRF6601 (IFP and IFN) are converted
to a single-ended signal by T3.
Rev. B | Page 28 of 32
Default Condition/
Option Settings
S1 = R55 = open
(not installed),
R56 = R33 = 0 Ω,
LODRV_EN = 0 V
LO input
Lock detect
R12 = 0 Ω (0402),
R11 = open (0402)
R62 = 0 Ω (0402),
R63 = open (0402)
R2 = open (0402)
R3 = R23 = open (0402)
Data Sheet
ADRF6601
OUTLINE DIMENSIONS
6.10
6.00 SQ
5.90
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
31
30
0.50
BSC
10
21
20
TOP VIEW
1.00
0.85
0.80
SEATING
PLANE
12° MAX
0.50
0.40
0.30
0.80 MAX
0.65 TYP
0.30
0.23
0.18
4.25
4.10 SQ
3.95
EXPOSED
PAD
(BOTTOM VIEW)
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
11
0.20 MIN
4.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
06-01-2012-D
5.85
5.75 SQ
5.65
PIN 1
INDICATOR
40 1
Figure 53. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad
(CP-40-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADRF6601ACPZ-R7
ADRF6601-EVALZ
1
Temperature Range
−40°C to +85°C
Package Description
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Z = RoHS Compliant Part.
Rev. B | Page 29 of 32
Package Option
CP-40-1
ADRF6601
Data Sheet
NOTES
Rev. B | Page 30 of 32
Data Sheet
ADRF6601
NOTES
Rev. B | Page 31 of 32
ADRF6601
Data Sheet
NOTES
©2010–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08546-0-1/14(B)
Rev. B | Page 32 of 32
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