ADRF6603

2100 MHz to 2600 MHz Rx Mixer with Integrated Fractional-N PLL and VCO ADRF6603 FEATURES Rx mixer with integrated fractional-N PLL RF input frequency range: 1100 MHz to 3200 MHz Internal LO frequency range: 2100 MHz to 2600 MHz Input P1dB: 14.6 dBm Input IP3: 27 dBm Input IP3 optimization via external pin SSB noise figure IP3SET pin open: 14.2 dB IP3SET pin at 3.3 V: 15.2 dB Voltage conversion gain: 6.9 dB Matched 200 Ω IF output impedance IF 3 dB bandwidth: 500 MHz Programmable via 3-wire SPI interface 40-lead, 6 mm × 6 mm LFCSP Table 1. Part No. ADRF6602 ADRF6603 Internal LO Range 1550 MHz 2150 MHz 2100 MHz 2600 MHz ±3 dB RFIN Balun Range 1000 MHz 3100 MHz 1100 MHz 3200 MHz ±1 dB RFIN Balun Range 1350 MHz 2750 MHz 1450 MHz 2850 MHz The PLL reference input can support input frequencies from 12 MHz to 160 MHz. The PFD output controls a charge pump whose output drives an off-chip loop filter. The loop filter output is then applied to an integrated VCO. The VCO output at 2× fLO is applied to an LO divider, as well as to a programmable PLL divider. The programmable PLL divider is controlled by a sigma-delta modulator (SDM). The modulus of the SDM can be programmed from 1 to 2047. The active mixer converts the single-ended 50 Ω RF input to a 200 Ω differential IF output. The IF output can operate up to 500 MHz. The ADRF6603 is fabricated using an advanced silicon-germanium BiCMOS process. It is available in a 40-lead, RoHS-compliant, 6 mm × 6 mm LFCSP with an exposed paddle. Performance is specified over the −40°C to +85°C temperature range. APPLICATIONS Cellular base stations GENERAL DESCRIPTION The ADRF6603 is a high dynamic range active mixer with integrated fractional-N phase-locked loop (PLL) and voltagecontrolled oscillator (VCO) for internal mixer LO generation. Along with the ADRF6602, the ADRF6603 forms a family of integrated PLL/mixers that cover the frequency range of 2100 MHz to 2600 MHz. VCC1 1 FUNCTIONAL BLOCK DIAGRAM VCC2 10 VCC_LO 17 VCC_MIX 22 VCC_V2I 27 VCC_LO 34 NC NC 32 33 ADRF6603 LODRV_EN 36 LON 37 BUFFER INTERNAL LO RANGE 2100MHz TO 2600MHz 3.3V LDO 2.5V LDO 2 DECL3P3 DECL2P5 LOP 38 PLL_EN 16 DATA 12 CLK 13 LE 14 SPI INTERFACE FRACTION MODULUS REG THIRD-ORDER FRACTIONAL INTERPOLATOR ×2 REF_IN 6 ÷2 ÷4 MUXOUT 8 4 7 11 15 20 21 23 24 25 28 30 31 35 BUFFER 9 INTEGER REG 2:1 MUX DIV BY 2, 1 VCO LDO 40 DECLVCO 26 RF IN N COUNTER 21 TO 123 MUX TEMP SENSOR – PHASE + FREQUENCY DETECTOR PRESCALER ÷2 CHARGE PUMP 250µA, 500µA (DEFAULT), 750µA, 1000µA RSET VCO CORE 29 IP3SET GND CP VTUNE IFP IFN Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. 08547-001 5 3 39 18 19 ADRF6603 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 RF Specifications .......................................................................... 3 Synthesizer/PLL Specifications ................................................... 4 Logic Input and Power Specifications ....................................... 5 Timing Characteristics ................................................................ 5 Absolute Maximum Ratings............................................................ 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 9 Register Structure ........................................................................... 11 Register 0—Integer Divide Control (Default: 0x0001C0)..... 11 Register 1—Modulus Divide Control (Default: 0x003001) .. 11 Register 2—Fractional Divide Control (Default: 0x001802) 12 Register 3—Σ-Δ Modulator Dither Control (Default: 0x10000B) .................................................................................... 12 Register 4—PLL Charge Pump, PFD, and Reference Path Control (Default: 0x0AA7E4)................................................... 13 Register 5—PLL Enable and LO Path Control (Default: 0x0000E5) .................................................................................... 14 Register 6—VCO Control and VCO Enable (Default: 0x1E2106) .................................................................................... 14 Register 7—Mixer Bias Enable and External VCO Enable (Default: 0x000007).................................................................... 14 Theory of Operation ...................................................................... 15 Programming the ADRF6603................................................... 15 Initialization Sequence .............................................................. 15 LO Selection Logic ..................................................................... 16 Applications Information .............................................................. 17 Basic Connections for Operation ............................................. 17 Evaluation Board ............................................................................ 18 Evaluation Board Control Software ......................................... 18 Schematics and Artwork ........................................................... 20 Evaluation Board Configuration Options ............................... 22 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23 REVISION HISTORY 3/10—Revision 0: Initial Version Rev. 0 | Page 2 of 24 ADRF6603 SPECIFICATIONS RF SPECIFICATIONS VS = 5 V; ambient temperature (TA) = 25°C; fREF = 38.4 MHz; fPFD = 38.4 MHz; high-side LO injection; fIF = 140 MHz; IIP3 optimized using capacitor DAC (0x1) and IP3SET (3.3 V), unless otherwise noted. Table 2. Parameter INTERNAL LO FREQUENCY RANGE RF INPUT FREQUENCY RANGE RF INPUT AT 2140 MHz Input Return Loss Input P1dB Second-Order Intercept (IIP2) Third-Order Intercept (IIP3) Single-Side Band Noise Figure LO to IF Leakage RF INPUT AT 2400 MHz Input Return Loss Input P1dB Second-Order Intercept (IIP2) Third-Order Intercept (IIP3) Single-Side Band Noise Figure LO to IF Leakage RF INPUT AT 2650 MHz Input Return Loss Input P1dB Second-Order Intercept (IIP2) Third-Order Intercept (IIP3) Single-Side Band Noise Figure LO to IF Leakage IF OUTPUT Voltage Conversion Gain IF Bandwidth Output Common-Mode Voltage Gain Flatness Gain Variation Output Swing Output Return Loss LO INPUT/OUTPUT (LOP, LON) Frequency Range Output Level (LO as Output) Input Level (LO as Input) Input Impedance Test Conditions/Comments ±3 dB RF input range Relative to 50 Ω (can be improved with external match) −5 dBm each tone (10 MHz spacing between tones) −5 dBm each tone (10 MHz spacing between tones) IP3SET = 3.3 V IP3SET = open At 1× LO frequency, 50 Ω termination at the RF port Relative to 50 Ω (can be improved with external match) −5 dBm each tone (10 MHz spacing between tones) −5 dBm each tone (10 MHz spacing between tones) IP3SET = 3.3 V IP3SET = open At 1× LO frequency, 50 Ω termination at the RF port Low side Injection Relative to 50 Ω (can be improved with external match) −5 dBm each tone (10 MHz spacing between tones) −5 dBm each tone (10 MHz spacing between tones) IP3SET = 3.3 V IP3SET = open At 1× LO frequency, 50 Ω termination at the RF port Differential 200 Ω load Small-signal 3 dB bandwidth External pull-up balun or inductors required Over frequency range, any 5 MHz/50 MHz Over full temperature range Differential 200 Ω load Relative to 200 Ω Externally applied 1× LO input, internal PLL disabled 250 1× LO into a 50 Ω load, LO output buffer enabled −7 ±6 50 Min 2100 1100 Typ Max 2600 3200 Unit MHz MHz dB dBm dBm dBm dB dB dBm dB dBm dBm dBm dB dB dBm dB dBm dBm dBm dB dB dBm dB MHz V dB dB V p-p dB 6000 MHz dBm dBm Ω −27 14.6 56 28 15.2 14.5 −42 −16 14.6 55 27.7 15.3 14.2 −43 −11 14.6 54 28.0 15.3 14.2 −42.5 6.9 500 5 0.2/1.0 1.0 2 −14 Rev. 0 | Page 3 of 24 ADRF6603 SYNTHESIZER/PLL SPECIFICATIONS VS = 5 V; ambient temperature (TA) = 25°C; fREF = 153.6 MHz; fPFD = 38.4 MHz; high-side LO injection; fIF = 140 MHz; IIP3 optimized using capacitor DAC (0x1) and IP3SET (3.3 V), unless otherwise noted. Table 3. Parameter SYNTHESIZER SPECIFICATIONS Frequency Range Figure of Merit Reference Spurs Test Conditions/Comments Synthesizer specifications referenced to 1× LO Internally generated LO PREF_IN = 0 dBm fREF = 153.6 MHz fREF/4 fREF/2 fREF > fREF fLO = 2100 MHz to 2600 MHz, fPFD = 38.4 MHz 1 kHz to 10 kHz offset 100 kHz offset 500 kHz offset 1 MHz offset 5 MHz offset 10 MHz offset 20 MHz offset 1 kHz to 40 MHz integration bandwidth REF_IN, MUXOUT pins 12 4 VOL (lock detect output selected) VOH (lock detect output selected) 0.25 2.7 50 Programmable to 250 μA, 500 μA, 750 μA, 1 mA 1 500 2.8 160 MHz pF V V % μA V Min 2100 −222 −107 −107 −86 −83 −90 −99.5 −120 −128 −142 −148 −149 0.4 20 40 Typ Max 2600 Unit MHz dBc/Hz dBc dBc dBc dBc dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz °rms MHz PHASE NOISE Integrated Phase Noise PFD Frequency REFERENCE CHARACTERISTICS REF_IN Input Frequency REF_IN Input Capacitance MUXOUT Output Level MUXOUT Duty Cycle CHARGE PUMP Pump Current Output Compliance Range Rev. 0 | Page 4 of 24 ADRF6603 LOGIC INPUT AND POWER SPECIFICATIONS VS = 5 V; ambient temperature (TA) = 25°C; fREF = 38.4 MHz; fPFD = 38.4 MHz; high-side LO injection; fIF = 140 MHz; IIP3 optimized using capacitor DAC (0x1) and IP3SET (3.3 V), unless otherwise noted. Table 4. Parameter LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN POWER SUPPLIES Voltage Range Supply Current Test Conditions/Comments CLK, DATA, LE Min 1.4 0 0.1 5 VCC1, VCC2, VCC_LO, VCC_MIX, and VCC_V2I pins 4.75 PLL only External LO mode (internal PLL disabled, IP3SET pin = 3.3 V) Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V) Power-down mode 5 98 163 261 30 5.25 V mA mA mA mA Typ Max 3.3 0.7 Unit V V μA pF TIMING CHARACTERISTICS VCC2 = 5 V ± 5%. Table 5. Parameter t1 t2 t3 t4 t5 t6 t7 Limit 20 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min ns min Description LE setup time DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width Timing Diagram t4 CLK t5 t2 DATA DB23 (MSB) DB22 t3 DB2 (CONTROL BIT C3) DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t1 LE t6 t7 08547-002 Figure 2. Timing Diagram Rev. 0 | Page 5 of 24 ADRF6603 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Supply Voltage, VCC1, VCC2, VCC_LO, VCC_MIX, VCC_V2I Digital I/O, CLK, DATA, LE IFP, IFN RFIN θJA (Exposed Paddle Soldered Down) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating −0.5 V to +5.5 V −0.3 V to +3.6 V −0.3 V to VCC + 0.3 V 18 dBm 35°C/W 150°C −40°C to +85°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. 0 | Page 6 of 24 ADRF6603 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 40 39 38 37 36 35 34 33 32 31 DECLVCO VTUNE LOP LON LODRV_EN GND VCC_LO NC NC GND VCC1 1 DECL3P3 2 CP 3 GND 4 RSET 5 REF_IN 6 GND 7 MUXOUT 8 DECL2P5 9 VCC2 10 PIN 1 INDICATOR ADRF6603 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 GND IP3SET GND VCC_V2I RFIN GND GND GND VCC_MIX GND Figure 3. Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 2 3 4, 7, 11, 15, 20, 21, 23, 24, 25, 28, 30, 31, 35 5 Mnemonic VCC1 DECL3P3 CP GND Description Power Supply for the 3.3 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin. Decoupling Node for 3.3 V LDO. Connect a 0.1 μF capacitor between this pin and ground. Charge Pump Output Pin. Connect to VTUNE through the loop filter. Ground. Connect these pins to a low impedance ground plane. RSET Charge Pump Current. The nominal charge pump current can be set to 250 μA, 500 μA, 750 μA, or 1 mA using Bit DB11 and Bit DB10 in Register 4 and by setting Bit DB18 to 0 (internal reference current). In this mode, no external RSET is required. If Bit DB18 is set to 1, the four nominal charge pump currents (INOMINAL) can be externally adjusted according to the following equation: ⎛ 217.4 × I CP R SET = ⎜ ⎜I ⎝ NOMINAL 6 8 9 10 12 13 14 16 REF_IN MUXOUT DECL2P5 VCC2 DATA CLK LE PLL_EN ⎞ ⎟ − 37.8 Ω ⎟ ⎠ 17, 34 18, 19 22 26 VCC_LO IFP, IFN VCC_MIX RFIN Reference Input. Nominal input level is 1 V p-p. Input range is 12 MHz to 160 MHz. Multiplexer Output. This output can be programmed to provide the reference output signal or the lock detect signal. The output is selected by programming the appropriate register. Decoupling Node for 2.5 V LDO. Connect a 0.1 μF capacitor between this pin and ground. Power Supply for the 2.5 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin. Serial Data Input. The serial data input is loaded MSB first; the three LSBs are the control bits. Serial Clock Input. The serial clock input is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz. Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one of the eight registers. The relevant latch is selected by the three control bits of the 24-bit word. PLL Enable. Switch between internal PLL and external LO input. When this pin is logic high, the mixer LO is automatically switched to the internal PLL and the internal PLL is powered up. When this pin is logic low, the internal PLL is powered down and the external LO input is routed to the mixer LO inputs. The SPI can also be used to switch modes. Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin. Mixer IF Outputs. These outputs should be pulled to VCC with RF chokes. Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin. RF Input (Single-Ended, 50 Ω). Rev. 0 | Page 7 of 24 08547-003 NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PADDLE SHOULD BE SOLDERED TO A LOW IMPEDANCE GROUND PLANE. GND DATA CLK LE GND PLL_EN VCC_LO IFP IFN GND 11 12 13 14 15 16 17 18 19 20 ADRF6603 Pin No. 27 29 32, 33 36 Mnemonic VCC_V2I IP3SET NC LODRV_EN Description Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin. Connect a resistor from this pin to a +5 V supply to adjust IIP3. Normally leave open. No Connection. LO Driver Enable. Together with Pin 16 (PLL_EN), this digital input pin determines whether the LOP and LON pins operate as inputs or outputs. LOP and LON become inputs if the PLL_EN pin is low or if the PLL_EN pin is set high with the PLEN bit (DB6 in Register 5) set to 0. LOP and LON become outputs if either the LODRV_EN pin or the LDRV bit (DB3 in Register 5) is set to 1 while the PLL_EN pin is set high. The external LO drive frequency must be 1× LO. This pin should not be left floating. Local Oscillator Input/Output. The internally generated 1× LO is available on these pins. When internal LO generation is disabled, an external 1× LO can be applied to these pins. VCO Control Voltage Input. This pin is driven by the output of the loop filter. The nominal input voltage range on this pin is 1.5 V to 2.5 V. Decoupling Node for VCO LDO. Connect a 100 pF capacitor and a 10 μF capacitor between this pin and ground. Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane. 37, 38 39 40 EP LON, LOP VTUNE DECLVCO EPAD Rev. 0 | Page 8 of 24 ADRF6603 TYPICAL PERFORMANCE CHARACTERISTICS CDAC = 0x1, IP3SET = 3.3 V, internally generated LO, RFIN = −10 dBm, fIF = 140 MHz, unless otherwise noted. 5 4 3 2 –40°C +25°C +85°C 45 40 35 –40°C +25°C +85°C INPUT IP3 (dBm) 08547-014 GAIN (dB) 1 0 –1 –2 30 25 20 15 –3 –4 –5 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 LO FREQUENCY (MHz) 10 5 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 LO FREQUENCY (MHz) Figure 4. Gain vs. LO Frequency Figure 7. IIP3 vs. LO Frequency, RFIN = −5 dBm 90 –40°C +25°C +85°C INPUT P1dB (dBm) 20 18 16 14 12 10 8 6 4 2 08547-015 08547-018 80 –40°C +25°C +85°C INPUT IP2 (dBm) 70 60 50 40 30 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 LO FREQUENCY (MHz) 0 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 LO FREQUENCY (MHz) Figure 5. IIP2 vs. LO Frequency, RFIN = −5 dBm Figure 8. IP1dB vs. LO Frequency 20 0 18 –40°C +25°C +85°C LO FEEDTHROUGH AMPLITUDE (dBm) 19 –10 –40°C +25°C +85°C NOISE FIGURE (dB) 17 16 15 14 13 12 11 –20 –30 –40 –50 08547-016 LO FREQUENCY (MHz) LO FREQUENCY (MHz) Figure 6. Noise Figure vs. LO Frequency Figure 9. LO Feedthrough to IF vs. LO Frequency, LO Output Turned Off Rev. 0 | Page 9 of 24 08547-019 10 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 –60 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 08547-017 ADRF6603 Phase noise measurements made at IF output, unless otherwise noted. –80 –90 1kHz OFFSET 1.0 0.9 0.8 –80 –90 –100 –110 –120 –130 –140 –150 –160 1k LO LO LO LO LO LO = 2115.2MHz = 2211.2MHz = 2307.2MHz = 2403.2MHz = 2499.2MHz = 2595.2MHz –100 0.7 –110 –120 1MHz OFFSET 100kHz OFFSET 10kHz OFFSET INTEGRATED PHASE NOISE (°rms) SPOT PHASE NOISE (dBc/Hz) 0.6 0.5 0.4 0.3 0.2 –130 –140 –150 –160 2100 INTERGRATED PHASE NOISE 10MHz OFFSET 0.1 08547-020 10k 100k 1M 10M 100M LO FREQUENCY (MHz) OFFSET FREQUENCY (Hz) Figure 10. PLL Spot Phase Noise at Various Offsets and Integrated Phase Noise vs. LO Frequency Figure 12. Phase Noise vs. Offset Frequency and LO Frequency (LO Frequency Varies from 2100 MHz to 2600 MHz) –75 –80 –85 –90 1× PFD OFFSET 2× PFD OFFSET SPURS LEVEL (dBc) –95 –100 –105 –110 2100 4× PFD OFFSET 0.25× AND 0.5× PFD OFFSET 2200 2300 2400 2500 2600 LO FREQUENCY (MHz) Figure 11. PLL Reference Spurs vs. LO Frequency 08547-021 Rev. 0 | Page 10 of 24 08547-022 2200 2300 2400 2500 0 2600 PHASE NOISE (dBc/Hz) ADRF6603 REGISTER STRUCTURE This section provides the register maps for the ADRF6603. The three LSBs determine the register that is programmed. REGISTER 0—INTEGER DIVIDE CONTROL (DEFAULT: 0x0001C0) RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVIDE MODE DB10 DM DB9 ID6 INTEGER DIVIDE RATIO DB8 ID5 DB7 ID4 DB6 ID3 DB5 ID2 DB4 ID1 DB3 ID0 CONTROL BITS DB2 DB1 DB0 C3(0) C2(0) C1(0) DM 0 1 DIVIDE MODE FRACTIONAL (DEFAULT) INTEGER ID6 0 0 0 0 ... ... 0 ... ... 1 1 1 1 1 ID5 0 0 0 0 ... ... 1 ... ... 1 1 1 1 1 ID4 1 1 1 1 ... ... 1 ... ... 1 1 1 1 1 ID3 0 0 0 1 ... ... 1 ... ... 0 1 1 1 1 ID2 1 1 1 0 ... ... 0 ... ... 1 0 0 0 0 ID1 0 1 1 0 ... ... 0 ... ... 1 0 0 1 1 ID0 1 0 1 0 ... ... 0 ... ... 1 0 1 0 1 INTEGER DIVIDE RATIO 21 (INTEGER MODE ONLY) 22 (INTEGER MODE ONLY) 23 (INTEGER MODE ONLY) 24 ... ... 56 (DEFAULT) ... ... 119 120 (INTEGER MODE ONLY) 121 (INTEGER MODE ONLY) 08547-004 122 (INTEGER MODE ONLY) 123 (INTEGER MODE ONLY) Figure 13. Register 0—Integer Divide Control Register Map REGISTER 1—MODULUS DIVIDE CONTROL (DEFAULT: 0x003001) RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 0 0 0 0 0 0 0 0 0 0 MD10 DB12 DB11 DB10 MD9 MD8 MD7 MODULUS VALUE DB9 MD6 DB8 MD5 DB7 MD4 DB6 MD3 DB5 MD2 DB4 MD1 DB3 MD0 CONTROL BITS DB2 DB1 DB0 C3(0) C2(0) C1(1) MD10 0 0 ... ... 1 ... ... 1 MD9 0 0 ... ... 1 ... ... 1 MD8 0 0 ... ... 0 ... ... 1 MD7 0 0 ... ... 0 ... ... 1 MD6 0 0 ... ... 0 ... ... 1 MD5 0 0 ... ... 0 ... ... 1 MD4 0 0 ... ... 0 ... ... 1 MD3 0 0 ... ... 0 ... ... 1 MD2 0 0 ... ... 0 ... ... 1 MD1 0 1 ... ... 0 ... ... 1 MD0 1 0 ... ... 0 ... ... 1 MODULUS VALUE 1 2 ... ... 1536 (DEFAULT) ... ... 2047 08547-005 Figure 14. Register 1—Modulus Divide Control Register Map Rev. 0 | Page 11 of 24 ADRF6603 REGISTER 2—FRACTIONAL DIVIDE CONTROL (DEFAULT: 0x001802) RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 0 0 0 0 0 0 0 0 0 0 FD10 DB12 DB11 DB10 FD9 FD8 FD7 FRACTIONAL VALUE DB9 FD6 DB8 FD5 DB7 FD4 DB6 FD3 DB5 FD2 DB4 FD1 DB3 FD0 CONTROL BITS DB2 DB1 DB0 C3(0) C2(1) C1(0) FD10 0 0 ... ... 0 ... ... FD9 0 0 ... ... 1 ... ... FD8 0 0 ... ... 1 ... ... FD7 0 0 ... ... 0 ... ... FD6 0 0 ... ... 0 ... ... FD5 0 0 ... ... 0 ... ... FD4 0 0 ... ... 0 ... ... FD3 0 0 ... ... 0 ... ... FD2 0 0 ... ... 0 ... ... FD1 0 0 ... ... 0 ... ... FD0 0 1 ... ... 0 ... ... FRACTIONAL VALUE 0 1 ... ... 768 (DEFAULT) ... ... 100 ms, set the PLEN and LVEN bits to 1. PROGRAMMING THE ADRF6603 The ADRF6603 is programmed via a 3-pin SPI port. The timing requirements for the SPI port are shown in Figure 2. Eight programmable registers, each with 24 bits, control the operation of the device. The register functions are listed in Table 8. After this procedure, the other registers can be programmed, in order, from Register 7 to Register 3, and then from Register 0 to Register 2, as described in the Programming the ADRF6603 section. Rev. 0 | Page 15 of 24 ADRF6603 LO SELECTION LOGIC The downconverting mixer in the ADRF6603 can be used without the internal PLL by applying an external differential LO to Pin 37 and Pin 38 (LON and LOP). In addition, when using an LO generated by the internal PLL, the LO signal can be accessed directly at these same pins. This function can be used for debugging purposes, or the internally generated LO can be used as the LO for a separate mixer. Table 9. LO Selection Logic Pin 16 (PLL_EN) 0 0 1 1 1 1 1 The operation of the LO generation and whether LOP and LON are inputs or outputs are determined by the logic levels applied at Pin 16 (PLL_EN) and Pin 36 (LODRV_EN), as well as Bit DB3 (LDRV) and Bit DB6 (PLEN) in Register 5. The combination of externally applied logic and internal bits required for particular LO functions is given in Table 9. Pins1 Pin 36 (LODRV_EN) X X X 0 X 1 Register 5 Bits1 Bit DB6 (PLEN) Bit DB3 (LDRV) 0 X 1 X 0 X 1 0 1 1 1 X Output Buffer Disabled Disabled Disabled Disabled Enabled Enabled Outputs LO External External External Internal Internal Internal X = don’t care. Rev. 0 | Page 16 of 24 ADRF6603 APPLICATIONS INFORMATION BASIC CONNECTIONS FOR OPERATION Figure 21 shows the schematic for the ADRF6603 evaluation board. The six power supply pins should be individually decoupled using 100 pF and 0.1 μF capacitors located as close as possible to the device. In addition, the internal decoupling nodes (DECL3P3, DECL2P5, and DECLVCO) should be decoupled with the capacitor values shown in Figure 21. The RF input is internally ac-coupled and needs no external bias. The IF outputs are open collector, and a bias inductor is required from these outputs to VCC. A peak-to-peak differential swing on RFIN of 1 V (0.353 V rms for a sine wave input) results in an IF output power of 4.7 dBm. The reference frequency for the PLL should be from 12 MHz to 160 MHz and should be applied to the REF_IN pin, which should be ac-coupled and terminated with a 50 Ω resistor as VCC R43 10kΩ (0402) S2 VCC RED +5V C7 0.1µF (0402) VCC1 RED R39 OPEN (0402) S1 OPEN R40 0Ω (0402) LO IN/OUT R41 0Ω (0402) 4 5 3 R6 0Ω (0402) C8 100pF (0402) VCC_LO 34 shown in Figure 21. The reference signal, or a divided-down version of the reference signal, can be brought back off chip at the multiplexer output pin (MUXOUT). A lock detect signal and a voltage proportional to the ambient temperature can also be selected on the multiplexer output pin. The loop filter is connected between the CP and VTUNE pins. When connected in this way, the internal VCO is operational. For information about the loop filter components, see the Evaluation Board Configuration Options section. Operation with an external VCO is also possible. In this case, the loop filter components should be referred to ground. The output of the loop filter is connected to the input voltage pin of the external VCO. The output of the VCO is brought back into the device on the LOP and LON pins, using a balun if necessary. P1 9-PIN DSUB 1 2 3 4 5 6 7 8 9 R19 0Ω R20 (0402) 0Ω (0402) R35 0Ω (0402) R36 0Ω R30 (0402) 0Ω (0402) R48 0Ω (0402) C31 OPEN (0402) C32 OPEN (0402) C30 OPEN (0402) PLL_EN DATA R44 OPEN (0402) R45 OPEN (0402) R42 OPEN (0402) R47 10kΩ (0402) C27 0.1µF (0402) R27 0Ω (0402) C26 100pF (0402) VCC_MIX 27 22 C25 0.1µF (0402) R26 0Ω (0402) C24 100pF (0402) VCC_LO 17 C23 0.1µF (0402) R25 0Ω (0402) C22 100pF (0402) VCC2 10 C20 0.1µF (0402) R24 0Ω (0402) C21 100pF (0402) VCC1 1 C19 0.1µF (0402) R17 0Ω (0402) C18 100pF (0402) CLK VCC_V2I 16 13 12 LE 14 9 DECL2P5 C16 R18 100pF 0Ω (0402) (0402) DECL3P3 C12 R8 100pF 0Ω (0402) (0402) RFIN R22 0Ω (0402) IP3SET R27 0Ω (0402) C27 0.1µF (0402) C17 0.1µF (0402) C42 10µF (0603) LODRV_EN LON 36 37 BUFFER SPI INTERFACE DIVIDER ÷2 2:1 MUX DIV BY 2, 1 26 C5 1nF LOP 38 1 (0402) C6 1nF (0402) FRACTION REG MODULUS INTEGER REG 2 T8 TC1-1-13+ BUFFER C11 0.1µF (0402) C41 OPEN (0603) ADRF6603 THIRD-ORDER FRACTIONAL INTERPOLATOR ×2 6 RFIN REF_IN R73 49.9Ω (0402) REFOUT C13 1nF (0402) REF_IN N COUNTER 21 TO 123 MUX TEMP SENSOR 4 7 PRESCALER ÷2 CHARGE PUMP 250µA, 500µA (DEFAULT), 750µA, 1000µA VCO CORE ÷2 ÷4 MUXOUT 8 – PHASE + FREQUENCY DETECTOR 29 R16 0Ω (0402) 11 15 20 21 23 24 25 38 30 31 35 RSET R2 R37 OPEN 0Ω (0402) (0402) 5 3 39 40 18 19 CP VTUNE DECLVCO IFP R62 0Ω (0402) VTUNE R63 OPEN (0402) VCC +5V IFN 1 2 4 RFOUT CP TEST POINT (ORANGE) R38 0Ω (0402) C14 270pF (0603) R9 18kΩ R65 0Ω (0402) (0402) R10 1.6kΩ (0603) C15 5.6nF (1206) R11 OPEN (0402) R27 3 0Ω (0402) C29 0.1µF (0402) R43 0Ω 5 (0402) C13 27pF (0603) C40 OPEN (0603) R12 0Ω (0402) R1 0Ω (0402) C1 100pF (0402) C43 10µF (0603) C2 OPEN (0402) Figure 21. Basic Connections for Operation of the ADRF6603 Rev. 0 | Page 17 of 24 08547-024 ADRF6603 EVALUATION BOARD Figure 24 shows the schematic of the RoHS-compliant evaluation board for the ADRF6603. This board has four layers and was designed using Rogers 4350 hybrid material to minimize high frequency losses. FR4 material is also adequate if the design can accept the slightly higher trace loss of this material. The evaluation board is designed to operate using the internal VCO of the device (the default configuration) or with an external VCO. To use an external VCO, R62 and R12 should be removed. Place 0 Ω resistors in R63 and R11. The input of the external VCO should be connected to the VTUNE SMA connector, and the external VCO output should be connected to the LO IN/OUT SMA connector. In addition to these hardware changes, internal register settings must also be changed to enable operation with an external VCO (see the Register 6— VCO Control and VCO Enable (Default: 0x1E2106) section). Additional configuration options for the evaluation board are described in Table 10. EVALUATION BOARD CONTROL SOFTWARE Software to program the ADRF6603 is available for download from www.analog.com. To install the software, download and extract the zip file. Then run the following installation file: ADRF6x0x_3p0p0_XP_install.exe The evaluation board can be connected to the PC using a PC parallel port or a USB port. These options are selectable from the opening menu of the software interface (see Figure 22). The evaluation board is shipped with a 25-pin parallel port cable for connection to the PC parallel port. To connect the evaluation board to a USB port, a USB adapter board (Part No. EVAL-ADF4XXXZ-USB) must be purchased from www.analog.com. This board connects to the PC using a standard USB cable with USB mini-connector at one end. An additional 25-pin male to 9-pin female adapter is required to mate the ADF4XXXZ-USB board to the 9-pin D-Sub connector on the ADRF6603 evaluation board. Figure 22. Control Software Opening Menu Figure 23 shows the main menu of the control software with the default settings displayed. Rev. 0 | Page 18 of 24 08547-025 ADRF6603 Figure 23. Main Window of the ADRF6603 Evaluation Board Software Rev. 0 | Page 19 of 24 08547-026 T7 P1-T7 P1-T7 1A 2 AGND P3-T7 P3-T7 3A 4A GND GND1 GND2 1 1 1 3 P4-T7 4 P4-T7 AGND VCC 1 VCC VCC_RF VCC_LO VCC_BB 1 6A 5 5A 6 ADRF6603 2A R29 0 R31 0 R32 0 T8 P4-T7 5 AGND VCC_SENSE SNS NC P1-6 R72 0 1 3 0 4 2 P1-T7 R69 LO IN SNS1 AGND P3-T7 10UF C28 AGND VTUNE AGND LO_EXTERN VCC_LO AGND VCC_LO 0 CP 100PF 0 1K 0 R68 0 R33 R10 806 SCHEMATICS AND ARTWORK R63 100K R6 C8 0.1UF C7 1 VCO_LDO LO_EXTERN 2P5V_LDO J1 10 J1 9 J1 8 J1 7 1 R38 R65 R9 C6 1NF 0 C5 1NF VCC1 1 VCC IP3SET 0 R67 AGND AGND 0 DNI OUTPUT_EN 3P3V_LDO 0 R66 C14 0 R37 1000PF C15 0.022UF C13 470PF C40 TBD R62 J1 6 J1 5 AGND VCC_SENSE AGND J1 4 J1 3 J1 2 VCC J1 1 VCC4 1 VCC R11 DNI R7 R55 10K 3 R12 0 2 R56 10K 0 C9 C10 100PF AGND 1 S1 0.1UF VCO_LDO AGND VCO_LDO 1 IP3SET C1 AGND AGND 40 NC LOP LON GND NC GND AGND IP3SET AGND R1 0 R8 0 DNI C12 AGND C43 DECLVCO VCC_LO 1 R27 3P3V1 1 R49 C2 0.1UF AGND 39 38 37 36 35 34 33 32 31 100PF LO OUT VCC_BB TBD 3P3V_LDO C41 C11 0.1UF 10UF 1 VCC1 GND IP3SET GND VCC_V2I Z1 RFIN GND GND GND VCC_MIX GND 29 28 27 26 25 24 R15 0 C4 4 GND AGND 22000PF C3 DNI 6 REF_IN Y1 VTUNE R60 TBD C27 0.1UF R43 0 10UF 100PF AGND AGND 30 AGND OSC_3P3V 1 3 CP 2 DECL3P3 AGND AGND AGND AGND R26 0 C24 100PF C25 0.1UF T3 1 2 3 VCC_RF 1 4 TC4-1W 6 LODRV_EN VCC_RF AGND R14 DNI R71 TBD GND DATA CLK LE GND PLL_EN VCC_LO IFP IFN R70 49.9 R16 0 11 2P5V 1 GND R35 C42 10UF P1 1 2 AGND VCC2 1 R17 0 C19 0.1UF C18 100PF VCC 4 5 6 7 8 9 AMP745781-4 P1-6 AGND AGND 3 P1-1 0.1UF 100PF 0 R30 R57 R36 0 0 0 1 DIG_GND 1 0 R20 0 R34 08547-023 VCC 1 LE AGND AGND 1 VCC5 Figure 24. Evaluation Board Schematic Rev. 0 | Page 20 of 24 R2 5R SET 10PF 8 MUXOUT AGND P1-1 10 VCC2 AGND 9 DECL2P5 C31 1000PF REFOUT 12 7 GND 23 22 21 E-PAD PAD 14 15 13 16 17 18 19 20 AGND C32 R50 1K DNI C16 100PF DNI AGND R19 0 DATA VCC_LO1 R24 AGND 0 C21 100PF AGND C33 R51 1K DNI 100PF DNI AGND R53 10K C34 R52 1K DNI 100PF DNI R54 10K 1 S2 OSC_3P3V AGND AGND R28 0 VCC_BB1 R25 0 C22 100PF C23 0.1UF AGND 1 VCC_BB AGND VCC C29 0.1UF R59 0 RFIN REFIN AGND AGND C35 IFP DNI VCC L1 TBD AGND R58 DNI VCC L2 1 TBD VCC_LO C20 0.1UF AGND DNI C36 IFN R47 0 R44 DNI AGND AGND 1 R18 0 C17 AGND 2P5V_LDO AGND CLK R48 0 AGND AGND 2 3 AGND OUTPUT_EN ADRF6603 08547-013 Figure 25. Evaluation Board Layout (Bottom) Figure 26. Evaluation Board Layout (Top) Rev. 0 | Page 21 of 24 08547-012 ADRF6603 EVALUATION BOARD CONFIGURATION OPTIONS Table 10. Component S1, R55, R56, R33 Description LO select. Switch and resistors to ground the LODRV_EN pin. The LODRV_EN pin setting, in combination with internal register settings, determines whether the LOP and LON pins function as inputs or outputs (see the LO Selection Logic section for more information). LO input/output. An external 1× LO or 2× LO can be applied to this single-ended input connector. Reference input. The input reference frequency for the PLL is applied to this connector. Input impedance is 50 Ω. Multiplexer output. The REFOUT connector connects directly to the MUXOUT pin. The on-board multiplexer can be programmed to bring out the following signals: REFIN, 2× REFIN, REFIN/2, REFIN/4. Temperature sensor output voltage. Lock detect indicator. Charge pump test point. The unfiltered charge pump signal can be probed at this test point. Note that the CP pin should not be probed during critical measurements such as phase noise. Loop filter. Loop filter components. Loop filter return. When the internal VCO is used, the loop filter components should be returned to Pin 40 (DECLVCO) by installing a 0 Ω resistor in R12. When an external VCO is used, the loop filter components can be returned to ground by installing a 0 Ω resistor in R11. Internal vs. external VCO. When the internal VCO is enabled, the loop filter components are connected directly to the VTUNE pin (Pin 39) by installing a 0 Ω resistor in R62. To use an external VCO, R62 should be left open. A 0 Ω resistor should be installed in R63, and the voltage input of the VCO should be connected to the VTUNE SMA connector. The output of the VCO is brought back into the PLL via the LO IN/OUT SMA connector. RSET pin. This pin is unused and should be left open. RF input. The RF input signal should be applied to the RFIN SMA connector. The RF input of the ADRF6603 is ac-coupled, therefore, no bias is necessary. IF output. The differential IF output signals from the ADRF6603 (IFP and IFN) are converted to a single-ended signal by T3. Default Condition/ Option Settings S1 = R55 = open (not installed) R56 = R33 = 0 Ω LODRV_EN = 0 V LO input LO IN/OUT SMA Connector REFIN SMA Connector REFOUT SMA Connector Lock detect CP Test Point R37, C14, R9, R10, C15, C13, R65, C40 R11, R12 R12 = 0 Ω (0402) R11 = open (0402) R62 = 0 Ω (0402) R63 = open (0402) R62, R63, VTUNE SMA Connector R2 RFIN SMA Connector T3 R2 = open (0402) R3 = R23 = open (0402) Rev. 0 | Page 22 of 24 ADRF6603 OUTLINE DIMENSIONS 6.00 BSC SQ 0.60 MAX 31 30 40 1 0.60 MAX PIN 1 INDICATOR PIN 1 INDICATOR TOP VIEW 5.75 BSC SQ 0.50 BSC 0.50 0.40 0.30 EXPOSED PAD (BOT TOM VIEW) 4.25 4.10 SQ 3.95 10 21 20 11 0.25 MIN 4.50 REF 12° MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 1.00 0.85 0.80 COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 Figure 27. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm × 6 mm Body, Very Thin Quad (CP-40-1) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADRF6603ACPZ-R7 ADRF6603-EVALZ 1 Temperature Range −40°C to +85°C Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board 072108-A SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Package Option CP-40-1 Z = RoHS Compliant Part. Rev. 0 | Page 23 of 24 ADRF6603 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08547-0-3/10(0) Rev. 0 | Page 24 of 24