ADRF6655-EVALZ

Broadband Up/Downconverting Mixer with Integrated Fractional-N PLL and VCO ADRF6655 FEATURES Broadband active mixer with integrated fractional-N PLL RF input frequency range: 100 MHz to 2500 MHz Internal LO frequency range: 1050 MHz to 2300 MHz Flexible IF output interface Input P1dB: 12 dBm Input IP3: 29 dBm Noise figure (SSB): 12 dB Voltage conversion gain: 6 dB Matched 200 Ω output impedance SPI serial interface for PLL programming 40-lead 6 mm × 6 mm LFCSP The programmable divider is controlled by an Σ-Δ modulator (SDM). The modulus of the SDM can be programmed between 1 and 2047. The broadband, active mixer employs a bias adjustment to allow for enhanced IP3 performance at the expense of increased supply current. The mixer provides an input IP3 exceeding 25 dBm with 12 dB single sideband NF under typical conditions. The IIP3 can be boosted to ~29 dBm with roughly 20 mA of additional supplied current. The mixer provides a typical voltage conversion gain of 6 dB with a 200 Ω differential IF output impedance. The IF output can be externally matched to support upconversion over a limited frequency range. The ADRF6655 is fabricated using an advanced silicon-germanium BiCMOS process. It is packaged in a 40-lead, exposed-paddle, Pb-free, 6 mm × 6 mm LFCSP. Performance is specified over a −40°C to +85°C temperature range. GENERAL DESCRIPTION The ADRF6655 is a high dynamic range active mixer with integrated PLL and VCO. The synthesizer uses a programmable integer-N/fractional-N PLL to generate a local oscillator input to the mixer. The PLL reference input is nominally 20 MHz. The reference input can be divided by or multiplied by and then applied to the PLL phase detector. The PLL can support input reference frequencies from 10 MHz to 160 MHz. The phase detector output controls a charge pump whose output is integrated in an off-chip loop filter. The loop filter output is then applied to an integrated VCO. The VCO output at 2 × fLO is then applied to a local oscillator (LO) divider as well as to a programmable PLL divider. FUNCTIONAL BLOCK DIAGRAM GND 36 GND 35 VCCLO 34 NC 33 NC 32 GND 31 30 GND LOSEL LON 37 BUFFER ADRF6655 29 IP3SET 28 GND 27 VCCMIX LOP 38 FRACTION MODULUS REG SPI INTERFACE THIRD-ORDER FRACTIONAL INTERPOLATOR N COUNTER 21 TO 123 ×2 REFIN 6 GND 7 ÷2 ÷4 3.3V LDO MUXOUT 8 1 2 GND 11 DATA 12 CLK 13 LE 14 GND 15 INTEGER REG LOSEL BUFFER MUX DIVIDER ÷2 OR ÷3 26 INP 25 INN PRESCALER VCO CORE 24 GND 23 GND MUX TEMP SENSOR – PHASE + FREQUENCY DETECTOR CHARGE PUMP 250µA, 500µA (DEFAULT), 750µA, 1000µA 3 4 5 22 VCCV2I 21 GND 2.5V LDO 9 10 39 VCO LDO 40 16 17 18 19 20 08817-001 VCC1 DECL1 CP GND RSET DECL2 VCC2 VTUNE DECL3 NC VCCLO OUTN OUTP GND Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. ADRF6655 TABLE OF CONTENTS Features .............................................................................................. 1  General Description ......................................................................... 1  Functional Block Diagram .............................................................. 1  Revision History ............................................................................... 2  Specifications..................................................................................... 3  Timing Characteristics ................................................................ 5  Absolute Maximum Ratings............................................................ 6  ESD Caution .................................................................................. 6  Pin Configuration and Function Despcriptions .......................... 7  Typical Performance Characteristics ............................................. 9  Downconversion........................................................................... 9  Upconversion .............................................................................. 11  PLL Characteristic ...................................................................... 12  Complimentary Cumulative Distribution Function (CCDF): Downconversion, LO = 1100 MHz, RF = 900 MHz .............. 14  Complimentary Cumulative Distribution Function (CCDF): Downconversion, LO = 1700 MHz, RF = 1900 MHz ............ 15  Complimentary Cumulative Distribution Function (CCDF): Upconversion Distribution ....................................................... 16  Circuit Description ......................................................................... 17  PLL and VCO Block ................................................................... 17  RF Mixer Block ........................................................................... 17  Digital Interfaces ........................................................................ 18  Analog Interfaces ............................................................................ 19  Supply Connections ................................................................... 19  Synthesizer Connections ........................................................... 19  Output Matching and Biasing................................................... 19  Input Matching ........................................................................... 20  IP3SET Linearization Feature ................................................... 21  CDAC Linearization Feature .................................................... 21  External LO Interface ................................................................ 21  Using an External VCO ............................................................. 22  ADRF6655 Control Software ........................................................ 23  PLL Loop Filter Design ............................................................. 23  Register Structure ........................................................................... 24  Device Programming ................................................................. 25  Initialization Sequence .............................................................. 25  Register 0—Integer Divide Control ......................................... 26  Register 1—Modulus Divide Control ...................................... 27  Register 2—Fractional Divide Control .................................... 27  Register 3—Σ-Δ Modulator Dither Control ........................... 28  Register 4—Charge Pump, PFD, and Reference Path Control ................................................................................ 29  Register 5—LO Path and Mixer Control................................. 31  Register 6—VCO Control and PLL Enables ........................... 32  Register 7—External VCO Control ......................................... 33  Characterization Setups ................................................................. 34  Evaluation Board Layout and Thermal Grounding ................... 38  Outline Dimensions ....................................................................... 41  Ordering Guide .......................................................................... 41  REVISION HISTORY 2/10—Revision 0: Initial Version Rev. 0 | Page 2 of 44 ADRF6655 SPECIFICATIONS VCC = 5 V; ambient temperature (TA) = 25°C; REFIN = 20 MHz, phase frequency detector (PFD) frequency = 20 MHz, IF output loaded into 4-to-1 transformer matched to a 50 Ω system, unless otherwise noted. Table 1. Parameter RF INPUT FREQUENCY RANGE IF OUTPUT FREQUENCY RANGE INTERNAL LO FREQUENCY RANGE EXTERNAL LO FREQUENCY RANGE MIXER Input Return Loss Output Return Loss IF Output Impedance Output Common Mode Voltage Conversion Gain Output Swing LO-to-IF Output Leakage DYNAMIC PERFORMANCE Upconversion Gain Flatness Gain Temperature Coefficient Output P1dB Second-Order Output Intercept (IIP2) Third-Order Output Intercept (IIP3) Output Noise Spectral Density Test Conditions/Comments Can be matched externally for improved return loss at higher frequencies (see the Output Matching and Biasing section) Divide-by-3 mode 1 Divide-by-2 mode1 Divide-by-2 mode 2 INP, INN; relative to 50 Ω, from 350 MHz to 2200 MHz using TC1-1-13M+ balun 3 OUTP, OUTN; relative to 50 Ω out to 200 MHz using TC4-1W output transformer option3 OUTP, OUTN OUTP, OUTN; external pull-up balun or inductors required IF output loaded into 200 Ω differential load Can be improved using external filtering IP3Set = 3.2 V 340 MHz RF input, 1200 MHz IF output using 1540 MHz LO (see Figure 56 for output matching network) Over ±50 MHz bandwidth for 1200 MHz output center frequency Average values from −40°C to +85°C −5 dBm each tone −5 dBm each tone, IP3SET = 3.2 V −5 dBm each tone, IP3SET = open IP3SET = 3.2 V, RF input terminated with 50 Ω IP3SET = 3.2 V, RF input = −5 dBm, fLO = 1315 MHz with fRF = 380 MHz applied, measured noise at fIF = 915 MHz 1880 MHz RF input, 140 MHz IF output using 1740 MHz LO Over ±50 MHz bandwidth for 1880 MHz input center frequency Average values from −40°C to +85°C IP3SET = 3.2 V IP3SET = open −5 dBm each tone −5 dBm each tone, IP3SET = 3.2 V −5 dBm each tone, IP3SET = open IP3SET = 3.2 V IP3SET = open −5 dBm RF input blocker applied at 995 MHz, fLO = 1200 MHz, noise measured at 5 MHz offset from IF output blocker IP3SET = 3.2 V IP3SET = open −5 dBm RF input power LOP, LON 1 × LO into a 50 Ω load, LO buffer enabled Min 100 LF 1050 1530 500 12 12 200 VPOS 6 2 −40 Typ Max 2500 2200 1530 2300 2300 Unit MHz MHz MHz MHz MHz dB dB Ω V dB V p-p dBm 0.25 −10 11 60 31 28 −160 −155 dB p-p mdB/°C dBm dBm dBm dBm dBm/Hz dBm/Hz Downconversion Gain Flatness Gain Temperature Coefficient Input P1dB Second-Order Input Intercept (IIP2) Third-Order Input Intercept (IIP3) SSB Noise Figure (NF) SSB Noise Figure Under Blocking Conditions 0.25 −10 14 12 50 27 26 14 12 dB p-p mdB/°C dBm dBm dBm dBm dBm dB dB IF/2 Spurious LO OUTPUT Output Level 20.75 20.25 −65 −7 dB dB dBc dBm Rev. 0 | Page 3 of 44 ADRF6655 Parameter SYNTHESIZER SPECIFICATIONS Fundamental VCO Sensitivity Spurs Reference/PFD Spurs Test Conditions/Comments Synthesizer specifications referenced to 1 × LO 4 VCO tuning sensitivity before divide-by-2 or divide-by-3 Measured at LO output fPFD/2 fPFD 2 × fPFD 4 × fPFD PFD frequency = 20 MHz4 @ 10 kHz offset @ 100 kHz offset @ 1 MHz offset @ 10 MHz offset 10 kHz to 40 MHz integration bandwidth @ 10 kHz offset @ 100 kHz offset @ 1 MHz offset @ 10 MHz offset 10 kHz to 40 MHz integration bandwidth 19.33 REFIN, MUXOUT 10 20 4 ±100 1 160 MHz pF μA V p-p V V μA 2.8 3.3 0.7 ±1 3 VCC1, VCC2, VCCLO 4.75 LO output buffer disabled PLL only Normal TX mode, IP3SET = 3.2 V, fLO ≤1530 MHz (divide-by-3) Normal TX mode, IP3SET = 3.2 V, fLO > 1530 MHz (divide-by-2) Normal RX mode, IP3SET = open, fLO ≤ 1530 MHz (divide-by-3) Normal RX mode, IP3SET = open, fLO > 1530 MHz (divide-by-2) Power-down mode 5 115 310 270 285 245 15 5.25 V mA mA mA mA mA mA V V V μA pF Min Typ 75 −95 −83 −85 −88 Max Unit MHz/V dBc dBc dBc dBc Phase Noise LO Frequency = 1330 MHz Integrated Phase Noise LO Frequency = 1840 MHz −85 −114 −138 −154 0.3 −83 −111 −136 −152 0.4 20 dBc/Hz dBc/Hz dBc/Hz dBc/Hz °rms dBc/Hz dBc/Hz dBc/Hz dBc/Hz °rms MHz Integrated Phase Noise PFD Frequency REFERENCE CHARACTERISTICS REFIN Input Frequency REFIN Input Capacitance REFIN Input Current REFIN Input Sensitivity MUXOUT Output Levels CHARGE PUMP Pump Current Output Compliance Range LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance POWER SUPPLIES Voltage Range Supply Current 40 AC-coupled VOL (lock detect output selected) VOH (lock detect output selected) CP Charge pump current adjustable using Register 4 and/or RSET (see Pin 5 description) CLK, DATA, LE 0.25 2.7 3.3 0.25 500 1 1.4 0 1 2 3 4 Internal LO path divider programmed via serial interface. See the LO Signal Chain section for additional information. See the External LO Interface section. Improved return loss can be achieved using external matching. See the Circuit Description section for more details. Measured on standard evaluation board with 1.5 kHz loop filter (C13 = 47 nF, C14 = 0.1 μF, C15 = 4.7 μF, R9 = 270 Ω, R10 = 68 Ω). Rev. 0 | Page 4 of 44 ADRF6655 TIMING CHARACTERISTICS Table 2. Serial Interface Timing, VCC = 5 V ± 5% Parameter t1 t2 t3 t4 t5 t6 t7 Limit 20 10 10 25 25 10 20 Unit ns minimum ns minimum ns minimum ns minimum ns minimum ns minimum ns minimum Test Conditions/Comments LE setup time DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width t4 CLK t5 t2 DATA DB23 (MSB) DB22 t3 DB2 (CONTROL BIT C3) DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t6 LE t7 t1 08817-002 Figure 2. Timing Diagram Rev. 0 | Page 5 of 44 ADRF6655 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage, VCC Digital I/O CLK, DATA, LE OUTP, OUTN LOP, LON INN, INP DECL3 Using External Bias Option θJA (Exposed Paddle Soldered Down)1 Maximum Junction Temperature Operating Temperature Range Storage Temperature Range 1 Rating 5.5 V −0.3 V to +3.6 V VCC 16 dBm 20 dBm 3.5 V 35°C/W 150°C −40°C to +85°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Per JDEC standard JESD 51-2. For information on optimizing thermal impedance, see the Evaluation Board Layout and Thermal Grounding section. Rev. 0 | Page 6 of 44 ADRF6655 PIN CONFIGURATION AND FUNCTION DESPCRIPTIONS 40 DECL3 39 VTUNE 36 GND 35 GND 34 VCCLO 31 GND 38 LOP 37 LON 33 NC 32 NC VCO LDO VCC1 1 30 GND ADRF6655 DECL1 2 3.3V LDO PD + CHARGE PUMP WIDEBAND UP/DOWN CONVERTER PFD 29 IP3SET CP 3 28 GND GND 4 VCO BAND AND CURRENT CAL/SET ×2 MUX GND 7 ENABLE MUXOUT 8 2.5V LDO ÷2 OR ÷4 PROGRAMMABLE DIVIDER PRESCALER 6 6 VCO CORE MUX ÷2 OR ÷3 27 VCCMIX RSET 5 26 INP REFIN 6 25 INN 24 GND 23 GND DECL2 9 THIRD-ORDER SDM FRACTION MODULUS SERIAL PORT INTEGER 22 VCCV2I VCC2 10 21 GND GND 11 DATA 12 CLK 13 GND 15 VCCLO 17 NC 16 OUTN 18 OUTP 19 LE 14 GND 20 NC = NO CONNECT Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4, 7, 11, 15, 20, 21, 23, 24, 28, 30, 31, 35, 36 Mnemonic VCC1 DECL1 CP GND Description Power Supply for Internal 3.3 V LDO. The power supply voltage range is 4.75 V to 5.25 V. Supply pin should be decoupled with 100 pF and 0.1 μF capacitors located close to the pin. Decoupling Node for 3.3 V LDO. Pin should be decoupled with 100 pF, 0.1 μF, and 10 μF capacitors located close to the pin. Charge Pump Output Pin. Connect this pin to VTUNE through the loop filter. Ground. Connect these pins to a low impedance ground plane. Rev. 0 | Page 7 of 44 08817-003 ADRF6655 Pin No. 5 Mnemonic RSET Description Charge Pump Current. The nominal charge pump current can be set to either 250 μA, 500 μA, 750 μA, or 1 mA using DB10 and DB11 of Register 4 and by setting DB18 to 0 (internal reference current). In this mode, no external RSET is required. If DB18 is set to 1, the four nominal charge pump currents (INOMINAL) can be externally tweaked according to ⎡ 217 . 4 × I CP , BASE ⎤ RSET [Ω ] = ⎢ ⎥ − 37 . 8 250 ⎣ ⎦ where ICP, BASE is the base charge pump current in μA. For further details on the charge pump current,see the Register 4—Charge Pump, PFD, and Reference Path Control section. Reference Input. Nominal input level is 1 V p-p. Input range is 10 MHz to 160 MHz. This pin must be ac-coupled. Multiplexer Output. This output allows either a digital lock detect, a voltage proportional to temperature, or a buffered, frequency-scaled reference signal to be accessed externally. The output is selected by programming the appropriate bits in Register 4. Decoupling Node for 2.5 V LDO. Pin should be decoupled with 100 pF, 0.1 μF, and 10 μF capacitors located close to the pin. Power Supply for Internal 2.5 V LDO. The power supply voltage range is 4.75 V to 5.25 V. Supply pin should be decoupled with 100 pF and 0.1 μF capacitors located close to the pin. Serial Data Input. The serial data input is loaded MSB first with the three LSBs being the control bits. Serial Clock Input. This serial clock input is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz. Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one of the six registers, the relevant latch being selected by the first three control bits of the 24-bit word. No Connection. Power Supply for LO Path. The power supply voltage range is 4.75 V to 5.25 V. Supply pin should be decoupled with 100 pF and 0.1 μF capacitors located close to the pin. Mixer IF Outputs. These pins should be pulled to VCC with RF chokes. Power Supply for Voltage to Current Input Stage. The power supply voltage range is 4.75 V to 5.25 V. Supply pin should be decoupled with 100 pF and 0.1 μF capacitors located close to the pin. Mixer RF Inputs. Differential RF Inputs. Internally matched to 50 Ω. This pin must be ac-coupled. Power Supply for Mixer. The power supply voltage range is 4.75 V to 5.25 V. Supply pin should be decoupled with 100 pF and 0.1 μF capacitors located close to the pin. Connect Resistor to VCC to Adjust IP3. Local Oscillator Input/Output. The internally generated 1 × fLO is available on these pins. When internal LO generation is disabled, an external 2 × fLO or 3 × fLO (depending on divider selection) can be applied to these pins. This pin must be ac-coupled. VCO Control Voltage Input. This pin is driven by the output of the loop filter. Nominal input voltage range on this pin is 1 V to 2.8 V. Decoupling Node for VCO LDO. Connect a 100 pF capacitor and a 10 μF capacitor between this pin and ground. The exposed paddle should be soldered to a low impedance ground plane. 6 8 REFIN MUXOUT 9 10 12 13 14 16, 32, 33 17, 34 18,19 22 25, 26 27 29 37, 38 DECL2 VCC2 DATA CLK LE NC VCCLO OUTN, OUTP VCCV2I INN, INP VCCMIX IP3SET LON, LOP 39 40 VTUNE DECL3 EPAD (EP) Rev. 0 | Page 8 of 44 ADRF6655 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, TA = 25°C, PFD = 20 MHz, REFIN = 20 MHz, IP3SET = 3.2 V, unless otherwise noted. DOWNCONVERSION Measured using typical downconversion circuit schematic with high-side LO and 140 MHz IF output, unless otherwise noted. 5 4 3 2 GAIN (dB) LOW-SIDE LO HIGH-SIDE LO +25°C –40°C +85°C 1 0 –1 –2 –3 –4 08817-086 1100 1300 1500 1700 1900 2100 2300 1100 1300 1500 1700 1900 2100 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 4. Conversion Gain vs. Input Frequency 20 IP3SET = 3.2V IP3SET = OPEN Figure 7. Input IP3 vs. Input Frequency 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 900 +25°C –40°C +85°C LOW-SIDE LO HIGH-SIDE LO +25°C –40°C +85°C 18 NOISE FIGURE (dB) 16 14 12 08817-123 1100 1300 1500 1700 1900 2100 1100 1300 1500 1700 1900 2100 2300 2500 RF FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 5. SSB Noise Figure vs. RF Frequency 30 28 26 IP3SET = 3.2V IP3SET = OPEN Figure 8. Input IP2 vs. Input Frequency 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 900 IP3SET = 3.2V IP3SET = OPEN +25°C –40°C +85°C NOISE FIGURE (dB) 22 20 18 16 14 12 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 08817-104 1100 1300 1500 1700 1900 2100 CW BLOCKER LEVEL (dBm) INPUT FREQUENCY (MHz) Figure 6. SSB Noise Figure vs. CW Blocker Level Rev. 0 | Page 9 of 44 Figure 9. Input P1dB vs. Input Frequency 08817-089 10 –50 INPUT P1 dB (dBm) 24 08817-088 10 900 INPUT IP2 (dBm) 08817-087 –5 900 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 900 INPUT IP3 (dBm) IP3SET = 3.2V IP3SET = OPEN +25°C –40°C +85°C ADRF6655 0 –5 –10 –15 S11 (dB) –20 –25 –30 –35 –40 08817-122 0 500 1000 1500 2000 2500 3000 1250 1450 1650 1850 2050 2250 FREQUENCY (MHz) LO FREQUENCY (MHz) Figure 10. RF Port Input Return Loss (S11) vs. Frequency Measured through TC1-1-13M+ 300 270 240 2.0 1.8 Figure 13. Supply Current vs. LO Frequency 0 –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 –11 –12 –13 –14 –15 –16 –17 –18 –19 –20 1050 +25°C –40°C +85°C OUTPUT CAPACITANCE (pF) 210 180 150 120 90 60 30 0 0 50 100 150 200 250 300 350 400 450 FREQUENCY (MHz) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 08817-124 1250 1450 1650 1850 2050 2250 LO FREQUENCY (MHz) Figure 11. IF Port Output Impedance vs. Frequency –40 –45 +25°C –40°C +85°C –20 –25 Figure 14. LO Port Output Power vs. LO Frequency LO-TO-IF OUTPUT LEAKAGE (dBm) LO-TO-RF INPUT LEAKAGE (dBm) –50 –55 –60 –65 –70 –75 –80 –85 –90 –95 1250 1450 1650 1850 2050 –30 –35 –40 –45 –50 –55 –60 –65 –70 –75 +25°C –40°C +85°C 1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250 LO FREQUENCY (MHz) LO FREQUENCY (MHz) Figure 12. LO-to-RF Input Port Leakage vs. LO Frequency Figure 15. LO-to-IF Output Port Leakage vs. LO Frequency Rev. 0 | Page 10 of 44 08817-014 2250 08817-090 –100 1050 –80 08817-092 0 500 LO OUTPUT POWER (dBm) 1.6 OUTPUT RESISTANCE (Ω) 08817-091 –45 400 380 360 340 320 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 1050 SUPPLY CURRENT (mA) IP3SET = 3.2V IP3SET = OPEN +25°C –40°C +85°C ADRF6655 UPCONVERSION Measured using typical upconversion circuit schematic with high-side LO and 340 MHz RF input, unless otherwise noted. 5 4 3 +25°C –40°C +85°C 35 34 33 32 31 OUTPUT IP3 (dBm) IP3SET = 3.2V IP3SET = OPEN +25°C –40°C +85°C 2 30 29 28 27 26 25 24 23 22 21 20 710 GAIN (dB) 1 0 –1 –2 –3 –4 810 910 1010 1110 1210 1310 1410 1510 1610 08817-093 810 910 1010 1110 1210 1310 1410 1510 1610 OUTPUT FREQUENCY (MHz) OUTPUT FREQUENCY (MHz) Figure 16. Conversion Gain vs. Output Frequency 0 Figure 19. Output IP3 vs. Output Frequency 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 710 fLO – 2 × fRF SPURIOUS RESPONSE (dBc) –10 –20 +25°C –40°C +85°C IP3SET = 3.2V IP3SET = OPEN +25°C –40°C +85°C –40 –50 –60 –70 –80 –90 08817-016 1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250 810 910 1010 1110 1210 1310 1410 1510 1610 LO FREQUENCY (MHz) OUTPUT FREQUENCY (MHz) Figure 17. fLO − 2 × fRF Spurious Response vs. LO Frequency (Relative to IF Output Power) 0 NOISE SPECTRAL DENSITY (dBm/Hz) –10 –20 –30 –40 –50 –60 –70 –80 1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 LO FREQUENCY (MHz) +25°C –40°C +85°C –100 –110 Figure 20. Output P1dB vs. Output Frequency LO-TO-IF OUTPUT LEAKAGE (dBm) –120 –130 –140 –150 –160 08817-105 810 910 1010 1110 1210 1310 1410 1510 1610 OUTPUT FREQUENCY (MHz) Figure 18. LO-to-IF Output Leakage vs. Frequency Figure 21. Output Noise Spectral Density vs. Output Frequency Rev. 0 | Page 11 of 44 08817-121 –170 710 08817-095 –100 OUTPUT P1dB (dBm) –30 08817-094 –5 710 ADRF6655 PLL CHARACTERISTIC Measured using typical downconversion circuit schematic with high-side LO and 140 MHz IF output, loop filter = 1.5 kHz, unless otherwise noted. 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 1k 10k 0 LO REFERENCE PFD SPURS (dBc) +25°C –10°C –40°C +70°C +85°C –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 08817-021 1 × PFD OFFSET 2 × PFD OFFSET 4 × PFD OFFSET +25°C –40°C +85°C PHASE NOISE (dBc/Hz) LO = 2275MHz LO = 1100MHz 100k 1M 10M 100M 1250 1450 1650 1850 2050 2250 OFFSET FREQUENCY (kHz) LO FREQUENCY (MHz) Figure 22. Typical Fractional-N Phase Noise Plot 1.0 0.9 +25°C –10°C –40°C +70°C +85°C 3.0 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 Figure 25. LO Reference/PFD Spurs vs. LO Frequency HIGH-SIDE LO LOW-SIDE LO INTEGRATED PHASE NOISE (°C rms) +25°C –40°C +85°C 0.8 0.7 0.5 0.4 0.3 0.2 0.1 08817-022 1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250 1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250 LO FREQUENCY (MHz) LO FREQUENCY (MHz) Figure 23.10 kHz to 40 MHz Integrated Phase Noise vs. LO Frequency 2500 1.9 1: 10ms 2.289999883GHz Figure 26. Tuning Voltage vs. LO Frequency FREQUENCY DEVIATION FROM 2.29GHz (Hz) 2000 1500 1000 VPTAT (V) 500 2.290G –500 –1000 –1500 –2000 0 10 1 LO = 1100MHz, IP3SET = 3.2V 1.8 1.7 1.6 1.5 LO = 2300MHz, IP3SET = 3.2V LO =2300MHz, IP3SET = OPEN 1.4 TIME (ms) 25 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) Figure 24. Lock Time for 10 MHz Step with 1.5 kHz Loop Filter Figure 27. VPTAT MUXOUT Voltage vs. Temperature Rev. 0 | Page 12 of 44 08817-097 –2500 08817-120 1.3 –40 –30 –20 –10 08817-025 0 VTUNE (V) 0.6 08817-096 –110 1050 ADRF6655 –60 AVERAGE –65 AVERAGE + 3 × ST DEV –70 –75 10kHz OFFSET –80 –85 –90 –95 –100 –105 –110 100kHz OFFSET –115 –120 –125 –130 1MHz OFFSET –135 –140 –145 –150 1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250 LO FREQUENCY (MHz) 08817-039 LO FREQUENCY (MHz) Figure 28. −40°C Spot Phase Noise vs. LO Frequency –60 AVERAGE –65 AVERAGE + 3 × ST DEV –70 –75 10kHz OFFSET –80 –85 –90 –95 –100 –105 100kHz OFFSET –110 –115 –120 –125 –130 1MHz OFFSET –135 –140 –145 –150 1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250 LO FREQUENCY (MHz) Figure 31. 70°C Spot Phase Noise vs. LO Frequency –60 AVERAGE –65 AVERAGE + 3 × ST DEV –70 –75 10kHz OFFSET –80 –85 –90 –95 –100 –105 100kHz OFFSET –110 –115 –120 –125 1MHz OFFSET –130 –135 –140 –145 –150 1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250 LO FREQUENCY (MHz) PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) 08817-040 Figure 29. −10°C Spot Phase Noise vs. LO Frequency –60 AVERAGE –65 AVERAGE + 3 × ST DEV –70 –75 10kHz OFFSET –80 –85 –90 –95 –100 –105 100kHz OFFSET –110 –115 –120 –125 –130 1MHz OFFSET –135 –140 –145 –150 1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250 LO FREQUENCY (MHz) Figure 32. 85°C Spot Phase Noise vs. LO Frequency PHASE NOISE (dBc/Hz) Figure 30. 25°C Spot Phase Noise vs. LO Frequency 08817-041 Rev. 0 | Page 13 of 44 08817-043 08817-042 –60 AVERAGE –65 AVERAGE + 3 × ST DEV –70 –75 10kHz OFFSET –80 –85 –90 –95 –100 –105 100kHz OFFSET –110 –115 –120 –125 1MHz OFFSET –130 –135 –140 –145 –150 1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) ADRF6655 COMPLIMENTARY CUMULATIVE DISTRIBUTION FUNCTION (CCDF): DOWNCONVERSION, LO = 1100 MHz, RF = 900 MHz VS = 5 V, TA = 25°C, PFD = 20 MHz, REFIN = 20 MHz, IP3SET = open, as measured using typical downconversion circuit schematic with high-side LO and 200 MHz IF output, unless otherwise noted. 100 IP3SET = 3.2V 95 IP3SET = OPEN 90 85 80 75 GAIN 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 –10 –8 –6 –4 –2 0 +25°C –40°C +85°C INPUT P1dB DISTRIBUTION PERCENTAGE (%) 08817-106 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 GAIN (dB), INPUT P1dB (dBm) NOISE FIGURE (dB) Figure 33. Gain and Input P1dB CCDF 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 12 Figure 36. Noise Figure CCDF 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 0 IP3SET = 3.2V IP3SET = OPEN DISTRIBUTION PERCENTAGE (%) +25°C –40°C +85°C DISTRIBUTION PERCENTAGE (%) IP3SET = 3.2V IP3SET = OPEN +25°C –40°C +85°C 08817-107 14 16 18 20 22 24 26 28 30 32 34 36 38 40 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 INPUT IP3 (dBm) VPTAT (V) Figure 34. Rx Input IP3 CCDF 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 –100 Figure 37. VPTAT MUXOUT Voltage DISTRIBUTION PERCENTAGE (%) +25°C –40°C +85°C –95 –90 –85 –80 –75 –70 –65 –60 –55 –50 LO-TO-RF LEAKAGE (dBm) Figure 35. Rx LO-to-RF Leakage CCDF 08817-098 Rev. 0 | Page 14 of 44 08817-109 08817-108 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 IP3SET = 3.2V IP3SET = OPEN DISTRIBUTION PERCENTAGE (%) +25°C –40°C +85°C ADRF6655 COMPLIMENTARY CUMULATIVE DISTRIBUTION FUNCTION (CCDF): DOWNCONVERSION, LO = 1700 MHz, RF = 1900 MHz VS = 5 V, TA = 25°C, PFD = 20 MHz, REFIN = 20 MHz, IP3SET = open, as measured using typical downconversion circuit schematic with high-side LO and 200 MHz IF output, unless otherwise noted. 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 IP3SET = 3.2V IP3SET = OPEN +25°C –40°C +85°C GAIN INPUT P1dB 08817-033 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NOISE FIGURE (dB) GAIN, INPUT P1dB (dB, dBm) Figure 38. Gain and Input P1dB 100 IP3SET = 3.2V 95 IP3SET = OPEN 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 INPUT IP3 (dBm) Figure 41. Rx Noise Figure CCDF 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 0.5 +25°C –40°C +85°C IP3SET = 3.2V IP3SET = OPEN +25°C –40°C +85°C DISTRIBUTION PERCENTAGE (%) 08817-034 DISTRIBUTION PERCENTAGE (%) 38 39 40 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 VPTAT (V) Figure 39. Rx Input IP3 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 –100 Figure 42. VPTAT MUXOUT Voltage IP3SET = 3.2V IP3SET = OPEN +25°C –40°C +85°C DISTRIBUTION PERCENTAGE (%) –90 –80 –70 –60 –50 –40 –30 LO-TO-RF LEAKAGE (dBm) Figure 40. Rx LO-to-RF Leakage 08817-099 Rev. 0 | Page 15 of 44 08817-038 08817-110 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 IP3SET = 3.2V IP3SET = OPEN +25°C –40°C +85°C DISTRIBUTION PERCENTAGE (%) DISTRIBUTION PERCENTAGE (%) ADRF6655 COMPLIMENTARY CUMULATIVE DISTRIBUTION FUNCTION (CCDF): UPCONVERSION DISTRIBUTION 100 95 90 85 80 75 GAIN 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 –10 –8 –6 –4 –2 100 IP3SET = 3.2V IP3SET = OPEN DISTRIBUTION PERCENTAGE (%) +25°C –40°C +85°C DISTRIBUTION PERCENTAGE (%) 90 80 70 60 50 40 30 20 10 08817-100 +25°C –40°C +85°C OUTPUT P1dB GAIN OUTPUT P1dB 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 GAIN (dB), OUTPUT P1dB (dBm) GAIN (dB), OUTPUT P1dB (dBm) Figure 43. Gain and Output P1dB CCDF, LO = 1220 MHz, RF = 340 MHz 100 90 DISTIBUTION PERCENTAGE (%) Figure 46. Gain and Output P1dB CCDF, LO = 1840 MHz, RF = 340 MHz 100 IP3SET = 3.2V IP3SET = OPEN 80 70 60 50 40 30 20 10 08817-101 DISTRIBUTION PERCENTAGE (%) +25°C –40°C +85°C 90 80 70 60 50 40 30 20 10 IP3SET = 3.2V IP3SET = OPEN +25°C –40°C +85°C 0 5 10 15 20 25 30 35 40 45 50 55 60 0 5 10 15 20 25 30 35 40 45 50 55 60 OUTPUT IP3 (dBm) OUTPUT IP3 (dBm) Figure 44. Output IP3 CCDF, LO = 1220 MHz, RF = 340 MHz 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 –100 Figure 47. Output IP3 CCDF, LO = 1840 MHz, RF = 340 MHz 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 –100 IP3SET = 3.2V IP3SET = OPEN DISTRIBUTION PERCENTAGE (%) –90 –80 –70 –60 –50 –40 –30 –20 –10 0 LO-TO-IF OUTPUT LEAKAGE (dBm) LO-TO-IF PORT LEAKAGE (dBm) Figure 45. LO-to-IF Output Leakage CCDF, LO = 1220 MHz, RF = 340 MHz Figure 48. LO-to-IF Output Leakage CCDF, LO = 1840 MHz, RF = 340 MHz Rev. 0 | Page 16 of 44 08817-114 –90 –80 –70 –60 –50 –40 –30 –20 –10 08817-113 DISTRIBUTION PERCENTAGE (%) +25°C –40°C +85°C IP3SET = 3.2V IP3SET = OPEN +25°C –40°C +85°C 08817-103 0 0 08817-102 0 –10 –8 –6 –4 –2 IP3SET = 3.2V IP3SET = OPEN ADRF6655 CIRCUIT DESCRIPTION The ADRF6655 can be subdivided into a PLL and VCO block and a mixer block. A detailed circuit description for each block follows. The VCO operates at twice the LO frequency for improved isolation. The nominal value of Kv is 75 MHz/V at the VCO output. As the VCO band is changed from 0 to 63, the size of the varactor is also changed, thus maintaining a roughly constant Kv across the entire operating range. PLL AND VCO BLOCK The PLL and VCO block, shown in Figure 49, is made up of a reference input block, a phase and frequency detector (PFD), a charge pump, a VCO, and a divide-by-N modulus block. An off-chip loop filter completes the loop. LOOP FILTER CP CP ×2 REFIN ÷2 ÷4 FRAC MOD INT PFD TO MIXER BLOCk BAND SELECT VTUNE RF MIXER BLOCK LO VCC 133 Ω 133Ω OUTN OUTP ÷2 OR ÷3 VCO SIF CDAC V2I IP3SET RFIN 08817-053 ADRF6655 MIXER BLOCK Figure 51. Mixer Block THIRD-ORDER INTERPOLATOR PROGRAMMABLE DIVIDER ADRF6655 PLL BLOCK DIAGRAM PRESCALER 08817-051 Figure 49. PLL and VCO Block The VCO is implemented with a single core that consists of 64 overlapping bands, as shown in Figure 50. The correct band is selected automatically by the VCO band calibration circuit when Register R0, Register R1, or Register R2 is programmed. The VCO band selection takes roughly 4000 PFD cycles. During calibration, an internal mux is used to disconnect the VCO input voltage from the VTUNE pin and apply an internal reference voltage for calibration. When calibration is complete, the VCO input voltage is reconnected to the VTUNE pin and normal PLL operation resumes. 2.4 The mixer portion of the ADRF6655, shown in Figure 51, consists of an LO signal chain, an RF voltage-to-current (V-to-I) converter, and a mixer core. The LO chain receives a signal from either the internal VCO or an external LO source. This LO signal then passes through a frequency divider, which can be set to divide-by-2 or divide-by-3, depending on the desired LO frequency. The differential RF inputs are converted into currents by the V-to-I converter and fed into the mixer core. A pair of 133 Ω pull-up resistors are used to present a ~250 Ω source impedance at the IF output. LO Signal Chain The LO chain consists of a mux that selects between the internal VCO and an external LO source. The LO signal can then be divided by 2 or divided by 3, providing a wide range of LO frequencies from 1050 MHz to 2300 MHz. A buffer then drives this divided down signal to the mixer core. The LO signal can also be observed via the LO I/O port when the internal VCO is selected. When the external LO buffer is enabled, the supply current and die temperature increase, resulting in a slight degradation of RF performance. In normal operation mode, the external LO buffer should be disabled to help minimize power consumption and provide optimal RF performance. 2.2 fVCO /2 (GHz) 2.0 1.8 1.6 1.0 1.5 VTUNE (V) 2.0 2.5 Figure 50. fVCO/2 vs. Tuning Voltage for All 64 Bands 08817-052 1.4 0.5 Rev. 0 | Page 17 of 44 ADRF6655 V-to-I Converter The differential RF input signal is applied to a pair of resistively degenerated common-emitter stages, which converts the differential input voltage to output currents. The input stage also provides 50 Ω termination to the RF input port. The linearity of this V-to-I stage can be optimized for a given frequency with Pin IP3SET at the expense of power dissipation and noise figure. An additional way of improving linearity without affecting power dissipation or noise figure is provided by the CDAC signal controlled by serial port interface (SPI). DIGITAL INTERFACES The ADRF6655 provides access to the many programmable features available within the IC using a 3-wire SPI control interface. The minimum delays and hold times are presented in the timing diagram in Figure 2. The SPI interface provides digital control of the internal PLL/VCO as well as several other features related to the mixer core, on-chip referencing, and available system monitoring functions. The MUXOUT pin provides access to several output signals that can be selected via the SPI interface. The available outputs are buffered, frequency-scaled versions of the reference, a PLL lock-detect signal, and an internal voltage that is proportional to the IC junction temperature. Details regarding the register settings and initialization sequence are included in the Register Structure section. Mixer Core The mixer core, based on the Gilbert cell design of four crossconnected transistors, takes the currents from the V-to-I stage and mixes them with the LO signal. This mixer core can be used as a downconvert mixer as is or as an upconvert mixer with an off-chip matching network for a given frequency range. CHARGE PUMP LOOP FILTER +5V 40 39 38 32 37 36 35 34 LON LOP GND GND 33 VCCLO VTUNE DECL3 +5V 1 VCC1 DECL1 CP GND RSET GND NC NC 31 GND IP3SET GND VCCMIX INP 30 2 29 VSET +5V 3 28 4 27 5 26 RSET EXTERNAL REFERENCE 6 ADRF6655 REFIN GND MUXOUT DECL2 VCC2 INN GND GND VCCV2I GND 25 RF INPUT MATCHING BALUN RF INPUT 7 24 MONITOR OUTPUT 8 23 9 22 +5V 10 21 +5V VCCLO OUTN OUTP 19 DATA GND GND 11 12 13 15 16 17 18 SPI CONTROL +5V NC = NO CONNECT 14 Figure 52. Basic Circuit Connections Rev. 0 | Page 18 of 44 08817-054 IF OUTPUT MATCHING BALUN AND BIAS 20 GND CLK LE NC IF OUTPUT ADRF6655 ANALOG INTERFACES OUTN OUTP The basic circuit connections for a typical ADRF6655 application are presented in Figure 52. ADRF6655 850MHz OUTPUT INTERFACE GND 20 SUPPLY CONNECTIONS The ADRF6655 has several supply connections and on-board regulated reference voltages that should be bypassed to ground using low inductance bypass capacitors located in close proximity to the supply and reference pins of the ADRF6655. Specifically Pin 1, Pin 2, Pin 9, Pin 10, Pin 17, Pin 22, Pin 27, and Pin 40 should be bypassed to ground using individual bypass capacitors. Pin 9 is the supply used for the on-board VCO, and for best phase noise performance, several bypass capacitors ranging from 100 pF to 10 μF may help to improve phase noise performance. For additional details on bypassing the supply nodes, refer to the evaluation board schematic in Figure 82. 18 19 12nH 0302CS 15nH 0302CS 1.5pF GJM 12nH 0302CS +VCC TC4-14G2+ 1nF 2.7pF GJM T3 IF OUT Figure 53. 850 MHz Output Matching Network Using the Center-Tap of the TC4-14T+ Transformer for Biasing the Open Collector Outputs (Output return loss measured to be better than 12 dB from 800 MHz to 925 MHz.) ADRF6655 OUTN OUTP GND 900MHz OUTPUT INTERFACE SYNTHESIZER CONNECTIONS The ADRF6655 includes an on-board VCO and PLL for LO synthesis. An external reference must be applied for the PLL to operate. The external reference should be ac-coupled and provide a ~1 V p-p nominal input level at Pin 6. The reference is compared to an internally divided version of the VCO output frequency to create a charge pump error current to control and lock the VCO. The charge pump output current is filtered and converted to a VTUNE control voltage through the external loop filter. ADIsimPLL™ can be a helpful tool when designing the external charge pump loop filter. The typical Kv of the VCO, the charge pump output current magnitude, and PFD frequency should all be considered when designing the loop filter. The charge pump current magnitude can be set internally or with an external RSET resistor connected to Pin 5 and ground, along with the internal digital settings applied to the PLL (see the Register 4—Charge Pump, PFD, and Reference Path Control section for more details). 18 19 20 47nH 0603CS 5.1nH 0402CS 150pF +VCC TC1-1-13M+ 1nF T3 IF OUT 68nH 0402CS 1pF GJM 5.1nH 0402CS 150pF 1nF Figure 54. 900 MHz Output Matching Network Using the TC1-1-13M+ 1:1 Impedance Ratio Balun and External Pull-Up Choke Inductors (Output return loss measured to be better than 12 dB from 815 MHz to 1075 MHz.) ADRF6655 OUTN OUTP GND 1200MHz OUTPUT INTERFACE 18 19 20 47nH 0603CS 2.1nH 0302CS 150pF +VCC TC1-1-13M+ 1nF IF OUT T3 OUTPUT MATCHING AND BIASING The ADRF6655 output stage consists of collector connected output transistors with on-board pull-up resistors. The output transistors and pull-up network presents a 200 Ω differential output impedance in parallel with a small amount of shunt capacitance. The measured RC equivalent impedance of Pin 18 and Pin 19 is ~250 Ω//1.5 pF. This impedance needs to be taken into consideration when designing the external output matching network. In addition to matching the presented output source impedance to the intended load impedance, it is important to provide pull-up choke connections to the supply pins to allow for dc current to directly supply the mixer output transistors. The reactance of the pull-up chokes may need to be considered when designing the output matching network. For convenience, several output matching/bias networks are presented in Figure 53 through Figure 58 for reference. 17nH 0302CS 1.8pF GJM 2.1nH 47nH 0603CS 1nF +VCC 150pF 08817-057 Figure 55. 1200 MHz Output Matching Network (Output return loss measured to be better than 12 dB from 950 MHz to 1500 MHz.) ADRF6655 OUTN OUTP GND 1300MHz OUTPUT INTERFACE 18 19 20 47nH 0603CS 2.7nH 0402CS 150pF +VCC TC1-1-13M+ 1nF IF OUT T3 10nH 0302CS 1.2pF GJM 2.7nH 0402CS 150pF 1nF Figure 56. 1300 MHz Output Matching Network (Output return loss measured to be better than 12 dB from 1075 MHz to 1525 MHz.) Rev. 0 | Page 19 of 44 08817-058 47nH 0603CS +VCC 08817-056 47nH 0603CS +VCC 08817-055 ADRF6655 2 ADRF6655 OUTN OUTP GND 1600MHz OUTPUT INTERFACE 1 0 –1 18 19 20 36nH 0Ω 15nH 1.5pF 0Ω 36nH 150pF –2 1nF IF OUT GAIN (dB) 08817-059 VCC 1nF –3 –4 –5 –6 –7 –8 900MHz MATCH –9 1200MHz MATCH 1600MHz MATCH –10 0.7 0.8 0.9 1.0 1.1 T6 VCC 150pF ANAREN BD1722J50200A00 1nF 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 OUTPUT FREQUENCY (GHz) ADRF6655 OUTN OUTP GND 2100MHz OUTPUT INTERFACE Figure 60. Measured Conversion Gain for 900 MHz, 1200 MHz, and 1600 MHz Matching Networks (See Figure 54, Figure 55, and Figure 57 for Implementation) 18 19 20 INPUT MATCHING 150pF 27nH 3pF 0603CS 3pF VCC TC1-1-13M+ 1nF IF OUT T3 1nF VCC 150pF Figure 58. 2100 MHz Output Matching Network (Output return loss measured to be better than 12 dB from 2000 MHz to 2200 MHz.) 35 OUTPUT IP3 OUTPUT IP3 AND OUTPUT P1dB (dBm) 30 25 20 15 10 5 0 0.7 08817-060 27nH 0603CS The ADRF6655 uses a balanced 50 Ω input impedance to help simplify external connections. For low loss interfacing, the driving source should be transformed to present a balanced 50 Ω source impedance. An appropriate 1:1 impedance ratio input balun should be used when attempting to interface to an unbalanced 50 Ω source. For input frequencies below ~1.5 GHz, the TC1-1-13M+ from Mini-Circuits or similar baluns should provide good return loss and maximum power gain. For higher frequencies, baluns, such as the TC1-1-43A+, are recommended for lowest insertion loss. The ac coupling capacitors can be optimized with the balun to provide optimum input match. A few examples are provided in Figure 61 for a range of different IF output frequencies. 0 TC1-1-43A+ WITH 10pF AC COUPLING TC1-1-43A+ WITH 3pF AC COUPLING TC1-1-43A+ WITH 1.8pF AC COUPLING –5 900MHz MATCH 1200MHz MATCH 1600MHz MATCH –10 OUTPUT P1dB S11 (dB) –15 –20 –25 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 OUTPUT FREQUENCY (GHz) 08817-061 –30 –35 0.5 1.0 1.5 2.0 2.5 3.0 FREQUENCY (GHz) Figure 61. Measured RF Input Return Loss Using the TC1-1-43A+ 1:1 Balun (Plotted for Several AC Coupling Capacitor Values) It is also possible to use lumped element LC lattice networks to transform an unbalanced source into a balanced source at the mixer input pins. In either case, the mixer input pins should be dc blocked using adequately sized series capacitors. Rev. 0 | Page 20 of 44 08817-063 Figure 59. Measured Output Linearity for 900 MHz, 1200 MHz, and 1600 MHz Matching Networks (See Figure 54, Figure 55, and Figure 57 for Implementation) 08817-062 Figure 57. 1600 MHz Output Matching Network (Output return loss measured to be better than 12 dB from 1400 MHz to 1680 MHz.) ADRF6655 IP3SET LINEARIZATION FEATURE The IP3SET pin (Pin 29) controls the overall current consumption of the mixer core depending on the applied voltage. If left open, the voltage on the IP3SET pin is ~2.3 V, and a typical input IP3 of ~25 dBm or higher can be expected across the operating frequency range. As the IP3SET voltage is increased, the overall supply current increases and the input IP3 can be improved from ~3 dB to 6 dB. For upconversion applications, an IP3SET voltage of ~3.2 V to 3.3 V results in very high output IP3 performance in excess of 30 dBm. Using an external resistor divider network connected between VCC and GND, the IP3SET voltage can be derived. Alternatively, the on-board 3.3 V LDO output (Pin 2) can be used to derive the applied IP3SET voltage. However, it is advisable to use good bypassing and a series inductor or ferrite choke to ensure good high frequency isolation between Pin 1 and Pin 29. If an auxiliary control DAC is available, the IP3SET pin can be driven dynamically in applications where power levels are changing over time, and it is desirable to conserve power at lower input signal levels. Figure 62 and Figure 63 illustrate the output linearity dependency on the IP3SET voltage. Note that gain is independent of the IP3SET voltage. 33 32 31 30 CDAC LINEARIZATION FEATURE In addition to the IP3SET broadband linearization solution, the ADRF6655 also includes a special linearizer designed to provide enhanced IP3 performance at higher input frequencies. At low input frequencies, the CDAC setting offers very little influence on input IP3, and a CDAC setting of 15 is usually recommended. At high input frequencies, the CDAC setting can boost input IP3 as much as 5 dB with essentially no increase in supplied power. At a given input frequency, the ADRF6655 offers an optimum CDAC setting to provide high input IP3 performance. The recommended optimum CDAC setting vs. RF input frequency is shown in Figure 64. 15 14 13 12 11 10 9 CDAC BEST CDAC AT 25°C INTERCEPT BEST CDAC AT 85°C 8 7 6 5 4 3 2 1 08817-066 OUTPUT IP3 (dBm) 29 28 27 26 25 24 23 22 OUTPUT FREQUENCY = 1210MHz OUTPUT FREQUENCY = 1500MHz 20 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 21 IP3SET (V) 0 1840 1940 2040 2140 2240 2340 2440 RF FREQUENCY (MHz) Figure 64. Optimum CDAC Setting for Downconversion vs. RF Input Frequency EXTERNAL LO INTERFACE The ADRF6655 provides the option to use an external signal source for the LO into the mixer. It is important to note that the applied LO signal is divided by 2 or divided by 3 prior to the actual mixer core within the ADRF6655. The divider is determined by the register settings in LO path and mixer control register, (see the Register 5—LO Path and Mixer Control section). The LO input pins (Pin 37 and Pin 38) present a broadband balanced 50 Ω input interface similar to the input pins (Pin 25 and Pin 26). The LOP and LON input pins should be dc blocked and driven from a balanced 50 Ω source. When not in use, the LOP and LON pins may be left unconnected. Figure 62. Output IP3 vs. IP3SET Voltage for Output Frequency 20 18 16 14 12 10 8 6 4 2 0 –2 –4 –6 –8 OUTPUT FREQUENCY = 1210 MHz OUTPUT FREQUENCY = 1500 MHz –10 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 OUTPUT FREQUENCY (MHz) GAIN OUTPUT P1dB GAIN (dB) Figure 63. Output P1dB and Gain vs. IP3SET Voltage 08817-112 08817-111 Rev. 0 | Page 21 of 44 ADRF6655 USING AN EXTERNAL VCO The ADRF6655 has the necessary provisions for interfacing an external VCO. A high performance discrete VCO may be desirable in applications that call for the very best phase noise performance. The basic circuit connections for interfacing an external VCO are included in Figure 65. It is important to select a VCO with a frequency tuning voltage range that covers the available charge pump output compliance range of 1 V to 2.8 V. The external VCO waveform needs to pass through the on-chip divide-by-2/divideby-3 programmable dividers before reaching the mixer. As a result, the VCO center frequency should be selected to be roughly 2× or 3× the desired LO signal frequency. The available output power for the selected VCO should be greater than −10 dBm to ensure adequate signal levels into the mixer core. The charge pump loop filter components should be designed to provide adequate phase margin for the given KVCO tuning sensitivity of the selected VCO. It is important to properly configure the digital registers for external VCO operation. When using an external VCO, the internal VCO should be disabled using DB17 in Register 6. Other register programmable LDOs, including the VCO LDO (DB18 in Register 6), should be enabled. For more information on programming the ADRF6655, see the ADRF6655 Control Software section. EXTERNAL VCO VTUNE LINE CHARGE PUMP LOOP FILTER +5V NC 40 39 38 37 36 35 LOP LON +5V 1 2 3 4 VCC1 DECL1 CP GND RSET REFIN GND 08817-067 RSET 5 EXTERNAL REFERENCE 6 7 Figure 65. External VCO Connections Rev. 0 | Page 22 of 44 VTUNE DECL3 ADRF6655 GND GND ADRF6655 ADRF6655 CONTROL SOFTWARE The ADRF6655 can be controlled from most PCs that include a parallel port output interface. A USB adapter board is also available from Analog Devices, Inc., to allow for control from PCs that do not have an accessible parallel port. The USB adapter evaluation documentation and ordering information can be found at www.analog.com by searching for EVAL-ADF4XXXZ-USB. The basic user interfaces are depicted in Figure 66 and Figure 67. After launching the software, the user is prompted to select a device from the ADRF product family. Upon selecting the ADRF6655, the main control interface should appear as shown in Figure 66. The main control interface allows the user to configure the device for various modes of operation. The internal synthesizer is controlled by clicking on any of the numeric values listed in the RF Section. Attempting to program the REF Input Frequency, the PFD Frequency, the VCO Frequency [2×LO], or other values in the RF section launches the Synthesizer Settings— ADRF6655 Broadband Mixer control module depicted in Figure 67. From the Synthesizer Settings control interface, the user can enter the desired Local Oscillator Frequency (MHz), Channel Step Resolution (kHz), and External Reference Frequency (MHz). The user can also enable the LO output buffer and divider options from this menu. After setting the desired values, it is important to click Upload All Registers and Windows for the new settings to take effect. Figure 67. ADRF6655 Synthesizer Settings User Interface PLL LOOP FILTER DESIGN Designing the external loop filter, which connects between the charge pump output and VCO tuning control pin, is easy with the help of ADIsimPLL. ADIsimPLL is a free software application available from Analog Devices for designing PLL loop filters. Several passive filter topologies are support in ADIsimPLL along with the necessary component placements on the evaluation board. When designing a PLL loop filter, it is important to consider settling time and phase noise requirements. Figure 68 provides measured phase noise performance for a typical fast and slow loop filter design. Note that the wider loop filter offers better close-in phase noise but degraded phase noise at greater offset frequencies. The narrow 1.5 kHz loop filter design provides the best phase noise at 100 kHz and 1 MHz carrier offsets but with the penalty of decreased frequency settling time and poorer close-in performance. 0 –20 –40 ADRF6655 1.5kHz LOOP FILTER LO = 2275MHz LO = 1100Hz –80 –100 –120 67kHz LOOP FILTER –140 –160 08817-071 PHASE NOISE (dBc/Hz) –60 Figure 66. ADRF6655 Software Control Interface 08817-069 –180 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (Hz) Figure 68. Phase Noise with Different Loop Filters Rev. 0 | Page 23 of 44 08817-070 ADRF6655 REGISTER STRUCTURE INTEGER DIVIDE CONTROL REGISTER (R0) RESERVED DB23 0 DB22 0 DB21 0 DB20 0 DB19 0 DB18 0 DB17 0 DB16 0 DB15 0 DB14 0 DB13 0 DB12 0 DIVIDE MODE DB11 DB10 0 DM DB9 DB8 ID6 ID5 INTEGER DIVIDE RATIO DB7 ID4 DB6 ID3 DB5 ID2 DB4 ID1 DB3 ID0 CONTROL BITS DB2 C3(0) DB1 C2(0) DB0 C1(0) MODULUS DIVIDE CONTROL REGISTER (R1) RESERVED DB23 0 DB22 0 DB21 0 DB20 0 DB19 0 DB18 0 DB17 0 DB16 0 DB15 0 DB14 0 DB13 MD10 DB12 MD9 DB11 MD8 MODULUS DIVIDE VALUE DB10 MD7 DB9 DB8 DB7 DB6 DB5 MD2 DB4 DB3 MD1 MD0 MD6 MD5 MD4 MD3 CONTROL BITS DB2 C3(0) DB1 C2(0) DB0 C1(1) FRACTIONAL DIVIDE CONTROL REGISTER (R2) RESERVED DB23 0 DB22 0 DB21 0 DB20 0 DB19 0 DB18 0 DB17 0 DB16 0 DB15 0 DB14 0 DB13 PD10 DB12 PD9 DB11 PD8 FRACTIONAL DIVIDE VALUE DB10 PD7 DB9 PD6 DB8 PD5 DB7 PD4 DB6 PD3 DB5 PD2 DB4 DB3 PD1 PD0 CONTROL BITS DB2 C3(0) DB1 C2(1) DB0 C1(0) Σ-Δ MODULATOR DITHER CONTROL REGISTER (R3) DITHER DITHER MAGNITUDE ENABLE DB23 0 DB22 DB21 DB20 DEN DITH1 DITH0 DITHER RESTART VALUE DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DB9 DV6 DB8 DV5 DB7 DV4 DB6 DV3 DB5 DV2 DB4 DV1 DB3 DV0 CONTROL BITS DB2 C3(0) DB1 C2(1) DB0 C1(1) CHARGE PUMP, PFD, AND REFERENCE PATH CONTROL REGISTER (R4) OUPUT MUX SOURCE DB23 DB22 INPUT REF PATH SOURCE CP REF DB18 CPM PDF PHASE OFFSET POLARITY PFD PHASE OFFSET MULTIPLIER VALUE CP CP CURRENT CNTL MULTIPLIER SRC CHARGE PUMP CONTROL DB8 DB7 PFD ANTIPFD EDGE BACKLASH SENSITIVITY DELAY DB6 PE1 DB5 PE0 DB4 DB3 CONTROL BITS DB2 DB1 C2(0) DB0 C1(0) DB21 DB20 DB19 RS0 DB17 CPBD DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 RMS2 RMS1 RMS0 RS1 CPB4 CPB3 CPB2 CPB1 CPB0 CPP1 CPP0 CPS CPC1 CPC0 PAB1 PAB0 C3(1) LO PATH AND MIXER CONTROL REGISTER (R5) MIXER LO LO OUTPUT CDAC DISTORTION PLL LO BIAS IN/OUT DRIVER COMPENSATION CONTROL BITS ENABLE ENABLE DIV 2/3 CNTRL ENABLE SETTING DB2 DB1 DB0 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 C3(1) C2(0) C1(1) 0 0 0 0 0 0 0 0 0 0 0 0 CDAC3 CDAC2 CDAC1 CDAC0 MBE PLEN LDIV LXL LDRV RESERVED VCO CONTROL AND PLL ENABLES REGISTER (R6) RESERVED DB23 DB22 DB21 0 0 0 CHARGE LDO VCO VCO VCO PUMP 3.3V LDO SWITCH ENABLE ENABLE ENABLE ENABLE CONTROL DB20 CPEN DB19 L3EN DB18 LVEN DB17 VCOEN DB16 VCOSW VCO AMPLITUDE SETTING VCO BS SRC VCO BAND SELECT CONTROL BITS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VC5 VC4 VC3 VC2 VC1 VC0 VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0) EXTERNAL VCO CONTROL REGISTER (R7) EXTERNAL VCO RES ENABLE DB23 0 DB22 XVCO 0 0 0 0 0 0 0 0 0 RESERVED DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 0 0 0 DB9 0 DB8 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 CONTROL BITS DB2 C3(1) DB1 C2(1) DB0 C1(1) 08817-068 Figure 69. Register Maps for ADRF6655 (The three control bits determine which register is programmed.) Rev. 0 | Page 24 of 44 ADRF6655 DEVICE PROGRAMMING The device is programmed through a 3-pin SPI port. The timing requirements for the SPI port are described in Figure 2. There are eight programmable registers, each with 24 bits, controlling the operation of the device. The register functions can be broken down as follows: • • • • • • • • Register 0—integer divide control Register 1—modulus divide control Register 2—fractional divide control Register 3—Σ-Δ modulator dither control Register 4—charge pump, PFD, and reference path control Register 5—LO path and mixer control Register 6—VCO controls and PLL enables Register 7—external VCO control INITIALIZATION SEQUENCE To ensure proper power-up of the ADRF6655, it is important to reset the PLL circuitry after the supply rail (VCC1, VCC2, VCCLO, VCCV2I, and VCCMIX) has settled to 5 V ± 0.25 V. Resetting the PLL ensures that the internal bias cells are properly configured even under poor supply start-up conditions. To ensure that the PLL is reset after power-up, the PLEN data bit (DB6) in Register 5 should be programmed to disable the PLL (PLEN = 0). After a delay of >100 ms, Register 5 should be programmed to enable the PLL (PLEN = 1). After this procedure, the registers should be programmed as follows: 1. 2. 3. 4. 5. 6. 7. 8. Register 7 Register 6 Register 4 Register 3 Register 2 Register 1 Delay >1 ms Register 0 Note that the PLL has internal calibration that must run whenever the device is programmed with a given frequency. This calibration is automatically run whenever Register 0, Register 1, or Register 2 is programmed. Software is available from Analog Devices that allows easy programming from an external PC. See the ADRF6655 Control Software section for additional details. When programming the frequency of the ADRF6655, normally only Register 2, Register 1, and Register 0 are programmed. When programming these registers, a short delay of >500 μs should be placed before programming the last register in the sequence (Register 0). This ensures that the VCO band calibration initiated by the first two register writes has sufficient time to complete before the final band calibration (for Register 0) is initiated. Rev. 0 | Page 25 of 44 ADRF6655 REGISTER 0—INTEGER DIVIDE CONTROL With R0[2:0] set to 000, the on-chip integer divide control register is programmed as shown in Figure 70. Divide Mode Divide mode determines whether fractional mode or integer mode is used. In integer mode, the RF VCO output frequency (fVCO) is calculated by fVCO = 2 × fPFD × (INT) (2) where INT is the integer divide ratio value (21 to 123 in integer mode). Integer Divide Ratio The integer divide ratio is used to set the INT value in Equation 1. The INT, FRAC, and MOD values make it possible to generate output frequencies that are spaced by fractions of the PFD frequency. The VCO frequency (FVCO) equation is fVCO = 2 × fPFD × (INT + (FRAC/MOD)) (1) where: fVCO is the output frequency of the internal VCO. fPFD is the frequency of operation of the phase-frequency detector. INT is the preset integer divide ratio value (24 to 119 in fractional mode). MOD is the preset fractional modulus (1 to 2047). FRAC is the preset fractional divider ratio value (0 to MOD − 1). RESERVED DB23 0 DB22 0 DB21 0 DB20 0 DB19 0 DB18 0 DB17 0 DB16 0 DB15 0 DB14 0 DB13 0 DB12 0 DB11 0 DIVIDE MODE DB10 DM INTEGER DIVIDE RATIO DB9 DB8 ID6 ID5 DB7 ID4 DB6 ID3 DB5 ID2 DB4 ID1 DB3 ID0 CONTROL BITS DB2 C3(0) DB1 C2(0) DB0 C1(0) DM 0 1 DIVIDE MODE FRACTIONAL INTEGER ID6 0 0 0 0 ... ... 0 ... ... 1 1 1 1 1 ID5 0 0 0 0 ... ... 1 ... ... 1 1 1 1 1 ID4 1 1 1 1 ... ... 1 ... ... 1 1 1 1 1 ID3 0 0 0 1 ... ... 1 ... ... 0 1 1 1 1 ID2 1 1 1 0 ... ... 0 ... ... 1 0 0 0 0 ID1 0 1 1 0 ... ... 0 ... ... 1 0 0 1 1 ID0 1 0 1 0 ... ... 0 ... ... 1 0 1 0 1 INTEGER DIVIDE RATIO 21 (INTEGER MODE ONLY) 22 (INTEGER MODE ONLY) 23 (INTEGER MODE ONLY) 24 ... ... 56 ... ... 119 120 (INTEGER MODE ONLY) 121 (INTEGER MODE ONLY) 08817-072 122 (INTEGER MODE ONLY) 123 (INTEGER MODE ONLY) Figure 70. Integer Divide Control Register (R0) Rev. 0 | Page 26 of 44 ADRF6655 REGISTER 1—MODULUS DIVIDE CONTROL With R1[2:0] set to 001, the on-chip modulus divide control register is programmed as shown in Figure 71. The MOD value is the preset fractional modulus ranging from 1 to 2047. RESERVED DB23 DB22 0 0 DB21 0 DB20 0 DB19 0 DB18 0 DB17 0 DB16 0 DB15 0 DB14 0 DB13 MD10 DB12 MD9 DB11 MD8 DB10 MD7 REGISTER 2—FRACTIONAL DIVIDE CONTROL With R2[2:0] set to 010, the on-chip fractional divide control register is programmed as shown in Figure 72. The FRAC value is the preset fractional modulus ranging from 0 to MOD − 1. MODULUS DIVIDE RATIO DB9 MD6 DB8 MD5 DB7 MD4 DB6 MD3 DB5 MD2 DB4 MD1 DB3 MD0 CONTROL BITS DB2 C3(0) DB1 C2(0) DB0 C1(1) MD10 0 0 ... ... 0 ... ... 1 MD9 0 0 ... ... 0 ... ... 1 MD8 0 0 ... ... 0 ... ... 1 MD7 0 0 ... ... 0 ... ... 1 MD6 0 0 ... ... 1 ... ... 1 MD5 0 0 ... ... 1 ... ... 1 MD4 0 0 ... ... 0 ... ... 1 MD3 0 0 ... ... 0 ... ... 1 MD2 0 0 ... ... 0 ... ... 1 MD1 0 1 ... ... 0 ... ... 1 MD0 1 0 ... ... 0 ... ... 1 MODULUS VALUE 1 2 ... ... 1536 ... ... 2047 08817-073 Figure 71. Modulus Divide Control Register (R1) RESERVED DB23 0 DB22 0 DB21 0 DB20 0 DB19 0 DB18 0 DB17 0 DB16 0 DB15 0 DB14 0 DB13 FD10 DB12 FD9 DB11 FD8 DB10 FD7 FRACTIONAL DIVIDE VALUE DB9 FD6 DB8 FD5 DB7 FD4 DB6 FD3 DB5 FD2 DB4 FD1 DB3 FD0 CONTROL BITS DB2 C3(0) DB1 C2(1) DB0 C1(0) FD10 0 0 ... ... 0 ... ... FD9 0 0 ... ... 1 ... ... FD8 0 0 ... ... 1 ... ... FD7 0 0 ... ... 0 ... ... FD6 0 0 ... ... 0 ... ... FD5 0 0 ... ... 0 ... ... FD4 0 0 ... ... 0 ... ... FD3 0 0 ... ... 0 ... ... FD2 0 0 ... ... 0 ... ... FD1 0 0 ... ... 0 ... ... FD0 0 1 ... ... 0 ... ... FRACTIONAL VALUE 0 1 ... ... 768 ... ...