5.9 GHz to 23.6 GHz,
Wideband, Microwave Upconverter
ADRF6780
Data Sheet
FEATURES
GENERAL DESCRIPTION
Wideband RF output frequency range: 5.9 GHz to 23.6 GHz
Two upconversion modes
Direct conversion from baseband I/Q to RF
Single sideband upconversion from real IF
LO input frequency range: 5.4 GHz to 14 GHz
LO doubler for up to 28 GHz
Matched 100 Ω balanced RF output, LO input, and IF input
High impedance baseband inputs
Sideband suppression and carrier feedthrough optimization
Variable attenuator and power detector for Tx power control
Programmable via 4-wire SPI interface
32-lead, 5 mm × 5 mm LFCSP microwave packaging
The ADRF6780 is a silicon germanium (SiGe) design, wideband,
microwave upconverter optimized for point to point microwave
radio designs operating in the 5.9 GHz to 23.6 GHz frequency
range.
The upconverter offers two modes of frequency translation. The
device is capable of direct conversion to radio frequency (RF)
from baseband I/Q input signals, as well as single sideband (SSB)
upconversion from a real intermediate frequency (IF) input
carrier frequency. The baseband inputs are high impedance and
are generally terminated off chip with 100 Ω differential back
terminations. The baseband I/Q input path can be disabled and
a modulated real IF signal anywhere from 0.8 GHz to 3.5 GHz can
fed into the IF input path and upconverted to 5.9 GHz to 23.6 GHz
while suppressing the unwanted sideband by typically better than
25 dBc. The serial port interface (SPI) allows tweaking of the
quadrature phase adjustment to allow optimum sideband
suppression. In addition, the SPI interface allows powering down
the output power detector to reduce power consumption when
power monitoring is not necessary.
APPLICATIONS
Point to point microwave radios
Radar, electronic warfare systems
Instrumentation, automatic test equipment (ATE)
The ADRF6780 upconverter comes in a compact, thermally
enhanced, 5 mm × 5 mm LFCSP package. The ADRF6780
operates over the −40°C to +85°C temperature range.
FUNCTIONAL BLOCK DIAGRAM
ALM
VPLO
LOIP
AGND
LOIN
VPLO
SEN
SDTO
32
31
30
29
28
27
26
25
1
VPDT
2
VPRF
3
AGND
4
RFOP
5
SPI
LOG
DET
×1
×2
BIAS
CONTROL
QUAD
SPLITTER
BUFFER
VVA
24
SCLK
23
SDIN
22
VP18
21
VPBI
20
IFIP
AGND
6
19
AGND
RFON
7
18
IFIN
AGND
8
17
RST
ADRF6780
9
10
VPRF
VATT
11
12
BBQN BBQP
13
14
15
16
BBIP
BBIN
VPBB
PWDN
14106-001
ADC
VDET
Figure 1.
Rev. D
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Tel: 781.329.4700 ©2016–2019 Analog Devices, Inc. All rights reserved.
Technical Support
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ADRF6780
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Carrier Feedthrough Nulling .................................................... 23
Applications ....................................................................................... 1
Sideband Suppression Optimization ....................................... 23
General Description ......................................................................... 1
Linearity ....................................................................................... 23
Functional Block Diagram .............................................................. 1
ADC ............................................................................................. 23
Revision History ............................................................................... 2
Wide Frequency Performance .................................................. 24
Specifications..................................................................................... 3
Layout .......................................................................................... 24
Absolute Maximum Ratings ............................................................ 6
LO Input Driven Differential vs. Single Ended .......................... 25
Thermal Resistance ...................................................................... 6
Register Summary .......................................................................... 27
ESD Caution .................................................................................. 6
Register Details: Wideband Upconverter .................................... 28
Pin Configuration and Function Descriptions ............................. 7
Control Register ......................................................................... 28
Typical Performance Characteristics ............................................. 9
ALARM_READBACK Register ............................................... 28
I/Q Mode ....................................................................................... 9
ALARM_MASK Register .......................................................... 29
IF Mode........................................................................................ 14
Enable Register ........................................................................... 29
Output Detector Performance .................................................. 19
Linearize Register ....................................................................... 30
Return Loss.................................................................................. 20
LO_PATH Register..................................................................... 30
Theory of Operation ...................................................................... 21
ADC_CONTROL Register ....................................................... 31
Baseband ...................................................................................... 21
ADC_OUTPUT Register .......................................................... 31
Single Sideband (SSB) Upconversion ...................................... 21
Basic Connections for Operation ................................................. 32
LO Input Path.............................................................................. 21
Outline Dimensions ....................................................................... 35
Serial Port Interface (SPI) .......................................................... 21
Ordering Guide .......................................................................... 35
Applications Information .............................................................. 23
REVISION HISTORY
1/2019—Rev. C to Rev. D
Changes to ADC Section ............................................................... 23
7/2018—Rev. B to Rev. C
Changed 32.95 to 9.18 in θJA Column, Table 3 ............................. 6
Changes to Ordering Guide .......................................................... 35
10/2017—Rev. A to Rev. B
Changes to Maximum Junction Temperature Parameter, Table 2 ... 6
Change to Table 4 ......................................................................................... 7
Changes to Figure 31 Caption ................................................................. 13
Changes to Ordering Guide..................................................................... 35
5/2016—Rev. 0 to Rev. A
Change to Table 4 ............................................................................. 7
Changes to Figure 40 ...................................................................... 15
Changes to Figure 47 ...................................................................... 16
Changes to Figure 58 ...................................................................... 18
Change to Figure 84 ....................................................................... 33
Changes to Table 16 ........................................................................ 34
3/2016—Revision 0: Initial Version
Rev. D | Page 2 of 35
Data Sheet
ADRF6780
SPECIFICATIONS
VPBB = VPBI = VPLO = 3.3 V, VP18 = 1.8 V, VPDT = VPRF = 5 V, TA = 25°C, LO = 0 dBm differential drive; baseband I/Q amplitude =
−15 dBm differential sine waves in quadrature with a 500 mV dc bias, baseband input termination with 100 Ω externally, IF amplitude =
−12 dBm differential sine waves, unless otherwise noted.
Table 1.
Parameter
RF OUTPUT FREQUENCY RANGE
LOCAL OSCILLATOR (LO) INPUT
FREQUENCY RANGE
LO AMPLITUDE RANGE
IF INPUT FREQUENCY RANGE
BASEBAND (BB) I/Q INPUT FREQUENCY
RANGE
I/Q MODULATOR PERFORMANCE
Modulator Voltage Gain
Output Noise Density
Output Third-Order Intercept (OIP3)
5.9 GHz to 10 GHz
10 GHz to 14 GHz
14 GHz to 20 GHz
20 GHz to 23.6 GHz
Fifth-Order Intermodulation Distortion
(IMD5)
Output Second-Order Intercept (OIP2)
5.9 GHz to 10 GHz
10 GHz to 14 GHz
14 GHz to 20 GHz
20 GHz to 23.6 GHz
Output 1 dB Compression Point (P1dB)
5.9 GHz to 10 GHz
10 GHz to 14 GHz
14 GHz to 20 GHz
20 GHz to 23.6 GHz
LO Feedthrough
Sideband Suppression
Test Conditions/Comments
Maximum gain at maximum gain setting
Minimum gain at minimum gain setting
Output carrier > −5 dBm
Output carrier > −14 dBm
Output carrier > −22.5 dBm
f1BB = 10 MHz, f2BB = 12 MHz, baseband I/Q amplitude
per tone = −15 dBm sine waves in quadrature with a
500 mV dc bias, 10 dB gain setting
f1 BB = 10 MHz, f2 BB = 12 MHz, baseband I/Q amplitude
per tone = −15 dBm sine waves in quadrature with a
500 mV dc bias, 10 dB gain setting
f1 BB = 10 MHz, f2 BB = 12 MHz, baseband I/Q amplitude
per tone = −15 dBm sine waves in quadrature with a
500 mV dc bias, 10 dB gain setting
At 10 dB gain setting
At maximum gain setting
At 10 dB gain setting
At maximum gain setting
At 10 dB gain setting
At maximum gain setting
At 10 dB gain setting
At maximum gain setting
At 10 dB gain setting (can be improved baseband dc
offset adjustment)
At 10 dB gain setting
Rev. D | Page 3 of 35
Min
5.9
5.4
Typ
Max
23.6
14
Unit
GHz
GHz
−6
0.8
DC
0
+6
3.5
750
dBm
GHz
MHz
10
13
−12
−147
−145
−136
dB
dB
dBc/Hz
dBc/Hz
dBc/Hz
24
25
27
27
65
dBm
dBm
dBm
dBm
dBm
65
65
66
50
dBm
dBm
dBm
dBm
10.5
11
11
12
10
12
10
11
−25
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
25
dBc
ADRF6780
Parameter
IF UPCONVERTER PERFORMANCE
Upconversion Voltage Gain
Output Noise Density
OIP3
5.9 GHz to 10 GHz
10 GHz to 14 GHz
14 GHz to 20 GHz
20 GHz to 23.6 GHz
IMD5
Output P1dB
5.9 GHz to 10 GHz
10 GHz to 14 GHz
14 GHz to 20 GHz
20 GHz to 23.6 GHz
LO Feedthrough
Sideband Suppression
Tx POWER DETECTOR PERFORMANCE
Output Level
Maximum
Minimum
±1 dB Dynamic Range
Output Voltage
Maximum
Minimum
Log Slope
Time
Rise
Fall
Response
RETURN LOSS
RF Output
LO Input
IF Input
Baseband I/Q Input Impedance
LOGIC INPUTS
Input High Voltage Range, VINH
Input Low Voltage Range, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
Data Sheet
Test Conditions/Comments
Min
Typ
Maximum gain at maximum gain setting
Minimum gain at minimum gain setting
Output carrier > −5 dBm
Output carrier > −14 dBm
Output carrier > −22.5 dBm
f1 IF = 1810 MHz, f2 IF = 1812 MHz, amplitude per tone
= −15 dBm sine waves in quadrature with ac bias,
7 dB gain setting
7
11
−14
−147
−145
−136
23.5
dB
dB
dBc/Hz
dBc/Hz
dBc/Hz
27
24
22.5
22.5
80
dBm
dBm
dBm
dBm
dBm
10.5
11.5
10
12
9.5
12
9.5
11.5
−35
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
25
dBc
2
−30
34
dBm
dBm
dB
1
0.2
25
V
V
mV/dB
134
ns
190
ns
30
ns
12
12
17
1
dB
dB
dB
MΩ
f1 IF = 1810 MHz, f2 IF = 1812 MHz, amplitude per tone
= −15 dBm sine waves in quadrature with ac bias,
7 dB gain setting
At 7 dB gain setting
At maximum gain setting
At 7 dB gain setting
At maximum gain setting
At 7 dB gain setting
At maximum gain setting
At 7 dB gain setting
At maximum gain setting
At 7 dB gain setting (can be improved by baseband dc
offset adjustment)
At 7 dB gain setting
PIN = off to −10 dBm, 10% to 90%,
C7 = 10 pF (see Figure 83)
PIN = −10 dBm to off, 10% to 90%,
C7 = 10 pF (see Figure 83)
C7 = 10 pF (see Figure 83)
100 Ω differential
100 Ω differential
100 Ω differential
VP18 − 0.4
0
1.8
0.4
100
3
Rev. D | Page 4 of 35
Max
Unit
V
V
µA
pF
Data Sheet
Parameter
LOGIC OUTPUTS
Output High Voltage Range, VOH
Output Low Voltage Range, VOL
Output High Current, IOH
POWER INTERFACE
VPBB, VPLO, VPBI
VPBB, VPLO, VPBI Supply Current
VP18
VP18 Supply Current
VPDT, VPRF
VPDT, VPRF Supply Current
Total Power Consumption
ADRF6780
Test Conditions/Comments
Min
Typ
VP18 − 0.4
0
3.15
×1 LO path enabled, IF path disabled
×2 LO path enabled, IF path disabled
×1 LO path enabled, IF path enabled
×2 LO path enabled, IF path enabled
1.7
4.75
×1/×2 LO path enabled, IF path disabled
×1/×2 LO path enabled, IF path enabled
×2 LO path enabled, IF path enabled
Power down
Rev. D | Page 5 of 35
3.3
340
390
490
540
1.8
1
5
180
160
2.58
35
Max
Unit
1.8
0.4
500
V
V
µA
3.45
V
mA
mA
mA
mA
V
mA
V
mA
mA
W
mW
1.9
5.25
50
ADRF6780
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
Supply Voltage
VPDT, VPRF
VPBB, VPLO, VPBI
VP18
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range (Soldering 60 sec)
θJA is thermal resistance, junction to ambient (°C/W), and θJC is
thermal resistance, junction to case (°C/W).
Rating
6.5 V
4.3 V
2.3 V
125°C
−40°C to +85°C
−55°C to +125°C
−65°C to +150°C
Table 3. Thermal Resistance
Package Type
32-Lead LFCSP
1
θJA1
9.18
θJC1
1.14
Unit
°C/W
See JEDEC Standard JESD51-2 for additional information on optimizing the
thermal impedance (printed circuit board (PCB) with 3 × 3 vias).
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. D | Page 6 of 35
Data Sheet
ADRF6780
32
31
30
29
28
27
26
25
PIN 1
INDICATOR
ALM
VPLO
LOIP
AGND
LOIN
VPLO
SEN
SDTO
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
ADRF6780
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
SCLK
SDIN
VP18
VPBI
IFIP
AGND
IFIN
RST
NOTES
1. SOLDER THE EXPOSED PAD TO A LOW IMPEDANCE
GROUND PLANE.
2. THE DEVICE NUMBER ON THE FIGURE DOES NOT
INDICATE THE LABEL ON THE PACKAGE. PLEASE
REFER TO PIN 1 INDICATOR FOR PIN LOCATIONS.
14106-002
VPRF
VATT
BBQN
BBQP
BBIP
BBIN
VPBB
PWDN
9
10
11
12
13
14
15
16
VDET
VPDT
VPRF
AGND
RFOP
AGND
RFON
AGND
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
Mnemonic
VDET
2
VPDT
3, 9
VPRF
4, 6, 8,
19, 29
5, 7
10
AGND
11 to
14
BBQN, BBQP,
BBIP, BBIN
15
VPBB
16
PWDN
17
RST
18, 20
IFIN, IFIP
21
VPBI
22
23
VP18
SDIN
24
25
SCLK
SDTO
26
SEN
RFOP, RFON
VATT
Description
RF Detector Output. The voltage output is proportional to the decibel RF output power. The detector slope is
nominally 50 mV/dB.
Power Supply Connection for the RF Detector. Decouple the VPDT pin with 100 pF and 0.1 µF capacitors as
close as possible to the pin. Note that this pin must always be supplied with 5 V.
Power Supply Connections for the RF Path. Decouple the VPRF pin with 100 pF and 0.1 µF capacitors as close
as possible to the pins.
Analog Grounds. Connect these pins to a low impedance ground plane.
RF Outputs. These outputs are 100 Ω differential outputs for the RF path. Frequency range is 5.9 GHz to 23.6 GHz.
Modulator Output Attenuator Control Input. The RF voltage variable attenuator is controlled by applying a
0 V to 2.6 V control voltage to the VATT pin. Increase the gain when VATT voltage increases. This pin is linear in
dB over central gain range.
I Channel and Q Channel Baseband Inputs. These inputs are high input impedance and are typically differentially
terminated to a 100 Ω resistor using an off chip termination. The nominal common-mode bias level on these
pins must be 0.5 V.
Power Supply Connection for Baseband Path. Decouple the VPBB pin with 100 pF and 0.1 µF capacitors as
close as possible to the pin.
Power Down. The ADRF6780 powers up when the PWDN pin is at a low logic level (1.2 V). When the ADRF6780 is powered up, the SPI can also be used
as a power-down capability. The PWDN pin has an internal 18 kΩ pull-down resistor.
Reset. This pin provides the ability to reset the SPI to the default register settings. Pull the RST pin to a logic
high level in normal operation. Driving the RST pin to a logic low level loads the default SPI register settings.
The RST pin has an internal 7.75 kΩ pull-up resistor.
IF Inputs. These inputs are 100 Ω differential inputs for IF upconversion, and they must be ac-coupled.
When the IF mode is set, remove the 0 Ω R10 to R13 resistors from the I/Q lines.
Power Supply Connection. Decouple the VPBI pin with 100 pF and 0.1 µF capacitors as close as possible to
the pin.
1.8 V Power Supply. Decouple the VP18 pin with 100 pF and 0.1 µF capacitors as close as possible to the pin.
Serial Data Input. Serial data applied to the SDIN pin is loaded into the SPI register upon a successful write
command as indicated in the timing diagrams (see Figure 68 to Figure 70). The first most significant bit (MSB)
is a control bit and it determines whether data is written to the register (logic high) or read from the serial
data output pin (logic low). The SDIN pin has an internal 18 kΩ pull-down resistor.
Serial Clock. This pin is the clock input for the SPI interface. The SCLK pin has an internal 18 kΩ pull-down resistor.
Serial Data Output. The SDTO pin provides a SPI readback capability. See the timing diagrams for normal
operation (see Figure 68 to Figure 70). The SDTO pin has an internal 18 kΩ pull-down resistor.
Serial Enable. When the SEN input pin goes high, the data stored in the shift registers is loaded into the
register. The SEN pin has an internal 7.75 kΩ pull-up resistor.
Rev. D | Page 7 of 35
ADRF6780
Pin No.
27, 31
Mnemonic
VPLO
28, 30
LOIN, LOIP
32
ALM
EP
Data Sheet
Description
Power Supply Connections for the LO Path. Decouple the VPLO pin with 100 pF and 0.1 µF capacitors as close
as possible to the pin.
LO Inputs. These inputs are 100 Ω differential inputs for the LO path. The LO input frequency range is 5.4 GHz
to 14 GHz. The on-chip LO frequency doubler can be enabled via a SPI command.
Alarm. The ALM pin indicates internal alarm conditions. The ALM pin is logic low when an alarm condition is
detected.
Exposed Pad. Solder the exposed pad to a low impedance ground plane.
Rev. D | Page 8 of 35
Data Sheet
ADRF6780
TYPICAL PERFORMANCE CHARACTERISTICS
VPBB = VPBI = VPLO = 3.3 V, VP18 = 1.8 V, VPDT = VPRF = 5 V, TA = 25°C, LO = 0 dBm differential drive, polyphase filter (PPF, ×1)
mode below 14 GHz and differential drive doubler (×2) mode above 14 GHz, VATT = 2.6 V, unless otherwise noted.
I/Q MODE
Baseband (BB) I/Q amplitude = −15 dBm, differential sine waves in quadrature with a 500 mV dc bias, BB I/Q frequency (fx BB) = 10 MHz,
BB input termination with 100 Ω externally, unless otherwise noted.
5
15
fRF = 6GHz
fRF = 10GHz
fRF = 15GHz
fRF = 20GHz
fRF = 24GHz
VATT = 2.6V
0
10
CONVERSION GAIN (dB)
–5
POUT (dBm)
–10
VATT = 1.5V
–15
–20
VATT = 0.4V
–25
5
0
–5
–30
–10
5
7
9
11
13
15
17
19
21
23
25
RF FREQUENCY (GHz)
–15
0.4
14106-003
–40
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
14106-006
–40°C
+25°C
+85°C
–35
2.6
VATT (V)
Figure 3. Output Power (POUT) vs. RF Frequency (fRF) at Three Gain Settings for
Various Temperatures, BB I/Q Amplitude = −15 dBm
Figure 6. Conversion Gain vs. VATT for Various RF Frequencies (fRF)
5
15
VATT = 2.6V
0
10
–5
VATT = 1.5V
P1dB (dBm)
POUT (dBm)
–10
–15
–20
VATT = 0.4V
5
0
–25
–30
–5
5
7
9
11
13
15
17
19
21
23
25
RF FREQUENCY (GHz)
–10
14106-004
–40
–40°C
+25°C
+85°C
5
7
9
11
13
15
17
19
21
23
25
RF FREQUENCY (GHz)
Figure 4. Output Power (POUT) vs. RF Frequency (fRF) at Three Gain Settings for
Various Supply Voltages, BB I/Q Amplitude = −15 dBm
14106-008
4.75V/3.15V
5.00V/3.30V
5.25V/3.45V
–35
Figure 7. Output 1 dB Compression Point (P1dB) vs. RF Frequency (fRF) at a 10
dB Gain Setting for Various Temperatures
5
15
0
VATT = 2.6V
10
–5
VATT = 1.5V
P1dB (dBm)
POUT (dBm)
–10
–15
–20
VATT = 0.4V
5
0
–25
–30
5
7
9
–5
LO = –3dBm
LO = –6dBm
LO = –9dBm
11
13
15
4.75V/3.15V
5.00V/3.30V
5.25V/3.45V
17
19
RF FREQUENCY (GHz)
21
23
25
–10
5
7
9
11
13
15
17
19
RF FREQUENCY (GHz)
Figure 5. Output Power (POUT) vs. RF Frequency (fRF) at Three Gain Settings for
Various LO Inputs, BB I/Q Amplitude = −15 dBm
21
23
25
14106-009
–40
= +9dBm
= +6dBm
= +3dBm
= 0dBm
14106-005
LO
LO
LO
LO
–35
Figure 8. Output 1 dB Compression Point (P1dB) vs. RF Frequency (fRF) at a
10 dB Gain Setting for Various Supply Voltages
Rev. D | Page 9 of 35
ADRF6780
Data Sheet
0
12
10
CARRIER FEEDTHROUGH (dBm)
8
4
2
0
–2
–4
5
7
9
LO = –3dBm
LO = –6dBm
LO = –9dBm
11
13
15
–20
–30
–40
–50
–60
–70
17
19
21
23
25
RF FREQUENCY (GHz)
–80
Figure 9. Output 1 dB Compression Point (P1dB) vs. RF Frequency (fRF) at a 10
dB Gain Setting for Various LO Inputs
9
11
13
15
17
19
21
23
25
Figure 12. Carrier Feedthrough vs. RF Frequency (fRF) at Three Gain Settings
and Temperatures Before Nulling
60
SIDEBAND SUPPRESSION (dB)
10
P1dB (dBm)
7
RF FREQUENCY (GHz)
15
5
0
–5
50
40
30
20
10
+85°C, VATT = 2.6V
+85°C, VATT = 1.5V
+85°C, VATT = 0.4V
MAXIMUM GAIN
10dB GAIN
5
7
9
11
13
15
17
19
21
23
25
RF FREQUENCY (GHz)
0
14106-011
–10
5
14106-012
–6
= +9dBm
= +6dBm
= +3dBm
= 0dBm
14106-010
LO
LO
LO
LO
–40°C, VATT = 2.6V
–40°C, VATT = 1.5V
–40°C, VATT = 0.4V
+25°C, VATT = 2.6V
+25°C, VATT = 1.5V
+25°C, VATT = 0.4V
Figure 10. Output 1 dB Compression Point (P1dB) vs. RF Frequency (fRF) at a
10 dB Gain Setting and the Maximum Gain Setting
5
7
9
11
–40°C, VATT = 2.6V
–40°C, VATT = 1.5V
–40°C, VATT = 0.4V
+25°C, VATT = 2.6V
+25°C, VATT = 1.5V
+25°C, VATT = 0.4V
13
15
17
19
21
23
25
RF FREQUENCY (GHz)
14106-013
P1dB (dBm)
6
–8
+85°C, VATT = 2.6V
+85°C, VATT = 1.5V
+85°C, VATT = 0.4V
–10
Figure 13. Sideband Suppression vs. RF Frequency (fRF) at Three Gain Settings
and Temperatures Before Nulling
80
15
P1dB (dBm)
5
0
–5
60
50
40
30
20
10
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
BB INPUT FREQUENCY (GHz)
1.6
1.8
2.0
0
14106-211
–10
Figure 11. Output 1 dB Compression Point (P1dB) vs. BB Input Frequency at a
10 dB Gain Setting
+85°C, VATT = 2.6V
+85°C, VATT = 1.5V
+85°C, VATT = 0.4V
5
7
9
11
–40°C, VATT = 2.6V
–40°C, VATT = 1.5V
–40°C, VATT = 0.4V
+25°C, VATT = 2.6V
+25°C, VATT = 1.5V
+25°C, VATT = 0.4V
13
15
17
19
RF FREQUENCY (GHz)
21
23
25
14106-014
SIDEBAND SUPPRESSION (dB)
70
10
Figure 14. Sideband Suppression vs. RF Frequency (fRF) at Three Gain Settings
and Temperatures after Nulling Using I_PATH_PHASE_ACCURACY and
Q_PATH_PHASE_ACCURACY at 25°C
Rev. D | Page 10 of 35
Data Sheet
ADRF6780
80
80
–40°C
+25°C
+85°C
70
60
50
50
40
30
30
20
20
10
10
5
7
9
11
13
15
17
19
21
23
25
RF FREQUENCY (GHz)
Figure 15. Third-Order Intermodulation Distortion (IMD3) vs. RF Frequency
(fRF) at a 10 dB Gain Setting for Various Temperatures, BB I/Q Amplitude =
−15 dBm per Tone
80
70
70
60
60
50
50
30
20
5
10
11
13
15
17
19
21
23
25
40
30
10
15
20
25
RF FREQUENCY (GHz)
0
14106-215
0
9
20
–40°C, RDAC_LINEARIZE
+25°C, RDAC_LINEARIZE
+85°C, RDAC_LINEARIZE
–40°C
+25°C
+85°C
10
7
LO = –3dBm
LO = –6dBm
LO = –9dBm
Figure 18. Third-Order Intermodulation Distortion (IMD3) vs. RF Frequency
(fRF) at a 10 dB Gain Setting for Various LO Inputs, BB I/Q Amplitude = −15
dBm per Tone
80
40
5
= +9dBm
= +6dBm
= +3dBm
= 0dBm
RF FREQUENCY (GHz)
IMD3 (dBm)
IMD3 (dBc)
0
LO
LO
LO
LO
Figure 16. Third-Order Intermodulation Distortion (IMD3) vs. RF Frequency
(fRF) at a 10 dB Gain Setting for Various RDAC_LINEARIZE Settings and Various
Temperatures, BB I/Q Amplitude = −15 dBm per Tone
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
BB INPUT FREQUENCY (GHz)
14106-219
0
Figure 19. Third-Order Intermodulation Distortion (IMD3) vs. BB Input
Frequency at a 10 dB Gain Setting, BB I/Q Amplitude = −15 dBm per Tone
80
70
4.75V/3.15V
5.00V/3.30V
5.25V/3.45V
70
60
60
50
50
IMD3 (dBc)
IMD3 (dBc)
40
14106-019
IMD3 (dBc)
60
14106-017
IMD3 (dBc)
70
40
40
30
30
20
10
10
5
7
9
11
13
15
17
19
RF FREQUENCY (GHz)
21
23
25
0
–30
14106-117
0
Figure 17. Third-Order Intermodulation Distortion (IMD3) vs. RF Frequency
(fRF) for Various Supply Voltages,
BB I/Q Amplitude = −15 dBm per Tone
fRF = 6GHz
fRF = 10GHz
fRF = 15GHz
fRF = 20GHz
fRF = 24GHz
–25
–20
–15
–10
–5
POUT (dBm PER TONE; PIN = –15dBm PER TONE)
0
14106-021
20
Figure 20. Third-Order Intermodulation Distortion (IMD3) vs. Output Power
(POUT) for Various RF Frequencies (fRF),
BB I/Q Amplitude = −15 dBm per Tone
Rev. D | Page 11 of 35
Data Sheet
80
35
70
30
60
25
50
20
15
30
10
20
5
10
5
7
9
11
13
15
17
19
21
23
25
RF FREQUENCY (GHz)
Figure 21. Output Third-Order Intercept (OIP3) vs. RF Frequency (fRF) at a 10
dB Gain Setting, BB I/Q Amplitude = −15 dBm per Tone
–20
–10
–15
0
–5
Figure 24. Fifth-Order Intermodulation Distortion (IMD5) vs. Output Power
(POUT) for Various RF Frequencies,
BB I/Q Amplitude = −15 dBm per Tone
fRF = 6GHz
fRF = 10GHz
fRF = 15GHz
fRF = 20GHz
fRF = 24GHz
30
70
60
OIP2 (dBm)
25
20
50
40
15
30
10
20
5
10
–23
–21
–19
–17
–15
–13
–11
–9
–7
–5
BB INPUT POWER (dBm PER TONE)
0
14106-222
0
–25
Figure 22. Output Third-Order Intercept (OIP3) vs. BB Input Power at a 10 dB
Gain Setting for Various RF Frequencies (fRF)
70
60
60
50
50
OIP2 (dBm)
70
30
20
20
LO
LO
LO
LO
10
–40°C
+25°C
+85°C
9
11
13
15
17
19
RF FREQUENCY (GHz)
21
23
25
0
14106-023
7
Figure 23. Fifth-Order Intermodulation Distortion (IMD5) vs. RF Frequency
(fRF) at a 10 dB Gain Setting for Various Temperatures, BB I/Q Amplitude =
−15 dBm per Tone
9
11
13
15
17
19
21
23
25
40
30
5
7
Figure 25. Output Second-Order Intercept (OIP2) vs. RF Frequency (fRF) at a 10
dB Gain Setting for Various Temperatures,
BB I/Q Amplitude = −15 dBm per Tone
80
10
5
RF FREQUENCY (GHz)
80
40
–40°C
+25°C
+85°C
14106-025
35
0
–25
POUT (dBm PER TONE; PIN = –15dBm PER TONE)
80
40
OIP3 (dBm)
0
–30
fRF = 6GHz
fRF = 10GHz
fRF = 15GHz
fRF = 20GHz
fRF = 24GHz
5
7
= +9dBm
= +6dBm
= +3dBm
= 0dBm
9
LO = –3dBm
LO = –6dBm
LO = –9dBm
11
13
15
17
19
RF FREQUENCY (GHz)
21
23
25
14106-026
0
IMD5 (dBc)
40
14106-024
IMD5 (dBc)
40
14106-020
OIP3 (dBm)
ADRF6780
Figure 26. Output Second-Order Intercept (OIP2) vs. RF Frequency (fRF) at a 10
dB Gain Setting for Various LO Inputs,
BB I/Q Amplitude = −15 dBm per Tone
Rev. D | Page 12 of 35
Data Sheet
80
5
60
POUT AT 15GHz, MAX GAIN (dBm)
fRF = 6GHz
fRF = 10GHz
fRF = 15GHz
fRF = 20GHz
fRF = 24GHz
70
OIP2 (dBm)
ADRF6780
50
40
30
20
0
–5
–10
–15
–20
–15
–10
–5
0
POUT (dBm PER TONE; PIN = –15dBm PER TONE)
–20
10
MAGNITUDE DELTA, RFON TO RFOP (dB)
–40°C
+25°C
+85°C
CARRIER TO NOISE (dBc/Hz)
150
145
140
135
9
11
13
15
17
19
21
23
25
RF FREQUENCY (GHz)
Figure 28. Output Noise Density vs. RF Frequency (fRF) at a 10 dB Gain Setting
for Various Temperatures with an Output Carrier of −5 dBm
155
CARRIER TO NOISE (dBc/Hz)
150
135
4
9
14
14106-028
130
–1
1.2
1.4
1.6
1.8
2.0
6
4
2
0
–2
–4
–6
–8
7
9
11
13
15
17
19
21
23
25
Figure 31. Magnitude Delta, RFON minus RFOP vs. RF Frequency (fRF) at
Three Different Gain Settings
140
VATT GAIN (dB)
1.0
RF FREQUENCY (GHz)
fRF = 6GHz
fRF = 10GHz
fRF = 15GHz
fRF = 20GHz
fRF = 24GHz
–6
0.8
VATT = 2.6V
VATT = 1.5V
VATT = 0.4V
8
5
145
125
–11
0.6
–10
14106-127
130
7
0.4
Figure 30. Bandwidth, POUT at 15 GHz and the Maximum Gain Setting vs. BB
Input Frequency
155
5
0.2
BB FREQUENCY (GHz)
Figure 27. Output Second-Order Intercept (OIP2) vs. Output Power (POUT) for
Various RF Frequencies (fRF), BB I/Q Amplitude = −15 dBm per Tone
125
0
14106-031
–25
14106-227
0
–30
14106-230
10
Figure 29. Output Noise Density vs. VATT Gain for Various RF Frequencies
(fRF) with an Input Carrier of −15 dBm
Rev. D | Page 13 of 35
ADRF6780
Data Sheet
IF MODE
IF frequency (IF mode) = 1900 MHz, IF amplitude = −12 dBm, input ac-coupled, unless otherwise noted.
15
5
fRF = 6GHz
fRF = 10GHz
fRF = 15GHz
fRF = 20GHz
fRF = 24GHz
VATT = 2.6V
0
10
POUT (dBm)
–10
CONVERSION GAIN (dB)
–5
VATT = 1.5V
–15
VATT = 0.4V
–20
–25
5
0
–5
–30
5
7
9
11
13
15
17
19
21
23
25
RF FREQUENCY (GHz)
–15
0.4
14106-037
–40
0.8
1.0
1.2
1.6
1.4
2.0
1.8
2.2
2.4
2.6
VATT (V)
Figure 32. Output Power (POUT) vs. RF Frequency (fRF) at Three Gain Settings
for Various Temperatures, IF Amplitude = −12 dBm
Figure 35. Conversion Gain vs. VATT at Various RF Frequencies (fRF)
5
15
–40°C
+25°C
+85°C
VATT = 2.6V
0
10
–5
–10
VATT = 1.5V
P1dB (dBm)
POUT (dBm)
0.6
14106-040
–10
–40°C
+25°C
+85°C
–35
–15
VATT = 0.4V
–20
5
0
–25
–30
–5
5
7
9
11
13
15
17
19
21
23
25
RF FREQUENCY (GHz)
–10
14106-038
–40
Figure 33. Output Power (POUT) vs. RF Frequency (fRF) at Three Gain Settings
for Various Supply Voltages, IF Amplitude = −12 dBm
7
9
11
13
15
17
19
21
23
25
RF FREQUENCY (GHz)
Figure 36. Output 1 dB Compression Point (P1dB) vs. RF Frequency (fRF) at a
7 dB Gain Setting for Various Temperatures
5
15
VATT = 2.6V
0
10
–5
–10
VATT = 1.5V
P1dB (dBm)
POUT (dBm)
5
14106-035
4.75/3.15
5.00/3.30
5.25/3.45
–35
–15
VATT = 0.4V
–20
5
0
–25
–30
–5
5
7
9
LO = –3dBm
LO = –6dBm
LO = –9dBm
11
13
15
17
19
RF FREQUENCY (GHz)
21
23
25
Figure 34. Output Power (POUT) vs. RF Frequency (fRF) at Three Gain Settings
for Various LO Inputs, IF Amplitude = −12 dBm
4.75V/3.15V
5.00V/3.30V
5.25V/3.45V
–10
5
7
9
11
13
15
17
19
RF FREQUENCY (GHz)
21
23
25
14106-137
–40
= +9dBm
= +6dBm
= +3dBm
= 0dBm
14106-039
LO
LO
LO
LO
–35
Figure 37. Output 1 dB Compression Point (P1dB) vs. RF Frequency (fRF) at a
7 dB Gain Setting for Various Supply Voltages
Rev. D | Page 14 of 35
Data Sheet
ADRF6780
0
15
+85°C, VATT = 2.6V
+85°C, VATT = 1.5V
+85°C, VATT = 0.4V
–10
CARRIER FEEDTHROUGH (dBm)
10
0
–5
–15
LO
LO
LO
LO
5
= +9dBm
= +6dBm
= +3dBm
= 0dBm
7
9
LO = –3dBm
LO = –6dBm
LO = –9dBm
11
13
15
13
19
–20
–30
–40
–50
–60
–70
17
19
21
23
25
RF FREQUENCY (GHz)
–80
14106-138
–10
–40°C, VATT = 2.6V
–40°C, VATT = 1.5V
–40°C, VATT = 0.4V
Figure 38. Output 1 dB Compression Point (P1dB) vs. RF Frequency (fRF) at a
7 dB Gain Setting for Various LO Inputs
5
7
9
11
15
17
21
23
25
RF FREQUENCY (GHz)
14106-047
P1dB (dBm)
5
+25°C, VATT = 2.6V
+25°C, VATT = 1.5V
+25°C, VATT = 0.4V
Figure 41. Carrier Feedthrough vs. RF Frequency (fRF) at Three Gain Settings
for Various Temperatures Before Nulling
40
15
35
5
0
–5
30
25
20
15
10
5
5
9
7
11
13
15
17
19
21
23
25
RF FREQUENCY (GHz)
0
14106-139
–10
MAXIMUM GAIN
7dB GAIN
Figure 39. 1 dB Output Compression Point (P1dB) vs. RF Frequency (fRF) at a
7 dB Gain Setting and the Maximum Gain Setting
+85°C, VATT = 2.6V
+85°C, VATT = 1.5V
+85°C, VATT = 0.4V
5
7
9
11
–40°C, VATT = 2.6V
–40°C, VATT = 1.5V
–40°C, VATT = 0.4V
+25°C, VATT = 2.6V
+25°C, VATT = 1.5V
+25°C, VATT = 0.4V
13
15
17
19
21
23
25
RF FREQUENCY (GHz)
14106-048
SIDEBAND SUPPRESSION (dB)
P1dB (dBm)
10
Figure 42. Sideband Suppression vs. RF Frequency (fRF) at Three Different
Gain Settings for Various Temperatures Before Nulling
80
15
70
10
5
IMD3 (dBc)
P1dB AT 15GHz (dBm)
60
0
50
40
30
20
–5
10
1.5
2.0
2.5
IF FREQUENCY (GHz)
3.0
3.5
4.0
0
Figure 40. Output 1 dB Compression Point (P1dB) at 15 GHz vs. IF Frequency
at a 7 dB Gain Setting
5
7
9
11
13
15
17
19
RF FREQUENCY (GHz)
21
23
25
14106-050
1.0
14106-240
–10
0.5
–40°C
+25°C
+85°C
Figure 43. Third-Order Intermodulation Distortion (IMD3) vs. RF Frequency (fRF) at
a 7 dB Gain Setting for Various Temperatures, IF Amplitude = −15 dBm per
Tone
Rev. D | Page 15 of 35
ADRF6780
Data Sheet
80
100
90
70
80
IMD3 AT 15GHz (dBc)
60
60
50
40
30
9
7
11
13
15
17
19
21
23
25
RF FREQUENCY (GHz)
70
70
60
60
50
50
IMD3 (dBc)
80
30
20
20
0
10
4.45V
5.00V
5.25V
5
7
9
11
13
15
17
19
21
23
25
RF FREQUENCY (GHz)
Figure 45. Third-Order Intermodulation Distortion (IMD3) vs. RF Frequency (fRF)
at a 7 dB Gain Setting and for Various Supply Voltages,
IF Amplitude = −15 dBm per Tone
0
–30
35
60
30
50
25
OIP3 (dBm)
70
3.5
4.0
fRF = 6GHz
fRF = 10GHz
fRF = 15GHz
fRF = 20GHz
fRF = 24GHz
–25
–20
–15
–10
0
–5
20
15
10
20
5
7
= +9dBm
= +6dBm
= +3dBm
= 0dBm
9
LO = –3dBm
LO = –6dBm
LO = –9dBm
11
13
15
5
17
19
RF FREQUENCY (GHz)
21
23
25
0
14106-052
LO
LO
LO
LO
10
0
3.0
Figure 48. Third-Order Intermodulation Distortion (IMD3) vs. Output Power
(POUT) for Various RF Frequencies (fRF), IF Amplitude = −15 dBm per Tone
40
30
2.5
POUT (dBm PER TONE; PIN = –15dBm PER TONE)
80
40
2.0
40
30
10
1.5
Figure 47. Third-Order Intermodulation Distortion (IMD3) at 15 GHz vs.
IF Frequency at a 7 dB Gain Setting
80
40
1.0
IF FREQUENCY (GHz)
14106-051
IMD3 (dBc)
Figure 44. Third-Order Intermodulation Distortion (IMD3) vs. RF Frequency (fRF)
at 7 dB Gain Setting for Various RDAC_LINEARIZE Settings and Various
Temperatures, IF Amplitude = −15 dBm per Tone
IMD3 (dBm)
0
0.5
14106-147
5
14106-053
0
30
10
14106-243
10
40
20
–40°C, RDAC_LINEARIZE
+25°C, RDAC_LINEARIZE
+85°C, RDAC_LINEARIZE
–40°C
+25°C
+85°C
20
50
Figure 46. Third-Order Intermodulation Distortion (IMD3) vs. RF Frequency (fRF) at
a 7 dB Gain Setting for Various LO Inputs, IF Amplitude = −15 dBm per Tone
5
7
9
11
13
15
17
19
RF FREQUENCY (GHz)
21
23
25
14106-148
IMD3 (dBc)
70
Figure 49. Output Third-Order Intercept (OIP3) vs. RF Frequency (fRF) at a 7 dB
Gain Setting, IF Amplitude = −15 dBm per Tone
Rev. D | Page 16 of 35
Data Sheet
ADRF6780
35
30
60
OIP2 (dBm)
25
20
15
40
30
20
5
10
–23
–21
–19
–17
–15
–13
–11
–9
–7
–5
IF INPUT POWER (dBm PER TONE)
Figure 50. Output Third-Order Intercept (OIP3) vs. IF Input Power at a
7 dB Gain Setting for Various RF Frequencies (fRF)
0
5
7
9
11
13
15
17
19
21
23
25
RF FREQUENCY (GHz)
Figure 53. Output Second-Order Intercept (OIP2) vs. RF Frequency (fRF) at a 7
dB Gain Setting for Various Temperatures, IF Amplitude = −15 dBm per Tone
90
80
80
70
70
LO
LO
LO
LO
= +9dBm
= +6dBm
= +3dBm
= 0dBm
LO = –3dBm
LO = –6dBm
LO = –9dBm
60
OIP2 (dBm)
60
IMD5 (dBc)
50
10
0
–25
–40°C
+25°C
+85°C
70
14106-250
OIP3 (dBm)
80
fRF = 6GHz
fRF = 10GHz
fRF = 15GHz
fRF = 20GHz
fRF = 24GHz
14106-057
40
50
40
50
40
30
30
20
20
7
9
11
13
15
17
19
21
23
25
RF FREQUENCY (GHz)
0
5
7
9
11
13
15
17
19
21
23
25
RF FREQUENCY (GHz)
Figure 51. Fifth-Order Intermodulation Distortion (IMD5) vs. RF Frequency (fRF) at
a 7 dB Gain Setting for Various Temperatures,
IF Amplitude = −15 dBm per Tone
14106-058
5
14106-055
0
10
–40°C
+25°C
+85°C
10
Figure 54. Output Second-Order Intercept (OIP2) vs. RF Frequency (fRF) at a 7
dB Gain Setting for Various LO Inputs, IF Amplitude = −15 dBm per Tone
90
80
80
70
70
60
fRF = 6GHz
fRF = 10GHz
fRF = 15GHz
fRF = 20GHz
fRF = 24GHz
OIP2 (dBm)
50
40
30
10
0
–30
fRF = 6GHz
fRF = 10GHz
fRF = 15GHz
fRF = 20GHz
fRF = 24GHz
–25
40
30
20
10
–20
–15
–10
–5
POUT (dBm PER TONE; PIN = –15dBm PER TONE)
0
0
–30
14106-056
20
50
–25
–20
–15
–10
–5
POUT (dBm PER TONE; PIN = –15dBm PER TONE)
Figure 52. Fifth-Order Intermodulation Distortion (IMD5) vs. Output Power
(POUT) for Various RF Frequencies (fRF), IF Amplitude = −15 dBm per Tone
0
14106-059
IMD5 (dBc)
60
Figure 55. Output Second-Order Intercept (OIP2) vs. Output Power (POUT) for
Various RF Frequencies (fRF), IF Amplitude = −15 dBm per Tone
Rev. D | Page 17 of 35
ADRF6780
Data Sheet
155
5
–40°C
+25°C
+85°C
140
135
125
5
7
9
11
13
15
17
19
21
23
25
RF FREQUENCY (GHz)
Figure 56. Output Noise Density vs. RF Frequency (fRF) at a 7 dB Gain Setting
for Various Temperatures with an Output Carrier of −5 dBm
CARRIER TO NOISE (dBc/Hz)
150
140
135
–8
–3
2
VATT GAIN (dB)
7
12
14106-156
130
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Figure 58. Bandwidth, POUT at 15 GHz and Maximum Gain Setting vs.
IF Frequency (fIF)
10
fRF = 6GHz
fRF = 10GHz
fRF = 15GHz
fRF = 20GHz
fRF = 24GHz
145
125
–13
–15
IF FREQUENCY (GHz)
MAGNITUDE DELTA, RFON TO RFOP (dB)
155
–10
–20
0.5
14106-155
130
–5
Figure 57. Output Noise Density vs. VATT Gain for Various RF Frequencies (fRF)
with an Input Carrier of −12 dBm
Rev. D | Page 18 of 35
VATT = 2.6V
VATT = 1.5V
VATT = 0.4V
8
6
4
2
0
–2
–4
–6
–8
–10
5
7
9
11
13
15
17
19
RF FREQUENCY (GHz)
21
23
25
14106-159
145
0
14106-158
POUT AT 15GHz, MAX GAIN (dBm)
CARRIER TO NOISE (dBc/Hz)
150
Figure 59. Magnitude Delta, RFON to RFOP vs. RF Frequency (fRF) at
Three Different Gain Settings
Data Sheet
ADRF6780
OUTPUT DETECTOR PERFORMANCE
1.2
1.4
–40°C
+25°C
+85°C
1.2
1.0
VDET (V)
0.8
0.6
0.6
0.4
0.2
0.2
–30
–25
–20
–15
–10
–5
0
5
10
POUT AT 15GHz (dBm)
Figure 60. Detector Output (VDET) vs. Output Power (POUT) at 15 GHz for
Various Temperatures
5
–40°C
+25°C
+85°C
4
3
2
1
0
–1
–2
–3
–4
–5
–35
–30
–25
–20
–15
–10
–5
0
5
10
POUT AT 15GHz (dBm)
14106-061
DETECTOR ERROR (dB)
0.8
0.4
14106-060
VDET (V)
1.0
0
–35
–40°C
+25°C
+85°C
Figure 61. Detector Error vs. Output Power (POUT) at 15 GHz for
Various Temperatures
Rev. D | Page 19 of 35
0
5
7
9
11
13
15
17
19
21
23
RF FREQUENCY (GHz)
Figure 62. Detector Output (VDET) vs. RF Frequency (fRF),
−5 dBm Output Power (POUT) for Various Temperatures
25
14106-062
1.4
ADRF6780
Data Sheet
RETURN LOSS
0
0
–40°C
+25°C
+85°C
–5
–10
–15
–20
7
9
11
13
15
17
19
21
23
25
RF FREQUENCY (GHz)
–25
14106-263
5
–40°C, BASEBAND I PORT
+25°C, BASEBAND I PORT
+85°C, BASEBAND I PORT
–40°C, BASEBAND Q PORT
+25°C, BASEBAND Q PORT
+85°C, BASEBAND Q PORT
0
1
2
3
4
5
6
IQ FREQUENCY (GHz)
Figure 63. RF Output Return Loss S11 vs. RF Frequency for Various
Temperatures
Figure 65. I/Q Input Return Loss S11 vs. I/Q Frequency for Various
Temperatures
0
0
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
–5
RETURN LOSS (dB)
–5
–10
–15
–20
–10
–15
–20
5
7
9
11
13
15
17
19
21
23
25
LO FREQUENCY (GHz)
Figure 64. LO Input Return Loss S11 vs. LO Frequency for Various
Temperatures
–30
0
1
2
3
4
IF FREQUENCY (GHz)
5
6
14106-266
–25
14106-264
RETURN LOSS (dB)
–15
–20
–25
–25
–10
14106-265
RETURN LOSS (dB)
RETURN LOSS (dB)
–5
Figure 66. IF Input Return Loss S11 vs. IF Frequency for Various Temperatures
Rev. D | Page 20 of 35
Data Sheet
ADRF6780
THEORY OF OPERATION
The ADRF6780 is a wideband microwave upconverter optimized
for point to point microwave radio designs operating in the
5.9 GHz to 23.6 GHz frequency range. A functional block
diagram of the device is shown in Figure 1. The ADRF6780 is
programmed via an SPI.
Figure 67 shows a block diagram of the LO path.
LOIP
LOIN
×2
AMP1
PPF
MUX
BASEBAND
The input impedance of the basebands are high input impedance.
These inputs are designed to operate with a 0.5 V commonmode voltage. These inputs are differentially terminated to a
100 Ω resistor using an off chip termination.
The linearity can be optimized by adding phase correction
signals to the current output via adjusting the I_PATH_PHASE_
ACCURACY register (Register 0x05, Bits[3:0]) and the Q_PATH_
PHASE_ACCURACY (Register 0x05, Bits[7:4]) register.
SINGLE SIDEBAND (SSB) UPCONVERSION
The IF input path can be fed anywhere from 0.8 GHz to 3.5 GHz.
The IF inputs path can be upconverted to 5.9 GHz to 23.6 GHz,
while suppressing the unwanted sideband by typically better than
25 dBc. The IF upconversion inputs are 100 Ω differential and
must be ac-coupled. In addition, the I/Q baseband input must stay
floating without any termination on their inputs.
LO INPUT PATH
The LO input path operates from 5.4 GHz to 14 GHz with a LO
amplitude range of −6 dBm to +6 dBm. It is built from two modes:
×1 mode (Register 0x03, Bit 2), which provides an LO output
frequency equal to the LO input frequency, and ×2 mode
(Register 0x03, Bit 3), which doubles the LO output frequency
from the LO input frequency. Note that, when enabling the LO
×2 mode (Register 0x03, Bit 3), the LO ×1 mode (Register 0x03,
Bit 2) must be disabled.
The LO path is designed to operate differentially. LOIP and
LOIN are the inputs to the LO path. It is recommended to
use the ADRF6780 with a LO differential input to achieve the
best performance.
14106-078
PPF
Figure 67. LO Path Block Diagram
SERIAL PORT INTERFACE (SPI)
The SPI of the ADRF6780 allows the user to configure the device
for specific functions or operations via a 4-pin SPI port. This
interface provides users with added flexibility and customization.
The SPI consists of four control lines: SCLK, SDIN, SDTO,
and SEN.
The ADRF6780 protocol consists of a write/read bit followed by
six register address bits, 16 data bits, and a parity bit. Both the
address and data fields are organized MSB first and end with the
least significant bit (LSB). For a write, set the first bit to 0, and
for a read, set this bit to 1.
The write cycle sampling must be done on the rising edge. The
16 bits of the serial write data are shifted in, MSB to LSB. The
ADRF6780 input logic level for the write cycle supports an 1.8 V
interface.
For a read cycle, up to 16 bits of serial read data are shifted out,
MSB first. After the 16 bits of data shift out, the parity bit shifts
out. The output logic level for a read cycle is 1.8 V.
The parity bit always follows the direction of the data. If parity
is not used, the transmitting end transmits zero instead of parity.
The parity is odd, which means that the total number of ones
transmitted during a command, including the read/write bit,
the address bit, the data bit, and the parity bit, must be odd.
Table 5. Serial Port Register Timing
Parameter
tDI, SETUP
tDI, HOLD
tCLK, HIGH
tCLK, LOW
tCLK, SEN_SETUP
Description
Data to clock setup time
Data to clock hold time
Clock high duration
Clock low duration
Clock to SEN setup time
Min
10
10
40 to 60
40 to 60
30
tCLK, DOT
tCLK, DOV
tCLK, SEN_INACTIVE
Clock to data out transition time
Clock to data out valid time
Clock to SEN inactive
tSEN_INACTIVE
Inactive SEN (between two operations)
Rev. D | Page 21 of 35
Typ
Max
Unit
ns
ns
%
%
ns
10
10
20
ns
ns
ns
80
ns
ADRF6780
Data Sheet
tCLK, HIGH
tCLK, LOW
SCLK
tCLK, SEN_SETU P
tSEN_INACTIVE
SEN
tCLK, DOT
tCLK, SEN_INACTIVE
tCLK, DOV
SDIN
14106-079
tDI, HOLD
tDI, SETUP
SDTO
Figure 68. Serial Port Register Timing Diagram
SEN
1
2
3
4
5
6
7
8
9
D15
D14
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SDIN
R/W
A5
A4
A3
A2
A1
A0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
P
14106-080
SCLK
Figure 69. Write Serial Port Timing Diagram
SEN
1
2
3
4
5
6
7
8
9
D15
D14
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SCLK
SDTO
R/W
A5
A4
A3
A2
A1
A0
D13
D12
D11
D10
D9
D8
D7
Figure 70. Read Serial Port Timing Diagram
Rev. D | Page 22 of 35
D6
D5
D4
D3
D2
D1
D0
P
14106-081
SDIN
Data Sheet
ADRF6780
APPLICATIONS INFORMATION
300
ADC VALUE
DETECTOR VOLTAGE(V)
1.25
1.05
200
150
0.65
100
Figure 14 shows the level of unwanted sideband signal achievable
from the ADRF6780 across the I_PATH_PHASE_ACCURACY
bits (Register 0x05, Bits[3:0]) and Q_PATH_PHASE_ACCURACY
(Register 0x05, Bits[7:4]) bits.
0
–35
0.25
0.05
–31
–27
–23
–19
–15
–11
–7
–3
1
RF OUTPUT POWER (dBm)
Figure 71. ADC Detector Output and Detector Output Power, I/Q Mode
300
ADC VALUE
DETECTOR VOLTAGE (V)
1.25
250
1.05
200
0.85
150
0.65
100
0.45
50
If further optimization is needed, adjust the amplitude and
phase externally through a TxDAC.
0
–35
DETECTOR VOLTAGE (V)
The ADRF6780 offers quadrature phase adjustment in the LO
path quadrature signals. Make these adjustments through the
I_PATH_PHASE_ACCURACY bits (Register 0x05, Bits[3:0])
and Q_PATH_PHASE_ACCURACY (Register 0x05, Bits[7:4])
bits to reject the unwanted sideband signal.
50
ADC VALUE
Sideband results from gain and phase imperfections between
the I and Q channels. Sideband also results from the quadrature
error in generating the quadrature LO signals. Quadrature I and Q
signals are constructed in the LO path, and the vector combination
of these signals at the RF output results in suppression of the
unwanted sideband. Deviation from perfect quadrature on these
signals limits the amount of achievable sideband suppression.
0.45
14106-089
SIDEBAND SUPPRESSION OPTIMIZATION
0.85
DETECTOR VOLTAGE (V)
250
0.25
0.05
–31
–27
–23
–19
–15
–11
–7
–3
1
RF OUTPUT POWER (dBm)
LINEARITY
14106-090
Carrier feedthrough results from minute dc offsets that occur on
the differential baseband inputs. In an I/Q modulator, nonzero
differential offsets mix with the LO and result in carrier
feedthrough to the RF output. In addition to this effect, some
of the signal power at the LO input couples directly to the RF
output (this may be because of the bond wire to bond wire coupling
or coupling through the silicon substrate). The net carrier
feedthrough at the RF output is the vector combination of the
signals that appear at the output because of these two effects. A
TxDAC can externally accomplish carrier feedthrough nulling.
SPI. Figure 71 shows normal operation at I/Q mode, an RF output
of 6.7 GHz, an I/Q input of 1 MHz, and a maximum gain. Figure 72
shows normal operation at IF mode and an RF output of 6.7 GHz,
an IF input of 800 MHz, and a maximum gain.
ADC VALUE
CARRIER FEEDTHROUGH NULLING
Figure 72. ADC Detector Output and Detector Output Power, IF Mode
The linearity in the ADRF6780 can be optimized through the
distortion cancellation circuit that is set up by the RDAC_
LINEARIZE bits (Register 0x04, Bits[7:0]) SPI settings. The
distortion cancellation circuit connects in parallel with the
baseband signal path in such a way that the fundamental is
minimally affected whereas the third-order portions cancel to
some degree. Adjusting the value of the RDAC_LINEARIZE
bits (Register 0x04, Bits[7:0]) changes the resistance value in
the cancellation path by fine tuning the amount of third-order
destructively added to the main signal path. It also serves as a
form or predistortion for third-order impedance generated
further down in the signal path.
Figure 16 and Figure 44 show the level of linearity improvement
achievable across the ADRF6780 RDAC_LINEARIZE bits.
ADC
The ADRF6780 includes an ADC that connects to a detector.
The user has an option to read the detector output from the
detector output pin (VDET, Pin 1) or using the ADC from the
The following procedure is to read back from the detector for
the first time. For each subsequent readback, repeat Step 4 to
Step 8. To read back from the detector using the ADC, take the
following steps:
1. Set Bit 7 of Register 0x03 to 1 (DETECTOR_ENABLE).
2. Set Bit 1 of Register 0x06 to 1 (ADC_ENABLE). Write
0x02 to Register 0x06.
3. Set Bit 0 of Register 0x06 to 1 (ADC_CLOCK_ENABLE).
Write 0x03 to Register 0x06.
4. Set Bit 2 of Register 0x06 to 1 (ADC_START). Write 0x07
to Register 0x06.
5. Wait approximately 200 µs for the ADC to be ready.
6. Read back Bit 8 of Register 0x0C to 1 (ADC_STATUS).
When the bit is high, proceed to Step 7.
7. Set Bit 2 of Register 0x06 to 0 (ADC_START).
8. Read back Bits[7:0] of Register 0x0C for the ADC
value (ADC_VALUE).
To disable the ADC, disable the ADC_CLOCK_ENABLE,
ADC_ENABLE, and ADC_START bits.
Rev. D | Page 23 of 35
ADRF6780
Data Sheet
WIDE FREQUENCY PERFORMANCE
LO Path ×1, ×2 Full Range
Figure 73 and Figure 74 show the typical performance of the
ADRF6780 when using values outside of the RF output
frequency range. It is important to understand that this
performance is typical and not guaranteed.
Figure 75 shows the typical performance of the ADRF6780
when the LO input frequency is used within the full frequency
range. It is important to understand that this performance is
typical and not guaranteed.
Figure 73 was tested in I/Q mode with an RF output frequency
of 1 GHz to 31 GHz. The LO input frequency was switched to
LO ×2 doubler mode above 14 GHz.
Figure 75 was tested with the LO path set to ×1 mode and ×2 mode
with a 5.9 GHz to 23.6 GHz frequency range in I/Q mode. It is
recommended to switch to LO ×2 doubler mode above 14 GHz to
achieve better performance out of the device.
Figure 74 was tested in IF mode with an RF output frequency of
1 GHz to 31 GHz. The LO input frequency was switched to LO
×2 doubler mode above 14 GHz.
5
–5
5
–15
POUT (dBm)
–5
–25
–35
–25
–45
–35
MAIN TONE (LO ×1)
MAIN TONE (LO ×2)
SIDEBAND (LO ×1)
SIDEBAND (LO ×2)
–55
–45
–65
–55
1
6
11
16
21
26
31
RF FREQUENCY (GHz)
Figure 73. Output Power (POUT) vs. RF Frequency (fRF) in I/Q Mode at
the Maximum Gain Setting, BB I/Q Amplitude = −15 dBm
7
9
11
13
15
17
19
21
23
25
Figure 75. LO ×1 Mode and LO ×2 Mode, Output Power (POUT) vs.
RF Frequency (fRF) in I/Q Mode at the Maximum Gain Setting,
BB I/Q Amplitude = −15 dBm
LAYOUT
Solder the exposed pad on the underside of the ADRF6780 to a
low thermal and electrical impedance ground plane. This pad is
typically soldered to an exposed opening in the solder mask on
the evaluation board. Connect these ground vias to all other
ground layers on the evaluation board to maximize heat
dissipation from the device package.
5
–5
–15
POUT (dBm)
5
RF FREQUENCY (GHz)
14106-073
–65
MAIN TONE
SIDEBAND
LO FEEDTHROUGH
LO FEEDTHROUGH (LO ×1)
LO FEEDTHROUGH (LO ×2)
14106-075
POUT (dBm)
–15
–25
–35
–45
–55
1
6
11
16
21
26
31
RF FREQUENCY (GHz)
14106-074
–65
MAIN TONE
SIDEBAND
LO FEEDTHROUGH
14106-093
Figure 74. Output Power (POUT) vs. RF Frequency (fRF) in IF Mode at
the Maximum Gain Setting, IF Amplitude = −12 dBm
Figure 76. Evaluation Board Layout for the ADRF6780 Package
Rev. D | Page 24 of 35
Data Sheet
ADRF6780
LO INPUT DRIVEN DIFFERENTIAL vs. SINGLE ENDED
The subharmonic measurement compares the two settings.
The LO input was set to doubler mode (×2) at a LO frequency
of 9 GHz, and the I/Q mode was set with a 10 MHz sine wave.
Table 6 represents the output frequencies of the upper sideband,
the lower sideband, and the LO leakage at the fundamental output
as well as the subharmonic output frequency at a maximum gain.
This section provides performance measurements that compare
the ADRF6780 using a differential LO input vs. a single-ended
LO input. When the device uses a single-ended configuration,
LOIP drives while LOIN terminates to 50 Ω.
Table 6. LO Single-Ended vs. Differential Configuration Performance
Mode
Single Ended
Differential
LO Input
Power (dBm)
−10
−6
0
+6
−10
−6
0
+6
Fundamental Output
Wanted Upper Unwanted Lower
Sideband,
Sideband,
LO – I/Q (dBm) LO + I/Q (dBm)
−2.20
−28.83
−2.09
−25.15
−1.94
−28.36
−2.01
−28.36
−1.84
−24.96
−1.85
−27.19
−1.84
−29.46
−1.85
−29.55
LO Leakage
(dBm)
−32.36
−33.22
−38.08
−42.58
−43.49
−38.86
−37.84
−37.70
Rev. D | Page 25 of 35
Subharmonic Output
Unwanted Upper Unwanted Lower
Sideband,
Sideband,
LO/2 – I/Q (dBm)
LO/2 + I/Q (dBm)
−16.26
−32.85
−18.01
−35.78
−22.83
−42.97
−20.17
−39.80
−29.66
−51.54
−33.18
−51.25
−38.04
−56.50
−40.08
−58.46
LO/2 Leakage
(dBm)
−36.16
−35.46
−41.50
−38.08
−45.85
−47.12
−58.25
−60.16
ADRF6780
Data Sheet
Gain, third-order intermodulation distortion (IMD3), and sideband rejection are also measured. RF frequencies from 5 GHz to 13 GHz
are produced in LO ×1 mode, while LO ×2 mode produced RF frequencies from 14 GHz to 25 GHz. In both differential (Figure 77 to
Figure 79) and single-ended (Figure 80 to Figure 82) configurations, the total LO power was swept from −10 dBm to +6 dBm. In differential
mode, the amplitude was the sum of the LOIP and LOIN inputs.
0
0
–5
–5
VATT = 2.6V
VATT = 2.6V
–10
–10
VATT = 1.5V
–15
POUT (dBm)
–20
VATT = 0.4V
–25
VATT = 0.4V
–25
–40
5
7
9
LO
LO
LO
LO
–35
11
13
15
17
19
21
23
25
RF FREQUENCY (GHz)
–40
Figure 77. LO Differential Input, Output Power (POUT) vs. RF Frequency (fRF) at
Three Gain Settings for Various LO Inputs,
BB I/Q Amplitude = −15 dBm
7
9
11
13
15
17
19
21
23
25
RF FREQUENCY (GHz)
Figure 80. LO Single-Ended Input, Output Power (POUT) vs. RF Frequency (fRF)
at Three Gain Settings for Various LO Inputs,
BB I/Q Amplitude = −15 dBm
80
70
70
60
60
50
50
IMD3 (dBc)
80
40
5
= –10dBm
= –6dBm
= 0dBm
= +6dBm
14106-096
= –10dBm
= –6dBm
= 0dBm
= +6dBm
14106-093
LO
LO
LO
LO
–35
40
30
30
20
20
10
0
5
7
= –10dBm
= –6dBm
= 0dBm
= +6dBm
9
11
13
15
17
19
21
23
25
RF FREQUENCY (GHz)
Figure 78. LO Differential Input, Third-Order Intermodulation Distortion (IMD3) vs.
RF Frequency (fRF) at a 10 dB Gain Setting (POUT ≈ −5 dBm per Tone)
0
50
SIDEBAND SUPPRESSION (dBc)
50
30
20
= –10dBm
= –6dBm
= 0dBm
= +6dBm
0
5
7
9
11
13
15
17
19
RF FREQUENCY (GHz)
21
23
25
Figure 79. LO Differential Input, Sideband Suppression vs. RF Frequency (fRF)
Before Nulling
9
11
13
15
17
19
21
23
25
40
30
20
10
LO
LO
LO
LO
= –10dBm
= –6dBm
= 0dBm
= +6dBm
7
9
0
14106-095
LO
LO
LO
LO
7
Figure 81. LO Single-Ended Input, Third-Order Intermodulation Distortion (IMD3)
vs. RF Frequency (fRF) at a 10 dB Gain Setting (POUT ≈ −5 dBm per Tone)
60
40
5
= –10dBm
= –6dBm
= 0dBm
= +6dBm
RF FREQUENCY (GHz)
60
10
LO
LO
LO
LO
10
14106-094
LO
LO
LO
LO
14106-098
IMD3 (dBc)
–20
–30
–30
SIDEBAND SUPPRESSION (dBc)
–15
5
11
13
15
17
19
RF FREQUENCY (GHz)
21
23
25
14106-097
POUT (dBm)
VATT = 1.5V
Figure 82. LO Single-Ended Input, Sideband Suppression vs. RF Frequency
(fRF) Before Nulling
Rev. D | Page 26 of 35
Data Sheet
ADRF6780
REGISTER SUMMARY
Table 7. Register Summary
Hex
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x00
Control
[15:8]
PARITY_EN
SOFT_RESET
[7:0]
0x01
ALARM_
READBACK
[15:8]
0x02
ALARM_MASK
[15:8]
0x03
Enable
[15:8]
RESERVED
CHIP_ID[3:0]
PARITY_
ERROR
TOO_FEW_
ERRORS
TOO_MANY_
ERRORS
ADDRESS_
RANGE_
ERROR
PARITY_
ERROR_
MASK
TOO_FEW_
ERRORS_
MASK
TOO_MANY_
ERRORS_
MASK
ADDRESS_
RANGE_
ERROR_MASK
Linearize
ADC_
CONTROL
[15:8]
[7:0]
[7:0]
0x0C
ADC_OUTPUT
DETECTOR_
ENABLE
LO_BUFFER_
ENABLE
IF_MODE_
ENABLE
IQ_MODE_
ENABLE
LO_X2_
ENABLE
RESERVED
0x06
[15:8]
[7:0]
R
RESERVED
0xFFFF
R/W
0x0157
R/W
0x0080
R/W
0x0000
R/W
0x0000
R/W
0x0010
R
VGA_BUFFER_
ENABLE
RDAC_LINEARIZE
[15:8]
0x0000
RESERVED
[7:0]
LO_PATH
RESERVED
RESERVED
[15:8]
0x05
R/W
RESERVED
[7:0]
0x04
R/W
0x0075
CHIP_REVISION
[7:0]
[7:0]
Reset
CHIP_ID[7:4]
RESERVED
LO_PPF_
ENABLE
LO_
ENABLE
LO_
SIDEBAND
Q_PATH_PHASE_ACCURACY
UC_BIAS_
ENABLE
RESERVED
I_PATH_PHASE_ACCURACY
RESERVED
RESERVED
VDET_
OUTPUT_
SELECT
RESERVED
ADC_VALUE
Rev. D | Page 27 of 35
ADC_
START
ADC_
ENABLE
ADC_CLOCK_
ENABLE
ADC_STATUS
ADRF6780
Data Sheet
REGISTER DETAILS: WIDEBAND UPCONVERTER
CONTROL REGISTER
Address: 0x00, Reset: 0x0075, Name: Control
15 14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1
[15] PARITY_EN (R/W)
Enable the Parity for Write Execution
[3:0] CHIP_REVISION (R)
Chip Revision
[14] SOFT_RESET (W)
SPI Soft Reset (SPI Soft Reset is
Not Self-Reset)
[11:4] CHIP_ID (R)
Chip ID
[13:12] RESERVED
Table 8. Bit Descriptions for Control
Bits
15
14
[13:12]
[11:4]
[3:0]
Bit Name
PARITY_EN
SOFT_RESET
RESERVED
CHIP_ID
CHIP_REVISION
Settings
Description
Enable the Parity for Write Execution
SPI Soft Reset (SPI Soft Reset is Not Self-Reset)
Reserved
Chip ID
Chip Revision
Reset
0x0
0x0
0x0
0x7
0x5
Access
R/W
W
R/W
R
R
ALARM_READBACK REGISTER
Address: 0x01, Reset: 0x0000, Name: ALARM_READBACK
15 14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15] PARITY_ERROR (R)
Parity Error
[11:0] RESERVED
[12] ADDRESS_RANGE_ERROR (R)
Address Range Error
[14] TOO_FEW_ERRORS (R)
Too Few Errors
[13] TOO_MANY_ERRORS (R)
Too Many Errors
Table 9. Bit Descriptions for ALARM_READBACK
Bits
15
14
13
12
[11:0]
Bit Name
PARITY_ERROR
TOO_FEW_ERRORS
TOO_MANY_ERRORS
ADDRESS_RANGE_ERROR
RESERVED
Settings
Description
Parity Error
Too Few Errors
Too Many Errors
Address Range Error
Reserved
Rev. D | Page 28 of 35
Reset
0x0
0x0
0x0
0x0
0x0
Access
R
R
R
R
R
Data Sheet
ADRF6780
ALARM_MASK REGISTER
Address: 0x02, Reset: 0xFFFF, Name: ALARM_MASK
15 14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
[15] PARITY_ERROR_MASK (R/W)
Parity Error Mask - Enable the Alarm
Output Pin
[11:0] RESERVED
[12] ADDRESS_RANGE_ERROR_MASK (R/W)
Address Range Error Mask - Enable
the Alarm Output Pin
[14] TOO_FEW_ERRORS_MASK (R/W)
Too Few Errors Mask -Enable the
Alarm Output Pin
[13] TOO_MANY_ERRORS_MASK (R/W)
Too Many Errors Mask - Enable the
Alarm Output Pin
Table 10. Bit Descriptions for ALARM_MASK
Bits
15
14
13
12
[11:0]
Bit Name
PARITY_ERROR_MASK
TOO_FEW_ERRORS_MASK
TOO_MANY_ERRORS_MASK
ADDRESS_RANGE_ERROR_MASK
RESERVED
Settings
Description
Parity Error Mask—Enable the Alarm Output Pin
Too Few Errors Mask—Enable the Alarm Output Pin
Too Many Errors Mask—Enable the Alarm Output Pin
Address Range Error Mask—Enable the Alarm Output Pin
Reserved
Reset
0x1
0x1
0x1
0x1
0xFFF
Access
R/W
R/W
R/W
R/W
R/W
ENABLE REGISTER
Address: 0x03, Reset: 0x0157, Name: Enable
15 14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 1
[15:9] RESERVED
[0] UC_BIAS_ENABLE (R/W)
UC Bias Enable
[8] VGA_BUFFER_ENABLE (R/W)
VGA Buffer Enable
[1] LO_ENABLE (R/W)
LO Enable
[7] DETECTOR_ENABLE (R/W)
Detector Enable
[2] LO_PPF_ENABLE (R/W)
LO x1 Enable
[6] LO_BUFFER_ENABLE (R/W)
LO Buffer Enable
[3] LO_X2_ENABLE (R/W)
LO x2 Enable
[5] IF_MODE_ENABLE (R/W)
IF Mode Enable
[4] IQ_MODE_ENABLE (R/W)
IQ Mode Enable
Table 11. Bit Descriptions for Enable
Bits
[15:9]
8
7
6
5
4
3
2
1
0
Bit Name
RESERVED
VGA_BUFFER_ENABLE
DETECTOR_ENABLE
LO_BUFFER_ENABLE
IF_MODE_ENABLE
IQ_MODE_ENABLE
LO_X2_ENABLE
LO_PPF_ENABLE
LO_ENABLE
UC_BIAS_ENABLE
Settings
Description
Reserved
VGA Buffer Enable
Detector Enable
LO Buffer Enable
IF Mode Enable
IQ Mode Enable
LO ×2 Enable
LO ×1 Enable
LO Enable
UC Bias Enable
Rev. D | Page 29 of 35
Reset
0x0
0x1
0x0
0x1
0x0
0x1
0x0
0x1
0x1
0x1
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADRF6780
Data Sheet
LINEARIZE REGISTER
Address: 0x04, Reset: 0x0080, Name: Linearize
15 14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
[15:8] RESERVED
[7:0] RDAC Linearize (R/W)
RDAC 8 Bits: for IMD Perform ance
Im provem ent (0-255)
Table 12. Bit Descriptions for Linearize
Bits
[15:8]
[7:0]
Bit Name
RESERVED
RDAC_LINEARIZE
Settings
Description
Reserved
RDAC 8 Bits: for IMD Performance Improvement (0 to 255)
Reset
0x0
0x80
Access
R/W
R/W
LO_PATH REGISTER
Address: 0x05, Reset: 0x0000, Name: LO_PATH
15 14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:11] RESERVED
[3:0] I_PATH_PHASE_ACCURACY (R/W)
CDAC for I Phase Accuracy
[10] LO_SIDEBAND (R/W)
Switch to the Other LO SideBand
[7:4] Q_PATH_PHASE_ACCURACY (R/W)
CDAC for Q Phase Accuracy
[9:8] RESERVED
Table 13. Bit Descriptions for LO_PATH
Bits
[15:11]
10
[9:8]
[7:4]
[3:0]
Bit Name
RESERVED
LO_SIDEBAND
RESERVED
Q_PATH_PHASE_ACCURACY
I_PATH_PHASE_ACCURACY
Settings
Description
Reserved
Switch to the Other LO Sideband
Reserved
CDAC for Q Phase Accuracy
CDAC for I Phase Accuracy
Rev. D | Page 30 of 35
Reset
0x0
0x0
0x0
0x0
0x0
Access
R/W
R/W
R/W
R/W
R/W
Data Sheet
ADRF6780
ADC_CONTROL REGISTER
Address: 0x06, Reset: 0x0000, Name: ADC_CONTROL
15 14 13 12
11 10
8
9
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:4] RESERVED
[0] ADC_CLOCK_ENABLE (R/W)
ADC Clock Enable
0: Disable.
1: Enable.
[3] VDET_OUTPUT_SELECT (R/W)
VDET Output Pin Select
0: VDET Output Select Disable.
1: VDET Output Select Enable.
[1] ADC_ENABLE (R/W)
ADC Enable and Com parator on
0: Disable.
1: Enable.
[2] ADC_START (R/W)
ADC FallEdge to Start ADCConversion-Write
High Then Low
0: ADC conversion activated at falling
edge.
1: Set ADC conversion control high.
Table 14. Bit Descriptions for ADC_CONTROL
Bits
[15:4]
3
Bit Name
RESERVED
VDET_OUTPUT_SELECT
Settings
0
1
2
ADC_START
0
1
1
ADC_ENABLE
0
1
0
ADC_CLOCK_ENABLE
0
1
Description
Reserved
VDET Output Pin Select
VDET Output Select Disable
VDET Output Select Enable
ADC Fall Edge to Start ADC Conversion Write High Then Low
ADC Conversion Activated at Falling Edge
Set ADC conversion control High
ADC Enable and Comparator On
Disable
Enable
ADC Clock Enable
Disable
Enable
Reset
0x0
0x0
Access
R/W
R/W
0x0
R/W
0x0
R/W
0x0
R/W
ADC_OUTPUT REGISTER
Address: 0x0C, Reset: 0x0010, Name: ADC_OUTPUT
15 14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:9] RESERVED
[7:0] ADC_VALUE (R)
Detector ADC 8 Bit Output
[8] ADC_STATUS (R)
ADC Busy
0: Busy.
1: Ready.
Table 15. Bit Descriptions for ADC_OUTPUT
Bits
[15:9]
8
Bit Name
RESERVED
ADC_STATUS
Settings
0
1
[7:0]
ADC_VALUE
Description
Reserved
ADC Busy
Busy
Ready
Detector ADC 8-Bit Output
Rev. D | Page 31 of 35
Reset
0x0
0x0
Access
R/W
R
0x0
R
ADRF6780
Data Sheet
BASIC CONNECTIONS FOR OPERATION
Figure 83 to Figure 85 show the basic connections for operating the ADRF6780 as it is implemented on the evaluation board of the device.
LOIP
LOIP
1
LOIN
1
LOIN
2 3 4
4 3 2
25-146-1000-92
AGND
AGND
3.3V_6780
3.3V_6780
C4
0.1UF
C0603
C10
4.7NF
C0402
C22
0.1UF
C0603
C20
4.7NF
C0402
C17
33PF
C0402
C14
33PF
C0402
ALMB
R8
5.1K
R0402
R2
C16
TBD0603
C0603
DNI
C7
10PF
C0402
C18
TBD0402
C0402
6780_CS
AGND
33
R0402
DNI
R3
AGND
5V
1.8V
3.3V_6780
1
RED
REDRED1
3.3V_6780
3.3V
33
R0402
C35
TBD0402
C0402
DNI
1.8V
VATT
GRN
ALMB
WHT
1
1
VDET
WHT
AGND
6780_VATT
C36
4.7NF
C0402
C31
33PF
C0402
6780_MISO
33
R0402
C19
TBD0402
C0402
DNI
C11
33PF
C0402
RED 1
ALMB
VDET
1.8V
AGND
AGND
3.3V
5V
1
6780_MOSI
C21
TBD0402
C0402
DNI
5V
C6
4.7NF
C0402
C34
TBD0402
C0402
DNI
AGND
AGND
C2
0.1UF
C0603
6780_SCK
AGND
C30
TBD0402
C0402
DNI
R9
0
R0402
R4
33
R0402
R5
AGND
AGND
VDET
C29
TBD0402
C0402
DNI
AGND
C39
0.1UF
C0603
1
GND1
BLK
AGND
GND2
BLK
1
AGND
AGND
C24
TBD0402
C0402
DNI
3.3V_6780
AGND
AGND
C5
5V
1
2
3
4
5
6
7
8
AGND
RFOP
1
2 3 4
6780_RFOP
25-146-1000-92
RFON
1
2 3 4
AGND
VDET
VPDT
VPRF
AGND
RFOP
AGND
RFON
AGND
5 4 3 2
ADRF6780
SCLK
SDIN
VP18
VPBI
IFIP
AGND
IFIN
RSTB
AGND
6780_RSTB
C32
TBD0402
C0402
RSTB
1
2
C37
TBD0603
C0603
DNI
9
10
11
12
13
14
15
16
AGND
AGND
AGND
1.8V
R7
10K
R0603
DNI
6780_RFON
25-146-1000-92
C33
33PF
C0402
C40
0.1UF
C0603
100PF
C0402
5 4 3 2
AGND
24
23
22
21
20
19
18
17
VPRF
VATT
BBQN
BBQP
BBIP
BBIN
VPBB
PWDN
AGND
32
31
30
29
28
27
26
25
PAD
C9
33PF
C0402
C3
4.7NF
C0402
ALMB
VPLO
LOIP
AGND
LOIN
VPLO
SENB
SDTO
C1
0.1UF
C0603
IFIN
1
100PF
C0402
DUT
IFIN
1
C41
IFIP
IFIP
AGND
C38
4.7NF
C0402
3
4
B3S1000
AGND
AGND
PWDN
5V
1.8V
PWDN
C15
33PF
C0402
C13
4.7NF
C0402
C8
0.1UF
C0603
DNI
C25
TBD0402
C0402
C27
R6
10K
R0603
C0603
DNI
AGND
1
2
69157-102
TBD0603
AGND
6780_VATT
AGND
R1
0
R0402
3.3V_6780
C12
TBD0402
C0402
DNI
C23
33PF
C0402
AGND
BBQN
C26
4.7NF
C0402
C28
0.1UF
C0603
BBIN
AGND
BBQP
R11
0
R23
BBQN
1
R24
5 4 3 2
50
R0402
R12
0
BBQP
1
BBIP
1
5 4 3 2
5 4 3 2
AGND
BBIN
1
R25
50
R0402
5 4 3 2
R26
50
R0402
AGND
AGND
AGND
AGND
R13
0
AGND
AGND
AGND
NOTES
1. WHEN THE IF MODE IS SET, REMOVE THE 0Ω R10 TO R13 RESISTORS FROM THE IQ LINES.
Figure 83. ADRF6780 Evaluation Board Schematic Page 1
Rev. D | Page 32 of 35
14106-100
R10
0
50
R0402
BBIP
Data Sheet
ADRF6780
USB
XC4
10UF
C3216
P
XC5
0.1UF
C0402
N
XC6
0.1UF
C0402
XC7
0.1UF
C0402
3.3V
XC8
0.1UF
C0402
USB_VCC
USB_DUSB_D+
AGND
1
2
3
4
5
3.3V
EN1
SHIELD
PINS
MOSI
MISO
SCK
3.3V
3.3V
PGC
10UF
C0603
3
AGND
CS2
USB_D–
USB_D+
1
2
4
6
7
8
9
10
12
13
MCLR_N
5
28
27
25
24
23
22
21
20
19
18
15
14
CS1
MISO
MOSI
SCK
R15
USB_VCC
R16
100K
R0402
PAD
AGND
Figure 84. ADRF6780 Evaluation Board Schematic Page 2
NANODAC
3.3V
SCK
MOSI
C45
10UF
C3216
AGND
1.8V LDO REGULATOR
U3
ADM7170ACPZ-1.8
U2
AD5601BCPZ
1 VDD
VOUT 6
2 SCLK
GND 5
3 SDIN SYNC_N 4
PAD
PAD
R14
CS2
6780_VATT
1.8V
R19
0
R0603
0
R0603
C42
4.7UF
C0603
AGND
AGND
1
2
3
4
VOUT
VIN 8
VOUT
VIN 7
SENSE
GND 6
5
SS
EN
EP
C43
PAD
1000PF
C0603
AGND
AGND
5V
C44
4.7UF
C0603
AGND
3.3V LDO REGULATORS
U5
ADM7172ACPZ-3.3
U4
ADM7172ACPZ-3.3
3.3V_6780
R17
0
R0603
C46
4.7UF
C0603
AGND
1
2
3
4
C47
1000PF
C0603
AGND
VOUT1
VOUT2
SENSE
SS
VIN1 8
VIN2 7
GND 6
EN 5
EP
PAD
FXL4TD245BQX
C
PGC
AGND
AGND
6780_CS
6780_MOSI
6780_MISO
6780_SCK
A
EN1
100K
R0402
PAD
16
14
B0
13
B1
12
B2
11
B3
USB
LB L293-N1N2-25-Z(BLUE)
VDD
VSS
OE_N
A0
A1
A2
A3
T_R0_N
T_R1_N
T_R2_N
T_R3_N
AGND
RA1_AN1_C2INA_RP1
RA0_AN0_C1INA_ULPWU_RP0
RB7_KBI3_PGD_RP10
RB6_KBI2_PGC_RP9
RB5_KBI1_SDI1_SDA1_RP8
RB4_KBI0_SCK1_SCL1_RP7
RB3_AN9_CTEDG2_VPO_RP6
RB2_AN8_CTEDG1_VMO_REFO_RP5
RB1_AN10_RTCC_RP4
RB0_AN12_INT0_RP3
RC7_RX1_DT1_SDO1_RP18
RC6_TX1_CK1_RP17
RA2_AN2_VREF_NEG_CVREF_C2INB
RA3_AN3_VREF_POS_C1INB
RA5_AN4_SS1_N_HLVDIN_RCV_RP2
OSC1_CLKI_RA7
OSC2_CLKO_RA6
RC0_T1OSO_T1CKI_RP11
RC1_T1OSI_UOE_N_RP12
RC2_AN11_CTPLS_RP13
RC4_D_NEG_VM
RC5_D_POS_VP
9
3
4
5
6
2
15
10
7
U1
16
VCCB
PAD
GND
8
PAD
XU1
PIC18F24J50-I/ML
17
11
VDDCORE_VCAP VUSB
26
AGND
1
VCCA
14106-101
AGND
XR2
10K
R0603
AGND
5V
C48
4.7UF
C0603
3.3V
R18
0
R0603
AGND
C49
4.7UF
C0603
AGND
AGND
VIN1
VIN2
GND
EN
VOUT1
VOUT2
SENSE
SS
C50
1000PF
C0603
EP
AGND
AGND
AGND
3.3V_6780
5V
C51
4.7UF
C0603
3.3V
14106-102
1
2
3
4
5
6
3.3V
XR6
80.6
R1206
XC12
C141
0.1UF
C0603
AGND
R20
0
CS1
AGND
XP1
PROGRAMMING HEADER
SAMTECTSW10608GS6PIN
C140
0.1UF
C0603
R22
10K
R0603
R21
0
R0603
DNI
PAD1
PAD2
PAD3
PAD4
1.8V
3.3V
XP2
MUSB-05-F-AB-SM-A-R
Figure 85. ADRF6780 Evaluation Board Schematic Page 3
Rev. D | Page 33 of 35
ADRF6780
Data Sheet
Table 16. Evaluation Board Configuration Options
Component
VPLO3.3V, VPDT5V, VPRF5V, VPBB3.3V, VPBI3.3V,
1P8V, AGND
LOIN, LOIP, VDET, RFON, RFOP, BBIN, BBIP, BBQN,
BBQN, IFIN, IFIP, VATT
SCLK, SDIN, SENB, SDTO
R2 to R5
5V, 3.3V, 3.3V_6780, 1.8V, VDET, ALMB, VATT,
GND1 to GND2
PWDN
Function
Power supplies and ground
Default Condition
Not applicable
Data and clock
Not applicable
SPI
33 Ω series resistors for SPI pins
Test points
Not applicable
R2, R3, R4, R5 = 33 Ω (0402)
Not applicable
Power-down function
R1, R9, R14, R15, R17 to R20, XR2, XR6
Shorts or power supply decoupling
resistors
R6, R7, R16, R22
Pull-up or pull-down resistors
C1 to C4, C6 to C11, C13 to C15, C17, C20, C22,
C23, C26, C28, C31, C33, C36, C38 to C40, C42
to C51, XC12, XC4 to XC8, C140, C141
The capacitors provide the required
decoupling of the supply related
pins
R10 to R13
Remove resistors when using IF
inputs (IF mode)
Resistors provide a broadband 50 Ω
termination for baseband input data
AC coupling capacitors
CS decoupling resistor
Do not install (DNI)
Apply 1.8 V on PWDN (Pin 2) jumper to power
down the device
R1, R9, R17, R18, R19 = 0 Ω (0402),
R8 = 5.1 kΩ (0402),
R15 = 100 kΩ (0402),
R14, R20 = 0 Ω (0402),
XR2 = 10 kΩ (0603),
XR6 = 80.6 Ω (1206)
R6, R7, R22 = 10 kΩ (0603),
R16 = 100 kΩ (0402)
XC4, C45 = 10 µF (3216),
XC12 = 10 µF (0603),
C42, C44, C46, C48, C49,
C51 = 4.7 µF (0603),
C1, C2, C4, C8, C22, C28,
C39, C40 = 0.1 µF (0603),
XC5, XC6, XC7, XC8 = 0.1 µF (0402),
C3, C6, C10, C13, C20, C26,
C36, C38 = 4.7 nF (0402),
C43, C47, C50 = 1000 pF (0603),
C9, C11, C14, C15, C17, C23, C31, C33 = 33 pF (0402),
C7 = 10 pF (0402),
C140, C141 = 0.1 µF (0603)
R10, R11, R12, R13 = 0 Ω (0201)
R23 to R26
C5, C41
C21
C12, C16, C18, C19, C24, C25, C27, C29, C30,
C32, C34, C35, C37, R21
XP1
XP2
Programming header
Mini USB connector
RSTB
USB
Reset button
Blue LED
XU1
U1
U3 to U5
Microcontroller
Level shifter
3.3 V and 1.8 V regulators
U2
DUT
AD5601 nanoDAC
ADRF6780, device under test
Rev. D | Page 34 of 35
R23, R24, R25, R26 = 49.9 Ω (0402)
C5, C41 = 100 pF (0402)
C21 = 100 pF (0402)
C16, C24, C34, C35 = 0402,
C27, C37, R21 = 0603,
C12, C18, C19, C25 = 0402,
C29, C30, C32 = 0402
Not applicable
Connect the mini USB cable to XP2 to interface
with the SPI
Click RSTB to reset the device
LED is blue when the USB is connected to XP2, and
the PC and the ADRF6780 evaluation board is
powered on with a 5 V supply
PIC18F24J50
FXL4TD245BQX
ADM7170 (U3) = 1.8 V regulator,
ADM7172 (U4) = 3.3 V regulator,
ADM7172 (U5) = 3.3 V regulator for ADRF6780
Not applicable
Not applicable
Data Sheet
ADRF6780
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
5.10
5.00 SQ
4.90
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
32
25
1
24
0.50
BSC
3.40
3.30 SQ
3.20
EXPOSED
PAD
8
17
0.45
0.40
0.35
TOP VIEW
0.80
0.75
0.70
END VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
PKG-003530
SEATING
PLANE
9
16
BOTTOM VIEW
0.20 MIN
3.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5
03-17-2017-B
PIN 1
INDICATOR
0.30
0.25
0.18
Figure 86. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADRF6780ACPZN
ADRF6780ACPZN-R2
ADRF6780ACPZN-R7
ADRF6780-EVALZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Z = RoHS Compliant Part.
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D14106-0-1/19(D)
Rev. D | Page 35 of 35
Package Option
CP-32-20
CP-32-20
CP-32-20
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