ADSP-2100 Family
DSP Microcomputers
ADSP-21xx
a
SUMMARY
16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory
Enhanced Harvard Architecture for Three-Bus
Performance: Instruction Bus & Dual Data Buses
Independent Computation Units: ALU, Multiplier/
Accumulator, and Shifter
Single-Cycle Instruction Execution & Multifunction
Instructions
On-Chip Program Memory RAM or ROM
& Data Memory RAM
Integrated I/O Peripherals: Serial Ports, Timer,
Host Interface Port (ADSP-2111 Only)
FUNCTIONAL BLOCK DIAGRAM
DATA ADDRESS
GENERATORS
DAG 1
DAG 2
MEMORY
PROGRAM
SEQUENCER
The ADSP-2101, ADSP-2105, and ADSP-2115 are no longer
available.
FLAGS
(ADSP-2111)
EXTERNAL
ADDRESS
BUS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ALU
MAC
SHIFTER
SERIAL PORTS
SPORT 0
TIMER
SPORT 1
HOST
INTERFACE
PORT
EXTERNAL
DATA
BUS
(ADSP-2111)
ADSP-2100 CORE
This data sheet describes the following ADSP-2100 Family
processors:
ADSP-2101
ADSP-2103
ADSP-2105
ADSP-2111
ADSP-2115
ADSP-2161/62/63/64
3.3 V Version of ADSP-2101
Low Cost DSP
DSP with Host Interface Port
Custom ROM-programmed DSPs
The following ADSP-2100 Family processors are not included
in this data sheet:
ADSP-2100A
DSP Microprocessor
ADSP-2165/66
ROM-programmed ADSP-216x processors
with powerdown and larger on-chip
memories (12K Program Memory ROM,
1K Program Memory RAM, 4K Data
Memory RAM)
ADSP-21msp5x
Mixed-Signal DSP Processors with
integrated on-chip A/D and D/A plus
powerdown
ADSP-2171
Speed and feature enhanced ADSP-2100
Family processor with host interface port,
powerdown, and instruction set extensions
for bit manipulation, multiplication, biased
rounding, and global interrupt masking
ADSP-2181
ADSP-21xx processor with ADSP-2171
features plus 80K bytes of on-chip RAM
configured as 16K words of program
memory and 16K words of data memory.
GENERAL DESCRIPTION
The ADSP-2100 Family processors are single-chip microcomputers optimized for digital signal processing (DSP)
and other high speed numeric processing applications. The
ADSP-21xx processors are all built upon a common core. Each
processor combines the core DSP architecture—computation
units, data address generators, and program sequencer—with
differentiating features such as on-chip program and data
memory RAM, a programmable timer, one or two serial ports,
and, on the ADSP-2111, a host interface port.
DATA
MEMORY
PROGRAM MEMORY ADDRESS
ARITHMETIC UNITS
FEATURES
25 MIPS, 40 ns Maximum Instruction Rate
Separate On-Chip Buses for Program and Data Memory
Program Memory Stores Both Instructions and Data
(Three-Bus Performance)
Dual Data Address Generators with Modulo and
Bit-Reverse Addressing
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory (e.g., EPROM )
Double-Buffered Serial Ports with Companding Hardware,
Automatic Data Buffering, and Multichannel Operation
ADSP-2111 Host Interface Port Provides Easy Interface
to 68000, 80C51, ADSP-21xx, Etc.
Automatic Booting of ADSP-2111 Program Memory
Through Host Interface Port
Three Edge- or Level-Sensitive Interrupts
Low Power IDLE Instruction
PGA, PLCC, PQFP, and TQFP Packages
MIL-STD-883B Versions Available
ADSP-2101, ADSP-2105, and ADSP-2115 are obsolete
PROGRAM
MEMORY
Refer to the individual data sheet of each of these processors for
further information.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
ADSP-21xx
Fabricated in a high speed, submicron, double-layer metal
CMOS process, the highest-performance ADSP-21xx processors operate at 25 MHz with a 40 ns instruction cycle time.
Every instruction can execute in a single cycle. Fabrication in
CMOS results in low power dissipation.
The ADSP-2100 Family’s flexible architecture and comprehensive instruction set support a high degree of parallelism.
In one cycle the ADSP-21xx can perform all of the following
operations:
•
•
•
•
•
Generate the next program address
Fetch the next instruction
Perform one or two data moves
Update one or two data address pointers
Perform a computation
TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 1
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . 4
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Host Interface Port (ADSP-2111) . . . . . . . . . . . . . . . . . . . . 6
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Program Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . 10
Program Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Boot Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Low Power IDLE Instruction . . . . . . . . . . . . . . . . . . . . . . 13
ADSP-216x Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Ordering Procedure for ADSP-216x ROM Processors . . . . 13
Wafer Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functional Differences for Older Revision Devices . . . . . . 14
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
SPECIFICATIONS
(ADSP-2101/2105/2115/2161/2163) . . . . . . . . . . . . . . . 17
Recommended Operating Conditions . . . . . . . . . . . . . . . . 17
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Supply Current & Power (ADSP-2101/2161/2163) . . . . . . 18
Power Dissipation Example . . . . . . . . . . . . . . . . . . . . . . . . 19
Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 19
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SPECIFICATIONS
(ADSP-2111) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Recommended Operating Conditions . . . . . . . . . . . . . . . . 21
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Supply Current & Power . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power Dissipation Example . . . . . . . . . . . . . . . . . . . . . . . . 23
Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 23
•
•
Receive and transmit data via one or two serial ports
Receive and/or transmit data via the host interface port
(ADSP-2111 only)
The ADSP-2101, ADSP-2105, and ADSP-2115 comprise the
basic set of processors of the family. Each of these three devices
contains program and data memory RAM, an interval timer,
and one or two serial ports. The ADSP-2103 is a 3.3 volt
power supply version of the ADSP-2101; it is identical to the
ADSP-2101 in all other characteristics. Table I shows the
features of each ADSP-21xx processor.
The ADSP-2111 adds a 16-bit host interface port (HIP) to the
basic set of ADSP-21xx integrated features. The host port
provides a simple interface to host microprocessors or
microcontrollers such as the 8031, 68000, or ISA bus.
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SPECIFICATIONS (ADSP-2103/2162/2164) . . . . . . . . . 25
Recommended Operating Conditions . . . . . . . . . . . . . . . . 25
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Supply Current & Power . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power Dissipation Example . . . . . . . . . . . . . . . . . . . . . . . . 27
Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 27
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
TIMING PARAMETERS
(ADSP-2101/2105/2111/2115/2161/2163) . . . . . . . . . . . . 29
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Interrupts & Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Bus Request–Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Host Interface Port (ADSP-2111) . . . . . . . . . . . . . . . . . . . 36
TIMING PARAMETERS (ADSP-2103/2162/2164) . . . . 44
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Interrupts & Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Bus Request–Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
PIN CONFIGURATIONS
68-Pin PGA (ADSP-2101) . . . . . . . . . . . . . . . . . . . . . . . . 51
68-Lead PLCC (ADSP-2101/2103/2105/2115/216x) . . . . 52
80-Lead PQFP (ADSP-2101/2103/2115/216x) . . . . . . . . . 53
80-Lead TQFP (ADSP-2115) . . . . . . . . . . . . . . . . . . . . . . 53
100-Pin PGA (ADSP-2111) . . . . . . . . . . . . . . . . . . . . . . . 54
100-Lead PQFP (ADSP-2111) . . . . . . . . . . . . . . . . . . . . . 55
PACKAGE OUTLINE DIMENSIONS
68-Pin PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
68-Lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
80-Lead PQFP, 80-Lead TQFP . . . . . . . . . . . . . . . . . . . . 58
100-Pin PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
100-Lead PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . 61-62
–2–
REV. C
ADSP-21xx
Table I. ADSP-21xx Processor Features
Feature
2101
Data Memory (RAM)
Program Memory (RAM)
Timer
Serial Port 0 (Multichannel)
Serial Port 1
Host Interface Port
Speed Grades (Instruction Cycle Time)
10.24 MHz (76.9 ns)
13.0 MHz (76.9 ns)
13.824 MHz (72.3 ns)
16.67 MHz (60 ns)
20.0 MHz (50 ns)
25 MHz (40 ns)
Supply Voltage
Packages
68-Pin PGA
68-Lead PLCC
80-Lead PQFP
80-Lead TQFP
100-Pin PGA
100-Lead PQFP
Temperature Grades
K Commercial 0°C to +70°C
B Industrial
–40°C to +85°C
T Extended
–55°C to +125°C
1K
2K
••
•
2103
2105
2115
2111
1K
2K
1
1
•
•
••
•
1K
2K
–
–
–
–
–
⁄2 K
1K
••
•
•
–
–
–
–
–
–
–
–
–
–
–
–
3.3 V
••
•
••
•
5V
–
••
•
–
•
•
–
5V
–
–
–
–
••
••
–
–
–
5V
5V
–
•
–
–
–
••
••
•
••
–
•••
–
–
••
–
–
–
⁄2 K
1K
–
–
–
–
••
•
••
••
•
–
–
••
–
–
Table II. ADSP-216x ROM-Programmed Processor Features
REV. C
Feature
2161
2162
2163
2164
Data Memory (RAM)
Program Memory (ROM)
Program Memory (RAM)
Timer
Serial Port 0 (Multichannel)
Serial Port 1
Supply Voltage
Speed Grades (Instruction Cycle Time)
10.24 MHz (97.6 ns)
16.67 MHz (60 ns)
25 MHz (40 ns)
Packages
68-Lead PLCC
80-Lead PQFP
Temperature Grades
K Commercial 0°C to +70°C
B Industrial –40°C to +85°C
1
1
1
1
••
•
••
•
•
••
•
••
•
•
–3–
⁄2 K
8K
–
5V
–
•
••
••
–
⁄2 K
8K
–
3.3 V
–
–
••
••
⁄2 K
4K
–
5V
–
••
••
••
⁄2 K
4K
–
3.3 V
–
–
••
••
ADSP-21xx
The ADSP-216x series are memory-variant versions of the
ADSP-2101 and ADSP-2103 that contain factory-programmed
on-chip ROM program memory. These devices offer different
amounts of on-chip memory for program and data storage.
Table II shows the features available in the ADSP-216x series of
custom ROM-coded processors.
The ADSP-216x products eliminate the need for an external
boot EPROM in your system, and can also eliminate the need
for any external program memory by fitting the entire application program in on-chip ROM. These devices thus provide an
excellent option for volume applications where board space and
system cost constraints are of critical concern.
Development Tools
The ADSP-21xx processors are supported by a complete set of
tools for system development. The ADSP-2100 Family Development Software includes C and assembly language tools that
allow programmers to write code for any of the ADSP-21xx
processors. The ANSI C compiler generates ADSP-21xx
assembly source code, while the runtime C library provides
ANSI-standard and custom DSP library routines. The ADSP21xx assembler produces object code modules which the linker
combines into an executable file. The processor simulators
provide an interactive instruction-level simulation with a
reconfigurable, windowed user interface. A PROM splitter
utility generates PROM programmer compatible files.
EZ-ICE® in-circuit emulators allow debugging of ADSP-21xx
systems by providing a full range of emulation functions such as
modification of memory and register values and execution
breakpoints. EZ-LAB® demonstration boards are complete DSP
systems that execute EPROM-based programs.
The EZ-Kit Lite is a very low-cost evaluation/development
platform that contains both the hardware and software needed
to evaluate the ADSP-21xx architecture.
Additional details and ordering information is available in the
ADSP-2100 Family Software & Hardware Development Tools data
sheet (ADDS-21xx-TOOLS). This data sheet can be requested
from any Analog Devices sales office or distributor.
Additional Information
This data sheet provides a general overview of ADSP-21xx
processor functionality. For detailed design information on the
architecture and instruction set, refer to the ADSP-2100 Family
User’s Manual, available from Analog Devices.
ARCHITECTURE OVERVIEW
Figure 1 shows a block diagram of the ADSP-21xx architecture.
The processors contain three independent computational units:
the ALU, the multiplier/accumulator (MAC), and the shifter.
The computational units process 16-bit data directly and have
provisions to support multiprecision computations. The ALU
performs a standard set of arithmetic and logic operations;
division primitives are also supported. The MAC performs
single-cycle multiply, multiply/add, and multiply/subtract
operations. The shifter performs logical and arithmetic shifts,
normalization, denormalization, and derive exponent operations.
The shifter can be used to efficiently implement numeric format
control including multiword floating-point representations.
The internal result (R) bus directly connects the computational
units so that the output of any unit may be used as the input of
any unit on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient use of these computational units.
The sequencer supports conditional jumps, subroutine calls,
and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-21xx executes looped code with zero
overhead—no explicit jump instructions are required to
maintain the loop.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers. The circular buffering feature is also used by
the serial ports for automatic data transfers to (and from) onchip memory.
Efficient data transfer is achieved with the use of five internal
buses:
•
•
•
•
•
Program Memory Address (PMA) Bus
Program Memory Data (PMD) Bus
Data Memory Address (DMA) Bus
Data Memory Data (DMD) Bus
Result (R) Bus
The two address buses (PMA, DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD, DMD) share a single external data bus.
The BMS, DMS, and PMS signals indicate which memory
space is using the external buses.
Program memory can store both instructions and data, permitting the ADSP-21xx to fetch two operands in a single cycle, one
from program memory and one from data memory. The
processor can fetch an operand from on-chip program memory
and the next instruction in the same cycle.
The memory interface supports slow memories and memorymapped peripherals with programmable wait state generation.
External devices can gain control of the processor’s buses with
the use of the bus request/grant signals (BR, BG).
EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc.
–4–
REV. C
ADSP-21xx
INSTRUCTION
REGISTER
DATA
ADDRESS
GENERATOR
#2
DATA
ADDRESS
GENERATOR
#1
PROGRAM
MEMORY
DATA
MEMORY
SRAM
or ROM
SRAM
PROGRAM
SEQUENCER
14
PMA BUS
14
DMA BUS
24
FLAGS
(ADSP-2111 Only)
BOOT
ADDRESS
GENERATOR
16
3
TIMER
PMA BUS
14
24
MUX
DMA BUS
PMD BUS
PMD BUS
24
BUS
EXCHANGE
16
EXTERNAL
ADDRESS
BUS
MUX
DMD BUS
DMD BUS
INPUT REGS
INPUT REGS
INPUT REGS
ALU
MAC
SHIFTER
OUTPUT REGS
OUTPUT REGS
OUTPUT REGS
16
COMPANDING
CIRCUITRY
HOST
PORT
CONTROL
TRANSMIT REG
TRANSMIT REG
RECEIVE REG
RECEIVE REG
SERIAL
PORT 0
(Not on ADSP-2105)
SERIAL
PORT 1
R Bus
5
5
HOST
PORT
DATA
EXTERNAL
DATA
BUS
11
EXTERNAL
HOST PORT
BUS
16
HOST INTERFACE PORT
(ADSP-2111 Only)
Figure 1. ADSP-21xx Block Diagram
One bus grant execution mode (GO Mode) allows the ADSP21xx to continue running from internal memory. A second
execution mode requires the processor to halt while buses are
granted.
Each ADSP-21xx processor can respond to several different
interrupts. There can be up to three external interrupts,
configured as edge- or level-sensitive. Internal interrupts can be
generated by the timer, serial ports, and, on the ADSP-2111,
the host interface port. There is also a master RESET signal.
Booting circuitry provides for loading on-chip program memory
automatically from byte-wide external memory. After reset,
three wait states are automatically generated. This allows, for
example, a 60 ns ADSP-2101 to use a 200 ns EPROM as
external boot memory. Multiple programs can be selected and
loaded from the EPROM with no additional hardware.
The data receive and transmit pins on SPORT1 (Serial Port 1)
can be alternatively configured as a general-purpose input flag
and output flag. You can use these pins for event signalling to
and from an external device. The ADSP-2111 has three
additional flag outputs whose states are controlled through
software.
A programmable interval timer can generate periodic interrupts.
A 16-bit count register (TCOUNT) is decremented every n
cycles, where n–1 is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
REV. C
Serial Ports
The ADSP-21xx processors include two synchronous serial
ports (“SPORTs”) for serial communications and multiprocessor communication. All of the ADSP-21xx processors have two
serial ports (SPORT0, SPORT1) except for the ADSP-2105,
which has only SPORT1.
The serial ports provide a complete synchronous serial interface
with optional companding in hardware. A wide variety of
framed or frameless data transmit and receive modes of operation are available. Each SPORT can generate an internal
programmable serial clock or accept an external serial clock.
Each serial port has a 5-pin interface consisting of the following
signals:
Signal Name
Function
SCLK
RFS
TFS
DR
DT
Serial Clock (I/O)
Receive Frame Synchronization (I/O)
Transmit Frame Synchronization (I/O)
Serial Data Receive
Serial Data Transmit
The ADSP-21xx serial ports offer the following capabilities:
Bidirectional—Each SPORT has a separate, double-buffered
transmit and receive function.
Flexible Clocking—Each SPORT can use an external serial
clock or generate its own clock internally.
–5–
ADSP-21xx
Flexible Framing—The SPORTs have independent framing
for the transmit and receive functions; each function can run in
a frameless mode or with frame synchronization signals internally generated or externally generated; frame sync signals may
be active high or inverted, with either of two pulse widths and
timings.
Different Word Lengths—Each SPORT supports serial data
word lengths from 3 to 16 bits.
Companding in Hardware—Each SPORT provides optional
A-law and µ-law companding according to CCITT recommendation G.711.
Flexible Interrupt Scheme—Receive and transmit functions
can generate a unique interrupt upon completion of a data word
transfer.
Autobuffering with Single-Cycle Overhead—Each SPORT
can automatically receive or transmit the contents of an entire
circular data buffer with only one overhead cycle per data word;
an interrupt is generated after the transfer of the entire buffer is
completed.
Multichannel Capability (SPORT0 Only)—SPORT0
provides a multichannel interface to selectively receive or
transmit a 24-word or 32-word, time-division multiplexed serial
bit stream; this feature is especially useful for T1 or CEPT
interfaces, or as a network communication scheme for multiple
processors. (Note that the ADSP-2105 includes only SPORT1,
not SPORT0, and thus does not offer multichannel operation.)
Alternate Configuration—SPORT1 can be alternatively
configured as two external interrupt inputs (IRQ0, IRQ1) and
the Flag In and Flag Out signals (FI, FO).
Host Interface Port (ADSP-2111)
The ADSP-2111 includes a Host Interface Port (HIP), a
parallel I/O port that allows easy connection to a host processor.
Through the HIP, the ADSP-2111 can be accessed by the host
processor as a memory-mapped peripheral. The host interface
port can be thought of as an area of dual-ported memory, or
mailbox registers, that allows communication between the
computational core of the ADSP-2111 and the host computer.
The host interface port is completely asynchronous. The host
processor can write data into the HIP while the ADSP-2111 is
operating at full speed.
Three pins configure the HIP for operation with different types
of host processors. The HSIZE pin configures HIP for 8- or 16bit communication with the host processor. HMD0 configures
the bus strobes, selecting either separate read and write strobes
or a single read/write select and a host data strobe. HMD1
selects either separate address (3-bit) and data (16-bit) buses or
a multiplexed 16-bit address/data bus with address latch enable.
Tying these pins to appropriate values configures the ADSP2111 for straight-wire interface to a variety of industry-standard
microprocessors and microcomputers.
The HIP contains six data registers (HDR5-0) and two status
registers (HSR7-6) with an associated HMASK register for
masking interrupts from individual HIP data registers. The HIP
data registers are memory-mapped in the internal data memory
of the ADSP-2111. The two status registers provide status
information to both the ADSP-2111 and the host processor.
HSR7 contains a software reset bit which can be set by both the
ADSP-2111 and the host.
HIP transfers can be managed using either interrupts or polling.
The HIP generates an interrupt whenever an HDR register
receives data from a host processor write. It also generates an
interrupt when the host processor has performed a successful
read of any HDR. The read/write status of the HDRs is also
stored in the HSR registers.
The HMASK register bits can be used to mask the generation of
read or write interrupts from individual HDR registers. Bits in
the IMASK register enable and disable all HIP read interrupts
or all HIP write interrupts. So, for example, a write to HDR4
will cause an interrupt only if both the HDR4 Write bit in
HMASK and the HIP Write interrupt enable bit in IMASK are
set.
The HIP provides a second method of booting the ADSP-2111
in which the host processor loads instructions into the HIP. The
ADSP-2111 automatically transfers the data, in this case
opcodes, to internal program memory. The BMODE pin
determines whether the ADSP-2111 boots from the host
processor through the HIP or from external EPROM over the
data bus.
Interrupts
The ADSP-21xx’s interrupt controller lets the processor
respond to interrupts with a minimum of overhead. Up to three
external interrupt input pins, IRQ0, IRQ1, and IRQ2, are
provided. IRQ2 is always available as a dedicated pin; IRQ1 and
IRQ0 may be alternately configured as part of Serial Port 1. The
ADSP-21xx also supports internal interrupts from the timer, the
serial ports, and the host interface port (on the ADSP-2111).
The interrupts are internally prioritized and individually
maskable (except for RESET which is non-maskable). The
IRQx input pins can be programmed for either level- or edgesensitivity. The interrupt priorities for each ADSP-21xx
processor are shown in Table III.
The ADSP-21xx uses a vectored interrupt scheme: when an
interrupt is acknowledged, the processor shifts program control
to the interrupt vector address corresponding to the interrupt
received. Interrupts can be optionally nested so that a higher
priority interrupt can preempt the currently executing interrupt
service routine. Each interrupt vector location is four instructions in length so that simple service routines can be coded
entirely in this space. Longer service routines require an
additional JUMP or CALL instruction.
Individual interrupt requests are logically ANDed with the bits
in the IMASK register; the highest-priority unmasked interrupt
is then selected.
The interrupt control register, ICNTL, allows the external
interrupts to be set as either edge- or level-sensitive. Depending
on bit 4 in ICNTL, interrupt service routines can either be
nested (with higher priority interrupts taking precedence) or be
processed sequentially (with only one interrupt service active at
a time).
–6–
REV. C
ADSP-21xx
The interrupt force and clear register, IFC, is a write-only
register that contains a force bit and a clear bit for each interrupt (except for level-sensitive interrupts and the ADSP-2111
HIP interrupts—these cannot be forced or cleared in software).
When responding to an interrupt, the ASTAT, MSTAT, and
IMASK status registers are pushed onto the status stack and
the PC counter is loaded with the appropriate vector address.
The status stack is seven levels deep (nine levels deep on the
ADSP-2111) to allow interrupt nesting. The stack is automatically popped when a return from the interrupt instruction is
executed.
Pin Definitions
Table IV (on next page) shows pin definitions for the ADSP21xx processors. Any inputs not used must be tied to VDD.
Table III. Interrupt Vector Addresses & Priority
ADSP-2105
Interrupt
Source
Interrupt
Vector Address
RESET Startup
IRQ2
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
0x0000
0x0004 (High Priority)
0x0010
0x0014
0x0018 (Low Priority)
ADSP-2101/2103/2115/216x
Interrupt
Source
Interrupt
Vector Address
RESET Startup
IRQ2
SPORT0 Transmit
SPORT0 Receive
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
0x0000
0x0004 (High Priority)
0x0008
0x000C
0x0010
0x0014
0x0018 (Low Priority)
ADSP-2111
Interrupt
Source
Interrupt
Vector Address
RESET Startup
IRQ2
HIP Write from Host
HIP Read to Host
SPORT0 Transmit
SPORT0 Receive
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
0x0000
0x0004 (High Priority)
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020 (Low Priority)
SYSTEM INTERFACE
Figure 3 shows a typical system for the ADSP-2101, ADSP2115, or ADSP-2103, with two serial I/O devices, a boot
EPROM, and optional external program and data memory. A
total of 15K words of data memory and 16K words of program
memory is addressable for the ADSP-2101 and ADSP-2103. A
total of 14.5K words of data memory and 15K words of
program memory is addressable for the ADSP-2115.
Figure 4 shows a system diagram for the ADSP-2105, with one
serial I/O device, a boot EPROM, and optional external
program and data memory. A total of 14.5K words of data
memory and 15K words of program memory is addressable for
the ADSP-2105.
Figure 5 shows a system diagram for the ADSP-2111, with two
serial I/O devices, a host processor, a boot EPROM, and
optional external program and data memory. A total of 15K
words of data memory and 16K words of program memory is
addressable.
Programmable wait-state generation allows the processors to
easily interface to slow external memories.
The ADSP-2101, ADSP-2103, ADSP-2115, and ADSP-2111
processors also provide either: one external interrupt (IRQ2)
and two serial ports (SPORT0, SPORT1), or three external
interrupts (IRQ2, IRQ1, IRQ0) and one serial port (SPORT0).
The ADSP-2105 provides either: one external interrupt (IRQ2)
and one serial port (SPORT1), or three external interrupts
(IRQ2, IRQ1, IRQ0) with no serial port.
Clock Signals
The ADSP-21xx processors’ CLKIN input may be driven by a
crystal or by a TTL-compatible external clock signal. The
CLKIN input may not be halted or changed in frequency during
operation, nor operated below the specified low frequency limit.
If an external clock is used, it should be a TTL-compatible
signal running at the instruction rate. The signal should be
connected to the processor’s CLKIN input; in this case, the
XTAL input must be left unconnected.
Because the ADSP-21xx processors include an on-chip oscillator circuit, an external crystal may also be used. The crystal
should be connected across the CLKIN and XTAL pins, with
two capacitors connected as shown in Figure 2. A parallelresonant, fundamental frequency, microprocessor-grade crystal
should be used.
CLKIN
XTAL
CLKOUT
ADSP-21xx
Figure 2. External Crystal Connections
REV. C
–7–
ADSP-21xx
A clock output signal (CLKOUT) is generated by the processor,
synchronized to the processor’s internal cycles.
Reset
The RESET signal initiates a complete reset of the ADSP-21xx.
The RESET signal must be asserted when the chip is powered
up to assure proper initialization. If the RESET signal is applied
during initial power-up, it must be held long enough to allow
the processor’s internal clock to stabilize. If RESET is activated
at any time after power-up and the input clock frequency does
not change, the processor’s internal clock continues and does
not require this stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is
applied to the processor and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 tCK cycles will ensure that the PLL has locked (this does
not, however, include the crystal oscillator start-up time).
During this power-up sequence the RESET signal should be
held low. On any subsequent resets, the RESET signal must
meet the minimum pulse width specification, tRSP.
To generate the RESET signal, use either an RC circuit with an
external Schmidt trigger or a commercially available reset IC.
(Do not use only an RC circuit.)
Table IV. ADSP-21xx Pin Definitions
Pin
Name(s)
# of
Pins
Input /
Output
Address
Data1
14
24
O
I/O
RESET
IRQ2
BR2
BG
PMS
DMS
BMS
RD
WR
MMAP
CLKIN, XTAL
CLKOUT
VDD
GND
SPORT03
SPORT1
or Interrupts & Flags:
IRQ0 (RFS1)
IRQ1 (TFS1)
FI (DR1)
FO (DT1)
FL2–0 (ADSP-2111 Only)
Host Interface Port
(ADSP-2111 Only)
HSEL
HACK
HSIZE
BMODE
HMD0
HMD1
HRD/HRW
HWR/HDS
HD15–0/HAD15-0
HA2/ALE
HA1–0/Unused
1
1
1
1
1
1
1
1
1
1
2
1
I
I
I
O
O
O
O
O
O
I
I
O
5
5
I/O
I/O
Address outputs for program, data and boot memory.
Data I/O pins for program and data memories. Input only for
boot memory, with two MSBs used for boot memory addresses.
Unused data lines may be left floating.
Processor Reset Input
External Interrupt Request #2
External Bus Request Input
External Bus Grant Output
External Program Memory Select
External Data Memory Select
Boot Memory Select
External Memory Read Enable
External Memory Write Enable
Memory Map Select Input
External Clock or Quartz Crystal Input
Processor Clock Output
Power Supply Pins
Ground Pins
Serial Port 0 Pins (TFS0, RFS0, DT0, DR0, SCLK0)
Serial Port 1 Pins (TFS1, RFS1, DT1, DR1, SCLK1)
1
1
1
1
3
I
I
I
O
O
External Interrupt Request #0
External Interrupt Request #1
Flag Input Pin
Flag Output Pin
General Purpose Flag Output Pins
1
1
1
1
1
1
1
1
16
1
2
I
O
I
I
I
I
I
I
I/O
I
I
HIP Select Input
HIP Acknowledge Output
8/16-Bit Host Select (0 = 16-Bit, 1 = 8-Bit)
Boot Mode Select (0 = Standard EPROM Booting, 1 = HIP Booting)
Bus Strobe Select (0 = RD/WR, 1 = RW/DS)
HIP Address/Data Mode Select (0 = Separate, 1 = Multiplexed)
HIP Read Strobe or Read/Write Select
HIP Write Strobe or Host Data Strobe Select
HIP Data or HIP Data and Address
Host Address 2 Input or Address Latch Enable Input
Host Address 1 and 0 Inputs
Function
NOTES
1
Unused data bus lines may be left floating.
2
BR must be tied high (to V DD) if not used.
3
ADSP-2105 does not have SPORT0. (SPORT0 pins are No Connects on the ADSP-2105.)
–8–
REV. C
ADSP-21xx
ADSP-2101
or ADSP-2103
or ADSP-2115
1x CLOCK
or
CRYSTAL
14
ADDR 13-0
A13-0
D
CLKIN
23-22
ADDR
XTAL
D15-8
24
CLKOUT
DATA 23-0
RESET
OE
CS
BMS
IRQ2
DATA
BR
ADDR
D23-0
MMAP
DATA
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
e.g. EPROM
2764
27128
27256
27512
A13-0
BG
SERIAL
DEVICE
BOOT
MEMORY
OE
WE
RD
WR
SPORT 1
SCLK1
RFS1 or IRQ0
TFS1 or IRQ1
DT1 or FO
DR1 or FI
CS
(OPTIONAL)
A13-0
ADDR
D23-8
SPORT 0
SCLK0
RFS0
TFS0
DT0
DR0
PROGRAM
MEMORY
DATA
PMS
OE
WE
DMS
CS
DATA
MEMORY
&
PERIPHERALS
(OPTIONAL)
THE TWO MSBs OF THE DATA BUS (D 23-22 ) ARE USED TO SUPPLY THE TWO MSBs OF THE
BOOT MEMORY EPROM ADDRESS. THIS IS ONLY REQUIRED FOR THE 27256 AND 27512.
Figure 3. ADSP-2101/ADSP-2103/ADSP-2115 System
ADSP-2105
A13-0
14
1x CLOCK
or
CRYSTAL
ADDR 13-0
D
CLKIN
23-22
ADDR
XTAL
24
CLKOUT
RESET
DATA 23-0
IRQ2
D15-8
DATA
OE
CS
BMS
BR
ADDR
D23-0
MMAP
DATA
(OPTIONAL)
e.g. EPROM
2764
27128
27256
27512
A13-0
BG
SERIAL
DEVICE
BOOT
MEMORY
SPORT 1
SCLK1
RFS1 or IRQ0
TFS1 or IRQ1
DT1 or FO
DR1 or FI
RD
OE
WE
WR
CS
PROGRAM
MEMORY
(OPTIONAL)
A13-0
ADDR
PMS
OE
DATA
MEMORY
&
PERIPHERALS
DMS
WE
CS
(OPTIONAL)
D23-8
DATA
THE TWO MSBs OF THE DATA BUS (D 23-22 ) ARE USED TO SUPPLY THE TWO MSBs OF THE
BOOT MEMORY EPROM ADDRESS. THIS IS ONLY REQUIRED FOR THE 27256 AND 27512.
Figure 4. ADSP-2105 System
REV. C
–9–
ADSP-21xx
ADSP-2111
A13-0
14
1x CLOCK
or
CRYSTAL
ADDR 13-0
D
CLKIN
23-22
BOOT
MEMORY
ADDR
D15-8
24
CLKOUT
DATA 23-0
RESET
BR
A13-0
ADDR
BG
D23-0
MMAP
DATA
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
SPORT 1
SCLK1
RFS1 or IRQ0
TFS1 or IRQ1
DT1 or FO
DR1 or FI
SPORT 0
SCLK0
RFS0
TFS0
DT0
DR0
e.g. EPROM
2764
27128
27256
27512
DATA
OE
CS
BMS
IRQ2
SERIAL
DEVICE
(OPTIONAL)
XTAL
OE
RD
WR
WE
CS
PROGRAM
MEMORY
(OPTIONAL)
A13-0
ADDR
D23-8
DATA
PMS
OE
WE
DMS
CS
FL0
FL1
FL2
DATA
MEMORY
&
PERIPHERALS
(OPTIONAL)
HOST
PROCESSOR
HOST INTERFACE PORT
7
(OPTIONAL)
CONTROL
16
DATA / ADDR
THE TWO MSBs OF THE DATA BUS (D 23-22 ) ARE USED TO SUPPLY THE TWO MSBs OF THE
BOOT MEMORY EPROM ADDRESS. THIS IS ONLY REQUIRED FOR THE 27256 AND 27512.
Figure 5. ADSP-2111 System
The data lines are bidirectional. The program memory select
(PMS) signal indicates accesses to program memory and can be
used as a chip select signal. The write (WR) signal indicates a
write operation and is used as a write strobe. The read (RD)
signal indicates a read operation and is used as a read strobe or
output enable signal.
The RESET input resets all internal stack pointers to the empty
stack condition, masks all interrupts, and clears the MSTAT
register. When RESET is released, the boot loading sequence is
performed (provided there is no pending bus request and the
chip is configured for booting, with MMAP = 0). The first
instruction is then fetched from internal program memory
location 0x0000.
Program Memory Interface
The on-chip program memory address bus (PMA) and on-chip
program memory data bus (PMD) are multiplexed with the onchip data memory buses (DMA, DMD), creating a single
external data bus and a single external address bus. The external
data bus is bidirectional and is 24 bits wide to allow instruction
fetches from external program memory. Program memory may
contain code and data.
The external address bus is 14 bits wide. For the ADSP-2101,
ADSP-2103, and ADSP-2111, these lines can directly address
up to 16K words, of which 2K are on-chip. For the ADSP-2105
and ADSP-2115, the address lines can directly address up to
15K words, of which 1K is on-chip.
The ADSP-21xx processors write data from their 16-bit
registers to 24-bit program memory using the PX register to
provide the lower eight bits. When the processor reads 16-bit
data from 24-bit program memory to a 16-bit data register, the
lower eight bits are placed in the PX register.
The program memory interface can generate 0 to 7 wait states
for external memory devices; default is to 7 wait states after
RESET.
Program Memory Maps
Program memory can be mapped in two ways, depending on the
state of the MMAP pin. Figure 6 shows the two program
memory maps for the ADSP-2101, ADSP-2103, and
ADSP-2111. Figure 8 shows the program memory maps for the
ADSP-2105 and ADSP-2115. Figures 7 and 9 show the
program memory maps for the ADSP-2161/62 and ADSP-2163/
64, respectively.
–10–
REV. C
ADSP-21xx
ADSP-2101/ADSP-2103/ADSP-2111
ADSP-2105/ADSP-2115
When MMAP = 0, on-chip program memory RAM occupies
2K words beginning at address 0x0000. Off-chip program
memory uses the remaining 14K words beginning at address
0x0800. In this configuration–when MMAP = 0–the boot
loading sequence (described below in “Boot Memory Interface”) is automatically initiated when RESET is released.
When MMAP = 0, on-chip program memory RAM occupies
1K words beginning at address 0x0000. Off-chip program
memory uses the remaining 14K words beginning at address
0x0800. In this configuration–when MMAP = 0–the boot
loading sequence (described below in “Boot Memory Interface”) is automatically initiated when RESET is released.
When MMAP = 1, 14K words of off-chip program memory
begin at address 0x0000 and on-chip program memory RAM is
located in the upper 2K words, beginning at address 0x3800. In
this configuration, program memory is not booted although it
can be written to and read under program control.
When MMAP = 1, 14K words of off-chip program memory
begin at address 0x0000 and on-chip program memory RAM is
located in the 1K words between addresses 0x3800–0x3BFF. In
this configuration, program memory is not booted although it
can be written to and read under program control.
0x0000
0x0000
0x0000
1K
2K
LOADED FROM
EXTERNAL
BOOT MEMORY
LOADED FROM
EXTERNAL
BOOT MEMORY
0x07FF
0x0800
0x0000
INTERNAL RAM
INTERNAL
RAM
0x03FF
0x0400
RESERVED
1K
EXTERNAL
EXTERNAL
14K
0x07FF
0x0800
14K
0x37FF
0x3800
EXTERNAL
INTERNAL RAM
1K
EXTERNAL
0x37FF
0x3800
14K
14K
0x3BFF
0x3C00
INTERNAL
RAM
RESERVED
1K
2K
0x0000
Figure 8. ADSP-2105/ADSP-2115 Program Memory Maps
0x0000
0x0000
2K
EXTERNAL
8K
INTERNAL
ROM
MMAP=1
No Booting
MMAP=0
MMAP=1
No Booting
Figure 6. ADSP-2101/ADSP-2103/ADSP-2111 Program
Memory Maps
0x3FFF
0x3FFF
0x3FFF
0x3FFF
MMAP=0
4K
INTERNAL
ROM
0x07FF
0x0800
0x0000
2K
EXTERNAL
0x07FF
0x0800
2K
INTERNAL
ROM
6K
INTERNAL
ROM
0x0FF0
RESERVED
RESERVED
0x1FF0
0x1FF0
0x0FFF
0x1000
0x0FFF
0x1000
RESERVED
0x1FFF
0x2000
0x1FFF
0x2000
0x0FF0
RESERVED
6K
EXTERNAL
10K
EXTERNAL
12K
EXTERNAL
8K
EXTERNAL
0x37FF
0x3800
0x37FF
0x3800
2K
INTERNAL
ROM
2K
INTERNAL
ROM
0x3FFF
MMAP=0
0x3FFF
0x3FFF
MMAP=1
MMAP=0
Figure 7. ADSP-2161/62 Program Memory Maps
REV. C
0x3FFF
MMAP=1
Figure 9. ADSP-2163/64 Program Memory Maps
–11–
ADSP-21xx
Data Memory Interface
All Processors
The data memory address bus (DMA) is 14 bits wide. The
bidirectional external data bus is 24 bits wide, with the upper 16
bits used for data memory data (DMD) transfers.
The remaining 14K of data memory is located off-chip. This
external data memory is divided into five zones, each associated
with its own wait-state generator. This allows slower peripherals
to be memory-mapped into data memory for which wait states
are specified. By mapping peripherals into different zones, you
can accommodate peripherals with different wait-state requirements. All zones default to seven wait states after RESET.
The data memory select (DMS) signal indicates access to data
memory and can be used as a chip select signal. The write (WR)
signal indicates a write operation and can be used as a write
strobe. The read (RD) signal indicates a read operation and can
be used as a read strobe or output enable signal.
The ADSP-21xx processors support memory-mapped I/O, with
the peripherals memory-mapped into the data memory address
space and accessed by the processor in the same manner as data
memory.
Data Memory Map
ADSP-2101/ADSP-2103/ADSP-2111
For the ADSP-2101, ADSP-2103, and ADSP-2111, on-chip
data memory RAM resides in the 1K words beginning at
address 0x3800, as shown in Figure 10. Data memory locations
from 0x3C00 to the end of data memory at 0x3FFF are
reserved. Control and status registers for the system, timer,
wait-state configuration, and serial port operations are located in
this region of memory.
ADSP-2105/ADSP-2115
For the ADSP-2105 and ADSP-2115, on-chip data memory
RAM resides in the 512 words beginning at address 0x3800,
also shown in Figure 10. Data memory locations from 0x3A00
to the end of data memory at 0x3FFF are reserved. Control and
status registers for the system, timer, wait-state configuration,
and serial port operations are located in this region of memory.
0x0000
1K EXTERNAL
DWAIT0
0x0400
0x0800
EXTERNAL
RAM
Three bits in the processors’ System Control Register select
which page is loaded by the boot memory interface. Another bit
in the System Control Register allows the forcing of a boot
loading sequence under software control. Boot loading from
Page 0 after RESET is initiated automatically if MMAP = 0.
The boot memory interface can generate zero to seven wait
states; it defaults to three wait states after RESET. This allows
the ADSP-21xx to boot from a single low cost EPROM such as
a 27C256. Program memory is booted one byte at a time and
converted to 24-bit program memory words.
The BMS and RD signals are used to select and to strobe the
boot memory interface. Only 8-bit data is read over the data
bus, on pins D8-D15. To accommodate up to eight pages of
boot memory, the two MSBs of the data bus are used in the
boot memory interface as the two MSBs of the boot memory
address: D23, D22, and A13 supply the boot page number.
The BR signal is recognized during the booting sequence. The
bus is granted after loading the current byte is completed. BR
during booting may be used to implement booting under control
of a host processor.
Bus Interface
The ADSP-21xx processors can relinquish control of their data
and address buses to an external device. When the external
device requires control of the buses, it asserts the bus request
signal (BR). If the ADSP-21xx is not performing an external
memory access, it responds to the active BR input in the next
cycle by:
0x3000
1K EXTERNAL
DWAIT3
0x3400
1K EXTERNAL
DWAIT4
0x3800
1K for ADSP-2101
ADSP-2103
ADSP-2111
On the ADSP-2101, ADSP-2103, and ADSP-2111, boot
memory is an external 64K by 8 space, divided into eight
separate 8K by 8 pages. On the ADSP-2105 and ADSP-2115,
boot memory is a 32K by 8 space, divided into eight separate
4K by 8 pages. The 8-bit bytes are automatically packed into
24-bit instruction words by each processor, for loading into onchip program memory.
The ADSP-2100 Family Assembler and Linker allow the
creation of programs and data structures requiring multiple boot
pages during execution.
1K EXTERNAL
DWAIT1
10K EXTERNAL
DWAIT2
Boot Memory Interface
512 for ADSP-2105
ADSP-2115
ADSP-216x
0x3A00
0x3C00
INTERNAL
RAM
MEMORY-MAPPED
CONTROL REGISTERS
& RESERVED
•
Three-stating the data and address buses and the PMS,
DMS, BMS, RD, WR output drivers,
•
•
Asserting the bus grant (BG) signal,
and halting program execution.
If the Go mode is set, however, the ADSP-21xx will not halt
program execution until it encounters an instruction that
requires an external memory access.
0x3FFF
Figure 10. Data Memory Map (All Processors)
–12–
REV. C
ADSP-21xx
If the ADSP-21xx is performing an external memory access
when the external device asserts the BR signal, it will not threestate the memory interfaces or assert the BG signal until the
cycle after the access completes (up to eight cycles later depending on the number of wait states). The instruction does not need
to be completed when the bus is granted; the ADSP-21xx will
grant the bus in between two memory accesses if an instruction
requires more than one external memory access.
When the BR signal is released, the processor releases the BG
signal, re-enables the output drivers and continues program
execution from the point where it stopped.
The bus request feature operates at all times, including when
the processor is booting and when RESET is active. If this
feature is not used, the BR input should be tied high (to VDD).
Devices for conversion into a ADSP-216x ROM product.
The ADSP-2101 EZ-ICE emulator can be used for development of ADSP-216x systems. For the 3.3 V ADSP-2162 and
ADSP-2164, a voltage converter interface board provides 3.3 V
emulation.
Additional overlay memory is used for emulation of ADSP2161/62 systems. It should be noted that due to the use of offchip overlay memory to emulate the ADSP-2161/62, a performance loss may be experienced when both executing instructions and fetching program memory data from the off-chip
overlay memory in the same cycle. This can be overcome by
locating program memory data in on-chip memory.
Ordering Procedure for ADSP-216x ROM Processors
To place an order for a custom ROM-coded ADSP-2161,
ADSP-2162, ADSP-2163, or ADSP-2164 processor, you must:
Low Power IDLE Instruction
The IDLE instruction places the ADSP-21xx processor in low
power state in which it waits for an interrupt. When an interrupt
occurs, it is serviced and execution continues with instruction
following IDLE. Typically this next instruction will be a JUMP
back to the IDLE instruction. This implements a low-power
standby loop.
The IDLE n instruction is a special version of IDLE that slows
the processor’s internal clock signal to further reduce power
consumption. The reduced clock frequency, a programmable
fraction of the normal clock rate, is specified by a selectable
divisor, n, given in the IDLE instruction. The syntax of the
instruction is:
1. Complete the following forms contained in the ADSP ROM
Ordering Package, available from your Analog Devices sales
representative:
ADSP-216x ROM Specification Form
ROM Release Agreement
ROM NRE Agreement & Minimum Quantity Order (MQO)
Acceptance Agreement for Pre-Production ROM Products
2. Return the forms to Analog Devices along with two copies of
the Memory Image File (.EXE file) of your ROM code. The
files must be supplied on two 3.5" or 5.25" floppy disks for
the IBM PC (DOS 2.01 or higher).
3. Place a purchase order with Analog Devices for non-recurring
engineering changes (NRE) associated with ROM product
development.
IDLE n;
where n = 16, 32, 64, or 128.
The instruction leaves the chip in an idle state, operating at the
slower rate. While it is in this state, the processor’s other
internal clock signals, such as SCLK, CLKOUT, and the timer
clock, are reduced by the same ratio. Upon receipt of an
enabled interrupt, the processor will stay in the IDLE state for
up to a maximum of n CLKIN cycles, where n is the divisor
specified in the instruction, before resuming normal operation.
After this information is received, it is entered into Analog
Devices’ ROM Manager System which assigns a custom ROM
model number to the product. This model number will be
branded on all prototype and production units manufactured to
these specifications.
When the IDLE n instruction is used, it slows the processor’s
internal clock and thus its response time to incoming interrupts–
the 1-cycle response time of the standard IDLE state is increased by n, the clock divisor. When an enabled interrupt is
received, the ADSP-21xx will remain in the IDLE state for up
to a maximum of n CLKIN cycles (where n = 16, 32, 64, or
128) before resuming normal operation.
To minimize the risk of code being altered during this process,
Analog Devices verifies that the .EXE files on both floppy disks
are identical, and recalculates the checksums for the .EXE file
entered into the ROM Manager System. The checksum data, in
the form of a ROM Memory Map, a hard copy of the .EXE file,
and a ROM Data Verification form are returned to you for
inspection.
When the IDLE n instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the IDLE state (a maximum of n
CLKIN cycles).
ADSP-216x Prototyping
You can prototype your ADSP-216x system with either the
ADSP-2101 or ADSP-2103 RAM-based processors. When code
is fully developed and debugged, it can be submitted to Analog
REV. C
–13–
ADSP-21xx
Functional Differences for Older Revision Devices
A signed ROM Verification Form and a purchase order for
production units are required prior to any product being
manufactured. Prototype units may be applied toward the
minimum order quantity.
Older revisions of the ADSP-21xx processors have slight
differences in functionality. The two differences are as follows:
•
Bus Grant (BG) is asserted in the same cycle that Bus
Request (BR) is recognized (i.e. when setup and hold time
requirements are met for the BR input). Bus Request input is
a synchronous input rather than asynchronous. (In newer
revision devices, BG is asserted in the cycle after BR is
recognized.)
•
Only the standard IDLE instruction is available, not the
clock-reducing IDLE n instruction.
Upon completion of prototype manufacture, Analog Devices
will ship prototype units and a delivery schedule update for
production units. An invoice against your purchase order for the
NRE charges is issued at this time.
There is a charge for each ROM mask generated and a minimum order quantity. Consult your sales representative for
details. A separate order must be placed for parts of a specific
package type, temperature range, and speed grade.
To determine the revision of a particular ADSP-21xx device,
inspect the marking on the device. For example, an ADSP-2101
of revision 6.0 will have the following marking:
a
ADSP-2101
KS-66
EE/A12345-6.0
∆ 9234
← Package & Speed
← Lot # & Revision Code
← Date Code
The revision codes for the older versions of each ADSP-21xx
device are as follows:
Processor
Old Functionality
New Functionality
ADSP-2101
ADSP-2105
ADSP-2115
ADSP-2111
ADSP-2103
Revision Code ≤ 5.0
No Revision Code
Revision Code < 1.0
RevisionCode < 2.0
Revision code ≤ 5.0
Revision Code ≥ 6.0
Revision Code ≥ 1.0
Revision Code ≥ 1.0
Revision Code ≥ 2.0
Revision code ≥ 6.0
–14–
REV. C
ADSP-21xx
The ADSP-21xx assembly language uses an algebraic syntax for
ease of coding and readability. The sources and destinations of
computations and data movements are written explicitly in each
assembly statement, eliminating cryptic assembler mnemonics.
operational parallelism. There are five basic categories of
instructions: data move instructions, computational instructions, multifunction instructions, program flow control instructions and miscellaneous instructions. Multifunction instructions
perform one or two data moves and a computation.
Every instruction assembles into a single 24-bit word and
executes in a single cycle. The instructions encompass a wide
variety of instruction types along with a high degree of
The instruction set is summarized below. The ADSP-2100
Family Users Manual contains a complete reference to the
instruction set.
Instruction Set
ALU Instructions
[IF cond]
AR|AF
=
=
=
=
=
=
=
=
=
=
=
=
=
=
xop + yop [+ C] ;
xop – yop [+ C– 1] ;
yop – xop [+ C– 1] ;
xop AND yop ;
xop OR yop ;
xop XOR yop ;
PASS xop ;
– xop ;
NOT xop ;
ABS xop ;
yop + 1 ;
yop – 1 ;
DIVS yop, xop ;
DIVQ xop ;
Add/Add with Carry
Subtract X – Y/Subtract X – Y with Borrow
Subtract Y – X/Subtract Y – X with Borrow
AND
OR
XOR
Pass, Clear
Negate
NOT
Absolute Value
Increment
Decrement
Divide
xop * yop ;
MR + xop * yop ;
MR – xop * yop ;
MR ;
0;
Multiply
Multiply/Accumulate
Multiply/Subtract
Transfer MR
Clear
Conditional MR Saturation
MAC Instructions
[IF cond]
IF MV
MR|MF =
=
=
=
=
SAT MR ;
Shifter Instructions
[IF cond]
[IF cond]
[IF cond]
[IF cond]
[IF cond]
SR = [SR OR] ASHIFT xop ;
SR = [SR OR] LSHIFT xop ;
SR = [SR OR] ASHIFT xop BY ;
SR = [SR OR] LSHIFT xop BY ;
SE = EXP xop ;
SB = EXPADJ xop ;
SR = [SR OR] NORM xop ;
Arithmetic Shift
Logical Shift
Arithmetic Shift Immediate
Logical Shift Immediate
Derive Exponent
Block Exponent Adjust
Normalize
Data Move Instructions
reg = reg ;
reg = ;
reg = DM () ;
dreg = DM (Ix , My) ;
dreg = PM (Ix , My) ;
DM () = reg ;
DM (Ix , My) = dreg ;
PM (Ix , My) = dreg ;
Register-to-Register Move
Load Register Immediate
Data Memory Read (Direct Address)
Data Memory Read (Indirect Address)
Program Memory Read (Indirect Address)
Data Memory Write (Direct Address)
Data Memory Write (Indirect Address)
Program Memory Write (Indirect Address)
Multifunction Instructions
|| , dreg = dreg ;
|| , dreg = DM (Ix , My) ;
|| , dreg = PM (Ix , My) ;
DM (Ix , My) = dreg , || ;
PM (Ix , My) = dreg , || ;
dreg = DM (Ix , My) , dreg = PM (Ix , My) ;
| , dreg = DM (Ix , My) , dreg = PM (Ix , My) ;
REV. C
Computation with Register-to-Register Move
Computation with Memory Read
Computation with Memory Read
Computation with Memory Write
Computation with Memory Write
Data & Program Memory Read
ALU/MAC with Data & Program Memory Read
–15–
ADSP-21xx
Program Flow Instructions
DO [UNTIL term] ;
[IF cond] JUMP (Ix) ;
[IF cond] JUMP ;
[IF cond] CALL (Ix) ;
[IF cond] CALL ;
IF [NOT ] FLAG_IN
JUMP ;
IF [NOT ] FLAG_IN
CALL ;
[IF cond] SET|RESET|TOGGLE FLAG_OUT [, ...] ;
[IF cond] RTS ;
[IF cond] RTI ;
IDLE [(n)] ;
Do Until Loop
Jump
Call Subroutine
Jump/Call on Flag In Pin
Modify Flag Out Pin
Return from Subroutine
Return from Interrupt Service Routine
Idle
Miscellaneous Instructions
NOP ;
MODIFY (Ix , My);
[PUSH STS] [, POP CNTR] [, POP PC] [, POP LOOP] ;
ENA|DIS
SEC_REG [, ...] ;
BIT_REV
AV_LATCH
AR_SAT
M_MODE
TIMER
G_MODE
No Operation
Modify Address Register
Stack Control
Mode Control
Notation Conventions
Ix
My
cond
term
dreg
reg
;
,
[
]
[, ...]
option1 | option2
Index registers for indirect addressing
Modify registers for indirect addressing
Immediate data value
Immediate address value
Exponent (shift value) in shift immediate instructions (8-bit signed number)
Any ALU instruction (except divide)
Any multiply-accumulate instruction
Any shift instruction (except shift immediate)
Condition code for conditional instruction
Termination code for DO UNTIL loop
Data register (of ALU, MAC, or Shifter)
Any register (including dregs)
A semicolon terminates the instruction
Commas separate multiple operations of a single instruction
Optional part of instruction
Optional, multiple operations of an instruction
List of options; choose one.
Assembly Code Example
The following example is a code fragment that performs the filter tap update for an adaptive filter based on a least-mean-squared
algorithm. Notice that the computations in the instructions are written like algebraic equations.
MF=MX0 * MY1 ( RND), MX0=DM(I2,M1);
{MF=error * b eta}
MR=MX0 * MF ( RND), AY0=PM(I6,M5);
DO adapt UNTIL CE;
AR=MR1+AY0, MX0=DM(I2,M1), AY0=PM(I6,M7);
adapt:
PM(I6,M6)= A R, MR=MX0 * MF ( RND);
MODIFY(I2,M3);
MODIFY(I6,M7);
{Point to oldest data}
{Point to start of data}
–16–
REV. C
ADSP-2101/2105/2115/2161/2163–SPECIFICATIONS
ADSP-21xx
RECOMMENDED OPERATING CONDITIONS
Parameter
K Grade
Min
Max
B Grade
Min
Max
T Grade
Min
Max
Unit
VDD
TAMB
4.50
0
4.50
–40
4.50
–55
5.50
+125
V
°C
Max
Unit
Supply Voltage
Ambient Operating Temperature
5.50
+70
5.50
+85
See “Environmental Conditions” for information on thermal specifications.
ELECTRICAL CHARACTERISTICS
Parameter
VIH
VIH
VIL
VOH
Hi-Level Input Voltage3, 5
Hi-Level CLKIN Voltage
Lo-Level Input Voltage1, 3
Hi-Level Output Voltage2, 3, 7
VOL
IIH
IIL
IOZH
IOZL
CI
CO
Lo-Level Output Voltage2, 3, 7
Hi-Level Input Current1
Lo-Level Input Current1
Tristate Leakage Current4
Tristate Leakage Current4
Input Pin Capacitance1, 8, 9
Output Pin Capacitance4, 8, 9, 10
Test Conditions
Min
@ VDD = max
@ VDD = max
@ VDD = min
@ VDD = min, IOH = –0.5 mA
@ VDD = min, IOH = –100 µA8
@ VDD = min, IOL = 2 mA
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max6
@ VDD = max, VIN = 0 V6
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
2.0
2.2
V
V
V
V
V
V
µA
µA
µA
µA
pF
pF
0.8
2.4
VDD – 0.3
0.4
10
10
10
10
8
8
NOTES
1
Input-only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR1, DR0 (not on ADSP-2105).
2
Output pins: BG, PMS, DMS, BMS, RD, WR, A0–A13, CLKOUT, DT1, DT0 (not on ADSP-2105).
3
Bidirectional pins: D0–D23, SCLK1, RFS1, TFS1, SCLK0 (not on ADSP-2105), RFS0 (not on ADSP-2105), TFS0 (not on ADSP-2105).
4
Tristatable pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RSF1, TFS1, DT0 (not on ADSP-2105), SCLK0 (not on ADSP-2105),
RFS0 (not on ADSP-2105), TFS0 (not on ADSP-2105).
5
Input-only pins: RESET, IRQ2, BR, MMAP, DR1, DR0 (not on ADSP-2105).
6
0 V on BR, CLKIN Active (to force tristate condition).
7
Although specified for TTL outputs, all ADSP-21xx outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads.
8
Guaranteed but not tested.
9
Applies to PGA, PLCC, PQFP package types.
10
Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS *
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient) . . . –55ºC to +125ºC
Storage Temperature Range . . . . . . . . . . . . . –65ºC to +150ºC
Lead Temperature (10 sec) PGA . . . . . . . . . . . . . . . . . +300ºC
Lead Temperature (5 sec) PLCC, PQFP, TQFP . . . . +280ºC
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-21xx processors feature proprietary ESD protection circuitry to dissipate high energy
electrostatic discharges (Human Body Model), permanent damage may occur to devices subjected
to such discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality. Unused devices must be stored in conductive foam or shunts,
and the foam should be discharged to the destination socket before the devices are removed. Per
method 3015 of MIL-STD-883, the ADSP-21xx processors have been classified as Class 1 devices.
REV. C
–17–
WARNING!
ESD SENSITIVE DEVICE
ADSP-21xx
SPECIFICATIONS (ADSP-2101/2105/2115/2161/2163)
SUPPLY CURRENT & POWER (ADSP-2101/2105/2115/2161/2163)
Parameter
Test Conditions
IDD
Supply Current (Dynamic)1
IDD
Supply Current (Idle)1, 3
Min
@ VDD = max, tCK = 40 ns2
@ VDD = max, tCK = 50 ns2
@ VDD = max, tCK = 72.3 ns2
@ VDD = max, tCK = 40 ns4
@ VDD = max, tCK = 50 ns
@ VDD = max, tCK = 72.3 ns
Max
Unit
38
31
24
12
11
10
mA
mA
mA
mA
mA
mA
NOTES
1
Current reflects device operating with no output loads.
2
VIN = 0.4 V and 2.4 V.
3
Idle refers to ADSP-21xx state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.
4
ADSP-2105 is not available in a 25 MHz speed grade.
For typical supply current (internal power dissipation) figures, see Figure 11.
IDD DYNAMIC
220
1
205mW
200
POWER – mW
180
160
V DD = 5.5V
157mW
140
129mW
120
V DD = 5.0V
100
118mW
100mW
80
74mW
60
10.00
V DD = 4.5V
13.83
20.00
25.00
FREQUENCY – MHz
30.00
IDD IDLE
70
IDD IDLE n MODES
3
65
1,2
64mW
64mW
60
51mW
40
30
IDD IDLE
55
49mW
38mW
V DD = 5.0V
28mW
V DD = 4.5V
POWER – mW
POWER – mW
50
60
V DD = 5.5V
35mW
50
45
20
40
10
35
0
10.00
13.83
20.00
25.00
FREQUENCY – MHz
30
10.00
30.00
51mW
IDLE 16
41mW
40mW
43mW
42mW
IDLE 128
13.83
20.00
25.00
FREQUENCY – MHz
30.00
VALID FOR ALL TEMPERATURE GRADES.
1 POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
2 IDLE REFERS TO ADSP-21xx OPERATION DURING EXECUTION OF IDLE INSTRUCTION.
DEASSERTED PINS ARE DRIVEN TO EITHER V DD OR GND.
3 MAXIMUM POWER DISSIPATION AT V
= 5.5V DURING EXECUTION OF IDLE n INSTRUCTION.
DD
Figure 11. ADSP-2101 Power (Typical) vs. Frequency
–18–
REV. C
ADSP-21xx
SPECIFICATIONS (ADSP-2101/2105/2115/2161/2163)
POWER DISSIPATION EXAMPLE
CAPACITIVE LOADING
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C × VDD2 × f
Figures 12 and 13 show capacitive loading characteristics for the
ADSP-2101, ADSP-2105, ADSP-2115, and ADSP-2161/2163.
8
C = load capacitance, f = output switching frequency.
7
RISE TIME (0.8V - 2.0V) – ns
Example:
In an ADSP-2101 application where external data memory is
used and no other outputs are active, power dissipation is
calculated as follows:
Assumptions:
•
External data memory is accessed every cycle with 50% of the
address pins switching.
•
External data memory writes occur every other cycle with
50% of the data pins switching.
•
•
VDD = 4.5V
6
5
4
3
2
1
Each address and data pin has a 10 pF total load at the pin.
0
0
The application operates at VDD = 5.0 V and tCK = 50 ns.
25
50
Total Power Dissipation = PINT + (C × VDD × f )
2
8
9
1
1
× 10 pF
× 10 pF
× 10 pF
× 10 pF
× 52 V
× 52 V
× 52 V
× 52 V
× 20 MHz
× 10 MHz
× 10 MHz
× 20 MHz
=
=
=
=
40.0 mW
22.5 mW
2.5 mW
5.0 mW
70.0 mW
Total power dissipation for this example = PINT + 70.0 mW.
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating:
4
VDD = 4.5V
3
2
1
0
–1
–2
–3
TAMB = TCASE – (PD × θ CA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
θ CA = Thermal Resistance (Case-to-Ambient)
θ JA = Thermal Resistance (Junction-to-Ambient)
θ JC = Thermal Resistance (Junction-to-Case)
0
25
50
75
100 125
150
175
CL – pF
Figure 13. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating Temperature)
Package
θJA
θJC
θCA
PGA
PLCC
PQFP
TQFP
18°C/W
27°C/W
60°C/W
60°C/W
9°C/W
16°C/W
18°C/W
18°C/W
9°C/W
11°C/W
42°C/W
42°C/W
REV. C
175
5
× VDD2 × f
VALID OUTPUT DELAY OR HOLD – ns
Address, DMS
Data, WR
RD
CLKOUT
150
Figure 12. Typical Output Rise Time vs. Load Capacitance, CL
(at Maximum Ambient Operating Temperature)
(C × VDD2 × f ) is calculated for each output:
# of
Pins × C
125
L
PINT = internal power dissipation (from Figure 11).
Output
75
100
C – pF
–19–
ADSP-21xx
SPECIFICATIONS (ADSP-2101/2105/2115/2161/2163)
TEST CONDITIONS
The decay time, tDECAY, is dependent on the capacitative load,
CL , and the current load, iL , on the output pin. It can be
approximated by the following equation:
Figure 14 shows voltage reference levels for ac measurements.
INPUT
3.0V
1.5V
0.0V
OUTPUT
2.0V
1.5V
0.8V
t DECAY =
CL × 0.5 V
iL
from which
tDIS = tMEASURED – tDECAY
is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop
driving.
Figure 14. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (t E NA) is the interval from
when a reference signal reaches a high or low voltage level to
when the output has reached a specified high or low trip point,
as shown in Figure 15. If multiple pins (such as the data bus)
are enabled, the measurement value is that of the first pin to
start driving.
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The
output disable time (tDIS) is the difference of tMEASURED and
tDECAY, as shown in Figure 15. The time tMEASURED is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage.
REFERENCE
SIGNAL
tMEASURED
tENA
tDIS
VOH (MEASURED)
VOH (MEASURED) – 0.5V
2.0V
VOL (MEASURED) +0.5V
1.0V
OUTPUT
VOL (MEASURED)
VOH (MEASURED)
VOL (MEASURED)
tDECAY
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE
APPROXIMATELY 1.5V.
Figure 15. Output Enable/Disable
IOL
TO
OUTPUT
PIN
+1.5V
50pF
IOH
Figure 16. Equivalent Device Loading for AC Measurements
(Except Output Enable/Disable)
–20–
REV. C
ADSP-2111–SPECIFICATIONS
ADSP-21xx
RECOMMENDED OPERATING CONDITIONS
Parameter
VDD
TAMB
Supply Voltage
Ambient Operating Temperature
K Grade
Min
Max
B Grade
Min
Max
T Grade
Min
Max
Unit
4.50
0
4.50
–40
4.50
–55
V
°C
5.50
+70
5.50
+85
5.50
+125
See “Environmental Conditions” for information on thermal specifications.
ELECTRICAL CHARACTERISTICS
Parameter
VIH
VIH
VIL
VOH
Hi-Level Input Voltage3, 5
Hi-Level CLKIN Voltage
Lo-Level Input Voltage1, 3
Hi-Level Output Voltage2, 3, 7
VOL
IIH
IIL
IOZH
IOZL
CI
CO
Lo-Level Output Voltage2, 3, 7
Hi-Level Input Current1
Lo-Level Input Current1
Tristate Leakage Curren4
Tristate Leakage Current4
Input Pin Capacitance1, 8, 9
Output Pin Capacitance4, 8, 9, 10
Test Conditions
Min
@ VDD = max
@ VDD = max
@ VDD = min
@ VDD = min, IOH = –0.5 mA
@ VDD = min, IOH = –100 µA8
@ VDD = min, IOL = 2 mA
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0V
@ VDD = max, VIN = VDD max6
@ VDD = max, VIN = 0V6
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
2.0
2.2
Max
0.8
2.4
VDD – 0.3
0.4
10
10
10
10
8
8
Unit
V
V
V
V
V
V
µA
µA
µA
µA
pF
pF
NOTES
1
Input-only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR1, DR0, HSEL, HSIZE, BMODE, HMD0, HMD1, HRD/HRW, HWR/HDS, HA2/ALE, HA1-0.
2
Output pins: BG, PMS, DMS, BMS, RD, WR, A0–A13, CLKOUT, DT1, DT0, HACK, FL2-0.
3
Bidirectional pins: D0–D23, SCLK1, RFS1, TFS1, SCLK0, RFS0, TFS0, HD0–HD15/HAD0–HAD15.
4
Tristatable pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RSF1, TFS1, DT0, SCLK0, RFS0, TFS0, HD0–HD15/HAD0–HAD15.
5
Input-only pins: RESET, IRQ2, BR, MMAP, DR1, DR0, HSEL, HSIZE, BMODE, HMD0, HMD1, HRD/HRW, HWR/HDS, HA2/ALE, HA1-0.
6
0 V on BR, CLKIN Active (to force tristate condition).
7
Although specified for TTL outputs, all ADSP-2111 outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads.
8
Guaranteed but not tested.
9
Applies to ADSP-2111 PGA and PQFP packages.
10
Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient) . . . –55ºC to +125ºC
Storage Temperature Range . . . . . . . . . . . . . –65ºC to +150ºC
Lead Temperature (10 sec) PGA . . . . . . . . . . . . . . . . . +300ºC
Lead Temperature (5 sec) PQFP . . . . . . . . . . . . . . . . . +280ºC
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
REV. C
–21–
ADSP-21xx
SPECIFICATIONS (ADSP-2111)
SUPPLY CURRENT & POWER (ADSP-2111)
Parameter
Test Conditions
IDD
Supply Current (Dynamic)1
IDD
Supply Current (Idle)1, 3
Min
@ VDD = max, tCK = 50 ns2
@ VDD = max, tCK = 60 ns2
@ VDD = max, tCK = 76.9 ns2
@ VDD = max, tCK = 50 ns
@ VDD = max, tCK = 60 ns
@ VDD = max, tCK = 76.9 ns
Max
Unit
60
52
46
18
16
14
mA
mA
mA
mA
mA
mA
NOTES
1
Current reflects device operating with no output loads.
2
VIN = 0.4 V and 2.4 V.
3
Idle refers to ADSP-21xx state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.
For typical supply current (internal power dissipation) figures, see Figure 17.
POWER, INTERNAL 1
330
330mW
310
POWER (P INT ) – mW
290
270
250
V DD = 5.5V
260mW
250mW
230
V DD = 5.0V
210
190
200mW
200mW
170
150
V DD = 4.5V
155mW
14
15
16 17 18 19
1/ tCK – MHz
20
POWER, IDLE 1,2
POWER, IDLE n MODES 3
70
100mW
90
80
V DD = 5.5V
80mW
70mW
70
60
55mW
V DD = 5.0V
40mW
V DD = 4.5V
50
40
50mW
55
16 17 18 19
1/ tCK – MHz
38mW
36mW
IDLE 16;
IDLE 128;
20
55mW
V DD = 5.0V
50
45
40
30
15
IDLE;
60
35
30
14
70mW
65
POWER (P IDLE n ) – mW
POWER (P DLE ) – mW
I
100
34mW
32mW
14
15
16 17 18 19
1/ tCK – MHz
20
VALID FOR ALL TEMPERATURE GRADES.
1 POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
2 IDLE REFERS TO ADSP-21xx OPERATION DURING EXECUTION OF IDLE INSTRUCTION.
DEASSERTED PINS ARE DRIVEN TO EITHER V DD OR GND.
3 MAXIMUM POWER DISSIPATION AT V
= 5.0V DURING EXECUTION OF IDLE n INSTRUCTION.
DD
Figure 17. ADSP-2111 Power (Typical) vs. Frequency
–22–
REV. C
ADSP-21xx
SPECIFICATIONS (ADSP-2111)
POWER DISSIPATION EXAMPLE
CAPACITIVE LOADING
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C × VDD2 × f
Figures 18 and 19 show capacitive loading characteristics for the
ADSP-2111.
C = load capacitance, f = output switching frequency.
14
RISE TIME (0.8V - 2.0V) – ns
Example:
In an ADSP-2111 application where external data memory is
used and no other outputs are active, power dissipation is
calculated as follows:
Assumptions:
•
External data memory is accessed every cycle with 50% of the
address pins switching.
•
External data memory writes occur every other cycle with
50% of the data pins switching.
•
•
Each address and data pin has a 10 pF total load at the pin.
VDD = 4.5V
12
10
8
6
4
2
25
50
75
100
125
150
CL – pF
The application operates at VDD = 5.0 V and tCK = 50 ns.
Total Power Dissipation = PINT + (C × VDD2 × f )
Figure 18. Typical Output Rise Time vs. Load Capacitance, CL
(at Maximum Ambient Operating Temperature)
PINT = internal power dissipation (from Figure 17).
Output
Address, DMS
Data, WR
RD
CLKOUT
# of
Pins × C
× 10 pF
× 10 pF
× 10 pF
× 10 pF
8
9
1
1
VALID OUTPUT DELAY OR HOLD – ns
(C × VDD2 × f ) is calculated for each output:
× VDD2 × f
×5 V
× 52 V
× 52 V
× 52 V
2
× 20 MHz
× 10 MHz
× 10 MHz
× 20 MHz
=
=
=
=
40.0 mW
22.5 mW
2.5 mW
5.0 mW
70.0 mW
Total power dissipation for this example = PINT + 70.0 mW.
ENVIRONMENTAL CONDITIONS
+10
VDD = 4.5V
+8
+6
+4
+2
NOMINAL
–2
–4
–6
25
Ambient Temperature Rating:
TAMB = TCASE – (PD × θ CA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
θ CA = Thermal Resistance (Case-to-Ambient)
θ JA = Thermal Resistance (Junction-to-Ambient)
θ JC = Thermal Resistance (Junction-to-Case)
50
75 100
CL – pF
125
150
Figure 19. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating Temperature)
Package
θJA
θJC
θCA
PGA
PQFP
35°C/W
42°C/W
18°C/W
18°C/W
17°C/W
23°C/W
REV. C
+12
–23–
ADSP-21xx
SPECIFICATIONS (ADSP-2111)
The decay time, tDECAY, is dependent on the capacitative load,
CL , and the current load, iL , on the output pin. It can be
approximated by the following equation:
TEST CONDITIONS
Figure 20 shows voltage reference levels for ac measurements.
t DECAY =
3.0V
1.5V
0.0V
INPUT
from which
tDIS = tMEASURED – tDECAY
2.0V
1.5V
0.8V
OUTPUT
CL × 0.5 V
iL
is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop
driving.
Figure 20. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (t E NA) is the interval from
when a reference signal reaches a high or low voltage level to
when the output has reached a specified high or low trip point,
as shown in Figure 21. If multiple pins (such as the data bus)
are enabled, the measurement value is that of the first pin to
start driving.
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The
output disable time (tDIS) is the difference of tMEASURED and
tDECAY, as shown in Figure 21. The time tMEASURED is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage.
REFERENCE
SIGNAL
tMEASURED
tENA
tDIS
VOH (MEASURED)
VOH (MEASURED) – 0.5V
2.0V
VOL (MEASURED) +0.5V
1.0V
VOH (MEASURED)
OUTPUT
VOL (MEASURED)
VOL (MEASURED)
tDECAY
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE
APPROXIMATELY 1.5V.
Figure 21. Output Enable/Disable
IOL
TO
OUTPUT
PIN
+1.5V
50pF
IOH
Figure 22. Equivalent Device Loading for AC Measurements
(Except Output Enable/Disable)
–24–
REV. C
ADSP-2103/2162/2164–SPECIFICATIONS
ADSP-21xx
RECOMMENDED OPERATING CONDITIONS
K Grade
Min
Max
B Grade
Min
Max
Unit
3.00
0
3.00
–40
3.60
+85
V
°C
Test Conditions
Min
Max
@ VDD = max
@ VDD = min
@ VDD = min, IOH = –0.5 mA6
@ VDD = min, IOL = 2 mA6
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max5
@ VDD = max, VIN = 0 V5
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
2.0
Parameter
Supply Voltage
Ambient Operating Temperature
VDD
TAMB
3.60
+70
See “Environmental Conditions” for information on thermal specifications.
ELECTRICAL CHARACTERISTICS
Parameter
VIH
VIL
VOH
VOL
IIH
IIL
IOZH
IOZL
CI
CO
Hi-Level Input Voltage1, 3
Lo-Level Input Voltage1, 3
Hi-Level Output Voltage2, 3, 6
Lo-Level Output Voltage2, 3, 6
Hi-Level Input Current1
Lo-Level Input Current1
Tristate Leakage Current4
Tristate Leakage Current4
Input Pin Capacitance1, 7, 8
Output Pin Capacitance4, 7, 8, 9
0.4
2.4
NOTES
1
Input-only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR1, DR0.
2
Output pins: BG, PMS, DMS, BMS, RD, WR, A0–A13, CLKOUT, DT1, DT0.
3
Bidirectional pins: D0–D23, SCLK1, RFS1, TFS1, SCLK0, RFS0, TFS0.
4
Tristatable pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RSF1, TFS1, DT0, SCLK0, RFS0, TFS0.
5
0 V on BR, CLKIN Active (to force tristate condition).
6
All ADSP-2103, ADSP-2162, and ADSP-2164 outputs are CMOS and will drive to V DD and GND with no dc loads.
7
Guaranteed but not tested.
8
Applies to PLCC and PQFP package types.
9
Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.5 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient) . . . . –40ºC to +85ºC
Storage Temperature Range . . . . . . . . . . . . . –65ºC to +150ºC
Lead Temperature (5 sec) PLCC, PQFP . . . . . . . . . . . +280ºC
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
REV. C
–25–
0.4
10
10
10
10
8
8
Unit
V
V
V
V
µA
µA
µA
µA
pF
pF
ADSP-21xx
SPECIFICATIONS (ADSP-2103/2162/2164)
SUPPLY CURRENT & POWER (ADSP-2103/2162/2164)
Parameter
IDD
IDD
Test Conditions
Supply Current (Dynamic)1
Supply Current (Idle)1, 3
Min
@ VDD = max, tCK = 72.3 ns2
@ VDD = max, tCK = 72.3 ns
Max
Unit
14
4
mA
mA
NOTES
1
Current reflects device operating with no output loads.
2
VIN = 0.4 V and 2.4 V.
3
Idle refers to ADSP-21xx state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.
For typical supply current (internal power dissipation) figures, see Figure 23.
IDLE DYNAMIC 1,2
50
48mW
45
V DD = 3.6V
V DD = 3.30V
POWER – mW
40
37mW
35
30
29mW
25
20
24mW
19mW
15
V DD = 3.0V
15mW
10
5
0
5.00
7.00
10.00
13.83
FREQUENCY – MHz
IDD IDLE n MODES 3
IDD IDLE 1
14
14
V DD = 3.6V
12
10
13mW
13mW
12
9mW
8
8mW
V DD = 3.30V
6mW
6
5mW
V DD = 3.0V
9mW
8
IDLE 16
6
4
2
2
7.00
10.00
13.83
FREQUENCY – MHz
0
5.00
15.00
7mW
6mW
5mW
4
0
5.00
IDD IDLE
10
10mW
POWER – mW
POWER – mW
15.00
4mW
IDLE 128
7.00
10.00
13.83
FREQUENCY – MHz
15.00
VALID FOR ALL TEMPERATURE GRADES.
1 POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
2 IDLE REFERS TO ADSP-21xx OPERATION DURING EXECUTION OF IDLE INSTRUCTION.
DEASSERTED PINS ARE DRIVEN TO EITHER V DD OR GND.
3 MAXIMUM POWER DISSIPATION AT V
= 3.6V DURING EXECUTION OF IDLE n INSTRUCTION.
DD
Figure 23. ADSP-2103 Power (Typical) vs. Frequency
–26–
REV. C
ADSP-21xx
SPECIFICATIONS (ADSP-2103/2162/2164)
POWER DISSIPATION EXAMPLE
CAPACITIVE LOADING
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C × VDD2 × f
Figures 24 and 25 show capacitive loading characteristics for the
ADSP-2103, ADSP-2162, and ADSP-2164.
C = load capacitance, f = output switching frequency.
Example:
•
External data memory is accessed every cycle with 50% of the
address pins switching.
•
External data memory writes occur every other cycle with
50% of the data pins switching.
•
•
Each address and data pin has a 10 pF total load at the pin.
RISE TIME (0.8V-2.0V) – ns
In an ADSP-2103 application where external data memory is
used and no other outputs are active, power dissipation is
calculated as follows:
Assumptions:
30
25
VDD = 3.0V
20
15
10
5
25
50
75
100
CL – pF
125
150
The application operates at VDD = 3.3 V and tCK = 100 ns.
Total Power Dissipation = PINT + (C × VDD2 × f )
Figure 24. Typical Output Rise Time vs. Load Capacitance, CL
(at Maximum Ambient Operating Temperature)
PINT = internal power dissipation (from Figure 23).
Output
# of
Pins × C
Address, DMS
Data, WR
RD
CLKOUT
8
9
1
1
× 10 pF
× 10 pF
× 10 pF
× 10 pF
× VDD2
×f
× 3.32 V
× 3.32 V
× 3.32 V
× 3.32 V
× 10 MHz
× 5 MHz
× 5 MHz
× 10 MHz
=
=
=
=
VALID OUTPUT DELAY OR HOLD – ns
(C × VDD2 × f ) is calculated for each output:
8.71 mW
4.90 mW
0.55 mW
1.09 mW
15.25 mW
Total power dissipation for this example = PINT + 15.25 mW.
+8
+6
+4
VDD = 3.0V
+2
NOMINAL
–2
25
75
100
125
150
C L – pF
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating:
Figure 25. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating Temperature)
TAMB = TCASE – (PD × θ CA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
θ CA = Thermal Resistance (Case-to-Ambient)
θ JA = Thermal Resistance (Junction-to-Ambient)
θ JC = Thermal Resistance (Junction-to-Case)
Package
θJA
θJC
θCA
PGA
PQFP
27°C/W
60°C/W
16°C/W
18°C/W
11°C/W
42°C/W
REV. C
50
–27–
ADSP-21xx
SPECIFICATIONS (ADSP-2103/2162/2164)
TEST CONDITIONS
Figure 26 shows voltage reference levels for ac measurements.
The decay time, tDECAY, is dependent on the capacitative load,
CL, and the current load, iL, on the output pin. It can be
approximated by the following equation:
VDD
2
INPUT
t DECAY =
from which
VDD
2
OUTPUT
CL × 0.5 V
iL
tDIS = tMEASURED – tDECAY
is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop
driving.
Figure 26. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (t E NA) is the interval from
when a reference signal reaches a high or low voltage level to
when the output has reached a specified high or low trip point,
as shown in Figure 27. If multiple pins (such as the data bus)
are enabled, the measurement value is that of the first pin to
start driving.
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The
output disable time (tDIS) is the difference of tMEASURED and
tDECAY, as shown in Figure 27. The time tMEASURED is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage.
REFERENCE
SIGNAL
tMEASURED
tENA
tDIS
VOH (MEASURED)
VOH (MEASURED) – 0.5V
2.0V
VOL (MEASURED) +0.5V
1.0V
VOH (MEASURED)
OUTPUT
VOL (MEASURED)
VOL (MEASURED)
tDECAY
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE
APPROXIMATELY 1.5V.
Figure 27. Output Enable/Disable
IOL
TO
OUTPUT
PIN
VDD
2
50pF
IOH
Figure 28. Equivalent Device Loading for AC Measurements
(Except Output Enable/Disable)
–28–
REV. C
ADSP-21xx
TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the
processor operates correctly with other devices.
TIMING NOTES
MEMORY REQUIREMENTS
Switching characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
The table below shows common memory device specifications
and the corresponding ADSP-21xx timing parameters, for your
convenience.
GENERAL NOTES
Memory
Device
Specification
ADSP-21xx
Timing
Parameter
Timing
Parameter
Definition
Address Setup to Write Start
Address Setup to Write End
Address Hold Time
Data Setup Time
Data Hold Time
OE to Data Valid
Address Access Time
tASW
tAW
tWRA
tDW
tDH
tRDD
tAA
A0–A13, DMS, PMS Setup before WR Low
A0–A13, DMS, PMS Setup before WR Deasserted
A0–A13, DMS, PMS Hold after WR Deasserted
Data Setup before WR High
Data Hold after WR High
RD Low to Data Valid
A0–A13, DMS, PMS, BMS to Data Valid
REV. C
–29–
ADSP-21xx
TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
CLOCK SIGNALS & RESET
Parameter
Timing Requirement:
tCK
CLKIN Period
tCKL
CLKIN Width Low
CLKIN Width High
tCKH
RESET Width Low
tRSP
Switching Characteristic:
CLKOUT Width Low
tCPL
CLKOUT Width High
tCPH
tCKOH
CLKIN High to CLKOUT
High
13 MHz
Min Max
13.824 MHz
Min
Max
16.67 MHz
Min
Max
20 MHz
Min
Max
25 MHz
Min Max
Frequency
Dependency
Min
Max
Unit
76.9 150
20
20
384.5
72.3
150
20
20
361.5
60
20
20
300
50
20
20
250
40
15
15
200
20
20
5tCK1
ns
ns
ns
ns
28.5
28.5
0
26.2
26.2
0
20
20
0
20
20
150
20
15
15
0
150
20
10
10
0
150
0.5tCK – 10
0.5tCK – 10
15
ns
ns
ns
NOTES
1
Applies after powerup sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles, assuming stable CLKIN (not including crystal
oscillator startup time).
tCK
tCKH
CLKIN
tCKL
tCKOH
tCPH
CLKOUT
tCPL
Figure 29. Clock Signals
–30–
REV. C
ADSP-21xx
TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
INTERRUPTS & FLAGS
Parameter
Timing Requirement:
IRQx1 or FI Setup before
tIFS
CLKOUT Low2, 3
tIFS
IRQx1 or FI Setup before
CLKOUT Low (ADSP-2111)2, 3
tIFH IRQx1 or FI Hold after CLKOUT
High2, 3
Switching Characteristic:
tFOH FO Hold after CLKOUT High 5
tFOD FO Delay from CLKOUT High
13 MHz
Min Max
13.824 MHz
Min
Max
16.67 MHz
Min Max
20 MHz
Min Max
25 MHz
Min Max
Frequency
Dependency
Min
Max
Unit
34.2
33.1
30
27.5
25
0.25tCK + 154
ns
37.2
36.1
33
30.5
28
0.25tCK + 184
ns
19.2
18.1
15
12.5
10
0.25tCK
ns
0
ns
ns
0
0
0
15
15
0
15
0
15
12
NOTES
1
IRQx=IRQ0, IRQ1, and IRQ2.
2
If IRQx and FI inputs meet t IFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise they will be recognized
during the following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the ADSP-2100 Family User’s Manual for further
information on interrupt servicing.)
3
Edge-sensitive interrupts require pulse widths greater than 10 ns. Level-sensitive interrupts must be held low until serviced.
4
tIFS (min) = 0.25tCK + 20 ns for ADSP-2101TG-50, ADSP-2101TG/883B-50, ADSP-2111TG-52, and ADSP-2111TG/883B-52 ( Extended Temperature Range
devices).
5
tFOH (min) = –5 ns for ADSP-2111TG-52 and ADSP-2111TG/883B-52 (Extended Temperature Range devices).
CLKOUT
tFOD
tFOH
FLAG
OUTPUT(S)
tIFH
IRQx
FI
tIFS
Figure 30. Interrupts & Flags
REV. C
–31–
ADSP-21xx
TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
BUS REQUEST/GRANT
Parameter
Timing Requirement:
tBH BR Hold after CLKOUT High 1
tBS BR Setup before CLKOUT Low 1
Switching Characteristic:
tSD CLKOUT High to DMS,
PMS, BMS, RD, WR Disable
tSDB DMS, PMS, BMS, RD, WR
Disable to BG Low
tSE BG High to DMS, PMS,
BMS, RD, WR Enable
tSEC DMS, PMS, BMS, RD, WR
Enable to CLKOUT High
Frequency
13 MHz
13.824 MHz 16.67 MHz 20 MHz
25 MHz
Dependency
Min Max Min Max Min Max Min Max Min Max Min
Max
Unit
24.2
39.2
ns
ns
23.1
38.1
39.2
20
35
38.1
17.5
32.5
35
15
30
32.5
0.25tCK + 5
0.25tCK + 20
30
0.25tCK + 20 ns
0
0
0
0
0
0
ns
0
0
0
0
0
0
ns
9.2
8.1
5
2.5
1.52
0.25tCK – 102
ns
NOTES
1
If BR meets the t BS and tBH setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR requires
a pulse width greater than 10 ns.
2
For 25 MHz only the minimum frequency dependency formula for t SEC = (0.25tCK – 8.5).
Section 10.2.4, “Bus Request/Grant,” on page 212 of the ADSP-2100 Family User’s Manual (1st Edition, 1993) states that “When BR is recognized, the processor
responds immediately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors: BG is asserted in the cycle after
BR is recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
WR
BG
tSD
tSEC
tSDB
tSE
Figure 31. Bus Request/Grant
–32–
REV. C
ADSP-21xx
TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
MEMORY READ
Parameter
Timing Requirement:
tRDD RD Low to Data Valid
tAA
A0–A13, PMS, DMS, BMS to Data Valid
tRDH Data Hold from RD High
Switching Characteristic:
tRP
RD Pulse Width
tCRD CLKOUT High to RD Low
tASR A0–A13, PMS, DMS, BMS Setup before
RD Low
tRDA A0–A13, PMS, DMS, BMS Hold after RD
Deasserted
tRWR RD High to RD or WR Low
13 MHz
Min Max
13.824 MHz
Min Max
23.5
37.7
23.2
36.2
0
33.5
14.2
9.2
0
29.2
16.67 MHz
Min Max
17
27
0
28.2
13.1
8.1
28.1
Timing Requirement:
tRDD RD Low to Data Valid
tAA
A0–A13, PMS, DMS, BMS to Data Valid
tRDH Data Hold from RD High
Switching Characteristic:
tRP
RD Pulse Width
tCRD CLKOUT High to RD Low
tASR A0–A13, PMS, DMS, BMS Setup before
RD Low
tRDA A0–A13, PMS, DMS, BMS Hold after RD
Deasserted
tRWR RD High to RD or WR Low
22
10
5
25
17
7.5
2.5
7
12
0
22.5
12
5
1.51
20
ns
ns
ns
ns
ns
ns
10.2
9.1
6
3.5
1
ns
33.5
31.2
25
20
15
ns
Max
Unit
0.5tCK – 13 + w
0.75tCK – 18 + w
ns
ns
0.25tCK + 10
ns
ns
0
0.5tCK – 8 + w
0.25tCK – 5
0.25tCK – 101
ns
0.25tCK – 9
0.5tCK – 5
ns
ns
NOTES
1
For 25 MHz only minimum frequency dependency formula for t ASR = (0.25t CK – 8.5).
w = wait states × tCK.
CLKOUT
A0 – A13
DMS, PMS
BMS
tRDA
RD
tASR
tCRD
tRP
tRWR
D
tRDD
tAA
WR
Figure 32. Memory Read
REV. C
12
19.5
0
Frequency Dependency
(CLKIN ≤ 25 MHz)
Min
Parameter
20 MHz
25 MHz
Min Max Min Max Unit
–33–
tRDH
ADSP-21xx
TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
MEMORY WRITE
Parameter
Switching Characteristic:
tDW
Data Setup before WR High
tDH
Data Hold after WR High
tWP
WR Pulse Width
tWDE WR Low to Data Enabled
tASW A0–A13, DMS, PMS Setup before
WR Low
tDDR Data Disable before WR or RD Low
tCWR CLKOUT High to WR Low
tAW
A0–A13, DMS, PMS, Setup before WR
Deasserted
tWRA A0–A13, DMS, PMS Hold after WR
Deasserted
tWWR WR High to RD or WR Low
13 MHz
13.824 MHz 16.67 MHz
Min Max Min Max Min
Max
20 MHz
Min Max
25 MHz
Min Max Unit
25.5
9.2
30.5
0
9.2
12
2.5
17
0
2.5
7
0
12
0
1.51
9.2
14.2
35.7
23.2
8.1
28.2
0
8.1
29.2
17
5
22
0
5
8.1
13.1
32.2
28.1
5
10
23
2.5
7.5
15.5
25
22.5
1.51
5
8
ns
ns
ns
ns
ns
20
ns
ns
ns
10.2
9.1
6
3.5
1
ns
33.5
31.2
25
20
15
ns
Frequency Dependency
(CLKIN ≤ 25 MHz)
Min
Max
Parameter
Switching Characteristic:
tDW Data Setup before WR High
tDH Data Hold after WR High
tWP WR Pulse Width
tWDE WR Low to Data Enabled
tASW A0–A13, DMS, PMS Setup before WR Low
tDDR Data Disable before WR or RD Low
tCWR CLKOUT High to WR Low
tAW A0–A13, DMS, PMS, Setup before WR
Deasserted
tWRA A0–A13, DMS, PMS Hold after WR
Deasserted
tWWR WR High to RD or WR Low
0.5tCK – 13 + w
0.25tCK – 10
0.5tCK – 8 + w
0
0.25tCK – 101
0.25tCK – 101
0.25tCK – 5
Unit
ns
ns
ns
0.25tCK + 10
ns
ns
ns
0.75tCK – 22 + w
ns
0.25tCK – 9
0.5tCK – 5
ns
ns
NOTES
1
For 25 MHz only the minimum frequency dependency formula for t ASW and tDDR = (0.25t CK – 8.5).
w = wait states × tCK.
CLKOUT
A0 – A13
DMS, PMS
tWR A
WR
tAS W
tWP
tWWR
tAW
tDH
tCWR
tDDR
D
tDW
tWDE
RD
Figure 33. Memory Write
–34–
REV. C
ADSP-21xx
TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
SERIAL PORTS
Parameter
Timing Requirement:
tSCK SCLK Period
tSCS
DR/TFS/RFS Setup before SCLK Low
tSCH DR/TFS/RFS Hold after SCLK Low
tSCP SCLKIN Width
Switching Characteristic:
tCC
CLKOUT High to SCLKOUT
tSCDE SCLK High to DT Enable
tSCDV SCLK High to DT Valid
tRH
TFS/RFSOUT Hold after SCLK High
tRD
TFS/RFSOUT Delay from SCLK High
tSCDH DT Hold after SCLK High
tTDE TFS (Alt) to DT Enable
tTDV TFS (Alt) to DT Valid
tSCDD SCLK High to DT Disable
tRDV RFS (Multichannel, Frame Delay Zero)
to DT Valid
12.5 MHz
Min Max
13.0 MHz
Min Max
13.824 MHz*
Min Max
80
8
10
30
76.9
8
10
28
72.3
8
10
28
19.2 34.2
0
20
0
20
0
0
18
25
20
18.1
0
20
0
35
20
0
20
0
0
18
25
20
Frequency
Dependency
Min
Max
ns
ns
ns
ns
33.1
0.25tCK 0.25tCK + 15ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
0
20
0
0
18
25
20
*Maximum serial port operating frequency is 13.824 MHz for all processor speed grades except the 12.5 MHz ADSP-2101 and 13.0 MHz ADSP-2111.
CLKOUT
tCC
tCC
tSCK
SCLK
tSCP
tSCS
DR
RFSIN
TFSIN
tSCH
tSCP
tRD
tRH
RFSOUT
TFSOUT
tSCDD
tSCDV
tSCDE
tSCDH
DT
tTDE
tTDV
TFS
( ALTERNATE
FRAME MODE )
tRDV
RFS
( MULTICHANNEL MODE,
FRAME DELAY 0 {MFD = 0} )
Figure 34. Serial Ports
REV. C
–35–
Unit
ADSP-21xx
TIMING PARAMETERS (ADSP-2111)
HOST INTERFACE PORT
Separate Data & Address (HMD1 = 0 )
Read Strobe & Write Strobe (HMD0 = 0)
Parameter
Timing Requirement:
tHSU HA2-0 Setup before Start of Write or Read1, 2
tHDSU Data Setup before End of Write3
tHWDH Data Hold after End of Write3
tHH HA2-0 Hold after End of Write or Read3, 4
tHRWP Read or Write Pulse Width5
Switching Characteristic:
tHSHK HACK Low after Start of Write or Read1, 2
tHKH HACK Hold after End of Write or Read3, 4
tHDE Data Enabled after Start of Read2
tHDD Data Valid after Start of Read2
tHRDH Data Hold after End of Read4
tHRDD Data Disabled after End of Read4
13.0 MHz
Min Max
16.67 MHz
Min Max
20 MHz
Min Max
8
8
3
3
30
8
8
3
3
30
8
8
3
3
30
0
0
0
20
20
0
0
0
23
0
20
20
23
0
10
0
0
0
Unit
ns
ns
ns
ns
ns
20
20
23
0
10
No Frequency
Dependency
10
ns
ns
ns
ns
ns
ns
NOTES
1
Start of Write = HWR Low and HSEL Low.
2
Start of Read = HRD Low and HSEL Low.
3
End of Write = HWR High or HSEL High.
4
End of Read = HRD High or HSEL High.
5
Read Pulse Width = HRD Low and HSEL Low, Write Pulse Width = HWR Low and HSEL Low.
–36–
REV. C
ADSP-21xx
HA2–0
ADDRESS
tHRWP
HSEL
tHSU
Host Write Cycle
HWR
tHH
HACK
tHSHK
tHKH
DATA
HD15–0
tHWDH
tHDSU
ADDRESS
HA2–0
tHRWP
HSEL
tHSU
HRD
tHH
Host Read Cycle
HACK
tHKH
tHSHK
DATA
HD15–0
tHDE
tHRDH
tHRDD
tHDD
Figure 35. Host Interface Port (HMD1 = 0, HMD0 = 0)
REV. C
–37–
ADSP-21xx
TIMING PARAMETERS (ADSP-2111)
HOST INTERFACE PORT
Separate Data & Address (HMD1 = 0)
Read/Write Strobe & Data Strobe (HMD0 = 1)
Parameter
Timing Requirement:
tHSU HA2-0, HRW Setup before Start of Write or Read1
tHDSU Data Setup before End of Write2
tHWDH Data Hold after End of Write2
tHH HA2-0, HRW Hold after End of Write or Read2
tHRWP Read or Write Pulse Width3
Switching Characteristic:
tHSHK HACK Low after Start of Write or Read1
tHKH HACK Hold after End of Write or Read2
tHDE Data Enabled after Start of Read1
tHDD Data Valid after Start of Read1
tHRDH Data Hold after End of Read2
tHRDD Data Disabled after End of Read2
13.0 MHz
Min Max
16.67 MHz
Min Max
20 MHz
Min Max
8
8
3
3
30
8
8
3
3
30
8
8
3
3
30
0
0
0
20
20
0
0
0
23
0
20
20
23
0
10
0
0
0
Unit
ns
ns
ns
ns
ns
20
20
23
0
10
No Frequency
Dependency
10
ns
ns
ns
ns
ns
ns
NOTES
1
Start of Write or Read = HDS Low and HSEL Low.
2
End of Write or Read = HDS High or HSEL High.
3
Read or Write Pulse Width = HDS Low and HSEL Low.
–38–
REV. C
ADSP-21xx
ADDRESS
HA2–0
tHRWP
HSEL
tHSU
HRW
Host Write Cycle
HDS
tHH
HACK
tHSHK
tHKH
DATA
HD15–0
tHWDH
tHDSU
ADDRESS
HA2–0
tHRWP
HSEL
tHSU
HRW
Host Read Cycle
tHH
HDS
HACK
tHKH
tHSHK
HD15–0
DATA
tHDE
tHRDH
tHDD
tHRDD
Figure 36. Host Interface Port (HMD1 = 0, HMD0 =1)
REV. C
–39–
ADSP-21xx
TIMING PARAMETERS (ADSP-2111)
HOST INTERFACE PORT
Multiplexed Data & Address (HMD1 = 1)
Read Strobe & Write Strobe (HMD0 = 0)
Parameter
Timing Requirement:
tHALP ALE Pulse Width
tHASU HAD15-0 Address Setup before ALE Low
tHAH HAD15-0 Address Hold after ALE Low
tHALS Start of Write or Read after ALE Low1, 2
tHDSU HAD15-0 Data Setup before End of Write3
tHWDH HAD15-0 Data Hold after End of Write3
tHRWP Read or Write Pulse Width5
Switching Characteristic:
tHSHK HACK Low after Start of Write or Read1, 2
tHKH HACK Hold after End of Write or Read3, 4
tHDE HAD15-0 Data Enabled after Start of Read2
tHDD HAD15-0 Data Valid after Start of Read2
tHRDH HAD15-0 Data Hold after End of Read4
tHRDD HAD15-0 Data Disabled after End of Read4
13.0 MHz
Min Max
16.67 MHz
Min Max
20 MHz
Min Max
15
5
2
15
8
3
30
15
5
2
15
8
3
30
15
5
2
15
8
3
30
0
0
0
20
20
0
0
0
23
0
20
20
23
0
10
0
0
0
Unit
ns
ns
ns
ns
ns
ns
ns
20
20
23
0
10
No Frequency
Dependency
10
ns
ns
ns
ns
ns
ns
NOTES
1
Start of Write = HWR Low and HSEL Low.
2
Start of Read = HRD Low and HSEL Low.
3
End of Write = HWR High or HSEL High.
4
End of Read = HRD High or HSEL High.
5
Read Pulse Width = HRD Low and HSEL Low, Write Pulse Width = HWR Low and HSEL Low.
–40–
REV. C
ADSP-21xx
ALE
tHALP
tHRWP
HSEL
tHALS
Host Write Cycle
HWR
tHKH
tHSHK
HACK
HD15–0
tHASU
tHAH
ADDRESS
DATA
tHDSU
tHWDH
ALE
tHALP
tHRWP
HSEL
tHALS
Host Read Cycle
HRD
tHKH
tHSHK
HACK
HAD15–0
tHASU
tHAH
tHDE
ADDRESS
DATA
tHDD
tHRDH
tHRDD
Figure 37. Host Interface Port (HMD1 = 1, HMD0 = 0)
REV. C
–41–
ADSP-21xx
TIMING PARAMETERS (ADSP-2111)
HOST INTERFACE PORT
Multiplexed Data & Address (HMD1 = 1)
Read/Write Strobe & Data Strobe (HMD0 = 1 )
Parameter
Timing Requirement:
tHALP ALE Pulse Width
tHASU HAD15-0 Address Setup before ALE Low
tHAH HAD15-0 Address Hold after ALE Low
tHALS Start of Write or Read after ALE Low1
tHSU HRW Setup before Start of Write or Read1
tHDSU HAD15-0 Data Setup before End of Write2
tHWDH HAD15-0 Data Hold after End of Write2
tHH HRW Hold after End of Write or Read2
tHRWP Read or Write Pulse Width3
Switching Characteristic:
tHSHK HACK Low after Start of Write or Read1
tHKH HACK Hold after End of Write or Read2
tHDE HAD15-0 Data Enabled after Start of Read1
tHDD HAD15-0 Data Valid after Start of Read1
tHRDH HAD15-0 Data Hold after End of Read2
tHRDD HAD15-0 Data Disabled after End of Read2
13.0 MHz
Min Max
16.67 MHz
Min Max
20 MHz
Min Max
15
5
2
15
8
5
3
3
30
15
5
2
15
8
5
3
3
30
15
5
2
15
8
5
3
3
30
0
0
0
20
20
0
0
0
23
0
20
20
23
0
10
0
0
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
23
0
10
No Frequency
Dependency
10
ns
ns
ns
ns
ns
ns
NOTES
1
Start of Write or Read = HDS Low and HSEL Low.
2
End of Write or Read = HDS High or HSEL High.
3
Read or Write Pulse Width = HDS Low and HSEL Low.
–42–
REV. C
ADSP-21xx
ALE
tHALP
tHRWP
HSEL
tHH
tHALS
HRW
tHSU
Host Write Cycle
HDS
tHSHK
HACK
HD15–0
tHASU
tHKH
tHAH
ADDRESS
DATA
tHDSU
tHWDH
ALE
tHALP
tHALS
tHRWP
HSEL
tHH
HRW
tHSU
Host Read Cycle
HDS
tHKH
tHSHK
HACK
tHASU
tHAH
tHDE
HD15–0
ADDRESS
DATA
tHDD
Figure 38. Host Interface Port (HMD1 = 1, HMD0 = 1)
REV. C
–43–
tHRDH
tHRDD
ADSP-21xx
TIMING PARAMETERS (ADSP-2103/2162/2164)
GENERAL NOTES
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the
processor operates correctly with other devices.
MEMORY REQUIREMENTS
The table below shows common memory device specifications
and the corresponding ADSP-21xx timing parameters, for your
convenience.
TIMING NOTES
Switching characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Memory Specification
ADSP-21xx
Timing Parameter
Timing Parameter Definition
Address Setup to Write Start
Address Setup to Write End
Address Hold Time
Data Setup Time
Data Hold Time
OE to Data Valid
Address Access Time
tASW
tAW
tWRA
tDW
tDH
tRDD
tAA
A0–A13, DMS, PMS Setup before WR Low
A0–A13, DMS, PMS Setup before WR Deasserted
A0–A13, DMS, PMS Hold after WR Deasserted
Data Setup before WR High
Data Hold after WR High
RD Low to Data Valid
A0–A13, DMS, PMS, BMS to Data Valid
–44–
REV. C
ADSP-21xx
TIMING PARAMETERS (ADSP-2103/2162/2164)
CLOCK SIGNALS & RESET
10.24 MHz
Min
Max
Parameter
Timing Requirement:
tCK
CLKIN Period
tCKL
CLKIN Width Low
tCKH
CLKIN Width High
tRSP
RESET Width Low
Switching Characteristic:
tCPL
CLKOUT Width Low
tCPH
CLKOUT Width High
tCKOH CLKIN High to CLKOUT High
97.6
20
20
488
Frequency
Dependency
Min
Max
Unit
5tCK1
ns
ns
ns
ns
150
38.8
38.8
0
0.5tCK – 10
0.5tCK – 10
20
ns
ns
ns
NOTES
1
Applies after powerup sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator startup time).
tCK
tCKH
CLKIN
tCKL
tCKOH
tCPH
CLKOUT
tCPL
Figure 39. Clock Signals
REV. C
–45–
ADSP-21xx
TIMING PARAMETERS (ADSP-2103/2162/2164)
INTERRUPTS & FLAGS
Parameter
Timing Requirement:
tIFS
IRQx1 or FI Setup before CLKOUT Low2, 3
tIFH
IRQx1 or FI Hold after CLKOUT High2, 3
Switching Characteristic:
tFOH
FO Hold after CLKOUT High
tFOD
FO Delay from CLKOUT High
10.24 MHz
Min
Max
Frequency
Dependency
Min
44.4
24.4
0.25tCK + 20
0.25tCK
0
15
Max
Unit
ns
ns
ns
ns
NOTES
1
IRQx=IRQ0, IRQ1, and IRQ2.
2
If IRQx and FI inputs meet t IFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise they will be recognized during the
following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the ADSP-2100 Family User’s Manual for further information on
interrupt servicing.)
3
Edge-sensitive interrupts require pulse widths greater than 10 ns. Level-sensitive interrupts must be held low until serviced.
CLKOUT
tFOD
tFOH
FLAG
OUTPUT(S)
tIFH
IRQx
FI
tIFS
Figure 40. Interrupts & Flags
–46–
REV. C
ADSP-21xx
TIMING PARAMETERS (ADSP-2103/2162/2164)
BUS REQUEST/GRANT
Parameter
Timing Requirement:
tBH
BR Hold after CLKOUT High1
tBS
BR Setup before CLKOUT Low1
Switching Characteristic:
tSD
CLKOUT High to DMS, PMS, BMS, RD, WR Disable
tSDB
DMS, PMS, BMS, RD, WR Disable to BG Low
tSE
BG High to DMS, PMS, BMS, RD, WR Enable
tSEC
DMS, PMS, BMS, RD, WR Enable to CLKOUT High
10.24 MHz
Min
Max
Frequency
Dependency
Min
29.4
44.4
0.25tCK + 5
0.25tCK + 20
44.4
Max
ns
ns
0.25tCK + 20
0
0
14.4
0.25tCK – 10
NOTES
1
If BR meets the t BS and tBH setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR
requires a pulse width greater than 10 ns.
Section 10.2.4, “Bus Request/Grant,” of the ADSP-2100 Family User’s Manual (1st Edition, ©1993) states that “When BR is recognized, the processor
responds immediately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors: BG is asserted in the
cycle after BR is recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
WR
BG
tSD
tSEC
tSDB
tSE
Figure 41. Bus Request/Grant
REV. C
–47–
Unit
ns
ns
ns
ns
ADSP-21xx
TIMING PARAMETERS (ADSP-2103/2162/2164)
MEMORY READ
10.24 MHz
Min
Max
Parameter
Timing Requirement:
tRDD
RD Low to Data Valid
tAA
A0–A13, PMS, DMS, BMS to Data Valid
tRDH
Data Hold from RD High
Switching Characteristic:
tRP
RD Pulse Width
tCRD
CLKOUT High to RD Low
tASR
A0–A13, PMS, DMS, BMS Setup before RD Low
tRDA
A0–A13, PMS, DMS, BMS Hold after RD Deasserted
tRWR
RD High to RD or WR Low
Frequency
Dependency
Min
33.8
49.2
Max
Unit
0.5tCK – 15 + w
0.75tCK – 24 + w
ns
ns
ns
0
43.8
19.4
12.4
14.4
38.8
34.4
0.5tCK – 5 + w
0.25tCK – 5
0.25tCK + 10
0.25tCK – 12
0.25tCK – 10
0.5tCK – 10
ns
ns
ns
ns
ns
w = wait states × tCK.
CLKOUT
A0 – A13
DMS, PMS
BMS
tRDA
RD
tASR
tCRD
tRP
tRWR
D
tRDD
tAA
tRDH
WR
Figure 42. Memory Read
–48–
REV. C
ADSP-21xx
TIMING PARAMETERS (ADSP-2103/2162/2164)
MEMORY WRITE
Parameter
10.24 MHz
Min
Max
Switching Characteristic:
tDW
Data Setup before WR High
tDH
Data Hold after WR High
tWP
WR Pulse Width
tWDE
WR Low to Data Enabled
tASW
A0–A13, DMS, PMS Setup before WR Low
tDDR
Data Disable before WR or RD Low
tCWR
CLKOUT High to WR Low
tAW
A0–A13, DMS, PMS, Setup before WR Deasserted
tWRA
A0–A13, DMS, PMS Hold After WR Deasserted
tWWR
WR High to RD or WR Low
38.8
14.4
43.8
0
12.4
14.4
19.4
58.2
14.4
38.8
Frequency
Dependency
Min
34.4
ns
ns
ns
0.25tCK – 12
0.25tCK – 10
0.25tCK – 5
0.25tCK + 10
0.75tCK – 15 + w
0.25tCK – 10
0.5tCK – 10
ns
ns
ns
ns
ns
ns
CLKOUT
A0 – A13
DMS, PMS
tWRA
WR
tWP
tWWR
tAW
tDH
tCWR
D
tDW
tWDE
RD
Figure 43. Memory Write
REV. C
–49–
Unit
0.5tCK – 10 + w
0.25tCK – 10
0.5tCK – 5 + w
w = wait states × tCK.
tASW
Max
tDDR
ADSP-21xx
TIMING PARAMETERS (ADSP-2103/2162/2164)
SERIAL PORTS
Frequency
Dependency
Min
Max
10.24 MHz
Min
Max
Parameter
Timing Requirement:
tSCK
SCLK Period
tSCS
DR/TFS/RFS Setup before SCLK Low
tSCH
DR/TFS/RFS Hold after SCLK Low
tSCP
SCLKin Width
Switching Characteristic:
tCC
CLKOUT High to SCLKout
tSCDE
SCLK High to DT Enable
tSCDV
SCLK High to DT Valid
tRH
TFS/RFSout Hold after SCLK High
tRD
TFS/RFSout Delay from SCLK High
tSCDH
DT Hold after SCLK High
tTDE
TFS (alt) to DT Enable
tTDV
TFS (alt) to DT Valid
tSCDD
SCLK High to DT Disable
tRDV
RFS (Multichannel, Frame Delay Zero)
to DT Valid
CLKOUT
97.6
8
10
28
tCK
24.4
0
39.4
0.25tCK
0.25tCK + 15
28
28
0
0
18
30
20
tCC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCK
SCLK
tSCP
tSCS
DR
RFSIN
TFSIN
ns
ns
ns
ns
0
tCC
Unit
tSCH
tSCP
tRD
tRH
RFSOUT
TFSOUT
tSCDD
tSCDV
tSCDE
tSCDH
DT
tTDE
tTDV
TFS
( ALTERNATE
FRAME MODE )
tRDV
RFS
( MULTICHANNEL MODE,
FRAME DELAY 0 {MFD = 0} )
Figure 44. Serial Ports
–50–
REV. C
ADSP-21xx
PIN CONFIGURATIONS
68-Pin PGA
L
1
K
J
H
G
F
E
D
C
B
V DD
A3
A1
RESET
BR
V DD
D22
D20
GND
A4
A2
A0
IRQ2
MMAP
D23
D21
D19
INDEX
(NC)
A
A
B
C
D
E
F
G
H
J
GND
D20
D22
V DD
BR
RESET
A1
A3
V DD
D23
MMAP
IRQ2
A0
A2
A4
A6
A5
2
A7
GND
3
A9
A8
4
A11
A10
5
A13
A12
6
DMS
PMS
7
1
1
D18
2
2
D18
D19
D21
D17
D16
3
3
D16
D17
INDEX
(NC)
D15
D14
4
4
D14
D15
D13
D12
5
5
D12
D13
GND
D11
6
6
D11
GND
D10
D9
7
7
D9
D10
K
L
1
2
A5
A6
3
GND
A7
4
A8
A9
5
A10
A11
6
A12
A13
7
PMS
DMS
8
BMS
BG
D8
D7
8
8
D7
D8
BG
BMS
8
9
XTAL
CLK
IN
D6
D5
9
9
D5
D6
CLK
IN
XTAL
9
CLK
OUT
RD
TFS0
GND
D3
10
10
D3
D4
D1
CLK
OUT
10
WR
DT0
RFS0
DR0
11
11
D2
D0
K
J
H
G
B
C
10
11
PGA PACKAGE
L
ADSP-2101
TOP VIEW
(PINS DOWN)
IRQ1
SCLK0 (TFS1)
FI
(DR1)
V DD
D1
D4
FO
(DT1)
IRQ0
(RFS1)
SCLK1
D0
D2
F
E
D
C
B
A
PGA PACKAGE
A
ADSP-2101
BOTTOM VIEW
(PINS UP)
V DD
FI
(DR1)
IRQ0
SCLK1 (RFS1)
D
E
IRQ1
(TFS1)
SCLK0
GND
TFS0
RD
FO
(DT1)
DR0
RFS0
DT0
WR
F
G
H
J
K
11
L
NC = NO CONNECT
REV. C
PGA
Number
Pin
Name
PGA
Number
Pin
Name
PGA
Number
Pin
Name
PGA
Number
Pin
Name
K11
K10
J11
J10
H11
H10
G11
G10
F11
F10
E11
E10
D11
D10
C11
C10
B11
WR
RD
DT0
TFS0
RFS0
GND
DR0
SCLK0
FO (DT1)
IRQ1 (TFS1)
IRQ0 (RFS1)
FI
(DR1)
SCLK1
VDD
D0
D1
D2
A10
B10
A9
B9
A8
B8
A7
B7
A6
B6
A5
B5
A4
B4
A3
B3
A2
D3
D4
D5
D6
D7
D8
D9
D10
D11
GND
D12
D13
D14
D15
D16
D17
D18
B1
B2
C1
C2
D1
D2
E1
E2
F1
F2
G1
G2
H1
H2
J1
J2
K1
GND
D19
D20
D21
D22
D23
VDD
MMAP
BR
IRQ2
RESET
A0
A1
A2
A3
A4
VDD
L2
K2
L3
K3
L4
K4
L5
K5
L6
K6
L7
K7
L8
K8
L9
K9
L10
C3
A5
A6
GND
A7
A8
A9
A10
A11
A12
A13
PMS
DMS
BMS
BG
XTAL
CLKIN
CLKOUT
Index (NC)
–51–
ADSP-21xx
PIN CONFIGURATIONS
D9
D8
D7
D6
D5
D4
D3
67
66
65
64
63
62
61
D12
3
D10
D13
4
D11
D14
5
68
D15
6
GND
D16
7
1
D17
8
2
D18
9
68-Lead PLCC
PIN 1
IDENTIFIER
GND
10
D19
11
59 D1
D20
12
58 D0
D21
13
57 VDD
D22
14
D23
15
60 D2
56 SCLK1
PLCC PACKAGE
55 FI (DR1)
VDD
16
MMAP
17
BR
18
IRQ2
19
RESET
20
A0
21
A1
22
A2
23
47 TFS0 (NC on ADSP-2105)
A3
24
46 DT0 (NC on ADSP-2105)
A4
25
45 RD
VDD
26
44 WR
54 IRQ0 (RFS1)
ADSP-2101
ADSP-2103
ADSP-2105
ADSP-2115
ADSP-2161/62/63/64
53 IRQ1 (TFS1)
52 FO (DT1)
51 SCLK0 (NC on ADSP-2105)
50 DR0 (NC on ADSP-2105)
49 GND
43
42
CLKIN
CLKOUT
41
XTAL
40
BG
39
BMS
38
48 RFS0 (NC on ADSP-2105)
DMS
37
PMS
36
A13
34
35
A12
A11
33
A10
32
A9
30
31
A8
A7
29
GND
28
A6
A5
27
TOP VIEW
(PINS DOWN)
NC = NO CONNECT
PLCC
Pin
Number Name
PLCC
Pin
Number Name
PLCC
Pin
Number Name
PLCC
Pin
Number Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
D11
GND
D12
D13
D14
D15
D16
D17
D18
GND
D19
D20
D21
D22
D23
VDD
MMAP
BR
IRQ2
RESET
A0
A1
A2
A3
A4
VDD
A5
A6
GND
A7
A8
A9
A10
A11
A12
A13
PMS
DMS
BMS
BG
XTAL
CLKIN
CLKOUT
WR
RD
DT0 (NC on ADSP-2105)
TFS0 (NC on ADSP-2105)
RFS0 (NC on ADSP-2105)
GND
DR0
(NC on ADSP-2105)
SCLK0 (NC on ADSP-2105)
–52–
FO
(DT1)
IRQ1 (TFS1)
IRQ0 (RFS1)
FI
(DR1)
SCLK1
VDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
REV. C
ADSP-21xx
PIN CONFIGURATIONS
VDD
VDD
A4
A3
A2
A1
A0
RESET
IRQ2
BR
MMAP
VDD
VDD
D23
D22
D21
D20
D19
GND
GND
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
80-Lead PQFP
80-Lead TQFP
A5
1
60
D18
A6
2
59
D17
GND
3
58
D16
GND
4
57
D15
A7
5
56
D14
A8
6
55
D13
A9
7
54
D12
A10
8
53
GND
A11
9
52
GND
A12
10
51
D11
A13
11
50
D10
PMS
12
49
D9
DMS
13
48
D8
BMS
14
47
D7
BG
15
46
D6
XTAL
16
45
D5
CLKIN
17
44
D4
NC
18
43
NC
NC
19
42
NC
NC
20
41
NC
PQFP PACKAGE
ADSP-2101
ADSP-2103
ADSP-2115
ADSP-2161/62/63/64
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
CLKOUT
WR
RD
DT0
TFS0
RFS0
GND
GND
DR0
SCLK0
FO (DT1)
IRQ1 (TFS1)
IRQ0 (RFS1)
F1 (DR1)
SCLK1
VDD
D0
D1
D2
D3
TOP VIEW
(PINS DOWN)
NC = NO CONNECT
PQFP/
TQFP
Pin
Number Name
PQFP/
TQFP
Pin
Number Name
PQFP/
TQFP
Pin
Number Name
PQFP/
TQFP
Pin
Number Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
REV. C
A5
A6
GND
GND
A7
A8
A9
A10
A11
A12
A13
PMS
DMS
BMS
BG
XTAL
CLKIN
NC
NC
NC
CLKOUT
WR
RD
DT0
TFS0
RFS0
GND
GND
DR0
SCLK0
FO (DT1)
IRQ1 (TFS1)
IRQ0 (RFS1)
FI
(DR1)
SCLK1
VDD
D0
D1
D2
D3
–53–
NC
NC
NC
D4
D5
D6
D7
D8
D9
D10
D11
GND
GND
D12
D13
D14
D15
D16
D17
D18
GND
GND
D19
D20
D21
D22
D23
VDD
VDD
MMAP
BR
IRQ2
RESET
A0
A1
A2
A3
A4
VDD
VDD
ADSP-21xx
PIN CONFIGURATIONS
100-Pin PGA
13
12
11
10
9
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
9
10
11
12
13
D1
D3
D5
D7
D10
D12
D13
D16
D18
D20
D21
D23
N
D2
D4
D6
D9
D11
D14
D17
D19
D22
GND
MMAP
M
D8
GND
D15
RESET
BR
L
V DD
PMS
K
DMS
BMS
J
RD
WR
BG
H
A1
A0
A2
G
A5
A4
A3
F
A6
GND
E
A8
A7
D
A11
A9
C
A12
A10
B
A13
VDD
A
12
13
D23
D21
D20
D18
D16
D13
D12
D10
D7
D5
D3
D1
V DD
N
N
V DD
M MMAP
GND
D22
D19
D17
D14
D11
D9
D6
D4
D2
D0
FL1
M
M
FL1
D0
D15
GND
D8
FL2
FL0
L
L
FL0
FL2
SCLK1
F1
(DR1)
K
F1
(DR1)
SCLK1
J
IRQ0
IRQ1
(TFS1) (RFS1)
N
L
K
J
BR
PMS
BMS
RESET
V DD
DMS
IRQ0
(RFS1)
PGA PACKAGE
ADSP-2111
IRQ1
(TFS1)
K
J
FO
(DT1)
GND
SCLK0
H
H
SCLK0
GND
FO
(DT1)
RFSO
TFS0
DR0
G
G
DR0
TFS0
RFSO
HACK
CLK
OUT
DT0
F
F
DT0
CLK
OUT
HACK
H
BG
WR
RD
G
A2
A0
A1
F
A3
A4
A5
E
GND
A6
BMODE
IRQ2
E
E
IRQ2
BMODE
D
A7
A8
HMD1
HMD0
D
D
HMD0
HMD1
C
A9
A11
B
A10
A12
A
HD15
TOP VIEW
(PINS DOWN)
HD13
HD11
INDEX
PIN
(NC)
HRD /
HRW
HSIZE
C
C
HA1
HSEL
HWR/
HDS
B
B
HA0
1
HD9
HD7
XTAL
HD8
V DD
HD4
HD3
HD2
HD0
HA2 /
ALE
4
3
2
VDD
A13
HD14
HD12
HD10
GND
HD6
HD5
CLK
IN
13
12
11
10
9
8
7
6
5
HD1
PGA PACKAGE
A
A
HSIZE
HRD/
HRW
INDEX
PIN
(NC)
HWR/
HDS
HSEL
HA1
HA0
HA2 /
ALE
2
1
ADSP-2111
BOTTOM VIEW
(PINS UP)
XTAL
HD7
HD9
HD4
V DD
HD8
HD1
HD3
HD11
HD13
HD15
HD0
HD2
CLK
IN
HD5
HD6
GND
HD10
HD12
HD14
3
4
5
6
7
8
9
10
11
NC = NO CONNECT
PGA
Pin
Number Name
PGA
Pin
Number Name
PGA
Pin
Number Name
PGA
Pin
Number Name
N13
N12
M13
M12
L13
L12
K13
K12
J13
J12
H13
H12
H11
G13
G12
G11
F13
F12
F11
E13
E12
D13
D12
C13
C12
B13
A13
A12
B12
A11
B11
A10
B10
A9
B9
A8
B8
C8
A7
B7
C7
A6
B6
C6
A5
B5
A4
B4
A3
B3
C3
A2
A1
B1
B2
C1
C2
D1
D2
E1
E2
F1
F2
F3
G1
G2
G3
H1
H2
H3
J1
J2
K1
K2
L1
L2
M1
N1
N2
M2
N3
M3
N4
M4
N5
M5
N6
M6
L6
N7
M7
L7
N8
M8
L8
N9
M9
N10
M10
N11
M11
D23
D21
MMAP
GND
BR
RESET
PMS
VDD
BMS
DMS
BG
WR
RD
A2
A0
A1
A3
A4
A5
GND
A6
A7
A8
A9
A11
A10
VDD
A13
A12
HD14
HD15
HD12
HD13
HD10
HD11
GND
HD8
HD9
HD6
VDD
HD7
HD5
HD4
XTAL
CLKIN
HD3
HD2
HD1
HD0
HA1
–54–
Index (NC)
HA2/ALE
HA0
HWR/HDS
HSEL
HSIZE
HRD/HRW
HMD0
HMD1
IRQ2
BMODE
DT0
CLKOUT
HACK
DR0
TFS0
RFS0
SCLK0
GND
FO (DT1)
IRQ1 (TFS1)
IRQ0 (RFS1)
FI
(DR1)
SCLK1
FL0
FL2
FL1
VDD
D1
D0
D3
D2
D5
D4
D7
D6
D10
D9
D8
D12
D11
GND
D13
D14
D15
D16
D17
D18
D19
D20
D22
REV. C
ADSP-21xx
PIN CONFIGURATIONS
13
12
11
10
9
8
7
6
5
4
3
2
1
100
99
98
97
96
95
94
93
92
91
90
89
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
GND
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
100-Lead Bumpered PQFP
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
BEVELED EDGE
PQFP PACKAGE
ADSP-2111
TOP VIEW
(PINS DOWN)
VDD
FL2
FL1
FL0
SCLK1
FI (DR1)
IRQ0 (RFS1)
IRQ1 (TFS1)
FO (DT1)
GND
SCLK0
DR0
RFS0
TFS0
DT0
CLKOUT
HACK
IRQ2
BMODE
HMD0
HMD1
HSIZE
HRD/HRW
HWR/HDS
HSEL
A12
A13
HD15
HD14
HD13
HD12
HD11
HD10
HD9
HD8
GND
VDD
HD7
HD6
HD5
HD4
XTAL
CLKIN
HD3
HD2
HD1
HD0
HA2/ALE
HA1
HA0
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
GND
MMAP
RESET
BR
VDD
PMS
DMS
BMS
RD
WR
BG
A0
A1
A2
A3
A4
A5
GND
A6
A7
A8
A9
A10
A11
VDD
NOTE: PIN 1 IS LOCATED AT THE CENTER OF THE BEVELED-EDGE SIDE OF THE PACKAGE.
PQFP
Pin
Number Name
PQFP
Pin
Number Name
PQFP
Pin
Number Name
PQFP
Pin
Number Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
REV. C
GND
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
GND
MMAP
RESET
BR
VDD
PMS
DMS
BMS
RD
WR
BG
A0
A1
A2
A3
A4
A5
GND
A6
A7
A8
A9
A10
A11
VDD
A12
A13
HD15
HD14
HD13
HD12
HD11
HD10
HD9
HD8
GND
VDD
–55–
HD7
HD6
HD5
HD4
XTAL
CLKIN
HD3
HD2
HD1
HD0
HA2/ALE
HA1
HA0
HSEL
HWR/HDS
HRD/HRW
HSIZE
HMD1
HMD0
BMODE
IRQ2
HACK
CLKOUT
DT0
TFS0
RFS0
DR0
SCLK0
GND
FO (DT1)
IRQ1 (TFS1)
IRQ0 (RFS1)
FI
(DR1)
SCLK1
FL0
FL1
FL2
VDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
ADSP-21xx
OUTLINE DIMENSIONS
ADSP-2101
68-Pin Grid Array (PGA)
PGA LOCATION A1 QUADRANT MARKING
e1
e2
1
2
3
4
GUIDE
PIN ONLY
e1
D
5
e2
TOP VIEW
6
7
8
9
10
11
L K J H G F E D C
D
SEATING
PLANE
B A
A1
A
L3
φb
φb1
e
SYMBOL
INCHES
MIN
TYP
MAX
A
0.123
A1
φb
0.164
MILLIMETERS
MIN
TYP
MAX
3.12
0.50
0.016
φb1
0.018
4.17
1.27
0.020
0.46
0.050
1.27
D
1.086
1.110
27.58
28.19
e1
0.988
1.012
25.10
25.70
e2
0.788
0.812
20.02
20.62
e
0.100
2.54
L3
0.180
4.57
–56–
REV. C
ADSP-21xx
OUTLINE DIMENSIONS
ADSP-21xx
68-Lead Plastic Leaded Chip Carrier (PLCC)
9
61
e
PIN 1 IDENTIFIER
D2
b
BOTTOM VIEW
(PINS UP)
TOP VIEW
(PINS DOWN)
D
b1
A1
D1
D
A
SYMBOL
INCHES
MIN
TYP
MAX
A
0.169
A1
0.175
4.29
0.104
14.37
4.45
12.64
b
0.017
0.018
0.019
0.43
10.46
0.48
b1
0.027
0.028
0.029
0.69
10.71
0.74
D
0.985
0.990
0.995
25.02
25.15
25.27
D1
0.950
0.952
0.954
24.13
24.18
24.23
D2
0.895
0.910
0.925
22.73
23.11
23.50
D
e
REV. C
0.172
MILLIMETERS
MIN
TYP
MAX
0.050
11.27
0.004
–57–
10.10
ADSP-21xx
OUTLINE DIMENSIONS
ADSP-21xx
80-Lead Metric Plastic Quad Flatpack (PQFP)
80-Lead Metric Thin Quad Flatpack (TQFP)
D
SEATING
PLANE
D1
A
D3
L
80
61
1
60
TOP VIEW
(PINS DOWN)
E3
D
20
E1
E
41
21
40
A2
e
B
A1
PQFP
SYMBOL
TQFP
MILLIMETERS
MIN
TYP
MAX
INCHES
MIN
TYP
MAX
MILLIMETERS
MIN TYP
MAX
INCHES
MIN
TYP MAX
2.45
0.096
1.60
0.063
A
A1
0.25
A2
1.90
2.00
2.10
0.075
0.079
0.083
D, E
16.95
17.20
17.45
0.667
0.678
D 1, E 1
13.90
14.00
14.10
0.547
12.35
12.43
D 3, E 3
0.010
0.05
0.15
0.002
0.006
1.40
1.45
0.053
0.055 0.057
0.690
15.75 16.00
16.25
0.620
0.630 0.640
0.551
0.555
13.95 14.00
14.05
0.549
0.551 0.553
0.486
0.490
12.35
12.43
1.35
0.486 0.490
0.65
0.80
0.95
0.026
0.031
0.037
0.50
0.60
0.75
0.020
0.024 0.030
e
0.57
0.65
0.73
0.023
0.026
0.029
0.57
0.65
0.73
0.022
0.026 0.029
B
0.22
0.30
0.38
0.009
0.012
0.015
0.25
0.30
0.35
0.010
0.012 0.014
D
L
0.10
0.004
–58–
0.10
0.004
REV. C
ADSP-21xx
OUTLINE DIMENSIONS
ADSP-2111
100-Pin Grid Array (PGA)
e1
PGA LOCATION A1 QUADRANT MARKING
e2
1
2
3
4
INDEX
PIN
ONLY
e1
D
5
6
e2
TOP VIEW
7
8
9
10
11
12
13
N M L
D
K J
H
G F
E
D C
A1
A
L3
SEATING
PLANE
φb
e
SYMBOL
INCHES
MIN
TYP
MAX
A
0.123
A1
φb
0.169
MILLIMETERS
MIN
TYP
MAX
3.12
0.050
0.016
φb1
REV. C
φ b1
0.018
4.29
1.27
0.020
0.41
0.050
0.46
0.51
1.27
D
1.308
1.32
1.342
33.22
33.53
34.09
e1
1.188
1.20
1.212
30.18
30.48
30.78
e2
0.988
1.00
1.012
25.10
25.4
25.70
e
0.100
2.54
L3
0.180
4.57
–59–
B A
ADSP-21xx
OUTLINE DIMENSIONS
ADSP-2111
100-Lead Bumpered Plastic Quad Flatpack (PQFP)
D
SEATING
PLANE
2
D
D
A
1
89
13
L
1
88
14
Beveled
Edge
TOP VIEW
(PINS DOWN)
D3 , E 3
E1
E
E2
64
38
D
39
63
A2
e
NOTE: PIN 1 IS THE CENTER PIN ON THE BEVELED-EDGE SIDE OF THE PACKAGE.
1
SYMBOL
MIN
INCHES
TYP
MAX
A
MILLIMETERS
MIN
TYP
MAX
0.180
4.572
A1
0.020
0.030
0.040
0.508
0.762
1.016
A2
0.130
0.140
0.150
3.302
3.556
3.810
D, E
0.875
0.880
0.885
22.225
22.352
22.479
D1, E 1
0.747
0.750
0.753
18.974
19.050
19.126
D2, E 2
0.897
0.900
0.903
22.784
22.860
22.936
0.600
0.603
15.240
15.316
D3, E 3
L
0.036
e
0.022
B
0.008
D
A
B
0.025
0.046
0.914
0.028
0.559
0.012
0.203
0.004
–60–
1.168
0.635
0.711
0.305
0.102
REV. C
ADSP-21xx
ORDERING GUIDE
Part Number1
Ambient
Temperature
Range
Instruction
Rate (MHz)
Package
Description
Package
Option
ADSP-2101KG-66
ADSP-2101BG-66
ADSP-2101KP-66
ADSP-2101BP-66
ADSP-2101KS-66
ADSP-2101BS-66
ADSP-2101KG-80
ADSP-2101BG-80
ADSP-2101KP-80
ADSP-2101BP-80
ADSP-2101KS-80
ADSP-2101BS-80
ADSP-2101KP-100
ADSP-2101BP-100
ADSP-2101KS-100
ADSP-2101BS-100
ADSP-2101KG-100
ADSP-2101BG-100
ADSP-2101TG-50
ADSP-2103KP-40 (3.3 V)
ADSP-2103BP-40 (3.3 V)
ADSP-2103KS-40 (3.3 V)
ADSP-2103BS-40 (3.3 V)
ADSP-2105KP-55
ADSP-2105BP-55
ADSP-2105KP-80
ADSP-2105BP-80
ADSP-2115KP-66
ADSP-2115BP-66
ADSP-2115KS-66
ADSP-2115BS-66
ADSP-2115KST-66
ADSP-2115BST-66
ADSP-2115KP-80
ADSP-2115BP-80
ADSP-2115KS-80
ADSP-2115BS-80
ADSP-2115KST-80
ADSP-2115BST-80
ADSP-2115KP-100
ADSP-2115BP-100
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
–55°C to +125°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
16.67 MHz
16.67 MHz
16.67 MHz
16.67 MHz
16.67 MHz
16.67 MHz
20.0 MHz
20.0 MHz
20.0 MHz
20.0 MHz
20.0 MHz
20.0 MHz
25.0 MHz
25.0 MHz
25.0 MHz
25.0 MHz
25.0 MHz
25.0 MHz
12.5 MHz
10.24 MHz
10.24 MHz
10.24 MHz
10.24 MHz
13.824 MHz
13.824 MHz
20.0 MHz
20.0 MHz
16.67 MHz
16.67 MHz
16.67 MHz
16.67 MHz
16.67 MHz
16.67 MHz
20.0 MHz
20.0 MHz
20.0 MHz
20.0 MHz
20.0 MHz
20.0 MHz
25.0 MHz
25.0 MHz
68-Pin PGA
68-Pin PGA
68-Lead PLCC
68-Lead PLCC
80-Lead PQFP
80-Lead PQFP
68-Pin PGA
68-Pin PGA
68-Lead PLCC
68-Lead PLCC
80-Lead PQFP
80-Lead PQFP
68-Pin PLCC
68-Pin PLCC
80-Lead PQFP
80-Lead PQFP
68-Lead PGA
68-Lead PGA
68-Pin PGA
68-Lead PLCC
68-Lead PLCC
80-Lead PQFP
80-Lead PQFP
68-Lead PLCC
68-Lead PLCC
68-Lead PLCC
68-Lead PLCC
68-Lead PLCC
68-Lead PLCC
80-Lead PQFP
80-Lead PQFP
80-Lead TQFP
80-Lead TQFP
68-Lead PLCC
68-Lead PLCC
80-Lead PQFP
80-Lead PQFP
80-Lead TQFP
80-Lead TQFP
68-Lead PLCC
68-Lead PLCC
G-68A
G-68A
P-68A
P-68A
S-80
S-80
G-68A
G-68A
P-68A
P-68A
S-80
S-80
P-68A
P-68A
S-80
S-80
G-68A
G-68A
G-68A
P-68A
P-68A
S-80
S-80
P-68A
P-68A
P-68A
P-68A
P-68A
P-68A
S-80
S-80
ST-80
ST-80
P-68A
P-68A
S-80
S-80
ST-80
ST-80
P-68A
P-68A
NOTES
1
K = Commercial Temperature Range (0°C to +70°C).
B = Industrial Temperature Range (–40°C to +85°C).
T = Extended Temperature Range (–55°C to +125°C).
G = Ceramic PGA (Pin Grid Array).
P = PLCC (Plastic Leaded Chip Carrier).
S = PQFP (Plastic Quad Flatpack).
ST = TQFP (Thin Quad Flatpack)
REV. C
–61–
ADSP-21xx
ORDERING GUIDE
Part Number1
Ambient
Temperature
Range
Instruction
Rate (MHz)
Package
Description
Package
Option
ADSP-2111KG-52
ADSP-2111BG-52
ADSP-2111KS-52
ADSP-2111BS-52
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
13.0 MHz
13.0 MHz
13.0 MHz
13.0 MHz
100-Pin PGA
100-Pin PGA
100-Lead PQFP
100-Lead PQFP
G-100A
G-100A
S-100A
S-100A
ADSP-2111KG-66
ADSP-2111BG-66
ADSP-2111KS-66
ADSP-2111BS-66
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
16.67 MHz
16.67 MHz
16.67 MHz
16.67 MHz
100-Pin PGA
100-Pin PGA
100-Lead PQFP
100-Lead PQFP
G-100A
G-100A
S-100A
S-100A
ADSP-2111KG-80
ADSP-2111BG-80
ADSP-2111KS-80
ADSP-2111BS-80
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
20.0 MHz
20.0 MHz
20.0 MHz
20.0 MHz
100-Pin PGA
100-Pin PGA
100-Lead PQFP
100-Lead PQFP
G-100A
G-100A
S-100A
S-100A
ADSP-2111TG-52
–55°C to +125°C
13.0 MHz
100-Pin PGA
G-100A
ADSP-2161KP-662
ADSP-2161BP-662
ADSP-2161KS-662
ADSP-2161BS-662
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
16.67 MHz
16.67 MHz
16.67 MHz
16.67 MHz
68-Lead PLCC
68-Lead PLCC
80-Lead PQFP
80-Lead PQFP
P-68A
P-68A
S-80
S-80
ADSP-2162KP-40 (3.3 V)2
ADSP-2162BP-40 (3.3 V)2
ADSP-2162KS-40 (3.3 V)2
ADSP-2162BS-40 (3.3 V)2
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
10.24 MHz
10.24 MHz
10.24 MHz
10.24 MHz
68-Lead PLCC
68-Lead PLCC
80-Lead PQFP
80-Lead PQFP
P-68A
P-68A
S-80
S-80
ADSP-2163KP-662
ADSP-2163BP-662
ADSP-2163KS-662
ADSP-2163BS-662
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
16.67 MHz
16.67 MHz
16.67 MHz
16.67 MHz
68-Lead PLCC
68-Lead PLCC
80-Lead PQFP
80-Lead PQFP
P-68A
P-68A
S-80
S-80
ADSP-2163KP-1002
ADSP-2163BP-1002
ADSP-2163KS-1002
ADSP-2163BS-1002
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
25 MHz
25 MHz
25 MHz
25 MHz
68-Lead PLCC
68-Lead PLCC
80-Lead PQFP
80-Lead PQFP
P-68A
P-68A
S-80
S-80
ADSP-2164KP-40 (3.3 V)2
ADSP-2164BP-40 (3.3 V)2
ADSP-2164KS-40 (3.3 V)2
ADSP-2164BS-40 (3.3 V)2
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
10.24 MHz
10.24 MHz
10.24 MHz
10.24 MHz
68-Lead PLCC
68-Lead PLCC
80-Lead PQFP
80-Lead PQFP
P-68A
P-68A
S-80
S-80
NOTES
1
K = Commercial Temperature Range (0°C to +70°C).
B = Industrial Temperature Range (–40°C to +85°C).
T = Extended Temperature Range (–55°C to +125°C).
G = Ceramic PGA (Pin Grid Array).
P = PLCC (Plastic Leaded Chip Carrier).
S = PQFP (Plastic Quad Flatpack).
2
Minimum order quantities required. Contact factory for further information.
–62–
REV. C
–63–
–64–
PRINTED IN U.S.A.
C1891b–10–2/96
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