SHARC
Digital Signal Processor
ADSP-21160M/ADSP-21160N
SUMMARY
FEATURES
High performance 32-bit DSP—applications in audio, medical, military, graphics, imaging, and communication
Super Harvard architecture—4 independent buses for dual
data fetch, instruction fetch, and nonintrusive, zero-overhead I/O
Backward compatible—assembly source level compatible
with code for ADSP-2106x DSPs
Single-instruction, multiple-data (SIMD) computational
architecture—two 32-bit IEEE floating-point computation
units, each with a multiplier, ALU, shifter, and register file
Integrated peripherals—integrated I/O processor, 4M bits
on-chip dual-ported SRAM, glueless multiprocessing features, and ports (serial, link, external bus, and JTAG)
100 MHz (10 ns) core instruction rate (ADSP-21160N)
Single-cycle instruction execution, including SIMD operations in both computational units
Dual data address generators (DAGs) with modulo and bitreverse addressing
Zero-overhead looping and single-cycle loop setup, providing efficient program sequencing
IEEE 1149.1 JTAG standard Test Access Port and on-chip
emulation
400-ball 27 mm × 27 mm PBGA package
Available in lead-free (RoHS compliant) package
200 million fixed-point MACs sustained performance
(ADSP-21160N)
CORE PROCESSOR
DAG1
8 x 4 x 32
DAG2
8 x 4 x 32
PROCESSOR PORT
ADDR
DATA
ADDR
DATA
I/O PORT
DATA
ADDR
DATA
ADDR
JTAG
6
TEST AND
EMULATION
PROGRAM
SEQUENCER
PM ADDRESS BUS
DM ADDRESS BUS
PM DATA BUS
BUS
CONNECT
(PX)
TWO INDEPENDENT
DUAL-PORTED BLOCKS
BLOCK 1
INSTRUCTION
CACHE
32 x 48-BIT
BLOCK 0
TIMER
DUAL-PORTED SRAM
DM DATA BUS
IOD
64
32
EXTERNAL
PORT
IOA
18
ADDR BUS
MUX
32
32
MULTIPROCESSOR
INTERFACE
16/32/40/48/64
DATA BUS
MUX
32/40/64
64
HOST PORT
MULT
DATA
REGISTER
FILE
(PEX)
16 x 40-BIT
BARREL
SHIFTER
ALU
BARREL
SHIFTER
DATA
REGISTER
FILE
(PEY)
16 x 40-BIT
MULT
DMA
CONTROLLER
IOP
REGISTERS
(MEMORY
MAPPED)
6
SERIAL PORTS
(2)
CONTROL,
STATUS AND
DATA BUFFERS
ALU
4
LINK PORTS
(6)
6
60
I/O PROCESSOR
Figure 1. Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. D
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©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADSP-21160M/ADSP-21160N
Single-instruction, multiple-data (SIMD)
architecture provides
Two computational processing elements
Concurrent execution—each processing element executes
the same instruction, but operates on different data
Code compatibility—at assembly level, uses the same
instruction set as the ADSP-2106x SHARC DSPs
Parallelism in buses and computational units allows
Single-cycle execution (with or without SIMD) of a multiply
operation, an ALU operation, a dual memory read or
write, and an instruction fetch
Transfers between memory and core at up to four
32-bit floating- or fixed-point words per cycle
Accelerated FFT butterfly computation through a multiply
with add and subtract
Memory attributes
4M bits on-chip dual-ported SRAM for independent access
by core processor, host, and DMA
4G word address range for off-chip memory
Memory interface supports programmable wait state generation and page-mode for off-chip memory
DMA controller supports
14 zero-overhead DMA channels for transfers between
ADSP-21160x internal memory and external memory,
external peripherals, host processor, serial ports, or link
ports
64-bit background DMA transfers at core clock speed, in
parallel with full-speed processor execution
Host processor interface to 16- and 32-bit microprocessors
Multiprocessing support provides
Glueless connection for scalable DSP multiprocessing
architecture
Distributed on-chip bus arbitration for parallel bus connect of up to 6 ADSP-21160x processors plus host
6 link ports for point-to-point connectivity and array
multiprocessing
Serial ports provide
Two synchronous serial ports with companding hardware
Independent transmit and receive functions
TDM support for T1 and E1 interfaces
64-bit-wide synchronous external port provides
Glueless connection to asynchronous and SBSRAM external memories
Rev. D |
Page 2 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
TABLE OF CONTENTS
General Description ................................................. 4
ESD Sensitivity ................................................... 19
ADSP-21160x Family Core Architecture .................... 4
Package Information ............................................ 19
Memory and I/O Interface Features ........................... 7
Timing Specifications ........................................... 20
Development Tools ............................................... 9
Output Drive Currents—ADSP-21160M ................... 47
Additional Information ......................................... 10
Output Drive Currents—ADSP-21160N ................... 47
Related Signal Chains ........................................... 10
Power Dissipation ............................................... 47
Pin Function Descriptions ........................................ 11
Test Conditions .................................................. 48
Specifications ......................................................... 15
Environmental Conditions .................................... 51
Operating Conditions—ADSP-21160M .................... 15
400-Ball PBGA Pin Configurations ............................. 52
Electrical Characteristics—ADSP-21160M ................. 16
Outline Dimensions ................................................ 57
Operating Conditions—ADSP-21160N ..................... 17
Surface-Mount Design ............................................. 57
Electrical Characteristics—ADSP-21160N ................. 18
Ordering Guide ..................................................... 58
Absolute Maximum Ratings ................................... 19
REVISION HISTORY
9/15—Rev. C to Rev. D
Removed model ADSP-21160NKB-100 (no longer available)
from Ordering Guide ............................................... 58
Rev. D |
Page 3 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
GENERAL DESCRIPTION
The ADSP-21160x SHARC® DSP family has two members:
ADSP-21160M and ADSP-21160N. The ADSP-21160M is fabricated in a 0.25 micron CMOS process. The ADSP-21160N is
fabricated in a 0.18 micron CMOS process. The ADSP-21160N
offers higher performance and lower power consumption than
the ADSP-21160M. Easing portability, the ADSP-21160x is
application source code compatible with first generation
ADSP-2106x SHARC DSPs in SISD (single instruction, single
data) mode. To take advantage of the processor’s SIMD (singleinstruction, multiple-data) capability, some code changes are
needed. Like other SHARC DSPs, the ADSP-21160x is a 32-bit
processor that is optimized for high performance DSP applications. The ADSP-21160x includes a core running up to
100 MHz, a dual-ported on-chip SRAM, an integrated I/O processor with multiprocessing support, and multiple internal
buses to eliminate I/O bottlenecks.
Table 2. ADSP-21160x Benchmarks
Table 1 shows major differences between the ADSP-21160M
and ADSP-21160N processors.
The functional block diagram (Figure 1 on Page 1) of the
ADSP-21160x illustrates the following architectural features:
Table 1. ADSP-21160x SHARC Processor Family Features
Feature
SRAM
Operating Voltage
Instruction Rate
Link Port Transfer Rate (6)
Serial Port Transfer Rate (2)
ADSP-21160M
4 Mbits
3.3 V I/O
2.5 V Core
80 MHz
80 MBytes/s
40 Mbits/s
ADSP-21160N
4 Mbits
3.3 V I/O
1.9 V Core
100 MHz
100 MBytes/s
50 Mbits/s
The ADSP-21160x introduces single-instruction, multiple-data
(SIMD) processing. Using two computational units
(ADSP-2106x SHARC DSPs have one), the ADSP-21160x can
double performance versus the ADSP-2106x on a range of DSP
algorithms.
Fabricated in a state-of-the-art, high speed, low power CMOS
process, the ADSP-21160N has a 10 ns instruction cycle time.
With its SIMD computational hardware running at 100 MHz,
the ADSP-21160N can perform 600 million math operations
per second (480 million operations for ADSP-21160M at a
12.5 ns instruction cycle time).
Table 2 shows performance benchmarks for the ADSP-21160x.
These benchmarks provide single-channel extrapolations of
measured dual-channel (SIMD) processing performance. For
more information on benchmarking and optimizing DSP code
for single- and dual-channel processing, see the Analog Devices
website (www.analog.com).
The ADSP-21160x continues the SHARC family’s industryleading standards of integration for DSPs, combining a high
performance 32-bit DSP core with integrated, on-chip system
features. These features include a 4M-bit dual-ported SRAM
memory, host processor interface, I/O processor that supports
14 DMA channels, two serial ports, six link ports, external parallel bus, and glueless multiprocessing.
Rev. D |
Page 4 of 58 |
Benchmark Algorithm
1024 Point Complex FFT
(Radix 4, with reversal)
FIR Filter (per tap)
IIR Filter (per biquad)
Matrix Multiply (pipelined)
[33] [31]
[44] [41]
Divide (y/x)
Inverse Square Root
DMA Transfer Rate
ADSP-21160M ADSP-21160N
80 MHz
100 MHz
115 μs
92 μs
6.25 ns
25 ns
5 ns
20 ns
56.25 ns
100 ns
37.5 ns
56.25 ns
560M bytes/s
45 ns
80 ns
30 ns
45 ns
800M bytes/s
• Two processing elements, each made up of an ALU, multiplier, shifter, and data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core every core processor cycle
• Interval timer
• On-chip SRAM (4M bits)
• External port that supports:
• Interfacing to off-chip memory peripherals
• Glueless multiprocessing support for six
ADSP-21160x SHARC DSPs
• Host port
• DMA controller
• Serial ports and link ports
• JTAG test access port
Figure 2 shows a typical single-processor system. A multiprocessing system appears in Figure 3 on Page 6.
ADSP-21160X FAMILY CORE ARCHITECTURE
The ADSP-21160x processor includes the following architectural features of the ADSP-2116x family core. The
ADSP-21160x is code compatible at the assembly level with the
ADSP-2106x and ADSP-21161.
SIMD Computational Engine
The ADSP-21160x contains two computational processing elements that operate as a single-instruction multiple-data (SIMD)
engine. The processing elements are referred to as PEX and
PEY, and each contains an ALU, multiplier, shifter, and register
file. PEX is always active, and PEY may be enabled by setting the
PEYEN mode bit in the MODE1 register. When this mode is
September 2015
ADSP-21160M/ADSP-21160N
Data Register File
ADSP-21160X
CLKIN
4
LINK
DEVICES
(6 MAX)
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
LBOOT
IRQ2–0
ADDR
CIF
DATA
ADDR31–0
FLAG3–0
TIMEXP DATA63–0
RDx
LXCLK
WRx
LXACK
ACK
LXDAT7–0
MS3–0
TCLK0
RCLK0
TFS0
RSF0
DT0
DR0
TCLK1
RCLK1
TFS1
RSF1
DT1
DR1
PAGE
SBTS
ADDR
DATA MEMORY/
MAPPED
OE
DEVICES
WE (OPTIONAL)
ACK
CS
CLKOUT
DMAR1–2
DMA DEVICE
(OPTIONAL)
DATA
DMAG1–2
CS
HBR
HBG
REDY
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
RPBA
BR1–6
ADDR
ID2–0
PA
DATA
RESET
BOOT
EPROM
(OPTIONAL)
BRST
DATA
3
CLK_CFG3–0
EBOOT
ADDRESS
4
CS
BMS
CONTROL
CLOCK
JTAG
6
A general-purpose data register file is contained in each processing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2116x enhanced
Harvard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0–R15 and in PEY as S0–S15.
Single-Cycle Fetch of Instruction and Four Operands
The processor features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data, and the program memory (PM) bus transfers both instructions and data
(see the functional block diagram 1). With the ADSP-21160x
DSP’s separate program and data memory buses and on-chip
instruction cache, the processor can simultaneously fetch four
operands and an instruction (from the cache), all in a single
cycle.
Instruction Cache
The ADSP-21160x includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, providing looped
operations, such as digital filter multiply- accumulates and FFT
butterfly processing.
Data Address Generators with Hardware Circular Buffers
Figure 2. Single-Processor System
enabled, the same instruction is executed in both processing elements, but each processing element operates on different data.
This architecture is efficient at executing math-intensive DSP
algorithms.
Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. In SIMD
mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this
requirement, entering SIMD mode also doubles the bandwidth
between memory and the processing elements. When using the
DAGs to transfer data in SIMD mode, two data values are transferred with each access of memory or the register file.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform single-cycle
instructions. The three units within each processing element are
arranged in parallel, maximizing computational throughput.
Single multifunction instructions execute parallel ALU and
multiplier operations. In SIMD mode, the parallel ALU and
multiplier operations occur in both processing elements. These
computation units support IEEE 32-bit single-precision floating-point, 40-bit extended-precision floating-point, and 32-bit
fixed-point data formats.
Rev. D |
Page 5 of 58 |
The ADSP-21160x DSP’s two data address generators (DAGs)
are used for indirect addressing and provide for implementing
circular data buffers in hardware. Circular buffers allow efficient
programming of delay lines and other data structures required
in digital signal processing, and are commonly used in digital
filters and Fourier transforms. The two DAGs of the product
contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs
automatically handle address pointer wraparound, reducing
overhead, increasing performance, and simplifying implementation. Circular buffers can start and end at any memory
location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations for concise programming. For example, the processor can conditionally execute a multiply, an add, and subtract,
in both processing elements, while branching, all in a single
instruction.
September 2015
ADDRESS
DATA
DATA
RESET
ADDRESS
ADSP-21160X #3
CLKIN
CONTROL
ADSP-21160X #6
ADSP-21160X #5
ADSP-21160X #4
CONTROL
ADSP-21160M/ADSP-21160N
ADDR31–0
DATA63–0
RPBA
3
ID2–0
CONTROL
011
PA
BR1–2, BR4–6
5
BR3
ADSP-21160X #2
CLKIN
ADDR31–0
RESET
DATA63–0
RPBA
3
ID2–0
CONTROL
010
PA
BR1, BR3–6
5
BR2
ADSP-21160X #1
CLKIN
RESET
ADDR31–0
ADDR
DATA63–0
DATA
3
ID2–0
001
BUS
PRIORITY
RESET
CLOCK
CONTROL
RPBA
RDx
OE
WRx
ACK
MS3–0
WE
BMS
PAGE
SBTS
CS
GLOBAL MEMORY
AND
PERIPHERALS
(OPTIONAL)
ACK
CS
ADDR
BOOT EPROM (OPTIONAL)
DATA
CS
HBR
HBG
REDY
PA
BR2–6
BR1
HOST PROCESSOR
INTERFACE (OPTIONAL)
ADDR
5
DATA
Figure 3. Shared Memory Multiprocessing System
Rev. D |
Page 6 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
MEMORY AND I/O INTERFACE FEATURES
Augmenting the ADSP-2116x family core, the ADSP-21160x
adds the following architectural features.
Internal
Memory
Space
Dual-Ported On-Chip Memory
IOP Reg’s
Long Word
Normal Word
Short Word
The ADSP-21160x contains four megabits of on-chip SRAM,
organized as two blocks of 2M bits each, which can be configured for different combinations of code and data storage
(Figure 4). Each memory block is dual-ported for single-cycle,
independent accesses by the core processor and I/O processor.
The dual-ported memory in combination with three separate
on-chip buses allows two data transfers from the core and one
from I/O processor, in a single cycle. The ADSP-21160x memory can be configured as a maximum of 128K words of
32-bit data, 256K words of 16-bit data, 85K words of 48-bit
instructions (or 40-bit data), or combinations of different word
sizes up to four megabits. All of the memory can be accessed as
16-, 32-, 48-, or 64-bit words. A 16-bit floating-point storage
format is supported that effectively doubles the amount of data
that may be stored on-chip. Conversion between the 32-bit
floating-point and 16-bit floating-point formats is done in a single instruction. While each memory block can store
combinations of code and data, accesses are most efficient when
one block stores data, using the DM bus for transfers, and the
other block stores instructions and data, using the PM bus for
transfers. Using the DM bus and PM bus in this way, with one
dedicated to each memory block, assures single-cycle execution
with two data transfers. In this case, the instruction must be
available in the cache.
Internal
Rev. D |
Page 7 of 58 |
Bank 0
MS0
Bank 1
MS1
Bank 2
MS2
Bank 3
MS3
0x08 0000
0x10 0000
Space
(ID = 001)
Internal
0x20 0000
Memory
Space
(ID = 010)
Internal
0x30 0000
Memory
Space
(ID = 011)
0x40 0000
Multiprocessor
Memory
Space
Internal
Memory
External
Memory
Space
Space
(ID = 100)
Internal
0x50 0000
Memory
Space
(ID = 101)
Internal
0x60 0000
Nonbanked
Memory
Space
(ID = 110)
Broadcast
The external port supports asynchronous, synchronous, and
synchronous burst accesses. ZBT synchronous burst SRAM can
be interfaced gluelessly. Addressing of external memory devices
is facilitated by on-chip decoding of high-order address lines to
generate memory bank select signals. Separate control lines are
also generated for simplified addressing of page-mode DRAM.
The ADSP-21160x provides programmable memory wait states
and external memory acknowledge controls to allow interfacing
to DRAM and peripherals with variable access, hold, and disable
time requirements.
0x80 0000
Memory
Off-Chip Memory and Peripherals Interface
The ADSP-21160x DSP’s external port provides the processor’s
interface to off-chip memory and peripherals. The 4G word offchip address space is included in the processor’s unified address
space. The separate on-chip buses—for PM addresses, PM data,
DM addresses, DM data, I/O addresses, and I/O data—are multiplexed at the external port to create an external system bus
with a single 32-bit address bus and a single 64-bit data bus. The
lower 32 bits of the external data bus connect to even addresses,
and the upper 32 bits of the 64 connect to odd addresses. Every
access to external memory is based on an address that fetches a
32-bit word, and with the 64-bit bus, two address locations can
be accessed at once. When fetching an instruction from external
memory, two 32-bit data locations are being accessed (16 bits
are unused). Figure 5 shows the alignment of various accesses to
external memory.
0x00 0000
0x02 0000
0x04 0000
0x70 0000
Write to
All DSPs
(ID = 111)
0x7F FFFF
0xFFFF FFFF
Figure 4. Memory Map
DMA Controller
The ADSP-21160x DSP’s on-chip DMA controller allows zerooverhead data transfers without processor intervention. The
DMA controller operates independently and invisibly to the
processor core, allowing DMA operations to occur while the
core is simultaneously executing its program instructions. DMA
transfers can occur between the processor’s internal memory
and external memory, external peripherals, or a host processor.
DMA transfers can also occur between the product’s DSP’s
internal memory and its serial ports or link ports. External bus
packing to 16-, 32-, 48-, or 64-bit words is performed during
DMA transfers. Fourteen channels of DMA are available on the
ADSP-21160x—six via the link ports, four via the serial ports,
and four via the processor’s external port (for either host processor, other ADSP-21160x processors, memory or I/O
transfers). Programs can be downloaded to the processor using
DMA transfers. Asynchronous off-chip peripherals can control
two DMA channels using DMA Request/Grant lines
(DMAR1–2, DMAG1–2). Other DMA features include
September 2015
ADSP-21160M/ADSP-21160N
(ADSP-21160N). Link port I/O is especially useful for point-topoint interprocessor communication in multiprocessing systems. The link ports can operate independently and
simultaneously. Link port data is packed into 48- or 32-bit
words, and can be directly read by the core processor or DMAtransferred to on-chip memory. Each link port has its own double-buffered input and output registers. Clock/acknowledge
handshaking controls link port transfers. Transfers are programmable as transmit or receive.
DATA63–0
63
55
47
39
31
23
15
7
BYTE 7
0
BYTE 0
RDL/WRL
RDH/WRH
64-BIT LONG WORD, SIMD, DMA, IOP REGISTER TRANSFERS
64-BIT TRANSFER FOR 48-BIT INSTRUCTION FETCH
Serial Ports
64-BIT TRANS. FOR 40-BIT EXT. PRECISION
32-BIT NORMAL WD. (EVEN ADDR.)
32-BIT NORMAL WORD (ODD ADDR)
RESTRICTED DMA, HOST, EPROM DATA ALIGNMENTS:
32-BIT PACKED
16-BIT PACKED
EPROM
Figure 5. External Data Alignment Options
interrupt generation upon completion of DMA transfers, twodimensional DMA, and DMA chaining for automatic linked
DMA transfers.
Multiprocessing
The ADSP-21160x offers powerful features tailored to multiprocessing DSP systems as shown in M. The external port and link
ports provide integrated glueless multiprocessing support.
The external port supports a unified address space (see Figure 4)
that allows direct interprocessor accesses of each processor’s
internal memory. Distributed bus arbitration logic is included
on-chip for simple, glueless connection of systems containing
up to six ADSP-21160x processors and a host processor. Master
processor changeover incurs only one cycle of overhead. Bus
arbitration is selectable as either fixed or rotating priority. Bus
lock allows indivisible read-modify-write sequences for semaphores. A vector interrupt is provided for interprocessor
commands. Maximum throughput for interprocessor data
transfer is 400M bytes/s (ADSP-21160N) over the external port.
Broadcast writes allow simultaneous transmission of data to all
ADSP-21160x DSPs and can be used to implement reflective
semaphores.
Six link ports provide for a second method of multiprocessing
communications. Each link port can support communications
to another ADSP-21160x. Using the links, a large multiprocessor system can be constructed in a 2D or 3D fashion. Systems
can use the link ports and cluster multiprocessing concurrently
or independently.
Link Ports
The processor features six 8-bit link ports that provide additional I/O capabilities. With the capability of running at
100 MHz rates, each link port can support 100M bytes/s
Rev. D |
Page 8 of 58 |
The processor features two synchronous serial ports that provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices. The serial ports can operate up
to half the clock rate of the core, providing each with a maximum data rate of 50M bits/s (ADSP-21160N). Independent
transmit and receive functions provide greater flexibility for
serial communications. Serial port data can be automatically
transferred to and from on-chip memory via a dedicated DMA.
Each of the serial ports offers a TDM multichannel mode. The
serial ports can operate with little-endian or big-endian transmission formats, with word lengths selectable from 3 bits to 32
bits. They offer selectable synchronization and transmit modes
as well as optional μ-law or A-law companding. Serial port
clocks and frame syncs can be generated internally or externally.
Host Processor Interface
The ADSP-21160x host interface allows easy connection to
standard microprocessor buses, both 16- and 32-bit, with little
additional hardware required. The host interface is accessed
through the ADSP-21160x DSP’s external port and is memorymapped into the unified address space. Four channels of DMA
are available for the host interface; code and data transfers are
accomplished with low software overhead. The host processor
communicates with the ADSP-21160x DSP’s external bus with
host bus request (HBR), host bus grant (HBG), ready (REDY),
acknowledge (ACK), and chip select (CS) signals. The host can
directly read and write the internal memory of the processor,
and can access the DMA channel setup and mailbox registers.
Vector interrupt support provides efficient execution of host
commands.
The host processor interface can be used in either multiprocessor or uniprocessor systems. For multiprocessor systems, host
access to the SHARC requires that address pins ADDR17,
ADDR18, ADDR19, and ADDR20 be driven low. It is not
enough to tie these pins to ground through a resistor (for example, 10 k). These pins must be driven low with a strong enough
drive strength (10 to 50 ) to overcome the SHARC keeper
latches present on these pins. If the drive strength provided is
not strong enough, data access failures can occur.
For uniprocessor SHARC systems using this host access feature,
address pins ADDR17, ADDR18, ADDR19, and ADDR20 may
be tied low (for example, through a 10 k ohm resistor), driven
low by a buffer/driver, or left floating. Any of these options is
sufficient.
September 2015
ADSP-21160M/ADSP-21160N
Program Booting
The internal memory of the ADSP-21160x can be booted at system power-up from an 8-bit EPROM, a host processor, or
through one of the link ports. Selection of the boot source is
controlled by the BMS (Boot Memory Select), EBOOT (EPROM
Boot), and LBOOT (Link/Host Boot) pins. 32-bit and 16-bit
host processors can be used for booting.
Phase-Locked Loop
The processor uses an on-chip PLL to generate the internal
clock for the core. Ratios of 2:1, 3:1, and 4:1 between the core
and CLKIN are supported. The CLK_CFG pins are used to
select the ratio. The CLKIN rate is the rate at which the synchronous external port operates.
Power Supplies
The processor has separate power supply connections for the
internal (VDDINT), external (VDDEXT), and analog (AVDD and
AGND) power supplies. The internal and analog supplies must
meet the VDDINT and AVDD requirement. The external supply
must meet the 3.3 V requirement. All external supply pins must
be connected to the same supply.
The PLL filter, Figure 6, must be added for each ADSP-21160x
in the system. VDDINT is the digital core supply. It is recommended that the capacitors be connected directly to AGND
using short thick trace. It is recommended that the capacitors be
placed as close to AVDD and AGND as possible. The connection
from AGND to the (digital) ground plane should be made after
the capacitors. The use of a thick trace for AGND is reasonable
only because the PLL is a relatively low power circuit—it does
not apply to any other ADSP-21160x GND connection.
10 ⍀
AVDD
VDDINT
0.01F
0.1F
AGND
seamlessly integrates available software add-ins to support real
time operating systems, file systems, TCP/IP stacks, USB stacks,
algorithmic software modules, and evaluation hardware board
support packages. For more information visit
www.analog.com/cces.
The other Analog Devices IDE, VisualDSP++, supports processor families introduced prior to the release of CrossCore
Embedded Studio. This IDE includes the Analog Devices VDK
real time operating system and an open source TCP/IP stack.
For more information visit www.analog.com/visualdsp. Note
that VisualDSP++ will not support future Analog Devices
processors.
EZ-KIT Lite Evaluation Board
For processor evaluation, Analog Devices provides wide range
of EZ-KIT Lite® evaluation boards. Including the processor and
key peripherals, the evaluation board also supports on-chip
emulation capabilities and other evaluation and development
features. Also available are various EZ-Extenders®, which are
daughter cards delivering additional specialized functionality,
including audio and video processing. For more information
visit www.analog.com and search on “ezkit” or “ezextender”.
EZ-KIT Lite Evaluation Kits
For a cost-effective way to learn more about developing with
Analog Devices processors, Analog Devices offer a range of EZKIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT
Lite evaluation board, directions for downloading an evaluation
version of the available IDE(s), a USB cable, and a power supply.
The USB controller on the EZ-KIT Lite board connects to the
USB port of the user’s PC, enabling the chosen IDE evaluation
suite to emulate the on-board processor in-circuit. This permits
the customer to download, execute, and debug programs for the
EZ-KIT Lite system. It also supports in-circuit programming of
the on-board Flash device to store user-specific boot code,
enabling standalone operation. With the full version of CrossCore Embedded Studio or VisualDSP++ installed (sold
separately), engineers can develop software for supported EZKITs or any custom system utilizing supported Analog Devices
processors.
Software Add-Ins for CrossCore Embedded Studio
Figure 6. Analog Power (AVDD) Filter Circuit
DEVELOPMENT TOOLS
Analog Devices supports its processors with a complete line of
software and hardware development tools, including integrated
development environments (which include CrossCore® Embedded Studio and/or VisualDSP++®), evaluation products,
emulators, and a wide variety of software add-ins.
Integrated Development Environments (IDEs)
Board Support Packages for Evaluation Hardware
For C/C++ software writing and editing, code generation, and
debug support, Analog Devices offers two IDEs.
The newest IDE, CrossCore Embedded Studio, is based on the
EclipseTM framework. Supporting most Analog Devices processor families, it is the IDE of choice for future processors,
including multicore devices. CrossCore Embedded Studio
Rev. D |
Analog Devices offers software add-ins which seamlessly integrate with CrossCore Embedded Studio to extend its capabilities
and reduce development time. Add-ins include board support
packages for evaluation hardware, various middleware packages, and algorithmic modules. Documentation, help,
configuration dialogs, and coding examples present in these
add-ins are viewable through the CrossCore Embedded Studio
IDE once the add-in is installed.
Page 9 of 58 |
Software support for the EZ-KIT Lite evaluation boards and EZExtender daughter cards is provided by software add-ins called
Board Support Packages (BSPs). The BSPs contain the required
drivers, pertinent release notes, and select example code for the
given evaluation hardware. A download link for a specific BSP is
September 2015
ADSP-21160M/ADSP-21160N
located on the web page for the associated EZ-KIT or EZExtender product. The link is found in the Product Download
area of the product web page.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena.
Middleware Packages
Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together well. A tool for viewing relationships between
specific applications and related components is available on the
www.analog.com website.
Analog Devices separately offers middleware add-ins such as
real time operating systems, file systems, USB stacks, and
TCP/IP stacks. For more information, see the following web
pages:
• www.analog.com/ucos3
• www.analog.com/ucfs
The application signal chains page in the Circuits from the Lab®
site (http:\\www.analog.com\circuits) provides:
• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
• www.analog.com/ucusbd
• Drill down links for components in each chain to selection
guides and application information
• www.analog.com/lwip
Algorithmic Modules
To speed development, Analog Devices offers add-ins that perform popular audio and video processing algorithms. These are
available for use with both CrossCore Embedded Studio and
VisualDSP++. For more information visit www.analog.com and
search on “Blackfin software modules” or “SHARC software
modules”.
• Reference designs applying best practice design techniques
Designing an Emulator-Compatible DSP Board (Target)
For embedded system test and debug, Analog Devices provides
a family of emulators. On each JTAG DSP, Analog Devices supplies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit
emulation is facilitated by use of this JTAG interface. The emulator accesses the processor’s internal features via the
processor’s TAP, allowing the developer to load code, set breakpoints, and view variables, memory, and registers. The
processor must be halted to send data and commands, but once
an operation is completed by the emulator, the DSP system is set
to run at full speed with no impact on system timing. The emulators require the target board to include a header that supports
connection of the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal termination, and emulator pod logic, see the application note
(EE-68) “Analog Devices JTAG Emulation Technical Reference” (www.analog.com/ee-68). This document is updated
regularly to keep pace with improvements to emulator support.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the
ADSP-21160x architecture and functionality. For detailed information on the Blackfin family core architecture and instruction
set, refer to the ADSP-21160 SHARC DSP Hardware Reference
and the ADSP-21160 SHARC DSP Instruction Set Reference. For
detailed information on the development tools for this processor, see the VisualDSP++ User’s Guide.
RELATED SIGNAL CHAINS
A signal chain is a series of signal conditioning electronic components that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Rev. D |
Page 10 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
PIN FUNCTION DESCRIPTIONS
ADSP-21160x pin definitions are listed below. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to
CLKIN (or to TCK for TRST).
Tie or pull unused inputs to VDD or GND, except for the
following:
• ADDR31–0, DATA63–0, PAGE, BRST, CLKOUT (ID2–0
= 00x) (Note: These pins have a logic-level hold circuit
enabled on the ADSP-21160x DSP with ID2–0 = 00x.)
• LxCLK, LxACK, LxDAT7–0 (LxPDRDE = 0) (Note: See
Link Port Buffer Control Register Bit definitions in the
ADSP-21160 SHARC DSP Hardware Reference.)
• DTx, DRx, TCLKx, RCLKx, EMU, TMS, TRST, TDI
(Note: These pins have a pull-up.)
The following symbols appear in the Type column of Table 3:
A = Asynchronous, G = Ground, I = Input, O = Output,
P = Power Supply, S = Synchronous, (A/D) = Active Drive,
(O/D) = Open Drain, and T = Three-State (when SBTS is
asserted, or when the ADSP-21160x is a bus slave).
• PA, ACK, MS3–0, RDx, WRx, CIF, DMARx, DMAGx
(ID2–0 = 00x) (Note: These pins have a pull-up enabled on
the ADSP-21160x with ID2–0 = 00x.)
Table 3. Pin Function Descriptions
Pin
ADDR31–0
Type
I/O/T
DATA63–0
I/O/T
MS3–0
O/T
RDL
I/O/T
RDH
I/O/T
WRL
I/O/T
WRH
I/O/T
Function
External Bus Address. The ADSP-21160x outputs addresses for external memory and peripherals
on these pins. In a multiprocessor system, the bus master outputs addresses for read/writes of the
internal memory or IOP registers of other ADSP-21160x DSPs. The ADSP-21160x inputs addresses
when a host processor or multiprocessing bus master is reading or writing its internal memory or
IOP registers. A keeper latch on the DSP’s ADDR31–0 pins maintains the input at the level it was
last driven (only enabled on the processor with ID2–0 = 00x).
External Bus Data. The ADSP-21160x inputs and outputs data and instructions on these pins. Pullup resistors on unused DATA pins are not necessary. A keeper latch on the DSP’s DATA63-0 pins
maintains the input at the level it was last driven (only enabled on the processor with ID2–0 = 00x).
Memory Select Lines. These outputs are asserted (low) as chip selects for the corresponding banks
of external memory. Memory bank size must be defined in the SYSCON control register. The MS3–0
outputs are decoded memory address lines. In asynchronous access mode, the MS3–0 outputs
transition with the other address outputs. In synchronous access modes, the MS3–0 outputs assert
with the other address lines; however, they deassert after the first CLKIN cycle in which ACK is
sampled asserted. MS3–0 has a 20 k internal pull-up resistor that is enabled on the ADSP-21160x
with ID2–0 = 00x.
Memory Read Low Strobe. RDL is asserted whenever ADSP-21160x reads from the low word of
external memory or from the internal memory of other ADSP-21160x DSPs. External devices,
including other ADSP-21160x DSPs, must assert RDL for reading from the low word of processor
internal memory. In a multiprocessing system, RDL is driven by the bus master. RDL has a 20 k
internal pull-up resistor that is enabled on the processor with ID2–0 = 00x.
Memory Read High Strobe. RDH is asserted whenever ADSP-21160x reads from the high word of
external memory or from the internal memory of other ADSP-21160x DSPs. External devices,
including other ADSP-21160x DSPs, must assert RDH for reading from the high word of
ADSP-21160x internal memory. In a multiprocessing system, RDH is driven by the bus master.
RDH has a 20 k internal pull-up resistor that is enabled on the processor with ID2–0 = 00x.
Memory Write Low Strobe. WRL is asserted when ADSP-21160x writes to the low word of external
memory or internal memory of other ADSP-21160x DSPs. External devices must assert WRL for
writing to ADSP-21160x DSP’s low word of internal memory. In a multiprocessing system, WRL is
driven by the bus master. WRL has a 20 k internal pull-up resistor that is enabled on the processor
with ID2–0 = 00x.
Memory Write High Strobe. WRH is asserted when ADSP-21160x writes to the high word of external
memory or internal memory of other ADSP-21160x DSPs. External devices must assert WRH for
writing to ADSP-21160x DSP’s high word of internal memory. In a multiprocessing system, WRH is
driven by the bus master. WRH has a 20 k internal pull-up resistor that is enabled on the processor
with ID2–0 = 00x.
Rev. D |
Page 11 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
Table 3. Pin Function Descriptions (Continued)
Pin
PAGE
Type
O/T
BRST
I/O/T
ACK
I/O/S
SBTS
I/S
IRQ2–0
I/A
FLAG3–0
I/O/A
TIMEXP
O
HBR
I/A
HBG
I/O
CS
I/A
REDY
O (O/D)
DMAR1
I/A
DMAR2
I/A
Function
DRAM Page Boundary. The processor asserts this pin to an external DRAM controller, to signal that
an external DRAM page boundary has been crossed. DRAM page size must be defined in the
processor’s memory control register (WAIT). DRAM can only be implemented in external memory
Bank 0; the PAGE signal can only be activated for Bank 0 accesses. In a multiprocessing system, PAGE
is output by the bus master. A keeper latch on the DSP’s PAGE pin maintains the output at the level
it was last driven (only enabled on the processor with ID2–0 = 00x).
Sequential Burst Access. BRST is asserted by ADSP-21160x or a host to indicate that data associated
with consecutive addresses is being read or written. A slave device samples the initial address and
increments an internal address counter after each transfer. The incremented address is not
pipelined on the bus. If the burst access is a read from the host to the processor, the
processor automatically increments the address as long as BRST is asserted. BRST is asserted after
the initial access of a burst transfer. It is asserted for every cycle after that, except for the last data
request cycle (denoted by RDx or WRx asserted and BRST negated). A keeper latch on the DSP’s
BRST pin maintains the input at the level it was last driven (only enabled on the processor with
ID2–0 = 00x).
Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external
memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off
completion of an external memory access. The ADSP-21160x deasserts ACK as an output to add
wait states to a synchronous access of its internal memory, by a synchronous host or another DSP
in a multiprocessor configuration. ACK has a 2 k internal pull-up resistor that is enabled on the
processor with ID2–0 = 00x.
Suspend Bus and Three-State. External devices can assert SBTS (low) to place the external bus
address, data, selects, and strobes in a high-impedance state for the following cycle. If the
ADSP-21160x attempts to access external memory while SBTS is asserted, the processor will halt
and the memory access will not be completed until SBTS is deasserted. SBTS should only be used
to recover from host processor and/or ADSP-21160x deadlock or used with a DRAM controller.
Interrupt Request Lines. These are sampled on the rising edge of CLKIN and may be either edgetriggered or level-sensitive.
Flag Pins. Each is configured via control bits as either an input or output. As an input, it can be tested
as a condition. As an output, it can be used to signal external peripherals.
Timer Expired. Asserted for four processor core clock (CCLK) cycles when the timer is enabled and
TCOUNT decrements to zero.
Host Bus Request. Must be asserted by a host processor to request control of the
ADSP-21160x DSP’s external bus. When HBR is asserted in a multiprocessing system, the processor
that is bus master will relinquish the bus and assert HBG. To relinquish the bus, the processor places
the address, data, select, and strobe lines in a high-impedance state. HBR has priority over all
processor bus requests (BR6–1) in a multiprocessing system.
Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may take
control of the external bus. HBG is asserted (held low) by the ADSP-21160x until HBR is released. In
a multiprocessing system, HBG is output by the processor bus master and is monitored by all others.
After HBR is asserted, and before HBG is given, HBG will float for 1 tCLK
(1 CLKIN cycle). To avoid erroneous grants, HBG should be pulled up with a 20 k to 50 k external
resistor.
Chip Select. Asserted by host processor to select the ADSP-21160x, for asynchronous transfer
protocol.
Host Bus Acknowledge. The ADSP-21160x deasserts REDY (low) to add wait states to an
asynchronous host access when CS and HBR inputs are asserted.
DMA Request 1 (DMA Channel 11). Asserted by external port devices to request DMA services.
DMAR1 has a 20 k internal pull-up resistor that is enabled on the ADSP-21160x with ID2–0 = 00x.
DMA Request 2 (DMA Channel 12). Asserted by external port devices to request DMA services.
DMAR2 has a 20 k internal pull-up resistor that is enabled on the ADSP-21160x with ID2–0 = 00x.
Rev. D |
Page 12 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
Table 3. Pin Function Descriptions (Continued)
Pin
ID2–0
Type
I
DMAG1
O/T
DMAG2
O/T
BR6–1
I/O/S
RPBA
I/S
PA
I/O/T
DTx
DRx
TCLKx
RCLKx
TFSx
RFSx
LxDAT7–0
O
I
I/O
I/O
I/O
I/O
I/O
LxCLK
I/O
LxACK
I/O
EBOOT
I
LBOOT
I
BMS
I/O/T
CLKIN
I
CLK_CFG3–0
I
Function
Multiprocessing ID. Determines which multiprocessing bus request (BR1–BR6) is used by the
ADSP-21160x. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, and so on. Use ID = 000
or ID = 001 in single-processor systems. These lines are a system configuration selection which
should be hardwired or only changed at reset.
DMA Grant 1 (DMA Channel 11). Asserted by ADSP-21160x to indicate that the requested DMA
starts on the next cycle. Driven by bus master only. DMAG1 has a 20 k internal pull-up resistor
that is enabled on the ADSP-21160x with ID2–0 = 00x.
DMA Grant 2 (DMA Channel 12). Asserted by ADSP-21160x to indicate that the requested DMA
starts on the next cycle. Driven by bus master only. DMAG2 has a 20 k internal pull-up resistor
that is enabled on the ADSP-21160x with ID2–0 = 00x.
Multiprocessing Bus Requests. Used by multiprocessing ADSP-21160x DSPs to arbitrate for bus
mastership. An ADSP-21160x only drives its own BRx line (corresponding to the value of its ID2–0
inputs) and monitors all others. In a multiprocessor system with less than six ADSP-21160x DSPs,
the unused BRx pins should be pulled high; the processor’s own BRx line must not be pulled high
or low because it is an output.
Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus
arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration selection which must be set to the same value on every ADSP-21160x. If the value of RPBA
is changed during system operation, it must be changed in the same CLKIN cycle on every
processor.
Priority Access. Asserting its PA pin allows an ADSP-21160x bus slave to interrupt background DMA
transfers and gain access to the external bus. PA is connected to all ADSP-21160x DSPs in the system.
If access priority is not required in a system, the PA pin should be left unconnected. PA has a 20 k
internal pull-up resistor that is enabled on the ADSP-21160x with ID2–0 = 00x.
Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 k internal pull-up resistor.
Data Receive (Serial Ports 0, 1). Each DR pin has a 50 k internal pull-up resistor.
Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 k internal pull-up resistor.
Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 k internal pull-up resistor.
Transmit Frame Sync (Serial Ports 0, 1).
Receive Frame Sync (Serial Ports 0, 1).
Link Port Data (Link Ports 0–5). Each LxDAT pin has a 50 k internal pull-down resistor that is
enabled or disabled by the LPDRD bit of the LCTL0–1 register.
Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50 k internal pull-down resistor that is
enabled or disabled by the LPDRD bit of the LCTL0–1 register.
Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50 k internal pull-down resistor
that is enabled or disabled by the LPDRD bit of the LCOM register.
EPROM Boot Select. For a description of how this pin operates, see Table 4. This signal is a system
configuration selection that should be hardwired.
Link Boot. For a description of how this pin operates, see Table 4. This signal is a system configuration selection that should be hardwired.
Boot Memory Select. Serves as an output or input as selected with the EBOOT and LBOOT pins; see
Table 4. This input is a system configuration selection that should be hardwired.
Local Clock In. CLKIN is the ADSP-21160x clock input. The ADSP-21160x external port cycles at the
frequency of CLKIN. The instruction cycle rate is a multiple of the CLKIN frequency; it is programmable at power-up. CLKIN may not be halted, changed, or operated below the specified frequency.
Core/CLKIN Ratio Control. ADSP-21160x core clock (instruction cycle) rate is equal to n x CLKIN
where n is user-selectable to 2, 3, or 4, using the CLK_CFG3–0 inputs. For clock configuration definitions, see the RESET & CLKIN section of the System Design chapter of the ADSP-21160 SHARC DSP
Hardware Reference.
Rev. D |
Page 13 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
Table 3. Pin Function Descriptions (Continued)
Pin
CLKOUT
Type
O/T
RESET
I/A
TCK
TMS
I
I/S
TDI
I/S
TDO
TRST
O
I/A
EMU
O (O/D)
CIF
O/T
VDDINT
P
VDDEXT
AVDD
P
P
AGND
GND
NC
G
G
Function
Local Clock Out. CLKOUT is driven at the CLKIN frequency by the processor. This output can be
three-stated by setting the COD bit in the SYSCON register. A keeper latch on the DSP’s CLKOUT
pin maintains the output at the level it was last driven (only enabled on the processor with
ID2-0 = 00x). Do not use CLKOUT in multiprocessing systems; use CLKIN instead.
Processor Reset. Resets the ADSP-21160x to a known state and begins execution at the program
memory location specified by the hardware reset vector address. The RESET input must be asserted
(low) at power-up.
Test Clock (JTAG). Provides a clock for JTAG boundary scan.
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 k internal pull-up
resistor.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 k internal
pull-up resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after powerup or held low for proper operation of the ADSP-21160x. TRST has a 20 k internal pull-up resistor.
Emulation Status. Must be connected to the ADSP-21160x emulator target board connector only.
EMU has a 50 k internal pull-up resistor.
Core Instruction Fetch. Signal is active low when an external instruction fetch is performed. Driven
by bus master only. Three-state when host is bus master. CIF has a 20 k internal pull-up resistor
that is enabled on the ADSP-21160x with ID2–0 = 00x.
Core Power Supply. Nominally 2.5 V (ADSP-21160M) or 1.9 V (ADSP-21160N) dc and supplies the
DSP’s core processor
I/O Power Supply. Nominally 3.3 V dc.
Analog Power Supply. Nominally 2.5 V (ADSP-21160M) or 1.9 V (ADSP-21160N) dc and supplies the
DSP’s internal PLL (clock generator). This pin has the same specifications as VDDINT, except that added
filtering circuitry is required. For more information, see Power Supplies on page 9.
Analog Power Supply Return.
Power Supply Return.
Do Not Connect. Reserved pins that must be left open and unconnected.
Table 4. Boot Mode Selection
EBOOT
1
0
0
0
0
1
LBOOT
0
0
1
0
1
1
BMS
Output
1 (Input)
1 (Input)
0 (Input)
0 (Input)
x (Input)
Booting Mode
EPROM (Connect BMS to EPROM chip select.)
Host Processor
Link Port
No Booting. Processor executes from external memory.
Reserved
Reserved
Rev. D |
Page 14 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
SPECIFICATIONS
OPERATING CONDITIONS—ADSP-21160M
Table 5 shows the recommended operating conditions for the
ADSP-21160M. Specifications are subject to change without
notice.
Table 5. Operating Conditions—ADSP-21160M
Parameter
VDDINT
AVDD
VDDEXT
TCASE
VIH1
VIH2
VIL
Internal (Core) Supply Voltage
Analog (PLL) Supply Voltage
External (I/O) Supply Voltage
Case Operating Temperature1
High Level Input Voltage,2 @ VDDEXT =Max
High Level Input Voltage,3 @ VDDEXT =Max
Low Level Input Voltage,2, 3 @ VDDEXT =Min
Min
2.37
2.37
3.13
0
2.2
2.3
–0.5
1
K Grade
Max
2.63
2.63
3.47
85
VDDEXT +0.5
VDDEXT +0.5
+0.8
Unit
V
V
V
ºC
V
V
V
See Environmental Conditions on Page 51 for information on thermal specifications.
Applies to input and bidirectional pins: DATA63–0, ADDR31–0, RDx, WRx, ACK, SBTS, IRQ2–0, FLAG3–0, HBG, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, PA, BRST,
TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, and RCLK1.
3
Applies to input pins: CLKIN, RESET, and TRST.
2
Rev. D |
Page 15 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
ELECTRICAL CHARACTERISTICS—ADSP-21160M
Table 6 shows ADSP-21160M electrical characteristics. These
specifications are subject to change without notification.
Table 6. Electrical Characteristics—ADSP-21160M
Parameter
VOH
VOL
IIH
IIL
IILPU1
IILPU2
IOZH
IOZL
IOZHPD
IOZLPU1
IOZLPU2
IOZHA
IOZLA
IDD-INPEAK
IDD-INHIGH
IDD-INLOW
IDD-IDLE
AIDD
CIN
High Level Output Voltage1
Low Level Output Voltage1
High Level Input Current3, 4, 5
Low Level Input Current3
Low Level Input Current Pull-Up14
Low Level Input Current Pull-Up25
Three-State Leakage Current6, 7, 8, 9
Three-State Leakage Current6
Three-State Leakage Current Pull-Down9
Three-State Leakage Current Pull-Up17
Three-State Leakage Current Pull-Up28
Three-State Leakage Current10
Three-State Leakage Current10
Supply Current (Internal)11
Supply Current (Internal)12
Supply Current (Internal)13
Supply Current (Idle)14
Supply Current (Analog)15
Input Capacitance16, 17
Test Conditions
@ VDDEXT =Min, IOH =–2.0 mA2
@ VDDEXT =Min, IOL =4.0 mA2
@ VDDEXT =Max, VIN =VDD Max
@ VDDEXT =Max, VIN =0 V
@ VDDEXT =Max, VIN =0 V
@ VDDEXT =Max, VIN =0 V
@ VDDEXT =Max, VIN =VDD Max
@ VDDEXT =Max, VIN =0 V
@ VDDEXT =Max, VIN =VDD Max
@ VDDEXT =Max, VIN =0 V
@ VDDEXT =Max, VIN =0 V
@ VDDEXT =Max, VIN =VDD Max
@ VDDEXT =Max, VIN =0 V
tCCLK =12.5 ns, VDDINT =Max
tCCLK =12.5 ns, VDDINT =Max
tCCLK =12.5 ns, VDDINT =Max
tCCLK =12.5 ns, VDDINT =Max
@AVDD =Max
fIN =1 MHz, TCASE =25°C, VIN =2.5 V
1
Min
2.4
Max
0.4
10
10
250
500
10
10
250
250
500
25
4
1400
875
625
400
10
4.7
Unit
V
V
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
mA
mA
mA
mA
mA
mA
pF
Applies to output and bidirectional pins: DATA63–0, ADDR31–0, MS3–0, RDx, WRx, PAGE, CLKOUT, ACK, FLAG3–0, TIMEXP, HBG, REDY, DMAG1, DMAG2, BR6–1,
PA, BRST, CIF, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, BMS, TDO, and EMU.
2
See Output Drive Currents—ADSP-21160M on Page 47 for typical drive current capabilities.
3
Applies to input pins: SBTS, IRQ2–0, HBR, CS, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK, and CLK_CFG3-0.
4
Applies to input pins with internal pull-ups: DR0, and DR1.
5
Applies to input pins with internal pull-ups: DMARx, TMS, TDI, and TRST.
6
Applies to three-statable pins: DATA63–0, ADDR31–0, PAGE, CLKOUT, ACK, FLAG3–0, REDY, HBG, BMS, BR6–1, TFSx, RFSx, and TDO.
7
Applies to three-statable pins with internal pull-ups: DTx, TCLKx, RCLKx, and EMU.
8
Applies to three-statable pins with internal pull-ups: MS3–0,RDx, WRx, DMAGx, PA, and CIF.
9
Applies to three-statable pins with internal pull-downs: LxDAT7–0, LxCLK, and LxACK.
10
Applies to ACK pulled up internally with 2 k during reset or ID2–0 = 00x.
11
The test program used to measure IDD-INPEAK represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power
measurements made using typical applications are less than specified. For more information, see Power Dissipation on Page 47.
12
IDD-INHIGH is a composite average based on a range of high activity code. For more information, see Power Dissipation on Page 47.
13
IDD-INLOW is a composite average based on a range of low activity code. For more information, see Power Dissipation on Page 47.
14
Idle denotes ADSP-21160M state during execution of IDLE instruction. For more information, see Power Dissipation on Page 47.
15
Characterized, but not tested.
16
Applies to all signal pins.
17
Guaranteed, but not tested.
Rev. D |
Page 16 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
OPERATING CONDITIONS—ADSP-21160N
Table 7 shows recommended operating conditions for the
ADSP-21160N. These specifications are subject to change
without notice.
Table 7. Operating Conditions—ADSP-21160N
Parameter
VDDINT
AVDD
VDDEXT
TCASE
VIH1
VIH2
VIL
Internal (Core) Supply Voltage
Analog (PLL) Supply Voltage
External (I/O) Supply Voltage
Case Operating Temperature1
High Level Input Voltage,2 @ VDDEXT =Max
High Level Input Voltage,3 @ VDDEXT =Max
Low Level Input Voltage,2, 3 @ VDDEXT =Min
Min
1.8
1.8
3.13
– 40
2.0
2.0
–0.5
C Grade
Max
2.0
2.0
3.47
+100
VDDEXT +0.5
VDDEXT +0.5
+0.8
1
Min
1.8
1.8
3.13
0
2.0
2.0
–0.5
K Grade
Max
2.0
2.0
3.47
85
VDDEXT +0.5
VDDEXT +0.5
+0.8
Unit
V
V
V
ºC
V
V
V
See Environmental Conditions on Page 51 for information on thermal specifications.
Applies to input and bidirectional pins: DATA63–0, ADDR31–0, RDx, WRx, ACK, SBTS, IRQ2–0, FLAG3–0, HBG, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, PA, BRST,
TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, and RCLK1.
3
Applies to input pins: CLKIN, RESET, and TRST.
2
Rev. D |
Page 17 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
ELECTRICAL CHARACTERISTICS—ADSP-21160N
Table 8 shows the electrical characteristics. Note that these specifications are subject to change without notification.
Table 8. Electrical Characteristics—ADSP-21160N
Parameter
VOH
VOL
IIH
IIL
IIHC
IILC
IIKH
IIKL
IIKH-OD
IIKL-OD
IILPU1
IILPU2
IOZH
IOZL
IOZHPD
IOZLPU1
IOZLPU2
IOZHA
IOZLA
IDD-INPEAK
IDD-INHIGH
IDD-INLOW
IDD-IDLE
AIDD
CIN
High Level Output Voltage1
Low Level Output Voltage1
High Level Input Current3, 4, 5
Low Level Input Current3
CLKIN High Level Input Current6
CLKIN Low Level Input Current6
Keeper High Load Current7
Keeper Low Load Current7
Keeper High Overdrive Current7, 8, 9
Keeper Low Overdrive Current7, 8, 9
Low Level Input Current Pull-Up14
Low Level Input Current Pull-Up25
Three-State Leakage Current10, 11, 12, 13
Three-State Leakage Current10
Three-State Leakage Current Pull-Down13
Three-State Leakage Current Pull-Up111
Three-State Leakage Current Pull-Up212
Three-State Leakage Current14
Three-State Leakage Current14
Supply Current (Internal)15
Supply Current (Internal)16
Supply Current (Internal)17
Supply Current (Idle)18
Supply Current (Analog)9
Input Capacitance19, 20
Test Conditions
@ VDDEXT =Min, IOH =–2.0 mA2
@ VDDEXT =Min, IOL =4.0 mA2
@ VDDEXT =Max, VIN =VDD Max
@ VDDEXT =Max, VIN =0 V
@ VDDEXT = Max, VIN = VDDEXT Max
@ VDDEXT = Max, VIN = 0 V
@ VDDEXT = Max, VIN = 2.0 V
@ VDDEXT = Max, VIN = 0.8 V
@ VDDEXT = Max
@ VDDEXT = Max
@ VDDEXT =Max, VIN =0 V
@ VDDEXT =Max, VIN =0 V
@ VDDEXT =Max, VIN =VDD Max
@ VDDEXT =Max, VIN =0 V
@ VDDEXT =Max, VIN =VDD Max
@ VDDEXT =Max, VIN =0 V
@ VDDEXT =Max, VIN =0 V
@ VDDEXT =Max, VIN =VDD Max
@ VDDEXT =Max, VIN =0 V
tCCLK =10.0 ns, VDDINT =Max
tCCLK =10.0 ns, VDDINT =Max
tCCLK =10.0 ns, VDDINT =Max
tCCLK =10.0 ns, VDDINT =Max
@AVDD =Max
fIN =1 MHz, TCASE =25°C, VIN =2.5 V
1
Min
2.4
–250
50
–300
300
Max
0.4
10
10
25
25
–50
200
250
500
10
10
250
250
500
25
4
960
715
550
450
10
4.7
Unit
V
V
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
mA
mA
mA
mA
mA
mA
pF
Applies to output and bidirectional pins: DATA63–0, ADDR31–0, MS3–0, RDx, WRx, PAGE, CLKOUT, ACK, FLAG3–0, TIMEXP, HBG, REDY, DMAG1, DMAG2, BR6–1,
PA, BRST, CIF, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, BMS, TDO, and EMU.
2
See Output Drive Currents 47 for typical drive current capabilities.
3
Applies to input pins: SBTS, IRQ2–0, HBR, CS, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK, and CLK_CFG3-0.
4
Applies to input pins with internal pull-ups: DR0, and DR1.
5
Applies to input pins with internal pull-ups: DMARx, TMS, TDI, and TRST.
6
Applies to CLKIN only.
7
Applies to all pins with keeper latches: ADDR31–0, DATA63–0, PAGE, BRST, and CLKOUT.
8
Current required to switch from kept high to low, or from kept low to high.
9
Characterized, but not tested.
10
Applies to three-statable pins: DATA63–0, ADDR31–0, PAGE, CLKOUT, ACK, FLAG3–0, REDY, HBG, BMS, BR6–1, TFSx, RFSx, and TDO.
11
Applies to three-statable pins with internal pull-ups: DTx, TCLKx, RCLKx, and EMU.
12
Applies to three-statable pins with internal pull-ups: MS3–0,RDx, WRx, DMAGx, PA, and CIF.
13
Applies to three-statable pins with internal pull-downs: LxDAT7–0, LxCLK, and LxACK.
14
Applies to ACK pulled up internally with 2 k during reset or ID2–0 = 00x.
15
The test program used to measure IDD-INPEAK represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power
measurements made using typical applications are less than specified. For more information, see Power Dissipation on Page 47.
16
IDD-INHIGH is a composite average based on a range of high activity code. For more information, see Power Dissipation on Page 47.
17
IDD-INLOW is a composite average based on a range of low activity code. For more information, see Power Dissipation on Page 47.
18
Idle denotes ADSP-21160N state during execution of IDLE instruction. For more information, see Power Dissipation on Page 47.
19
Applies to all signal pins.
20
Guaranteed, but not tested.
Rev. D |
Page 18 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
ABSOLUTE MAXIMUM RATINGS
PACKAGE INFORMATION
Stresses at or above those listed in Table 9 (ADSP-21160M) and
Table 10 (ADSP-21160N) may cause permanent damage to the
product. These are stress ratings only; functional operation of
the product at these or any other conditions above those indicated in the operational section of this specification is not
implied. Operation beyond the maximum operating conditions
for extended periods may affect product reliability.
The information presented in Figure 7 provides details about
the package branding for the ADSP-21160M/ADSP-21160N
processor. For a complete listing of product availability, see
Ordering Guide on Page 58.
a
Table 9. Absolute Maximum Ratings—ADSP-21160M
Parameter
Internal (Core) Supply Voltage (VDDINT)
Analog (PLL) Supply Voltage (AVDD)
External (I/O) Supply Voltage (VDDEXT)
Input Voltage
Output Voltage Swing
Load Capacitance
Storage Temperature Range
ADSP-21160a
Rating
–0.3 V to +3.0 V
–0.3 V to +3.0 V
–0.3 V to +4.6 V
–0.5 V to VDDEXT + 0.5 V
–0.5 V to VDDEXT + 0.5 V
200 pF
–65C to +150C
tppZ-cc
vvvvvv.x n.n
#yyww country_of_origin
S
Figure 7. Typical Package Brand
Table 11. Package Brand Information
Table 10. Absolute Maximum Ratings—ADSP-21160N
Parameter
Internal (Core) Supply Voltage (VDDINT)
Analog (PLL) Supply Voltage (AVDD)
External (I/O) Supply Voltage (VDDEXT)
Input Voltage
Output Voltage Swing
Load Capacitance
Storage Temperature Range
Rating
–0.3 V to +2.3 V
–0.3 V to +2.3 V
–0.3 V to +4.6 V
–0.5 V to VDDEXT + 0.5 V
–0.5 V to VDDEXT + 0.5 V
200 pF
–65C to +150C
Brand Key
a
t
pp
Z
cc
vvvvvv.x
n.n
#
yyww
ESD SENSITIVITY
ESD (electrostatic discharge sensitive
device)
Charged devices and circuit boards can
discharge without detection. Although this
product features patented or proprietary
protection circuitry, damage may occur on
devices subjected to high energy ESD.
Therefore, proper ESD precautions should be
taken to avoid performance degradation or
loss of functionality.
Rev. D |
Page 19 of 58 |
September 2015
Field Description
ADSP-21160 Model (M or N)
Temperature Range
Package Type
RoHS Compliant Designation
See Ordering Guide
Assembly Lot Code
Silicon Revision
RoHS Compliant Designation
Date Code
ADSP-21160M/ADSP-21160N
TIMING SPECIFICATIONS
The ADSP-21160x DSP’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the
internal clock, the DSP uses an internal phase-locked loop
(PLL). This PLL-based clocking minimizes the skew between
the system clock (CLKIN) signal and the DSP’s internal clock
(the clock source for the external port logic and I/O pads).
The ADSP-21160x DSP’s internal clock (a multiple of CLKIN)
provides the clock signal for timing internal memory, processor
core, link ports, serial ports, and external port (as required for
read/write strobes in asynchronous access mode). During reset,
program the ratio between the DSP’s internal clock frequency
and external (CLKIN) clock frequency with the CLK_CFG3–0
pins. Even though the internal clock is the clock source for the
external port, the external port clock always switches at the
CLKIN frequency. To determine switching frequencies for the
serial and link ports, divide down the internal clock, using the
programmable divider control of each port (TDIVx/RDIVx for
the serial ports and LxCLKD1–0 for the link ports).
Note the following definitions of various clock periods that are a
function of CLKIN and the appropriate ratio control:
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
During processor reset (RESET pin low) or software reset (SRST
bit in SYSCON register = 1), deassertion (MS3–0, HBG,
DMAGx, RDx, WRx, CIF, PAGE, BRST) and three-state
(FLAG3-0, LxCLK, LxACK, LxDAT7-0, ACK, REDY, PA,
TFSx, RFSx, TCLKx, RCLKx, DTx, BMS, TDO, EMU, DATA)
timings differ. These occur asynchronously to CLKIN, and may
not meet the specifications published in the timing requirements and switching characteristics tables. The maximum delay
for deassertion and three-state is one tCK from RESET pin assertion low or setting the SRST bit in SYSCON. During reset the
DSP will not respond to SBTS, HBR, and MMS accesses. HBR
asserted before reset will be recognized, but an HBG will not be
returned by the DSP until after reset is deasserted and the DSP
has completed bus synchronization.
• tLCLK = (tCCLK) LR
Unless otherwise noted, all timing specifications (Timing
Requirements and Switching Characteristics) listed on pages 21
through 46 apply to both ADSP-21160M and ADSP-21160N.
• tSCLK = (tCCLK) SR
Power-Up Sequencing
• tCCLK = (tCK) / CR
where:
For power-up sequencing, see Table 12 and Figure 8. During the
power-up sequence of the DSP, differences in the ramp-up rates
and activation time between the two power supplies can cause
current to flow in the I/O ESD protection circuitry. To prevent
this damage to the ESD diode protection circuitry, Analog
Devices recommends including a bootstrap Schottky diode (see
Figure 9). The bootstrap Schottky diode connected between the
VDDINT and VDDEXT power supplies protects the ADSP-21160x
from partially powering the VDDEXT supply. Including a Schottky
diode will shorten the delay between the supply ramps and thus
prevent damage to the ESD diode protection circuitry. With this
technique, if the VDDINT rail rises ahead of the VDDEXT rail, the
Schottky diode pulls the VDDEXT rail along with the VDDINT rail.
• LCLK = Link Port Clock
• SCLK = Serial Port Clock
• tCK = CLKIN Clock Period
• tCCLK = (Processor) Core Clock Period
• tLCLK = Link Port Clock Period
• tSCLK = Serial Port Clock Period
• CR = Core/CLKIN Ratio (2, 3, or 4:1,
determined by CLK_CFG3–0 at reset)
• LR = Link Port/Core Clock Ratio (1, 2, 3, or 4:1,
determined by LxCLKD)
• SR = Serial Port/Core Clock Ratio (wide range,
determined by CLKDIV)
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times.
See Figure 33 on Page 49 under Test Conditions for voltage reference levels.
Switching characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given
Rev. D |
Page 20 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
Table 12. Power-Up Sequencing
Parameter
Timing Requirements
tRSTVDD
RESET Low Before VDDINT/VDDEXT on
VDDINT on Before VDDEXT
tIVDDEVDD
tCLKVDD
CLKIN Running After valid VDDINT/VDDEXT1
CLKIN Valid Before RESET Deasserted
tCLKRST
tPLLRST
PLL Control Setup Before RESET Deasserted
Switching Characteristics
tCORERST
DSP Core Reset Deasserted After RESET Deasserted
Min
0
– 50
0
102
203
Max
+200
200
Unit
ns
ms
ms
μs
μs
4096tCK3, 4
1
Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their VDDINT and VDDEXT rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds,
depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal after meeting worst-case start-up timing of oscillators. Refer to your oscillator manufacturer’s data sheet for start-up time.
3
Based on CLKIN cycles.
4
CORERST is an internal signal only. The 4096 cycle count is dependent on tSRST specification. If setup time is not met, one additional CLKIN cycle may be added to the core
reset time, resulting in 4097 cycles maximum.
RESET
tRSTVDD
VDDINT
tIVDDEVDD
VDDEXT
tCLKVDD
CLKIN
tCLKRST
CLK_CFG3-0
tPLLRST
tCORERST
CORERST
Figure 8. Power-Up Sequencing
Rev. D |
Page 21 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
VDDEXT
VOLTAGE REGULATOR
VDDEXT
ADSP-21160x
VDDINT
VOLTAGE REGULATOR
VDDINT
Figure 9. Dual Voltage Schottky Diode
Clock Input
For clock input, see Table 13 and Figure 10.
Table 13. Clock Input
Parameter
Timing Requirements
tCK
CLKIN Period
tCKL
CLKIN Width Low
tCKH
CLKIN Width High
tCKRF
CLKIN Rise/Fall (0.4 V–2.0 V)
tCCLK
Core Clock Period
ADSP-21160M
80 MHz
Min
Max
ADSP-21160N
100 MHz
Unit
Min
Max
25
10.5
10.5
20
7.5
7.5
12.5
tCK
CLKIN
tCKH
tCKL
Figure 10. Clock Input
Rev. D |
Page 22 of 58 |
September 2015
80
40
40
3
40
10
80
40
40
3
30
ns
ns
ns
ns
ns
ADSP-21160M/ADSP-21160N
Reset
For reset, see Table 14 and Figure 11.
Table 14. Reset
Parameter
Timing Requirements
tWRST
RESET Pulsewidth Low1
tSRST
RESET Setup Before CLKIN High2
Min
Max
4tCK
8
Unit
ns
ns
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming
stable VDD and CLKIN (not including start-up time of external clock oscillator).
2
Only required if multiple ADSP-21160x DSPs must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple
ADSP-21160x DSPs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.
CLKIN
tSRST
tWRST
RESET
Figure 11. Reset
Rev. D |
Page 23 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
Interrupts
For interrupts, see Table 15 and Figure 12.
Table 15. Interrupts
Parameter
Timing Requirements
tSIR
IRQ2–0 Setup Before CLKIN High1
tHIR
IRQ2–0 Hold After CLKIN High1
IRQ2–0 Pulsewidth2
tIPW
1
2
Min
Max
Unit
6
0
2+tCK
ns
ns
ns
Only required for IRQx recognition in the following cycle.
Applies only if tSIR and tHIR requirements are not met.
CLKIN
tSIR
tHIR
IRQ2–0
tIPW
Figure 12. Interrupts
Timer
For timer, see Table 16 and Figure 13.
Table 16. Timer
Parameter
Switching Characteristic
tDTEX
CLKIN High to TIMEXP1
1
Min
Max
Unit
1
9
ns
For ADSP-21160M, specification is 7 ns, maximum.
CLKIN
tDTEX
tDTEX
TIMEXP
Figure 13. Timer
Rev. D |
Page 24 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
Flags
For flags, see Table 17 and Figure 14.
Table 17. Flags
Parameter
Timing Requirements
tSFI
FLAG3–0 IN Setup Before CLKIN High1
tHFI
FLAG3–0 IN Hold After CLKIN High1
FLAG3–0 IN Delay After RDx/WRx Low1, 2
tDWRFI
tHFIWR
FLAG3–0 IN Hold After RDx/WRx Deasserted1
Min
Max
4
1
10
0
Switching Characteristics
tDFO
FLAG3–0 OUT Delay After CLKIN High
tHFO
FLAG3–0 OUT Hold After CLKIN High
tDFOE
CLKIN High to FLAG3–0 OUT Enable
CLKIN High to FLAG3–0 OUT Disable3
tDFOD
9
1
1
tCK– tCCLK +5
1
Flag inputs meeting these setup and hold times for instruction cycle N will affect conditional instructions in instruction cycle N+2.
For ADSP-21160M, specification is 12 ns, maximum.
3
For ADSP-21160M, specification is 5 ns, maximum.
2
CLKIN
tDFOE
tDFO
tDFO
tHFO
FLAG3–0 OUT
FLAG OUTPUT
CLKIN
tSFI
tHFI
FLAG3–0 IN
tDWRFI
tHFIWR
RDx
WRx
FLAG INPUT
Figure 14. Flags
Rev. D |
Page 25 of 58 |
September 2015
tDFOD
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-21160M/ADSP-21160N
of Table 18. These specifications apply when the ADSP-21160x
is the bus master accessing external memory space in asynchronous access mode.
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to
memories (and memory-mapped peripherals) without reference
to CLKIN except for the ACK pin requirements listed in note 6
Table 18. Memory Read—Bus Master
Parameter
Timing Requirements
Address, CIF, Selects Delay to Data Valid1, 2, 3, 4
tDAD
tDRLD
RDx Low to Data Valid1, 4, 5
tHDA
Data Hold from Address, Selects6
tSDS
Data Setup to RDx High1
tHDRH
Data Hold from RDx High6
tDAAK
ACK Delay from Address, Selects2, 7
ACK Delay from RDx Low7
tDSAK
tSAKC
ACK Setup to CLKIN7
tHAKC
ACK Hold After CLKIN
Min
Max
Unit
tCK – 0.25tCCLK – 8.5+W
tCK – 0.5tCCLK +W
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
8
1
tCK – 0.5tCCLK – 12+W
tCK – 0.75tCCLK – 11+W
0.5tCCLK +3
1
Switching Characteristics
tDRHA
Address, CIF, Selects Hold After RDx High
0.25tCCLK – 1+H
tDARL
Address, CIF, Selects to RDx Low2
0.25tCCLK – 3
RDx Pulsewidth
tCK – 0.5tCCLK – 1+W
tRW
tRWR
RDx High to WRx, RDx, DMAGx Low
0.5tCCLK – 1+HI
W = (number of wait states specified in WAIT register) tCK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
1
ns
ns
ns
ns
Data Delay/Setup: User must meet tDAD, tDRLD, or tSDS.
The falling edge of MSx, BMS is referenced.
3
For ADSP-21160M, specification is tCK–0.25tCCLK–11+W ns, maximum.
4
The maximum limit of timing requirement values for tDAD and tDRLD parameters are applicable for the case where AMI_ACK is always high.
5
For ADSP-21160M, specification is 0.75tCK–11+W ns, maximum.
6
Data Hold: User must meet tHDA or tHDRH in asynchronous access mode. See Example System Hold Time Calculation on page 49 for the calculation of hold times given capacitive
and dc loads.
7
For asynchronous access, ACK is sampled only after the programmed wait states for the access have been counted. For the first CLKIN cycle of a new external memory access,
ACK must be driven low (deasserted) by tDAAK, tDSAK, or tSAKC. For the second and subsequent cycles of an asynchronous external memory access, the tSAKC and tHAKC must be
met for both assertion and deassertion of ACK signal.
2
Rev. D |
Page 26 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
tHDA
ADDRESS
MSx, BMS,
CIF
tDARL
tDRHA
tRW
RD
tDRLD
tSDS
tDAD
tHDRH
DATA
tDSAK
tDAAK
tRWR
ACK
tSAKC
tHAKC
CLKIN
WR, DMAG
Figure 15. Memory Read—Bus Master
Rev. D |
Page 27 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
of Table 19. These specifications apply when the ADSP-21160x
is the bus master accessing external memory space in asynchronous access mode.
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to
memories (and memory-mapped peripherals) without reference
to CLKIN except for the ACK pin requirements listed in note 1
Table 19. Memory Write—Bus Master
Parameter
Timing Requirements
ACK Delay from Address, Selects1, 2
tDAAK
tDSAK
ACK Delay from WRx Low1
tSAKC
ACK Setup to CLKIN1
tHAKC
ACK Hold After CLKIN1
Min
Max
Unit
tCK – 0.5tCCLK –12+W
tCK – 0.75tCCLK – 11+W
ns
ns
ns
ns
0.5tCCLK +3
1
Switching Characteristics
tDAWH
Address, CIF, Selects to WRx Deasserted2
tCK – 0.25tCCLK – 3+W
Address, CIF, Selects to WRx Low2
0.25tCCLK – 3
tDAWL
tWW
WRx Pulsewidth
tCK – 0.5tCCLK – 1+W
tDDWH
Data Setup before WRx High3
tCK – 0.5tCCLK – 1+W
tDWHA
Address Hold after WRx Deasserted
0.25tCCLK – 1+H
tDWHD
Data Hold after WRx Deasserted
0.25tCCLK – 1+H
tDATRWH
Data Disable after WRx Deasserted4
0.25tCCLK – 2+H
0.25tCCLK +2+H
WRx High to WRx, RDx, DMAGx Low
0.5tCCLK – 1+HI
tWWR
tDDWR
Data Disable before WRx or RDx Low
0.25tCCLK – 1+I
tWDE
WRx Low to Data Enabled
–0.25tCCLK – 1
W = (number of wait states specified in WAIT register) × tCK.
H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
For asynchronous access, ACK is sampled only after the programmed wait states for the access have been counted. For the first CLKIN cycle of a new external memory
access, ACK must be driven low (deasserted) by tDAAK or tDSAK or tSAKC. For the second and subsequent cycles of an asynchronous external memory access, the tSAKC and
tHAKC must be met for both assertion and deassertion of ACK signal.
2
The falling edge of MSx, BMS is referenced.
3
For ADSP-21160M, specification is tCK–0.25tCCLK–12.5+W ns, minimum.
4
See Example System Hold Time Calculation on Page 49 for calculation of hold times given capacitive and dc loads.
Rev. D |
Page 28 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
ADDRESS
MSx, BMS,
CIF
t
tDAWL
t DWHA
DAWH
t WW
WR
tWWR
t DATRWH
tWDE
t DDWH
tDDWR
DATA
tDAAK
tDSAK
t DWHD
ACK
t HAKC
tSAKC
CLKIN
RD, DMAG
Figure 16. Memory Write—Bus Master
Rev. D |
Page 29 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
Synchronous Read/Write—Bus Master
See Table 20 and Figure 17. Use these specifications for interfacing to external memory systems that require CLKIN—relative
timing or for accessing a slave ADSP-21160x (in multiprocessor
memory space). These synchronous switching characteristics
are also valid during asynchronous memory reads and writes
except where noted (see Memory Read–Bus Master on page 26
and Memory Write–Bus Master on page 28).
When accessing a slave ADSP-21160x, these switching characteristics must meet the slave’s timing requirements for
synchronous read/writes (see Synchronous Read/Write–Bus
Slave on page 32). The slave ADSP-21160x must also meet these
(bus master) timing requirements for data and acknowledge
setup and hold times.
Table 20. Synchronous Read/Write—Bus Master
Parameter
Timing Requirements
tSSDATI
Data Setup Before CLKIN
tHSDATI
Data Hold After CLKIN
ACK Setup Before CLKIN
tSACKC
tHACKC
ACK Hold After CLKIN
Min
Max
5.5
1
0.5tCCLK +3
1
Switching Characteristics
tDADDO
Address, MSx, BMS, BRST, CIF Delay After CLKIN
tHADDO
Address, MSx, BMS, BRST, CIF Hold After CLKIN
tDPGO
PAGE Delay After CLKIN
RDx High Delay After CLKIN
tDRDO
tDWRO
WRx High Delay After CLKIN
tDRWL
RDx/WRx Low Delay After CLKIN
tDDATO
Data Delay After CLKIN1
tHDATO
Data Hold After CLKIN
tDACKMO
ACK Delay After CLKIN2, 3
tACKMTR
ACK Disable Before CLKIN2
CLKOUT Delay After CLKIN4
tDCKOO
tCKOP
CLKOUT Period
tCKWH
CLKOUT Width High
tCKWL
CLKOUT Width Low
ns
ns
ns
ns
10
1.5
1.5
0.25tCCLK – 1
0.25tCCLK – 1
0.25tCCLK – 1
1.5
3
–3
0.5
tCK – 1
tCK/2 – 2
tCK/2 – 2
1
Unit
11
0.25tCCLK +9
0.25tCCLK +9
0.25tCCLK +9
0.25tCCLK +9
9
5
tCK5 +1
tCK/2+22
tCK/2+22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
For ADSP-21160M, specification is 12.5 ns, maximum.
Applies to broadcast write, master precharge of ACK.
3
For ADSP-21160M, specification is 0.25tCCLK+3 ns (minimum) and .25tCCLK+9 ns (maximum).
4
For ADSP-21160M, specification is 2 ns, minimum.
5
Applies only when the DSP drives a bus operation; CLKOUT held inactive or three-state otherwise. For more information, see the System Design chapter in the
ADSP-21160 SHARC DSP Hardware Reference.
2
Rev. D |
Page 30 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
CLKIN
tCKOP
tCKWH
tDCKOO
tCKWL
CLKOUT
tDADDO
tHADDO
ADDRESS
MSx, BRST,
CIF
tDPGO
PAGE
tHACKC
tSACKC
ACK
(IN)
tDACKMO
tACKMTR
ACK
(OUT)
READ CYCLE
tDRWL
tDRDO
RDx
tSSDATI
tHSDATI
DATA
(IN)
WRITE CYCLE
tDWRO
tDRWL
WRx
tHDATO
tDDATO
DATA
(OUT)
Figure 17. Synchronous Read/Write—Bus Master
Rev. D |
Page 31 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
Synchronous Read/Write—Bus Slave
See Table 21 and Figure 18. Use these specifications for
ADSP-21160x bus master accesses of a slave’s IOP registers or
internal memory (in multiprocessor memory space). The bus
master must meet these (bus slave) timing requirements.
Table 21. Synchronous Read/Write—Bus Slave
Parameter
Timing Requirements
tSADDI
Address, BRST Setup Before CLKIN
tHADDI
Address, BRST Hold After CLKIN
RDx/WRx Setup Before CLKIN
tSRWI
tHRWI
RDx/WRx Hold After CLKIN
tSSDATI
Data Setup Before CLKIN
tHSDATI
Data Hold After CLKIN
Min
5
1
5
1
5.5
1
Switching Characteristics
tDDATO
Data Delay After CLKIN1
Data Hold After CLKIN
tHDATO
tDACKC
ACK Delay After CLKIN
tHACKO
ACK Hold After CLKIN
1
Max
ns
ns
ns
ns
ns
ns
0.25 tCCLK + 9
1.5
10
1.5
For ADSP-21160M, specification is 12.5 ns, maximum.
CLKIN
tSADDI
tHADDI
ADDRESS
BRST
tHACKO
tDACKC
ACK
tSRWI
READ ACCESS
tHRWI
RDx
tHDATO
tDDATO
DATA
(OUT)
WRITE ACCESS
tHRWI
tSRWI
WRx
tSSDATI
DATA
(IN)
Figure 18. Synchronous Read/Write—Bus Slave
Rev. D |
Page 32 of 58 |
September 2015
Unit
tHSDATI
ns
ns
ns
ns
ADSP-21160M/ADSP-21160N
Multiprocessor Bus Request and Host Bus Request
See Table 22 and Figure 19. Use these specifications for passing
of bus mastership between multiprocessing ADSP-21160x DSPs
(BRx) or a host processor, both synchronous and asynchronous
(HBR, HBG).
Table 22. Multiprocessor Bus Request and Host Bus Request
Parameter
Timing Requirements
tHBGRCSV
HBG Low to RDx/WRx/CS Valid1
tSHBRI
HBR Setup Before CLKIN2
HBR Hold After CLKIN2
tHHBRI
tSHBGI
HBG Setup Before CLKIN
tHHBGI
HBG Hold After CLKIN High
tSBRI
BRx, PA Setup Before CLKIN
tHBRI
BRx, PA Hold After CLKIN High
tSRPBAI
RPBA Setup Before CLKIN
RPBA Hold After CLKIN
tHRPBAI
Switching Characteristics
tDHBGO
HBG Delay After CLKIN
tHHBGO
HBG Hold After CLKIN3
tDBRO
BRx Delay After CLKIN
tHBRO
BRx Hold After CLKIN
PA Delay After CLKIN, Slave
tDPASO
tTRPAS
PA Disable After CLKIN, Slave
tDPAMO
PA Delay After CLKIN, Master
tPATR
PA Disable Before CLKIN, Master4
tDRDYCS
REDY (O/D) or (A/D) Low from CS and HBR Low5, 6
tTRDYHG
REDY (O/D) Disable or REDY (A/D) High from HBG5, 7
tARDYTR
REDY (A/D) Disable from CS or HBR High5
Min
Max
6
1
6
1
9
1
6
2
6.5 + tCK + tCCLK – 12.5CR ns
ns
ns
ns
ns
ns
ns
ns
ns
7
1.5
8
1.5
8
1.5
0.25tCCLK +9
0.25tCCLK – 5.5
0.5tCK+1.0
tCK +15
11
1
For ADSP-21160M, specification is 19 ns, maximum.
Only required for recognition in the current cycle.
3
For ADSP-21160M, specification is 2 ns, maximum.
4
For ADSP-21160M, specification is 0.25tCK–5 ns, minimum.
5
(O/D) = open drain, (A/D) = active drive.
6
For ADSP-21160M, specification is 0.5tCK ns, maximum.
7
For ADSP-21160M, specification is tCK+25 ns, maximum.
2
Rev. D |
Page 33 of 58 |
September 2015
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-21160M/ADSP-21160N
CLKIN
tSH B R I
tH H BR I
HBR
t DH B GO
tH HB G O
HBG (OUT)
t DB R O
tH B RO
BRx (OUT)
tTR PA S
tD PA S O
PA (OUT)
(SLAVE)
tP A TR
tD PA M O
PA (OUT)
(MASTER)
t SH B GI
tH H B GI
HBG (IN)
tSB R I
tH B R I
BRx, PA (IN)
tS R PB A I
tH R PB A I
RPBA
HRB
CS
tTR D YH G
t DR D YC S
REDY
(O/ D)
tA R DY TR
REDY
(A/D)
tH B GR CS V
HBG (OUT)
RDx
WRx
CS
O /D = OPEN DRAIN, A/D = ACTIVE DRI VE
Figure 19. Multiprocessor Bus Request and Host Bus Request
Rev. D |
Page 34 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
Asynchronous Read/Write—Host to ADSP-21160x
Use these specifications (Table 23, Table 24, Figure 20, and
Figure 21) for asynchronous host processor accesses of an
ADSP-21160x, after the host has asserted CS and HBR (low).
After HBG is returned by the ADSP-21160x, the host can drive
the RDx and WRx pins to access the ADSP-21160x DSP’s
internal memory or IOP registers. HBR and HBG are assumed
low for this timing.
Table 23. Read Cycle
Parameter
Timing Requirements
Address Setup/CS Low Before RDx Low
tSADRDL
tHADRDH
Address Hold/CS Hold Low After RDx
tWRWH
RDx/WRx High Width
tDRDHRDY
RDx High Delay After REDY (O/D) Disable
tDRDHRDY
RDx High Delay After REDY (A/D) Disable
Switching Characteristics
tSDATRDY
Data Valid Before REDY Disable from Low
tDRDYRDL
REDY (O/D) or (A/D) Low Delay After RDx Low1
tRDYPRD
REDY (O/D) or (A/D) Low Pulsewidth for Read2
tHDARWH
Data Disable After RDx High3
Min
Max
Unit
0
2
5
0
0
ns
ns
ns
ns
ns
2
ns
ns
ns
ns
11
tCK – 4
1.5
6
1
For ADSP-21160M, specification is 7 ns, minimum.
For ADSP-21160M, specification is tCK ns, minimum.
3
For ADSP-21160M, specification is 2 ns, minimum.
2
Table 24. Write Cycle
1
2
Parameter
Timing Requirements
tSCSWRL
CS Low Setup Before WRx Low
tHCSWRH
CS Low Hold After WRx High
tSADWRH
Address Setup Before WRx High
Address Hold After WRx High
tHADWRH
tWWRL
WRx Low Width1
tWRWH
RDx/WRx High Width
tDWRHRDY
WRx High Delay After REDY (O/D) or (A/D) Disable
tSDATWH
Data Setup Before WRx High
tHDATWH
Data Hold After WRx High
Min
0
0
6
2
tCCLK+1
5
0
5
4
Switching Characteristics
tDRDYWRL
REDY (O/D) or (A/D) Low Delay After WRx/CS Low
tRDYPWR
REDY (O/D) or (A/D) Low Pulsewidth for Write2
5.75 + 0.5tCCLK
Page 35 of 58 |
September 2015
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
For ADSP-21160M, specification is 7 ns, minimum.
For ADSP-21160M, specification is 12 ns, minimum.
Rev. D |
Max
ns
ns
ADSP-21160M/ADSP-21160N
READ CYCLE
ADDRESS/CS
tHADRDH
tSADRDL
tWRWH
RDx
tHDARWH
DATA (OUT)
tSDATRDY
tDRDYRDL
tDRDHRDY
tRDYPRD
REDY (O/D)
REDY (A/D)
Figure 20. Asynchronous Read—Host to ADSP-21160x
WRITE CYCLE
ADDRESS
tSADWRH
tSCSWRL
tHADWRH
tHCSWRH
CS
tWWRL
tWRWH
WRx
tHDATWH
tSDATWH
DATA (IN)
tDRDYWRL
tRDYPWR
tDWRHRDY
REDY (O/D)
REDY (A/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 21. Asynchronous Write—Host to ADSP-21160x
Rev. D |
Page 36 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
Three-State Timing—Bus Master, Bus Slave
See Table 25 and Figure 22. These specifications show how the
memory interface is disabled (stops driving) or enabled
(resumes driving) relative to CLKIN and the SBTS pin. This
timing is applicable to bus master transition cycles (BTC) and
host transition cycles (HTC) as well as the SBTS pin.
Table 25. Three-State Timing—Bus Master, Bus Slave
Parameter
Timing Requirements
tSTSCK
SBTS Setup Before CLKIN
tHTSCK
SBTS Hold After CLKIN1
Min
Max
6
2
Switching Characteristics
tMIENA
Address/Select Enable After CLKIN
Strobes Enable After CLKIN2
tMIENS
tMIENHG
HBG Enable After CLKIN
tMITRA
Address/Select Disable After CLKIN3
tMITRS
Strobes Disable After CLKIN2, 4, 5
tMITRHG
HBG Disable After CLKIN6
tDATEN
Data Enable After CLKIN7, 8
Data Disable After CLKIN7, 9
tDATTR
tACKEN
ACK Enable After CLKIN7
tACKTR
ACK Disable After CLKIN7
tCDCEN
CLKOUT Enable After CLKIN10
tCDCTR
CLKOUT Disable After CLKIN
tATRHBG
Address, MSx Disable Before HBG Low11
tSTRHBG
RDx, WRx, DMAGx Disable Before HBG Low11
Page Disable Before HBG Low11
tPTRHBG
tBTRHBG
BMS Disable Before HBG Low11
tMENHBG
Memory Interface Enable After HBG High12, 13
ns
ns
1.5
1.5
1.5
0.5
0.25tCCLK – 4
0.5
0.25tCCLK +1
0.5
1.5
1.5
0.5
tCCLK – 3
1.5tCK – 6
tCK + 0.25tCCLK – 6
tCK – 6
0.5tCK – 6.5
tCK – 5
1
For ADSP-21160M, specification is 1 ns, minimum.
Strobes = RDx, WRx, and DMAGx.
3
For ADSP-21160M, specification is 0.25tCCLK–1 ns (minimum) and 0.25tCCLK+4 ns (maximum).
4
If access aborted by SBTS, then strobes disable before CLKIN [0.25tCCLK + 1.5 (min.), 0.25tCCLK + 5 (max.)]
5
For ADSP-21160M, specification is 0.25tCCLK ns (maximum).
6
For ADSP-21160M, specification is 3.5 ns (minimum).
7
In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
8
For ADSP-21160M, specification is 1.5 ns (minimum) and 10 ns (maximum).
9
For ADSP-21160M, specification is 1.5 ns (minimum).
10
For ADSP-21160M, specification is 0.5 ns (minimum).
11
Not specified for ADSP-21160M.
12
Memory Interface = Address, RDx, WRx, MSx, PAGE, DMAGx, and BMS (in EPROM boot mode).
13
For ADSP-21160M, specification is tCK+5 ns (maximum).
2
Rev. D |
Page 37 of 58 |
Unit
September 2015
9
9
9
9
0.25tCCLK+1.5
8
0.25tCCLK + 7
5
9
5
9
tCCLK +1
1.5tCK + 5
tCK + 0.25tCCLK + 5
tCK + 5
0.5tCK + 1.5
tCK +6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-21160M/ADSP-21160N
CLKIN
tSTSCK
tHTSCK
SBTS
tMIENA, tMIENS, tMIENHG
tMITRA, tMITRS, tMITRHG
MEMORY
INTERFACE
tDATTR
tDATEN
DATA
tACKTR
tACKEN
ACK
tCDCEN
tCDCTR
CLKOUT
tATRHBG
tSTRHBG
tPTRHBG
tBTRHBG
HBG
tMENHBG
MEMORY
INTERFACE
MEMORY INTERFACE = ADDRESS, RDx, WRx, MSx, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)
Figure 22. Three-State Timing—Bus Master, Bus Slave
Rev. D |
Page 38 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
signals. For Paced Master mode, the data transfer is controlled
by ADDR31–0, RDx, WRx, MS3–0, and ACK (not DMAGx).
For Paced Master mode, the Memory Read-Bus Master, Memory Write-Bus Master, and Synchronous Read/Write-Bus
Master timing specifications for ADDR31–0, RDx, WRx,
MS3–0, PAGE, DATA63–0, and ACK also apply.
DMA Handshake
See Table 26 and Figure 23. These specifications describe the
three DMA handshake modes. In all three modes, DMARx is
used to initiate transfers. For handshake mode, DMAGx controls the latching or enabling of data externally. For external
handshake mode, the data transfer is controlled by the
ADDR31–0, RDx, WRx, PAGE, MS3–0, ACK, and DMAGx
Table 26. DMA Handshake
Parameter
Timing Requirements
DMARx Setup Before CLKIN1
tSDRC
tWDR
DMARx Width Low (Nonsynchronous)2, 3
tSDATDGL
Data Setup After DMAGx Low4, 5
tHDATIDG
Data Hold After DMAGx High
tDATDRH
Data Valid After DMARx High4, 6
tDMARLL
DMARx Low Edge to Low Edge7
DMARx Width High2, 8
tDMARH
Min
Max
3
0.5tCCLK +2.5
tCK – 0.5tCCLK –7
2
tCK +3
tCK
0.5tCCLK +1
Switching Characteristics
tDDGL
DMAGx Low Delay After CLKIN
0.25tCCLK +1
tWDGH
DMAGx High Width
0.5tCCLK – 1+HI
tWDGL
DMAGx Low Width
tCK – 0.5tCCLK – 1
tHDGC
DMAGx High Delay After CLKIN
tCK – 0.25tCCLK +1.5
Data Valid Before DMAGx High9
tCK – 0.25tCCLK – 8
tVDATDGH
tDATRDGH
Data Disable After DMAGx High10
0.25tCCLK – 3
tDGWRL
WRx Low Before DMAGx Low
–1.5
tDGWRH
DMAGx Low Before WRx High
tCK – 0.5tCCLK – 2 +W
11
tDGWRR
WRx High Before DMAGx High
–1.5
tDGRDL
RDx Low Before DMAGx Low
–1.5
tDRDGH
RDx Low Before DMAGx High
tCK – 0.5tCCLK –2+W
11
RDx High Before DMAGx High
–1.5
tDGRDR
tDGWR
DMAGx High to WRx, RDx, DMAGx Low
0.5tCCLK – 2+HI
tDADGH
Address/Select Valid to DMAGx High12
15.5
tDDGHA
Address/Select Hold after DMAGx High
1
W = (number of wait states specified in WAIT register) tCK.
HI = tCK (if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
1
0.25tCCLK +9
tCK – 0.25tCCLK +9
tCK – 0.25tCCLK +5
0.25tCCLK +1.5
2
2
2
2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Only required for recognition in the current cycle.
Maximum throughput using DMARx / DMAGx handshaking equals tWDR + tDMARH = (0.5tCCLK +1) + (0.5tCCLK +1)=10.0 ns (100 MHz). This throughput limit applies to
non-synchronous access mode only.
3
For ADSP-21160M, specification is tCCLK+4.5 ns, minimum.
4
tSDATDGL is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the
data can be driven tDATDRH after DMARx is brought high.
5
For ADSP-21160M, specification is 0.75tCCLK–7 ns, maximum.
6
For ADSP-21160M, specification is tCLK+10 ns, maximum.
7
Use tDMARLL if DMARx transitions synchronous with CLKIN. Otherwise, use tWDR and tDMARH.
8
For ADSP-21160M, specification is tCCLK+4.5 ns, minimum.
9
tVDATDGH is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then tVDATDGH = tCK – 0.25tCCLK – 8 + (n × tCK) where
n equals the number of extra cycles that the access is prolonged.
10
See Example System Hold Time Calculation on page 49 for calculation of hold times given capacitive and dc loads.
11
This parameter applies for synchronous access mode only.
12
For ADSP-21160M, specification is 18 ns, minimum.
2
Rev. D |
Page 39 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
CLKIN
tSDRC
tDMARLL
tSDRC
tWDR
tDMARH
DMARx
tHDGC
tDDGL
tWDGL
tWDGH
DMAGx
TRANSFERS BETWEEN ADSP-2116X
INTERNAL MEMORY AND EXTERNAL DEVICE
tDATRDGH
tVDATDGH
DATA
(FROM ADSP-2116X TO EXTERNAL DRIVE)
tDATDRH
tSDATDGL
tHDATIDG
DATA
(FROM EXTERNAL DRIVE TO ADSP-2116X)
TRANSFERS BETWEEN EXTERNAL DEVICE AND
EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE)
tDGWRL
tDGWRH
WRx
tDGWRR
(EXTERNAL DEVICE TO EXTERNAL MEMORY)
tDGRDR
RDx
tDGRDL
(EXTERNAL MEMORY TO EXTERNAL DEVICE)
tDRDGH
tDADGH
tDDGHA
ADDR
MSx
* MEMORY READ BUS MASTER, MEMORY WRITE BUS MASTER, OR SYNCHRONOUS READ/WRITE BUS MASTER
TIMING SPECIFICATIONS FOR ADDR31–0, RDx, WRx, MS3–0 AND ACK ALSO APPLY HERE.
Figure 23. DMA Handshake
Rev. D |
Page 40 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
maximum delay that can be introduced in LCLK, relative to
LDATA (hold skew = tLCLKTWL minimum + tHLDCH – tHLDCL). Calculations made directly from speed specifications result in
unrealistically small skew times, because they include multiple
tester guardbands.
Link Ports—Receive, Transmit
For link ports, see Table 27, Table 28, Figure 24, and Figure 25.
Calculation of link receiver data setup and hold, relative to link
clock, is required to determine the maximum allowable skew
that can be introduced in the transmission path, between
LDATA and LCLK. Setup skew is the maximum delay that can
be introduced in LDATA, relative to LCLK (setup
skew = tLCLKTWH minimum – tDLDCH – tSLDCL). Hold skew is the
Note that there is a two-cycle effect latency between the link
port enable instruction and the DSP enabling the link port.
Table 27. Link Ports—Receive
Parameter
Timing Requirements
tSLDCL
Data Setup Before LCLK Low
tHLDCL
Data Hold After LCLK Low1
LCLK Period
tLCLKIW
tLCLKRWL
LCLK Width Low2
tLCLKRWH
LCLK Width High3
Min
2.5
3
tLCLK
4
4
Switching Characteristics
tDLALC
LACK Low Delay After LCLK High4, 5
9
Max
ns
ns
ns
ns
ns
17
1
For ADSP-21160M, specification is 2.5 ns, minimum.
For ADSP-21160M, specification is 6 ns, minimum.
3
For ADSP-21160M, specification is 6 ns, minimum.
4
LACK goes low with tDLALC relative to rise of LCLK after first nibble, but does not go low if the receiver’s link buffer is not about to fill.
5
For ADSP-21160M, specification is 12 ns, minimum.
2
RECEIVE
tLCLKIW
tLCLKRWH
tLCLKRWL
LCLK
tHLDCL
tSLDCL
IN
LDAT(7:0)
tDLALC
LACK (OUT)
Figure 24. Link Ports—Receive
Rev. D |
Page 41 of 58 |
September 2015
Unit
ns
ADSP-21160M/ADSP-21160N
Table 28. Link Ports—Transmit
Parameter
Timing Requirements
tSLACH
LACK Setup Before LCLK High
LACK Hold After LCLK High
tHLACH
Min
Max
Unit
14
–2
Switching Characteristics
tDLDCH
Data Delay After LCLK High
tHLDCH
Data Hold After LCLK High
tLCLKTWL
LCLK Width Low1
tLCLKTWH
LCLK Width High2
tDLACLK
LCLK Low Delay After LACK High3
ns
ns
4
–2
0.5tLCLK – 0.5
0.5tLCLK –0.5
0.5tLCLK +4
ns
ns
ns
ns
ns
0.5tLCLK +0.5
0.5tLCLK +0.5
3/2tLCLK +11
1
For ADSP-21160M, specification is 0.5tLCLK–1.5 ns (minimum) and 0.5tLCLK+1.5 ns (maximum).
For ADSP-21160M, specification is 0.5tLCLK–1.5 ns (minimum) and 0.5tLCLK+1.5 ns (maximum).
3
For ADSP-21160M, specification is 0.5tLCLK+5 ns (minimum) and 3tLCLK+11 ns (maximum).
2
TRANSMIT
tLCLKTWH
tLCLKTWL
LAST NIBBLE/BYTE
TRANSMITTED
FIRST NIBBLE/BYTE
TRANSMITTED
LCLK INACTIVE
(HIGH)
LCLK
tDLDCH
tHLDCH
LDAT(7:0)
OUT
tSLACH
tHLACH
LACK (IN)
THE tSLACH REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE/BYTE TRANSMITTED.
Figure 25. Link Ports—Transmit
Rev. D |
Page 42 of 58 |
September 2015
tDLACLK
ADSP-21160M/ADSP-21160N
Serial Ports
For serial ports, see Table 29, Table 30, Table 31, Table 32,
Table 33, Table 34, Table 35, Figure 26, and Figure 27. To determine whether communication is possible between two devices
at clock speed n, the following specifications must be confirmed:
1) frame sync delay and frame sync setup and hold, 2) data delay
and data setup and hold, and 3) SCLK width.
Table 29. Serial Ports—External Clock
Parameter
Timing Requirements
TFS/RFS Setup Before TCLK/RCLK1
tSFSE
tHFSE
TFS/RFS Hold After TCLK/RCLK1
tSDRE
Receive Data Setup Before RCLK1
tHDRE
Receive Data Hold After RCLK1, 2
tSCLKW
TCLK/RCLK Width3
tSCLK
TCLK/RCLK Period
Min
Max
3.5
4
1.5
6.5
8
2tCCLK
Unit
ns
ns
ns
ns
ns
ns
1
Referenced to sample edge.
For ADSP-21160M, specification is 4 ns, minimum.
3
For ADSP-21160M, specification is 14 ns, minimum.
2
Table 30. Serial Ports—Internal Clock
Parameter
Timing Requirements
tSFSI
TFS Setup Before TCLK1; RFS Setup Before RCLK1
tHFSI
TFS/RFS Hold After TCLK/RCLK1, 2
tSDRI
Receive Data Setup Before RCLK1
tHDRI
Receive Data Hold After RCLK1
1
2
Min
Max
8
tCCLK/2 + 1
6.5
3
Unit
ns
ns
ns
ns
Referenced to sample edge.
For ADSP-21160M, specification is 1 ns, minimum.
Table 31. Serial Ports—External or Internal Clock
Parameter
Switching Characteristics
tDFSE
RFS Delay After RCLK (Internally Generated RFS)1
RFS Hold After RCLK (Internally Generated RFS)1
tHOFSE
1
Min
Max
Unit
13
ns
ns
Max
Unit
13
ns
ns
ns
ns
3
Referenced to drive edge.
Table 32. Serial Ports—External Clock
Parameter
Switching Characteristics
tDFSE
TFS Delay After TCLK (Internally Generated TFS)1
TFS Hold After TCLK (Internally Generated TFS)1
tHOFSE
tDDTE
Transmit Data Delay After TCLK1
tHDTE
Transmit Data Hold After TCLK1
1
Min
3
16
0
Referenced to drive edge.
Rev. D |
Page 43 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
Table 33. Serial Ports—Enable and Three-State
Parameter
Switching Characteristics
tDDTEN
Data Enable from External TCLK1
Data Disable from External TCLK1
tDDTTE
tDDTIN
Data Enable from Internal TCLK1
tDDTTI
Data Disable from Internal TCLK1
1
Min
Max
4
Unit
3
ns
ns
ns
ns
Max
Unit
4.5
ns
ns
ns
ns
ns
10
0
Referenced to drive edge.
Table 34. Serial Ports—Internal Clock
Parameter
Switching Characteristics
TFS Delay After TCLK (Internally Generated TFS)1
tDFSI
tHOFSI
TFS Hold After TCLK (Internally Generated TFS)1
tDDTI
Transmit Data Delay After TCLK1
tHDTI
Transmit Data Hold After TCLK1
tSCLKIW
TCLK/RCLK Width2
Min
–1.5
7.5
0
0.5tSCLK –1.5
1
Referenced to drive edge.
2
For ADSP-21160M, specification is 0.5tSCLK–2.5 ns (minimum) and 0.5tSCLK+2 ns (maximum)
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
RCLK
tSFSE/I
tHOFSE/I
RFS
tDDTE/I
tHDTE/I
tDDTENFS
DT
1ST BIT
2ND BIT
tDDTLFSE
LATE EXTERNAL TFS
DRIVE
SAMPLE
DRIVE
TCLK
tHOFSE/I
tSFSE/I
TFS
tDDTE/I
TDDTENFS
tHDTE/I
1ST BIT
DT
2ND BIT
tDDTLFSE
Figure 26. Serial Ports—External Late Frame Sync
Rev. D |
Page 44 of 58 |
September 2015
0.5tSCLK +1.5
ADSP-21160M/ADSP-21160N
Table 35. Serial Ports—External Late Frame Sync
Parameter
Switching Characteristics
tDDTLFSE
Data Delay from Late External TFS or External RFS with MCE = 1,
MFD = 01
tDDTENFS
Data Enable from Late FS or MCE = 1, MFD = 01
1
Min
Max
Unit
13
ns
1.0
ns
MCE = 1, TFS enable and TFS valid follow tDDTLFSE and tDDTENFS.
DATA RECEIVE— INTERNAL CLOCK
DRIVE
EDGE
DATA RECEIVE— EXTERNAL CLOCK
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
RCLK
SAMPLE
EDGE
tSCLKW
RCLK
tDFSE
tDFSE
tSFSI
tHOFSE
tHOFSE
tHFSI
RFS
tSFSE
tHFSE
tSDRE
tHDRE
RFS
tSDRI
tHDRI
DR
DR
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT— INTERNAL CLOCK
DRIVE
EDGE
DATA TRANSMIT— EXTERNAL CLOCK
SAMPLE
EDGE
tSCLKIW
DRIVE
EDGE
SAMPLE
EDGE
tSCLKW
TCLK
TCLK
tDFSE
tDFSI
tHOFSI
tSFSI
tHFSI
tHOFSE
TFS
tSFSE
TFS
tDDTI
tDDTE
tHDTE
tHDTI
DT
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE EDGE
DRIVE EDGE
TCLK /
RCLK
TCLK
(EXT)
tDDTTE
tDDTEN
DT
DRIVE
EDGE
TCLK
(INT)
DRIVE
EDGE
TCLK /
RCLK
tDDTIN
DT
Figure 27. Serial Ports
Rev. D |
Page 45 of 58 |
September 2015
tDDTTI
tHFSE
ADSP-21160M/ADSP-21160N
JTAG Test Access Port and Emulation
For JTAG Test Access Port and emulation, see Table 36 and
Figure 28.
Table 36. JTAG Test Access Port and Emulation
Parameter
Timing Requirements
tTCK
TCK Period
tSTAP
TDI, TMS Setup Before TCK High
tHTAP
TDI, TMS Hold After TCK High
tSSYS
System Inputs Setup Before TCK Low1
System Inputs Hold After TCK Low1
tHSYS
tTRSTW
TRST Pulsewidth
Min
Max
tCK
5
6
7
18
4tCK
Unit
ns
ns
ns
ns
ns
ns
Switching Characteristics
tDTDO
TDO Delay from TCK Low
tDSYS
System Outputs Delay After TCK Low2
13
30
1
ns
ns
System Inputs = DATA63–0, ADDR31–0, RDx, WRx, ACK, SBTS, HBR, HBG, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, IRQ2–0, FLAG3–0, PA, BRST, DR0, DR1,
TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, and RESET.
2
System Outputs = DATA63–0, ADDR31–0, MS3–0, RDx, WRx, ACK, PAGE, CLKOUT, HBG, REDY, DMAG1, DMAG2, BR6–1, PA, BRST, CIF, FLAG3–0, TIMEXP,
DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, and BMS.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 28. JTAG Test Access Port and Emulation
Rev. D |
Page 46 of 58 |
September 2015
tHSYS
ADSP-21160M/ADSP-21160N
OUTPUT DRIVE CURRENTS—ADSP-21160M
Figure 29 shows typical I–V characteristics for the output drivers of the ADSP-21160M. The curves represent the current
drive capability of the output drivers as a function of output
voltage.
120
% Peak IDD-INPEAK
% High IDD-INHIGH
% Low IDD-INLOW
+ % Peak IDD-IDLE
= IDDINT
SOURCE (VDDEXT) CURRENT –mA
100
VDDEXT = 3.47V, 0°C
80
VDDEXT = 3.3V, 25°C
60
VDDEXT = 3.13V,
85°C
40
20
0
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
–20
–40
• The number of output pins that switch during each
cycle (O)
VDDEXT = 3.47V, 0°C
–60
VDDEXT = 3.3V, 25°C
–80
• The maximum frequency at which they can switch (f)
VDDEXT = 3.13V,
85°C
–100
• Their load capacitance (C)
–120
0
0.5
1
1.5
2
2.5
SOURCE (VDDEXT) VOLTAGE – V
3
3.5
• Their voltage swing (VDD)
and is calculated by:
Figure 29. ADSP-21160M Typical Drive Currents
PEXT = O × C × VDD2 × f
OUTPUT DRIVE CURRENTS—ADSP-21160N
Figure 30 shows typical I–V characteristics for the output drivers of the ADSP-21160N. The curves represent the current drive
capability of the output drivers as a function of output voltage.
VDDEXT = 3.47V, –45°C
VDDEXT = 3.3V, 25°C
60
• A system with one bank of external data memory—
asynchronous RAM (64-bit)
40
VOH
20
• Four 64K × 16 RAM chips are used, each with a load
of 10 pF
VDDEXT = 3.11V, 115°C
0
• External data memory writes occur every other cycle, a rate
of 1/(2 tCK), with 50% of the pins switching
VDDEXT = 3.11V, 115°C
–20
VDDEXT = 3.3V, 25°C
VOL
• The bus cycle time is 50 MHz (tCK = 20 ns).
–40
The PEXT equation is calculated for each class of pins that
can drive, as shown in Table 38.
–60
VDDEXT = 3.47V, –45°C
–80
The load capacitance should include the processor’s package
capacitance (CIN). The switching frequency includes driving the
load high and then back low. Address and data pins can drive
high and low at a maximum rate of 1/(2tCK). The write strobe
can switch every cycle at a frequency of 1/tCK. Select pins switch
at 1/(2tCK), but selects can switch on each cycle.
Example for ADSP-21160N: Estimate PEXT with the following
assumptions:
80
SOURCE (VDDEXT) CURRENT – mA
Internal power dissipation is dependent on the instruction
execution sequence and the data operands involved. Using the
current specifications (IDD-INPEAK, IDD-INHIGH, IDD-INLOW, and
IDD-IDLE) from Electrical Characteristics—ADSP-21160M on
Page 16 and Electrical Characteristics—ADSP-21160N on
Page 18 and the current-versus-operation information in
Table 37, engineers can estimate the ADSP-21160x DSP’s
internal power supply (VDDINT) input current for a specific
application, according to the formula:
0
0.5
1
1.5
2
2.5
3
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
3.5
SWEEP (VDDEXT) VOLTAGE – V
PTOTAL = PEXT + PINT + PPLL
where:
Figure 30. ADSP-21160N Typical Drive Currents
• PEXT is from Table 38
POWER DISSIPATION
Total power dissipation has two components: one due to internal circuitry and one due to the switching of external output
drivers.
Rev. D |
Page 47 of 58 |
• PINT is IDDINT × 1.9 V, using the calculation IDDINT listed in
Power Dissipation on page 47
• PPLL is AIDD × 1.9 V, using the value for AIDD listed in Electrical Characteristics—ADSP-21160M on Page 16 and
Electrical Characteristics—ADSP-21160N on Page 18
September 2015
ADSP-21160M/ADSP-21160N
Table 37. ADSP-21160x Operation Types vs. Input Current
Operation
Instruction Type
Instruction Fetch
Core Memory Access2
Internal Memory DMA
External Memory DMA
Data Bit Pattern for Core
Memory Access and DMA
1
2
Peak Activity1
Multifunction
Cache
2 per tCK Cycle
(DM 3 64 and PM 3 64)
1 per 2 tCCLK Cycles
1 per External Port Cycle (364)
Worst Case
High Activity1
Multifunction
Internal Memory
1 per tCK Cycle
(DM 3 64)
1 per 2 tCCLK Cycles
1 per External Port Cycle (3 64)
Random
Low Activity1
Single Function
Internal Memory
None
None
None
N/A
Peak activity = IDD-INPEAK, high activity = IDD-INHIGH, and low activity = IDD-INLOW. The state of the PEYEN bit (SIMD versus SISD mode) does not influence these calculations.
These assume a 2:1 core clock ratio. For more information on ratios and clocks (tCK and tCCLK), see the timing ratio definitions on page 20.
Table 38. External Power Calculations (ADSP-21160N Example)
Pin Type
Address
MS0
WRx
Data
CLKOUT
No. of Pins
15
1
2
64
1
% Switching
50
0
50
×C
× 44.7 pF
× 44.7 pF
× 44.7 pF
× 14.7 pF
× 4.7 pF
× VDD2
× 10.9 V
× 10.9 V
× 10.9 V
× 10.9 V
× 10.9 V
×f
× 24 MHz
× 24 MHz
× 24 MHz
× 24 MHz
× 48 MHz
PEXT
Note that the conditions causing a worst-case PEXT are different
from those causing a worst-case PINT. Maximum PINT cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching
simultaneously.
TEST CONDITIONS
= PEXT
= 0.088 W
= 0.000 W
= 0.023 W
= 0.123 W
= 0.003 W
= 0.237 W
voltage decaysV from the measured output high or output low
voltage. tDECAY is calculated with test loads CL and IL, and with
V equal to 0.5 V.
REFERENCE
SIGNAL
The test conditions for timing parameters appearing in
ADSP-21160x specifications on page 17 include output disable
time, output enable time, and capacitive loading.
tMEASURED
tDIS
tENA
VOH (MEASURED)
Output Disable Time
Output pins are considered to be disabled when they stop driving, go into a high-impedance state, and start to decay from
their output high or low voltage. The time for the voltage on the
bus to decay by V is dependent on the capacitive load, CL and
the load current, IL. This decay time can be approximated by the
following equation:
VOH (MEASURED) – $V 2.0V
VOL (MEASURED)
tDECAY = (CLV)/IL
Page 48 of 58 |
tDECAY
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS VOLTAGE
TO BE APPROXIMATELY 1.5V
The output disable time tDIS is the difference between tMEASURED
and tDECAY as shown in Figure 31. The time tMEASURED is the interval from when the reference signal switches to when the output
Rev. D |
VOL (MEASURED) + $V 1.0V
Figure 31. Output Enable/Disable
September 2015
ADSP-21160M/ADSP-21160N
Output Enable Time
Capacitive Loading
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start driving. The output enable time tENA is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the output enable/disable diagram (Figure 31). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 32). Figure 34, Figure 35, Figure 37,
and Figure 38 show how output rise time varies with capacitance. Figure 36 and Figure 39 graphically show how output
delays and holds vary with load capacitance. (Note that this
graph or derating does not apply to output disable delays; see
Output Disable Time on Page 48.) The graphs of Figure 34
through Figure 39 may not be linear outside the ranges shown.
Example System Hold Time Calculation
506
TO
OUTPUT
PIN
30
25
RISE AND FALL TIMES – ns
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose V
to be the difference between the ADSP-21160x DSP’s output
voltage and the input threshold for the device requiring the hold
time. A typical V will be 0.4 V. CL is the total bus capacitance
(per data line), and IL is the total leakage or three-state current
(per data line). The hold time will be tDECAY plus the minimum
disable time (i.e., tDATRWH for the write cycle).
RISE TIME
20
Y = 0.086687X + 2.18
15
FALL TIME
10
Y = 0.072781X + 1.99
5
1.5V
0
0
50
100
150
200
LOAD CAPACITANCE – pF
30pF
Figure 32. Equivalent Device Loading for AC Measurements (Includes All
Fixtures)
Figure 34. ADSP-21160M Typical Output Rise Time (10%–90%, VDDEXT = Max)
vs. Load Capacitance
25
1.5V
20
1.5V
Figure 33. Voltage Reference Levels for AC Measurements (Except Output
Enable/Disable)
RISE AND FALL TIMES – ns
INPUT
OR
OUTPUT
RISE TIME
Y = 0.0813x + 2.312
15
TBD
FALL TIME
10
Y = 0.0834x + 1.0653
5
0
0
50
100
150
LOAD CAPACITANCE – pF
200
250
Figure 35. ADSP-21160M Typical Output Rise Time (10%–90%, VDDEXT = Min)
vs. Load Capacitance
Rev. D |
Page 49 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
25
15
RISE AND FALL TIMES – ns
OUTPUT DELAY OR HOLD – ns
20
10
Y = 0.085526X – 3.87
5
20
RISE TIME
Y = 0.0813x + 2.312
15
FALL TIME
10
Y = 0.0834x + 1.0653
5
0
0
–5
0
50
100
150
0
50
100
150
LOAD CAPACITANCE – pF
200
200
LOAD CAPACITANCE – pF
Figure 36. ADSP-21160M Typical Output Delay or Hold vs. Load Capacitance
(at Max Case Temperature)
Figure 38. ADSP-21160N Typical Output Rise Time (20%–80%, VDDEXT = Min)
vs. Load Capacitance
12
10
OUTPUT DELAY OR HOLD – ns
20
18
RISE AND FALL TIMES – ns
16
RISE TIME
14
Y = 0.0716x + 2.9043
12
10
8
FALL TIME
6
Y = 0.0751x + 1.4882
4
8
6
4
Y = 0.0716x – 3.9037
2
0
–2
–4
0
2
50
100
150
200
LOAD CAPACITANCE – pF
0
0
50
100
150
200
Figure 39. ADSP-21160N Typical Output Delay or Hold vs. Load Capacitance
(at Max Case Temperature)
LOAD CAPACITANCE – pF
Figure 37. ADSP-21160N Typical Output Rise Time (20%–80%, VDDEXT = Max)
vs. Load Capacitance
Rev. D |
Page 50 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
ENVIRONMENTAL CONDITIONS
Thermal Characteristics
The ADSP-21160x DSPs are provided in a 400-Ball PBGA (Plastic Ball Grid Array) package.
The ADSP-21160x is specified for a case temperature (TCASE).
To ensure that the TCASE data sheet specification is not exceeded,
a heatsink and/or an air flow source may be used. Use the centerblock of ground pins (for ADSP-21160M, PBGA balls:
H8-13, J8-13, K8-13, L8-13, M8-13, N8-13; for ADSP-21160N,
PBGA balls: F7-14, G7-14, H7-14, J7-14, K7-14, L7-14, M-14,
N7-14, P7-14, R7-15) to provide thermal pathways to the
printed circuit board’s ground plane. A heatsink should be
attached to the ground plane (as close as possible to the thermal
pathways) with a thermal adhesive.
T CASE = T AMB + PD CA
• TCASE = Case temperature (measured on top surface
of package)
• TAMB = Ambient temperature °C
• PD = Power dissipation in W (this value depends upon the
specific application; a method for calculating PD is shown
under Power Dissipation).
• CA = Value from Table 39.
• JB = 6.46°C/W
Table 39. Airflow Over Package Versus CA
Airflow (Linear Ft./Min.)
CA (°C/W)1
1
0
12.13
200
9.86
400
8.7
JC = 3.6 °C/W
Rev. D |
Page 51 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
400-BALL PBGA PIN CONFIGURATIONS
Table 40 lists the pin assignments for the PBGA package, and
the pin configurations diagram in Figure 40 (ADSP-21160M)
and Figure 41 (ADSP-21160N) show the pin assignment
summary.
Table 40. 400-Ball PBGA Pin Assignments
Pin Name
DATA[14]
DATA[13]
DATA[10]
DATA[8]
DATA[4]
DATA[2]
TDI
TRST
RESET
RPBA
IRQ0
FLAG1
TIMEXP
NC1
NC
TFS1
RFS1
RCLK0
DT0
L0DAT[4]
DATA[30]
DATA[29]
DATA[23]
DATA[21]
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
GND
VDDINT
VDDINT
VDDINT
VDDINT
VDDEXT
L1DAT[6]
L1DAT[5]
L1ACK
L1DAT[1]
Pin No.
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
E01
E02
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
Pin Name
DATA[22]
DATA[16]
DATA[15]
DATA[9]
DATA[6]
DATA[3]
DATA[0]
TCK
EMU
IRQ2
FLAG3
FLAG0
NC1
NC
DT1
RCLK1
RFS0
TCLK0
L0DAT[5]
L0DAT[2]
DATA[34]
DATA[33]
DATA[27]
DATA[26]
VDDEXT
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
L1DAT[4]
L1DAT[3]
L1DAT[0]
L2DAT[7]
(See Footnotes 1 and 2)
Pin No.
Pin Name
B01
DATA[24]
B02
DATA[18]
B03
DATA[17]
B04
DATA[11]
B05
DATA[7]
B06
DATA[5]
B07
DATA[1]
B08
TMS
B09
TD0
B10
IRQ1
B11
FLAG2
B12
NC1
B13
NC
B14
TCLK1
B15
DR1
B16
DR0
B17
L0DAT[7]
B18
L0DAT[6]
B19
L0ACK
B20
L0DAT[0]
F01
DATA[38]
F02
DATA[35]
F03
DATA[32]
F04
DATA[31]
F05
VDDEXT
F06
VDDINT
F07
GND
F08
GND
F09
GND
F10
GND
F11
GND
F12
GND
F13
GND
F14
GND
F15
VDDINT
F16
VDDEXT
F17
L1DAT[2]
F18
L2DAT[6]
F19
L2DAT[4]
F20
L2CLK
Rev. D |
Page 52 of 58 |
September 2015
Pin No.
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
G01
G02
G03
G04
G05
G06
G07
G08
G09
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
Pin Name
DATA[28]
DATA[25]
DATA[20]
DATA[19]
DATA[12]
VDDEXT
VDDINT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDEXT
TFS0
L1DAT[7]
L0CLK
L0DAT[3]
L0DAT[1]
L1CLK
DATA[40]
DATA[39]
DATA[37]
DATA[36]
VDDEXT
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
L2DAT[5]
L2ACK
L2DAT[3]
L2DAT[1]
Pin No.
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
H01
H02
H03
H04
H05
H06
H07
H08
H09
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
ADSP-21160M/ADSP-21160N
Table 40. 400-Ball PBGA Pin Assignments (Continued)
Pin Name
DATA[44]
DATA[43]
DATA[42]
DATA[41]
VDDEXT
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
L2DAT[2]
L2DAT[0]
HBG
HBR
NC
NC
DATA[48]
DATA[51]
VDDEXT
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
L3DAT[5]
L3DAT[6]
L3DAT[4]
L3CLK
DATA[61]
DATA[62]
ADDR[3]
ADDR[2]
VDDEXT
VDDEXT
Pin No.
J01
J02
J03
J04
J05
J06
J07
J08
J09
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
N01
N02
N03
N04
N05
N06
N07
N08
N09
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
U01
U02
U03
U04
U05
U06
Pin Name
CLK_CFG_0
DATA[46]
DATA[45]
DATA[47]
VDDEXT
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
BR6
BR5
BR4
BR3
DATA[49]
DATA[50]
DATA[52]
DATA[55]
VDDEXT
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
L3DAT[2]
L3DAT[1]
L3DAT[3]
L3ACK
ADDR[4]
ADDR[6]
ADDR[7]
ADDR[10]
ADDR[14]
ADDR[18]
(See Footnotes 1 and 2)
Pin No.
Pin Name
K01
CLKIN
K02
CLK_CFG_1
K03
AGND
K04
CLK_CFG_2
K05
VDDEXT
K06
VDDINT
K07
GND
K08
GND
K09
GND
K10
GND
K11
GND
K12
GND
K13
GND
K14
GND
K15
VDDINT
K16
VDDEXT
K17
BR2
K18
BR1
K19
ACK
K20
REDY
P01
DATA[53]
P02
DATA[54]
P03
DATA[57]
P04
DATA[60]
P05
VDDEXT
P06
VDDINT
P07
GND
P08
GND
P09
GND
P10
GND
P11
GND
P12
GND
P13
GND
P14
GND
P15
GND
P16
VDDEXT
P17
L4DAT[5]
P18
L4DAT[6]
P19
L4DAT[7]
P20
L3DAT[0]
V01
ADDR[5]
V02
ADDR[9]
V03
ADDR[12]
V04
ADDR[15]
V05
ADDR[17]
V06
ADDR[20]
Rev. D |
Page 53 of 58 |
September 2015
Pin No.
L01
L02
L03
L04
L05
L06
L07
L08
L09
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
R01
R02
R03
R04
R05
R06
R07
R08
R09
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
W01
W02
W03
W04
W05
W06
Pin Name
AVDD
CLK_CFG_3
CLKOUT
NC2
VDDEXT
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
PAGE
SBTS
PA
L3DAT[7]
DATA[56]
DATA[58]
DATA[59]
DATA[63]
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDEXT
L4DAT[3]
L4ACK
L4CLK
L4DAT[4]
ADDR[8]
ADDR[11]
ADDR[13]
ADDR[16]
ADDR[19]
ADDR[21]
Pin No.
M01
M02
M03
M04
M05
M06
M07
M08
M09
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
T01
T02
T03
T04
T05
T06
T07
T08
T09
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
Y01
Y02
Y03
Y04
Y05
Y06
ADSP-21160M/ADSP-21160N
Table 40. 400-Ball PBGA Pin Assignments (Continued)
Pin Name
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
L5DAT[7]
L4DAT[0]
L4DAT[1]
L4DAT[2]
1
2
Pin No.
U07
U08
U09
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
Pin Name
ADDR[22]
ADDR[25]
ADDR[28]
ID0
ADDR[1]
MS1
CS
RDL
DMAR2
L5DAT[0]
L5DAT[2]
L5ACK
L5DAT[4]
L5DAT[6]
(See Footnotes 1 and 2)
Pin No.
Pin Name
V07
ADDR[23]
V08
ADDR[26]
V09
ADDR[29]
V10
ID1
V11
ADDR[0]
V12
BMS
V13
MS2
V14
CIF
V15
RDH
V16
DMAG2
V17
LBOOT
V18
L5DAT[1]
V19
L5DAT[3]
V20
L5DAT[5]
Pin No.
W07
W08
W09
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Pin Name
ADDR[24]
ADDR[27]
ADDR[30]
ADDR[31]
ID2
BRST
MS0
MS3
WRH
WRL
DMAG1
DMAR1
EBOOT
L5CLK
For ADSP-21160M, Pin Name and function is defined as VDDEXT. For ADSP-21160N, Pin Name and function is defined as No Connect (NC).
For ADSP-21160M, Pin Name and function is defined as GND. For ADSP-21160N, Pin Name and function is defined as No Connect (NC).
Rev. D |
Page 54 of 58 |
September 2015
Pin No.
Y07
Y08
Y09
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
ADSP-21160M/ADSP-21160N
20
18
19
16
17
14
15
12
13
10
11
8
9
6
7
4
5
2
3
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
KEY:
1
VDDINT
GND
VDDEXT
AGND
AVDD
I/O SIGNALS
NO CONNECTION
1 USE THE CENTER BLOCK OF GROUND PINS (PBGA BALLS: H8-13, J8-13, K8-13, L8-13,
M8-13, N8-13) TO PROVIDE THERMAL PATHWAYS TO YOUR PRINTED CIRCUIT BOARD’S
GROUND PLANE.
Figure 40. ADSP-21160M 400-Ball PBGA Pin Configurations (Bottom View, Summary)
Rev. D |
Page 55 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
20
18
19
16
17
14
15
12
13
10
11
8
9
6
7
4
5
2
3
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
KEY:
1
VDDINT
GND
VDDEXT
AGND
AVDD
I/O SIGNALS
NO CONNECTION
1 USE THE CENTER BLOCK OF GROUND PINS (PBGA BALLS: F7-14, G7-14, H7-14, J7-14,
K7-14, L7-14, M7-14, N7-14, P7-14, R7-15) TO PROVIDE THERMAL PATHWAYS TO YOUR
PRINTED CIRCUIT BOARD’S GROUND PLANE.
Figure 41. ADSP-21160N 400-Ball PBGA Pin Configurations (Bottom View, Summary)
Rev. D |
Page 56 of 58 |
September 2015
ADSP-21160M/ADSP-21160N
OUTLINE DIMENSIONS
The ADSP-21160x processors are available in a
27 mm × 27 mm, 400-ball PBGA lead-free package.
BALL A1 PAD CORNER
27.20
27.00 SQ
26.80
20 18 16 14 12 10 8 6 4 2
19 17 15 13 11 9 7 5 3 1
BALL A1
INDICATOR
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
24.13
BSC
SQ
1.27
BSC
BOTTOM VIEW
TOP VIEW
2.49
2.32
2.15
1.19
1.17
1.15
0.60
0.55
0.50
DETAIL A
SEATING
PLANE
0.70
0.60
0.50
0.90
0.75
0.60
BALL DIAMETER
0.20 MAX
COPLANARITY
DETAIL A
Figure 42. 400-Ball Plastic Grid Array (PBGA) (B-400) Compliant to JEDEC Standards MS-034-BAL-2 (Dimensions in Millimeters)
SURFACE-MOUNT DESIGN
The following table is provided as an aide to PCB design.
For industry-standard design recommendations, refer to
IPC-7351, Generic Requirements for Surface-Mount Design
and Land Pattern Standard.
Package
400-Ball Grid Array (PBGA)
Ball Attach Type
Solder Mask Defined (SMD)
Rev. D |
Solder Mask Opening
0.63 mm diameter
Page 57 of 58 |
September 2015
Ball Pad Size
0.76 mm diameter
ADSP-21160M/ADSP-21160N
ORDERING GUIDE
Model
ADSP-21160MKBZ-80
ADSP-21160MKB-80
ADSP-21160NCBZ-100
ADSP-21160NCB-100
ADSP-21160NKBZ-100
1
Notes
1
1
1
Temperature Range
0°C to +85°C
0°C to +85°C
–40°C to +100°C
–40°C to +100°C
0°C to +85°C
Instruction
Rate
80 MHz
80 MHz
100 MHz
100 MHz
100 MHz
On-Chip
SRAM
4M bits
4M bits
4M bits
4M bits
4M bits
Package Description
400-Ball Plastic Ball Grid Array (PBGA)
400-Ball Plastic Ball Grid Array (PBGA)
400-Ball Plastic Ball Grid Array (PBGA)
400-Ball Plastic Ball Grid Array (PBGA)
400-Ball Plastic Ball Grid Array (PBGA)
Z = RoHS Compliant Part.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02426-0-9/15(D)
Rev. D |
Page 58 of 58 |
September 2015
Package
Option
B-400
B-400
B-400
B-400
B-400
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