ADSP-21367

a SUMMARY SHARC® Processors ADSP-21367/ADSP-21368/ADSP-21369 Code compatible with all other members of the SHARC family The ADSP-21367/ADSP-21368/ADSP-21369 are available with a 333 MHz core instruction rate with unique audiocentric peripherals such as the digital audio interface, S/PDIF transceiver, serial ports, 8-channel asynchronous sample rate converter, precision clock generators, and more. For complete ordering information, see Ordering Guide on Page 56. High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Single-instruction, multiple-data (SIMD) computational architecture On-chip memory—2M bit of on-chip SRAM and 6M bit of onchip mask programmable ROM CORE PROCESSOR TIMER INSTRUCTION CACHE 32 × 48-BIT JTAG TEST & EMULATION 4 BLOCK OF ON-CHIP MEMORY 2M BIT RAM 6M BIT ROM FLAGS4-15 PWM 32 DATA CONTROL PINS DAG1 8 × 4 × 32 DAG2 8 × 4 × 32 PROGRAM SEQUENCER ADDR DATA EXTERNAL PORT SDRAM CONTROLLER 7 18 PM ADDRESS BUS DM ADDRESS BUS 32 32 PM DATA BUS 64 ASYNCHRONOUS MEMORY INTERFACE SHARED MEMORY INTERFACE IOA(24) IOD(32) 3 CONTROL 24 ADDRESS 8 DM DATA BUS 64 PROCESSING ELEMENT (PEX) PROCESSING ELEMENT (PEY) PX REGISTER IOP REGISTER (MEMORY MAPPED) CONTROL, STATUS, & DATA BUFFERS DMA CONTROLLER 34 CHANNELS MEMORY-TOMEMORY DMA (2) DAI ROUTING UNIT 4 PRECISION CLOCK GENERATORS (4) GPIO FLAGS/ IRQ/TIMEXP SRC (8 CHANNELS) SERIAL PORTS (8) INPUT DATA PORT/ PDAP DAI PINS SPI PORT (2) TWO WIRE INTERFACE DPI PINS DPI ROUTING UNIT UART (2) S SPDIF (Rx/Tx) TIMERS (3) DIGITAL AUDIO INTERFACE 20 DIGITAL PERIPHERAL INTERFACE I/O PROCESSOR 14 Figure 1. Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADSP-21367/ADSP-21368/ADSP-21369 KEY FEATURES—PROCESSOR CORE At 333 MHz (3 ns) core instruction rate, the processors perform 2 GFLOPS/666 MMACS 2M bit on-chip, SRAM (0.75M bit in blocks 0 and 1, and 0.25M bit in blocks 2 and 3) for simultaneous access by the core processor and DMA 6M bit on-chip, mask-programmable ROM (3M bit in block 0 and 3M bit in block 1) Dual data address generators (DAGs) with modulo and bitreverse addressing Zero-overhead looping with single-cycle loop setup, providing efficient program sequencing Single-instruction, multiple-data (SIMD) architecture provides: Two computational processing elements Concurrent execution Code compatibility with other SHARC family members at the assembly level Parallelism in buses and computational units allows: single cycle executions (with or without SIMD) of a multiply operation, an ALU operation, a dual memory read or write, and an instruction fetch Transfers between memory and core at a sustained 6.4G bytes/s bandwidth at 333 MHz core instruction rate Digital audio interface (DAI) includes eight serial ports, four precision clock generators, an input data port, an S/PDIF transceiver, an 8-channel asynchronous sample rate converter, and a signal routing unit Digital peripheral interface (DPI) includes three timers, two UARTs, two SPI ports, and a two wire interface port Outputs of PCG's C and D can be driven on to DPI pins Eight dual data line serial ports that operate at up to 50M bits/s on each data line—each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair TDM support for telecommunications interfaces including 128 TDM channel support for newer telephony interfaces such as H.100/H.110 Up to 16 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port, configurable as eight channels of serial data or seven channels of serial data and up to a 20-bit wide parallel data channel Signal routing unit provides configurable and flexible connections between all DAI/DPI components 2 muxed flag/IRQ lines 1 muxed flag/timer expired line /MS pin 1 muxed flag/IRQ /MS pin INPUT/OUTPUT FEATURES DMA controller supports: 34 zero-overhead DMA channels for transfers between internal memory and a variety of peripherals 32-bit DMA transfers at peripheral clock speed, in parallel with full-speed processor execution 32-bit wide external port provides glueless connection to both synchronous (SDRAM) and asynchronous memory devices Programmable wait state options: 2 SCLK to 31 SCLK cycles Delay-line DMA engine maintains circular buffers in external memory with tap/offset-based reads SDRAM accesses at 133 MHz and asynchronous accesses at 66 MHz Shared-memory support allows multiple DSPs to automatically arbitrate for the bus and gluelessly access a common memory device Shared memory interface (ADSP-21368 only) support provides: Glueless connection for scalable DSP multiprocessing architecture Distributed on-chip bus arbitration for parallel bus Connect of up to four ADSP-21368 processors and global memory Four memory select lines allow multiple external memory devices DEDICATED AUDIO COMPONENTS S/PDIF-compatible digital audio receiver/transmitter supports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards Left-justified, I2S, or right-justified serial data input with 16-, 18-, 20- or 24-bit word widths (transmitter) Four independent asynchronous sample rate converters (SRC). Each converter has separate serial input and output ports, a de-emphasis filter providing up to –140 dB SNR performance, stereo sample rate converter (SRC) and supports left-justified, I2S, TDM, and right-justified modes and 24, 20, 18, and 16 audio data word lengths Pulse-width modulation provides: 16 PWM outputs configured as four groups of four outputs supports center-aligned or edge-aligned PWM waveforms ROM-based security features include: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multiplier/divider ratios Dual voltage: 3.3 V I/O, 1.2 V or 1.3 V core Available in 256-ball SBGA and 208-lead MQFP packages (see Ordering Guide on Page 56) Rev. A | Page 2 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 TABLE OF CONTENTS Summary ................................................................1 Key Features—Processor Core ..................................2 Input/Output Features ............................................2 Dedicated Audio Components ..................................2 General Description ..................................................4 Core Architecture ..................................................4 Memory Architecture .............................................5 External Memory ...................................................5 Input/Output Features ............................................7 System Design .......................................................9 Development Tools .............................................. 10 Additional Information ......................................... 11 Pin Function Descriptions ........................................ 12 Data Modes ........................................................ 15 Boot Modes ........................................................ 15 Core Instruction Rate to CLKIN Ratio Modes ............. 15 Specifications ......................................................... 16 Operating Conditions ........................................... 16 Electrical Characteristics ........................................ 17 Package Information ............................................ 18 Maximum Power Dissipation ................................. 18 Absolute Maximum Ratings ................................... 18 ESD Sensitivity .................................................... 18 Timing Specifications ........................................... 19 Output Drive Currents .......................................... 47 Test Conditions ................................................... 47 Capacitive Loading ............................................... 47 Thermal Characteristics ........................................ 48 256-Ball SBGA Pinout .............................................. 49 208-Lead MQFP Pinout ............................................ 52 Package Dimensions ................................................ 54 Surface-Mount Design .......................................... 55 Ordering Guide ...................................................... 56 Rev. A | Page 3 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 GENERAL DESCRIPTION The ADSP-21367/ADSP-21368/ADSP-21369 SHARC processors are members of the SIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. These processors are source code-compatible with the ADSP-2126x and ADSP-2116x DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. The processors are 32-bit/40-bit floating point processors optimized for high performance automotive audio applications with its large on-chip SRAM, and mask-programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital audio interface (DAI). As shown in the functional block diagram on Page 1, the processors use two computational units to deliver a significant performance increase over the previous SHARC processors on a range of DSP algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the ADSP-21367/ADSP-21368/ ADSP-21369 processors achieve an instruction cycle time of up to 3.0 ns at 333 MHz. With its SIMD computational hardware, the processors can perform two GFLOPS running at 333 MHz. Table 1 shows performance benchmarks for these devices. Table 1. Processor Benchmarks (at 333 MHz) Benchmark Algorithm 1024 Point Complex FFT (Radix 4, with reversal) FIR Filter (per tap)1 IIR Filter (per biquad)1 Matrix Multiply (pipelined) [3×3] × [3×1] [4×4] × [4×1] Divide (y/×) Inverse Square Root 1 • On-chip mask-programmable ROM (6M bit) • JTAG test access port The block diagram of the ADSP-21368 on Page 1 also illustrates the following architectural features: • DMA controller • Eight full-duplex serial ports • Digital audio interface that includes four precision clock generators (PCG), an input data port (IDP), an S/PDIF receiver/transmitter, eight channels asynchronous sample rate converters, eight serial ports, eight serial interfaces, a 16-bit parallel input port (PDAP), a flexible signal routing unit (DAI SRU). • Digital peripheral interface that includes three timers, an I2C® interface, two UARTs, two serial peripheral interfaces (SPI), and a flexible signal routing unit (DPI SRU). CORE ARCHITECTURE The ADSP-21367/ADSP-21368/ADSP-21369 are code compatible at the assembly level with the ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-21367/ADSP-21368/ ADSP-21369 share architectural features with the ADSP-2126x and ADSP-2116x SIMD SHARC processors, as detailed in the following sections. Speed (at 333 MHz) 27.9 μs 1.5 ns 6.0 ns 13.5 ns 23.9 ns 10.5 ns 16.3 ns SIMD Computational Engine The processors contain two computational processing elements that operate as a single-instruction, multiple-data (SIMD) engine. The processing elements are referred to as PEX and PEY and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY may be enabled by setting the PEYEN mode bit in the MODE1 register. When this mode is enabled, the same instruction is executed in both processing elements, but each processing element operates on different data. This architecture is efficient at executing math intensive DSP algorithms. Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each access of memory or the register file. Assumes two files in multichannel SIMD mode. The ADSP-21367/ADSP-21368/ADSP-21369 continues SHARC’s industry-leading standards of integration for DSPs, combining a high performance 32-bit DSP core with integrated, on-chip system features. The block diagram of the ADSP-21368 on Page 1, illustrates the following architectural features: • Two processing elements, each of which comprises an ALU, multiplier, shifter, and data register file • Data address generators (DAG1, DAG2) • Program sequencer with instruction cache • PM and DM buses capable of supporting four 32-bit data transfers between memory and the core at every core processor cycle • Three programmable interval timers with PWM generation, PWM capture/pulse width measurement, and external event counter capabilities • On-chip SRAM (2M bit) Rev. A | Independent, Parallel Computation Units Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all operations in a single cycle. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel Page 4 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit singleprecision floating-point, 40-bit extended precision floatingpoint, and 32-bit fixed-point data formats. MEMORY ARCHITECTURE The ADSP-21367/ADSP-21368/ADSP-21369 processors add the following architectural features to the SIMD SHARC family core. Data Register File A general-purpose data register file is contained in each processing element. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the ADSP-2136x enhanced Harvard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0–S15. On-Chip Memory The processors contain two megabits of internal RAM and six megabits of internal mask-programmable ROM. Each block can be configured for different combinations of code and data storage (see Table 2 on Page 6). Each memory block supports single-cycle, independent accesses by the core processor and I/O processor. The memory architecture, in combination with its separate on-chip buses, allow two data transfers from the core and one from the I/O processor, in a single cycle. The SRAM can be configured as a maximum of 64K words of 32-bit data, 128K words of 16-bit data, 42K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to two megabits. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Using the DM bus and PM buses, with one bus dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. Single-Cycle Fetch of Instruction and Four Operands The ADSP-21367/ADSP-21368/ADSP-21369 feature an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data (see Figure 1 on Page 1). With separate program and data memory buses and on-chip instruction cache, the processors can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. Instruction Cache The processors include an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full-speed execution of core, looped operations such as digital filter multiply-accumulates, and FFT butterfly processing. Data Address Generators with Zero-Overhead Hardware Circular Buffer Support The ADSP-21367/ADSP-21368/ADSP-21369 have two data address generators (DAGs). The DAGs are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any memory location. EXTERNAL MEMORY The external port provides a high performance, glueless interface to a wide variety of industry-standard memory devices. The 32-bit wide bus may be used to interface to synchronous and/or asynchronous memory devices through the use of its separate internal memory controllers. The first is an SDRAM controller for connection of industry-standard synchronous DRAM devices and DIMMs (Dual Inline Memory Module), while the second is an asynchronous memory controller intended to interface to a variety of memory devices. Four memory select pins enable up to four separate devices to coexist, supporting any desired combination of synchronous and asynchronous device types. NonSDRAM external memory address space is shown in Table 3. SDRAM Controller The SDRAM controller provides an interface of up to four separate banks of industry-standard SDRAM devices or DIMMs, at speeds up to fSCLK. Fully compliant with the SDRAM standard, each bank has its own memory select line (MS0–MS3), and can be configured to contain between 16M bytes and 128M bytes of memory. SDRAM external memory address space is shown in Table 4. Flexible Instruction Set The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the ADSP-21367/ADSP-21368/ADSP-21369 can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetching up to four 32-bit values from memory—all in a single instruction. Rev. A | Page 5 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Table 2. Internal Memory Space 1 IOP Registers 0x0000 0000–0x0003 FFFF Long Word (64 Bits) BLOCK 0 ROM (Reserved) 0x0004 0000–0x0004 BFFF Reserved 0x0004 F000–0x0004 FFFF BLOCK 0 SRAM 0x0004 C000–0x0004 EFFF BLOCK 1 ROM (Reserved) 0x0005 0000–0x0005 BFFF Reserved 0x0005 F000–0x0005 FFFF BLOCK 1 SRAM 0x0005 C000–0x0005 EFFF BLOCK 2 SRAM 0x0006 0000–0x0006 0FFF Reserved 0x0006 1000– 0x0006 FFFF BLOCK 3 SRAM 0x0007 0000–0x0007 0FFF Reserved 0x0007 1000–0x0007 FFFF 1 Extended Precision Normal or Instruction Word (48 Bits) BLOCK 0 ROM (Reserved) 0x0008 0000–0x0008 FFFF Reserved 0x0009 4000–0x0009 FFFF BLOCK 0 SRAM 0x0009 0000–0x0009 3FFF BLOCK 1 ROM (Reserved) 0x000A 0000–0x000A FFFF Reserved 0x000B 4000–0x000B FFFF BLOCK 1 SRAM 0x000B 0000–0x000B 3FFF BLOCK 2 SRAM 0x000C 0000–0x000C 1554 Reserved 0x000C 1555–0x000C 3FFF BLOCK 3 SRAM 0x000E 0000–0x000E 1554 Reserved 0x000E 1555–0x000F FFFF Normal Word (32 Bits) BLOCK 0 ROM (Reserved) 0x0008 0000–0x0009 7FFF Reserved 0x0009 E000–0x0009 FFFF BLOCK 0 SRAM 0x0009 8000–0x0009 DFFF BLOCK 1 ROM (Reserved) 0x000A 0000–0x000B 7FFF Reserved 0x000B E000–0x000B FFFF BLOCK 1 SRAM 0x000B 8000–0x000B DFFF BLOCK 2 SRAM 0x000C 0000–0x000C 1FFF Reserved 0x000C 2000–0x000D FFFF BLOCK 3 SRAM 0x000E 0000–0x000E 1FFF Reserved 0x000E 2000–0x000F FFFF Short Word (16 Bits) BLOCK 0 ROM (Reserved) 0x0010 0000–0x0012 FFFF Reserved 0x0013 C000–0x0013 FFFF BLOCK 0 SRAM 0x0013 0000–0x0013 BFFF BLOCK 1 ROM (Reserved) 0x0014 0000–0x0016 FFFF Reserved 0x0017 C000–0x0017 FFFF BLOCK 1 SRAM 0x0017 0000–0x0017 BFFF BLOCK 2 SRAM 0x0018 0000–0x0018 3FFF Reserved 0x0018 4000–0x001B FFFF BLOCK 3 SRAM 0x001C 0000–0x001C 3FFF Reserved 0x001C 4000–0x001F FFFF The ADSP-21368 and ADSP-21369 processors include a customer-definable ROM block. Please contact your Analog Devices sales representative for additional details. The controller maintains all of the memory banks as a contiguous address space so that the processor sees this as a single address space, even if different size devices are used in the different banks. A set of programmable timing parameters is available to configure the SDRAM banks to support slower memory devices. The memory banks can be configured as either 32 bits wide for maximum performance and bandwidth or 16 bits wide for minimum device count and lower system cost. The SDRAM controller address, data, clock, and control pins can drive loads up to 30 pF. For larger memory systems, the SDRAM controller external buffer timing should be selected and external buffering should be provided so that the load on the SDRAM controller pins does not exceed 30 pF. Table 3. External Memory for NonSDRAM Addresses Size in Words 14M 16M 16M 16M Table 4. External Memory for SDRAM Addresses Size in Words 62M 64M 64M 64M Bank Bank 0 Bank 1 Bank 2 Bank 3 Address Range 0x0020 0000 – 0x03FF FFFF 0x0400 0000 – 0x07FF FFFF 0x0800 0000 – 0x0BFF FFFF 0x0C00 0000 – 0x0FFF FFFF Asynchronous Controller The asynchronous memory controller provides a configurable interface for up to four separate banks of memory or I/O devices. Each bank can be independently programmed with different timing parameters, enabling connection to a wide variety of memory devices including SRAM, ROM, flash, and EPROM, as well as I/O devices that interface with standard memory control lines. Bank 0 occupies a 14M word window and banks 1, 2, and 3 occupy a 16M word window in the processor’s address space but, if not fully populated, these windows are not made contiguous by the memory controller logic. The banks can also be configured as 8-bit, 16-bit, or 32-bit wide buses for ease of interfacing to a range of memories and I/O devices tailored either to high performance or to low cost and power. Bank Bank 0 Bank 1 Bank 2 Bank 3 Address Range 0x0020 0000 – 0x00FF FFFF 0x0400 0000 – 0x04FF FFFF 0x0800 0000 – 0x08FF FFFF 0x0C00 0000 – 0x0CFF FFFF Rev. A | Page 6 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 The asynchronous memory controller is capable of a maximum throughput of 264M bytes/s using a 66 MHz external bus speed. Other features include 8-bit to 32-bit and 16-bit to 32-bit packing and unpacking, booting from bank select 1, and support for delay line DMA. the SPI interface, two for the external port, and two for memory-to-memory transfers. Programs can be downloaded to the processors using DMA transfers. Other DMA features include interrupt generation upon completion of DMA transfers, and DMA chaining for automatic linked DMA transfers. Delay Line DMA The ADSP-21367/ADSP-21368/ADSP-21369 processors provide delay line DMA functionality. This allows processor reads and writes to external delay line buffers (in external memory, SRAM, or SDRAM) with limited core interaction. Shared External Memory The ADSP-21368 processor supports connecting to common shared external memory with other ADSP-21368 processors to create shared external bus processor systems. This support includes: • Distributed, on-chip arbitration for the shared external bus • Fixed and rotating priority bus arbitration • Bus time-out logic • Bus lock Multiple processors can share the external bus with no additional arbitration logic. Arbitration logic is included on-chip to allow the connection of up to four processors. Bus arbitration is accomplished through the BR1-4 signals and the priority scheme for bus arbitration is determined by the setting of the RPBA pin. Table 5 on Page 12 provides descriptions of the pins used in multiprocessor systems. Digital Audio and Digital Peripheral Interfaces (DAI/DPI) The digital audio and digital periphal interfaces (DAI and DPI) provide the ability to connect various peripherals to any of the DSP’s DAI or DPI pins (DAI_P20–1 and DPI_P14–1). Programs make these connections using the signal routing units (SRU1 and SRU2), shown in Figure 1. The SRUs are matrix routing units (or group of multiplexers) that enable the peripherals provided by the DAI and DPI to be interconnected under software control. This allows easy use of the associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with nonconfigurable signal paths. The DAI and DPI also include eight serial ports, an S/PDIF receiver/transmitter, four precision clock generators (PCG), eight channels of synchronous sample rate converters, and an input data port (IDP). The IDP provides an additional input path to the processor core, configurable as either eight channels of I2S serial data or as seven channels plus a single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the processor’s serial ports. For complete information on using the DAI and DPI, see the ADSP-21368 SHARC Processor Hardware Reference. INPUT/OUTPUT FEATURES The I/O processor provides 34 channels of DMA, as well as an extensive set of peripherals. These include a 20-pin digital audio interface which controls: • Eight serial ports • S/PDIF receiver/transmitter • Four precision clock generators • Four stereo sample rate converters • Internal data port/parallel data acquisition port The processors also contain a 14-pin digital peripheral interface which controls: • Three general-purpose timers • Two serial peripheral interfaces • Two universal asynchronous receiver/transmitters (UARTs) • A two-wire interface (I2C-compatible) Serial Ports The processors feature eight synchronous serial ports (SPORTs) that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as Analog Devices’ AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and frame sync. The data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel. Serial ports are enabled via 16 programmable and simultaneous receive or transmit pins that support up to 32 transmit or 32 receive channels of audio data when all eight SPORTS are enabled, or eight full duplex TDM streams of 128 channels per frame. The serial ports operate at a maximum data rate of 50M bits/s. Serial port data can be automatically transferred to and from on-chip memory via dedicated DMA channels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. One SPORT provides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared. DMA Controller The processor’s on-chip DMA controller allows data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur between the processor’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) ports, the IDP (input data port), the parallel data acquisition port (PDAP), or the UART. Thirty-four channels of DMA are available on the ADSP-21367/ADSP-21368/ADSP-21369—16 via the serial ports, eight via the input data port, four for the UARTs, two for Rev. A | Page 7 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Serial ports operate in five modes: • Standard DSP serial mode • Multichannel (TDM) mode with support for packed I S mode • I2S mode • Packed I2S mode • Left-justified sample pair mode Left-justified sample pair mode is a mode where in each frame sync cycle two samples of data are transmitted/received—one sample on the high segment of the frame sync, the other on the low segment of the frame sync. Programs have control over various attributes of this mode. Each of the serial ports supports the left-justified sample pair and I2S protocols (I2S is an industry-standard interface commonly used by audio codecs, ADCs, and DACs such as the Analog Devices AD183x family), with two data pins, allowing four left-justified sample pair or I2S channels (using two stereo devices) per serial port, with a maximum of up to 32 I2S channels. The serial ports permit little-endian or big-endian transmission formats and word lengths selectable from 3 bits to 32 bits. For the left-justified sample pair and I2S modes, dataword lengths are selectable between 8 bits and 32 bits. Serial ports offer selectable synchronization and transmit modes as well as optional μ-law or A-law companding selection on a per channel basis. Serial port clocks and frame syncs can be internally or externally generated. The serial ports also contain frame sync error detection logic where the serial ports detect frame syncs that arrive early (for example, frame syncs that arrive while the transmission/reception of the previous word is occurring). All the serial ports also share one dedicated error interrupt. 2 Digital Peripheral Interface (DPI) The digital peripheral interface provides connections to two serial peripheral interface ports (SPI), two universal asynchronous receiver-transmitters (UARTs), a two-wire interface (TWI), 12 flags, and three general-purpose timers. Serial Peripheral (Compatible) Interface The processors contain two serial peripheral interface ports (SPIs). The SPI is an industry-standard synchronous serial link, enabling the SPI-compatible port to communicate with other SPI-compatible devices. The SPI consists of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The ADSP-21367/ ADSP-21368/ADSP-21369 SPI-compatible peripheral implementation also features programmable baud rate and clock phase and polarities. The SPI-compatible port uses open drain drivers to support a multimaster configuration and to avoid data contention. UART Port The processors provide a full-duplex universal asynchronous receiver/transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. The UART also has multiprocessor communication capability using 9-bit address detection. This allows it to be used in multidrop networks through the RS-485 data interface standard. The UART port also includes support for five data bits to eight data bits, one stop bit or two stop bits, and none, even, or odd parity. The UART port supports two modes of operation: • PIO (programmed I/O) – The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive. • DMA (direct memory access) – The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates. The UART port’s baud rate, serial data format, error code generation and status, and interrupts are programmable: • Supporting bit rates ranging from (fSCLK/ 1,048,576) to (fSCLK/16) bits per second. • Supporting data formats from 7 bits to 12 bits per frame. • Both transmit and receive operations can be configured to generate maskable interrupts to the processor. Where the 16-bit UART_Divisor comes from the DLH register (most significant eight bits) and DLL register (least significant eight bits). S/PDIF-Compatible Digital Audio Receiver/Transmitter and Synchronous/Asynchronous Sample Rate Converter The S/PDIF receiver/transmitter has no separate DMA channels. It receives audio data in serial format and converts it into a biphase encoded signal. The serial data input to the receiver/transmitter can be formatted as left-justified, I2S, or right-justified with word widths of 16, 18, 20, or 24 bits. The serial data, clock, and frame sync inputs to the S/PDIF receiver/transmitter are routed through the signal routing unit (SRU). They can come from a variety of sources such as the SPORTs, external pins, the precision clock generators (PCGs), or the sample rate converters (SRC) and are controlled by the SRU control registers. The sample rate converter (SRC) contains four SRC blocks and is the same core as that used in the AD1896 192 kHz stereo asynchronous sample rate converter and provides up to 128 dB SNR. The SRC block is used to perform synchronous or asynchronous sample rate conversion across independent stereo channels, without using internal processor resources. The four SRC blocks can also be configured to operate together to convert multichannel audio data without phase mismatches. Finally, the SRC can be used to clean up audio data from jittery clock sources such as the S/PDIF receiver. Rev. A | Page 8 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 In conjunction with the general-purpose timer functions, autobaud detection is supported. midpoint of the PWM period. In this mode, it is possible to produce asymmetrical PWM patterns that produce lower harmonic distortion in three-phase PWM inverters. Timers The ADSP-21367/ADSP-21368/ADSP-21369 have a total of four timers: a core timer that can generate periodic software interrupts and three general-purpose timers that can generate periodic interrupts and be independently set to operate in one of three modes: • Pulse waveform generation mode • Pulse width count/capture mode • External event watchdog mode The core timer can be configured to use FLAG3 as a timer expired signal, and each general purpose timer has one bidirectional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A single control and status register enables or disables all three general-purpose timers independently. ROM-Based Security The ADSP-21367/ADSP-21368/ADSP-21369 have a ROM security feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code when enabled. When using this feature, the processor does not boot-load any external code, executing exclusively from internal SRAM/ROM. Additionally, the processor is not freely accessible via the JTAG port. Instead, a unique 64-bit key, which must be scanned in through the JTAG or test access port will be assigned to each customer. The device will ignore a wrong key. Emulation features and external boot modes are only available after the correct key is scanned. SYSTEM DESIGN The following sections provide an introduction to system design options and power supply issues. Two-Wire Interface Port (TWI) The TWI is a bidirectional 2-wire, serial bus used to move 8-bit data while maintaining compliance with the I2C bus protocol. The TWI master incorporates the following features: • Simultaneous master and slave operation on multiple device systems with support for multimaster data arbitration • Digital filtering and timed event processing • 7-bit and 10-bit addressing • 100K bits/s and 400K bits/s data rates • Low interrupt rate Program Booting The internal memory of the processors can be booted up at system power-up from an 8-bit EPROM via the external port, an SPI master or slave, or an internal boot. Booting is determined by the boot configuration (BOOT_CFG1–0) pins (see Table 7 on Page 15). Selection of the boot source is controlled via the SPI as either a master or slave device, or it can immediately begin executing from ROM. Power Supplies The processors have separate power supply connections for the internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS) power supplies. The internal and analog supplies must meet the 1.3 V requirement for the 333 MHz device and 1.2 V for the 266 MHz device. The external supply must meet the 3.3 V requirement. All external supply pins must be connected to the same power supply. Note that the analog supply pin (AVDD) powers the processor’s internal clock generator PLL. To produce a stable clock, it is recommended that PCB designs use an external filter circuit for the AVDD pin. Place the filter components as close as possible to the AVDD/AVSS pins. For an example circuit, see Figure 2. (A recommended ferrite chip is the muRata BLM18AG102SN1D). To reduce noise coupling, the PCB should use a parallel pair of power and ground planes for VDDINT and GND. Use wide traces to connect the bypass capacitors to the analog power (AVDD) and ground (AVSS) pins. Note that the AVDD and AVSS pins specified in Figure 2 are inputs to the processor and not the analog ground plane on the board—the AVSS pin should connect directly to digital ground (GND) at the chip. Pulse-Width Modulation The PWM module is a flexible, programmable, PWM waveform generator that can be programmed to generate the required switching patterns for various applications related to motor and engine control or audio power control. The PWM generator can generate either center-aligned or edge-aligned PWM waveforms. In addition, it can generate complementary signals on two outputs in paired mode or independent signals in nonpaired mode (applicable to a single group of four PWM waveforms). The entire PWM module has four groups of four PWM outputs each. Therefore, this module generates 16 PWM outputs in total. Each PWM group produces two pairs of PWM signals on the four PWM outputs. The PWM generator is capable of operating in two distinct modes while generating center-aligned PWM waveforms: single update mode or double update mode. In single update mode the duty cycle values are programmable only once per PWM period. This results in PWM patterns that are symmetrical about the midpoint of the PWM period. In double update mode, a second updating of the PWM registers is implemented at the Rev. A | Page 9 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 100nF VDDINT 10nF 1nF ADSP-213xx AVDD developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action. Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can: • View mixed C/C++ and assembly code (interleaved source and object information) • Insert breakpoints • Set conditional breakpoints on registers, memory, and stacks • Trace instruction execution • Perform linear or statistical profiling of program execution • Fill, dump, and graphically plot the contents of memory • Perform source level debugging • Create custom debugger windows The VisualDSP++ IDDE lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the SHARC development tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits programmers to: • Control how the development tools process inputs and generate outputs • Maintain a one-to-one correspondence with the tool’s command line switches The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system. Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the system state, when debugging an application that uses the VDK. VisualDSP++ Component Software Engineering (VCSE) is Analog Devices’ technology for creating, using, and reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software applications. The user can download components from the Web, drop them into the application, and publish component archives from within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language. HI-Z FERRITE BEAD CHIP AVSS LOCATE ALL COMPONENTS CLOSE TO AVDD AND AVSS PINS Figure 2. Analog Power (AVDD) Filter Circuit Target Board JTAG Emulator Connector Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21367/ ADSP-21368/ADSP-21369 processors to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor’s JTAG interface ensures that the emulator will not affect target system loading or timing. For complete information on Analog Devices’ SHARC DSP Tools product line of JTAG emulator operation, see the appropriate “Emulator Hardware User’s Guide.” DEVELOPMENT TOOLS The processors are supported with a complete set of CROSSCORE® software and hardware development tools, including Analog Devices emulators and VisualDSP++® development environment. The same emulator hardware that supports other SHARC processors also fully emulates the ADSP-21367/ADSP21368/ADSP-21369. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The SHARC has architectural features that improve the efficiency of compiled C/C++ code. The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the Rev. A | Page 10 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Use the Expert Linker to visually manipulate the placement of code and data on the embedded system. View memory utilization in a color-coded graphical form, easily move code and data to different areas of the processor or external memory with a drag of the mouse and examine runtime stack and heap usage. The expert linker is fully compatible with the existing linker definition file (LDF), allowing the developer to move between the graphical and textual environments. In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the SHARC processor family. Hardware tools include SHARC processor PC plug-in cards. Thirdparty software tools include DSP libraries, real-time operating systems, and block diagram design tools. in-circuit programming of the on-board flash device to store user-specific boot code, enabling the board to run as a standalone unit without being connected to the PC. With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any custom-defined system. Connecting one of Analog Devices JTAG emulators to the EZ-KIT Lite board enables high speed, non-intrusive emulation. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-21367/ADSP-21368/ADSP-21369 architecture and functionality. For detailed information on the ADSP-2136x family core architecture and instruction set, refer to the ADSP-21368 SHARC Processor Hardware Reference and the ADSP2136x/ADSP-2137x SHARC Processor Programming Reference. Designing an Emulator-Compatible DSP Board (Target) The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG test access port (TAP) on each JTAG DSP. Nonintrusive in-circuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing. To use these emulators, the target board must include a header that connects the DSP’s JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)—use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support. Evaluation Kit Analog Devices offers a range of EZ-KIT Lite® evaluation platforms to use as a cost effective method to learn more about developing or prototyping applications with Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite includes an evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Also included are sample application programs, power supply, and a USB cable. All evaluation versions of the software tools are limited for use only with the EZ-KIT Lite product. The USB controller on the EZ-KIT Lite board connects the board to the USB port of the user’s PC, enabling the VisualDSP++ evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also allows Rev. A | Page 11 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 PIN FUNCTION DESCRIPTIONS The following symbols appear in the Type column of Table 5: A = asynchronous, G = ground, I = input, O = output, O/T = output three-state, P = power supply, S = synchronous, (A/D) = active drive, (O/D) = open drain, (pd) = pull-down resistor, (pu) = pull-up resistor. Table 5. Pin List State During/ After Reset (ID = 00x) Pulled high/ driven low Pulled high/ pulled high Name ADDR23–0 DATA31–0 Type O/T (pu)1 I/O (pu)1 Description External Address. The processors output addresses for external memory and peripherals on these pins. External Data. Data pins can be multiplexed to support external memory interface data (I/O), the PDAP (I), FLAGS (I/O), and PWM (O). After reset, all DATA pins are in EMIF mode and FLAG(0-3) pins are in FLAGS mode (default). When configured using the IDP_PDAP_CTL register, IDP Channel 0 scans the DATA31–8 pins for parallel input data. Digital Audio Interface. These pins provide the physical interface to the DAI SRU. The DAI SRU configuration registers define the combination of on-chip audiocentric peripheral inputs or outputs connected to the pin, and to the pin’s output enable. The configuration registers then determines the exact behavior of the pin. Any input or output signal present in the DAI SRU may be routed to any of these pins. The DAI SRU provides the connection from the serial ports (8), the SRC module, the S/PDIF module, input data ports (2), and the precision clock generators (4), to the DAI_P20–1 pins. Pullups can be disabled via the DAI_PIN_PULLUP register. Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU. The DPI SRU configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pin’s output enable. The configuration registers of these peripherals then determines the exact behavior of the pin. Any input or output signal present in the DPI SRU may be routed to any of these pins. The DPI SRU provides the connection from the timers (3), SPIs (2), UARTs (2), flags (12) TWI (1), and general-purpose I/O (9) to the DPI_P14–1 pins. The TWI output is an open-drain output—so the pins used for I2C data and clock should be connected to logic level 0. Pull-ups can be disabled via the DPI_PIN_PULLUP register. Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access. DAI _P20–1 I/O with programmable pu2 Pulled high/ pulled high DPI _P14–1 I/O with programmable pu2 Pulled high/ pulled high ACK I (pu)1 RD WR SDRAS SDCAS SDWE O/T (pu)1 O/T (pu)1 O/T (pu)1 O/T (pu)1 O/T (pu)1 Pulled high/ driven high Pulled high/ driven high Pulled high/ driven high Pulled high/ driven high Pulled high/ driven high External Port Read Enable. RD is asserted whenever the processors read a word from external memory. External Port Write Enable. WR is asserted when the processors write a word to external memory. SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other SDRAM command pins, defines the operation for the SDRAM to perform. SDRAM Column Address Select. Connect to SDRAM’s CAS pin. In conjunction with other SDRAM command pins, defines the operation for the SDRAM to perform. SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin. Rev. A | Page 12 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Table 5. Pin List State During/ After Reset (ID = 00x) Pulled high/ driven high Pulled high/ driven low High-Z/driving Name SDCKE SDA10 Type O/T (pu)1 O/T (pu)1 Description SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK signal. For details, see the data sheet supplied with the SDRAM device. SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with nonSDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses. SDRAM Clock Output 0. SDRAM Clock Output 1. Additional clock for SDRAM devices. For systems with multiple SDRAM devices, handles the increased clock load requirements, eliminating need of off-chip clock buffers. Either SDCLK1 or both SDCLKx pins can be three-stated. SDCLK0 SDCLK1 O/T O/T MS0–1 O/T (pu)1 Pulled high/ driven high Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corresponding banks of external memory. The MS3-0 lines are decoded memory address lines that change at the same time as the other address lines. When no external memory access is occurring, the MS3-0 lines are inactive; they are active, however, when a conditional memory access instruction is executed, whether or not the condition is true. The MS1 pin can be used in EPORT/FLASH boot mode. See the hardware reference for more information. FLAG0/Interrupt Request 0. FLAG1/Interrupt Request 1. FLAG2/Interrupt Request 2/Memory Select 2. FLAG[0]/IRQ0 FLAG[1]/IRQ1 FLAG[2]/IRQ2/ MS2 FLAG[3]/TIMEXP/ MS3 TDI TDO TMS TCK TRST EMU CLK_CFG1–0 I/O I/O I/O with programmable pu (for MS mode) I/O with programmable pu (for MS mode) I (pu) O/T I (pu) I I (pu) O/T (pu) I High-Z/high-Z High-Z/high-Z High-Z/high-Z High-Z/high-Z FLAG3/Timer Expired/Memory Select 3. Test Data Input (JTAG). Provides serial data for the boundary scan logic. Test Data Output (JTAG). Serial scan output of the boundary scan path. Test Mode Select (JTAG). Used to control the test state machine. Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed low) after power-up, or held low for proper operation of the processor Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the processor. Emulation Status. Must be connected to the ADSP-21367/ADSP-21368/ADSP-21369 Analog Devices DSP Tools product line of JTAG emulator target board connectors only. Core/CLKIN Ratio Control. These pins set the start-up clock frequency. See Table 8 for a description of the clock configuration modes. Note that the operating frequency can be changed by programming the PLL multiplier and divider in the PMCTL register at any time after the core comes out of reset. Boot Configuration Select. These pins select the boot mode for the processor. The BOOT_CFG pins must be valid before reset is asserted. See Table 7 for a description of the boot modes. BOOT_CFG1–0 I Rev. A | Page 13 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Table 5. Pin List State During/ After Reset (ID = 00x) Name RESET Type I Description Processor Reset. Resets the processor to a known state. Upon deassertion, there is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution from the hardware reset vector address. The RESET input must be asserted (low) at power-up. Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal. Local Clock In. Used with XTAL. CLKIN is the processor’s clock input. It configures the processors to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the processor to use an external clock such as an external clock oscillator. CLKIN may not be halted, changed, or operated below the specified frequency. XTAL CLKIN O I RESETOUT/ CLKOUT O/T Driven low/ driven high Reset Out/Local Clock Out. Reset out provide a 4096 cycle delay that allows the PLL to lock. This pin can also be configured as a CLKOUT signal to clock synchronous peripherals and memory. The functionality can be switched between the PLL output clock and reset out by setting Bit 12 of the PMCTL register. The default is reset out. External Bus Request. Used by the ADSP-21368 processor to arbitrate for bus mastership. A processor only drives its own BRx line (corresponding to the value of its ID2-0 inputs) and monitors all others. In a system with less than four processors, the unused BRx pins should be tied high; the processor’s own BRx line must not be tied high or low because it is an output. Processor ID. Determines which bus request (BR4–1) is used by the ADSP-21368 processor. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, and so on. Use ID = 000 or 001 in single-processor systems. These lines are a system configuration selection that should be hardwired or only changed at reset. ID = 101,110, and 111 are reserved. Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for the ADSP-21368 external bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration selection which must be set to the same value on every processor in the system. BR4–1 I/O (pu)1 Pulled high/ pulled high ID2–0 I (pd) RPBA I (pu)1 1 2 The pull-up is always enabled on the ADSP-21367 and ADSP-21369 processors. The pull-up on the ADSP-21368 processor is only enabled on the processor with ID2–0 = 00x Pull-up can be enabled/disabled, value of pull-up cannot be programmed. Rev. A | Page 14 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 DATA MODES The upper 32 data pins of the external memory interface are muxed (using bits in the SYSCTL register) to support the external memory interface data (input/output), the PDAP (input only), the FLAGS (input/output), and the PWM channels (output). Table 6 provides the pin settings. Table 6. Function of Data Pins DATA PIN MODE 000 001 010 011 100 101 110 111 1 DATA31–16 EPDATA32–0 FLAGS/PWM15–01 FLAGS/PWM15–01 FLAGS/PWM15–01 PDAP (DATA + CTRL) PDAP (DATA + CTRL) DATA15–8 EPDATA15–0 FLAGS15–8 FLAGS15–0 DATA7–0 EPDATA7–0 EPDATA7–0 FLAGS7–0 Reserved Three-state all pins These signals can be FLAGS or PWM or a mix of both. However, they can be selected only in groups of four. Their function is determined by the control signals FLAGS/PWM_SEL. For more information, see the ADSP-21368 SHARC Processor Hardware Reference. BOOT MODES Table 7. Boot Mode Selection BOOT_CFG1–0 00 01 10 Booting Mode SPI Slave Boot SPI Master Boot EPROM/FLASH Boot CORE INSTRUCTION RATE TO CLKIN RATIO MODES For details on processor timing, see Timing Specifications and Figure 4 on Page 19. Table 8. Core Instruction Rate/CLKIN Ratio Selection CLK_CFG1–0 00 01 10 Core to CLKIN Ratio 6:1 32:1 16:1 Rev. A | Page 15 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 SPECIFICATIONS OPERATING CONDITIONS 333 MHz Parameter1 VDDINT AVDD VDDEXT VIH 2 266 MHz Max 1.365 1.365 3.47 VDDEXT + 0.5 +0.8 VDDEXT + 0.5 +1.19 Min 1.14 1.14 3.13 2.0 –0.5 1.74 –0.5 0 Max 1.26 1.26 3.47 VDDEXT + 0.5 +0.8 VDDEXT + 0.5 +1.19 +120 Unit V V V V V V V °C °C °C Description Internal (Core) Supply Voltage Analog (PLL) Supply Voltage External (I/O) Supply Voltage High Level Input Voltage @ VDDEXT = max Low Level Input Voltage @ VDDEXT = min High Level Input Voltage @ VDDEXT = max Low Level Input Voltage @ VDDEXT = min Junction Temperature 208-Lead MQFP @ TAMBIENT 0°C to +70°C 256-Ball SBGA @ TAMBIENT 0°C to +70°C 256-Ball SBGA @ TAMBIENT –40°C to +85°C Min 1.235 1.235 3.13 2.0 –0.5 1.74 –0.5 VIL2 VIH_CLKIN3 VIL_CLKIN TJ 3 0 –40 +110 +125 1 2 Specifications subject to change without notice. Applies to input and bidirectional pins: DATAx, ACK, RPBA, BRx, IDx, FLAGx, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RESET, TCK, TMS, TDI, TRST. 3 Applies to input pin CLKIN. Rev. A | Page 16 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 ELECTRICAL CHARACTERISTICS Parameter1 VOH2 VOL IIH IIL 2 4, 5 Description High Level Output Voltage Low Level Output Voltage High Level Input Current Low Level Input Current High Level Input Current Pull-down Low Level Input Current Pull-up Three-State Leakage Current Three-State Leakage Current Three-State Leakage Current Pull-up Test Conditions @ VDDEXT = min, IOH = –1.0 mA3 @ VDDEXT = min, IOL = 1.0 mA 3 Min 2.4 Typ Max Unit V 0.4 10 10 250 200 10 10 200 700 900 10 4.7 V μA μA μA μA μA μA μA mA mA mA pF @ VDDEXT = max, VIN = VDDEXT max @ VDDEXT = max, VIN = 0 V @ VDDEXT = max, VIN = 0 V @ VDDEXT = max, VIN = 0 V @ VDDEXT = max, VIN = VDDEXT max @ VDDEXT = max, VIN = 0 V @ VDDEXT = max, VIN = 0 V tCCLK = 3.75 ns, VDDINT = 1.2 V, 25°C tCCLK = 3.00 ns, VDDINT = 1.3 V, 25°C AVDD = max fIN = 1 MHz, TCASE = 25°C, VIN = 1.3 V 4, 6, 7 6 IIHPD IILPU IOZH IOZL 5 8, 9 8, 10 9 11 IOZLPU IDD-INTYP AIDD12 CIN 1 2 Supply Current (Internal) Supply Current (Analog) Input Capacitance 13, 14 Specifications subject to change without notice. Applies to output and bidirectional pins: ADDRx, DATAx, RD, WR, MSx, BRx, FLAGx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDCLKx, EMU, TDO, CLKOUT. 3 See Output Drive Currents on Page 47 for typical drive current capabilities. 4 Applies to input pins without internal pull-ups: BOOT_CFGx, CLK_CFGx, CLKIN, RESET, TCK. 5 Applies to input pins with internal pull-ups: ACK, RPBA, TMS, TDI, TRST. 6 Applies to input pins with internal pull-downs: IDx. 7 Applies to input pins with internal pull-ups disabled: ACK, RPBA. 8 Applies to three-statable pins without internal pull-ups: FLAGx, SDCLKx, TDO. 9 Applies to three-statable pins with internal pull-ups: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, EMU. 10 Applies to three-statable pins with internal pull-ups disabled: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10 11 See Engineer-to-Engineer Note 299 for further information. 12 Characterized, but not tested. 13 Applies to all signal pins. 14 Guaranteed, but not tested. Rev. A | Page 17 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 PACKAGE INFORMATION The information presented in Figure 3 provides details about the package branding for the ADSP-21367/ADSP-21368/ ADSP-21369 processors. For a complete listing of product availability, see Ordering Guide on Page 56. MAXIMUM POWER DISSIPATION See Engineer-to-Engineer Note (EE-299) for detailed thermal and power information regarding maximum power dissipation. For information on package thermal specifications, see Thermal Characteristics on Page 48. ABSOLUTE MAXIMUM RATINGS a ADSP-2136x tppZ-cc vvvvvv.x n.n yyww country_of_origin S Figure 3. Typical Package Brand Stresses greater than those listed in Table 10 may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 10. Absolute Maximum Ratings Parameter Internal (Core) Supply Voltage (VDDINT) Analog (PLL) Supply Voltage (AVDD) External (I/O) Supply Voltage (VDDEXT) Input Voltage Output Voltage Swing Load Capacitance Storage Temperature Range Junction Temperature Under Bias Rating –0.3 V to +1.5 V –0.3 V to +1.5 V –0.3 V to +4.6 V –0.5 V to +3.8 V –0.5 V to VDDEXT + 0.5 V 200 pF –65°C to +150°C 125°C Table 9. Package Brand Information Brand Key t pp Z cc vvvvvv.x n.n yyww Field Description Temperature Range Package Type Lead Free Option (optional) See Ordering Guide Assembly Lot Code Silicon Revision Date Code ESD SENSITIVITY CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-21367/ADSP-21368/ADSP-21369 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 18 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 TIMING SPECIFICATIONS The processor’s internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor core, and serial ports. During reset, program the ratio between the processor’s internal clock frequency and external (CLKIN) clock frequency with the CLK_CFG1–0 pins (see Table 8 on Page 15). To determine switching frequencies for the serial ports, divide down the internal clock, using the programmable divider control of each port (DIVx for the serial ports). The processor’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the processor uses an internal phase-locked loop (PLL). This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the processor’s internal clock. Figure 4 shows core to CLKIN ratios of 6:1, 16:1, and 32:1 with external oscillator or crystal. Note that more ratios are possible and can be set through software using the power management control register (PMCTL). For more information, see the ADSP-2136x/ADSP-2137x SHARC Processor Programming Reference. Note the definitions of various clock periods shown in Table 12 which are a function of CLKIN and the appropriate ratio control shown in Table 11. Table 11. ADSP-21367/ADSP-21368/ADSP-21369 CLKOUT and CCLK Clock Generation Operation Timing Requirements CLKIN CCLK Description Input Clock Core Clock Calculation 1/tCK 1/tCCLK Table 12. Clock Periods Timing Requirements tCK tCCLK tPCLK tSCLK tSDCLK tSPICLK 1 Description1 CLKIN Clock Period (Processor) Core Clock Period (Peripheral) Clock Period = 2 × tCCLK Serial Port Clock Period = (tPCLK) × SR SDRAM Clock Period = (tCCLK) × SDR SPI Clock Period = (tPCLK) × SPIR where: SR = serial port-to-core clock ratio (wide range, determined by SPORT CLKDIV bits in DIVx register) SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register setting) SPICLK = SPI Clock SDR = SDRAM-to-Core Clock Ratio (values determined by bits 20–18 of the PMCTL register) PLLICLK CLKIN XTAL XTAL OSC INDIV ÷1, 2 PLLM DIVEN ÷2, 4, 8, 16 CCLK (CORE CLOCK) ÷2 PCLK (PERIPHERAL CLOCK) CLK_CFG [1:0] (6:1, 16:1, 32:1) ÷ 2, 2.5, 3, 3.5, 4 SDCLK (SDRAM CLOCK) CLKOUT OR RSTOUT RESET DELAY Figure 4. Core Clock and System Clock Relationship to CLKIN Rev. A | Page 19 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times. See Figure 39 on Page 47 under Test Conditions for voltage reference levels. Switching Characteristics specify how the processor changes its signals. Circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given circumstance. Use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices. Rev. A | Page 20 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Power-Up Sequencing The timing requirements for processor startup are given in Table 13. Table 13. Power-Up Sequencing Timing Requirements (Processor Startup) Parameter Timing Requirements tRSTVDD tIVDDEVDD tCLKVDD1 tCLKRST tPLLRST Min RESET Low Before VDDINT/VDDEXT On VDDINT On Before VDDEXT CLKIN Valid After VDDINT/VDDEXT Valid CLKIN Valid Before RESET Deasserted PLL Control Setup Before RESET Deasserted 0 –50 0 102 20 Max Unit ns ms ms μs μs +200 +200 Switching Characteristic Core Reset Deasserted After RESET Deasserted tCORERST 1 4096tCK + 2 tCCLK 3, 4 Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.2 volt rails and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem. 2 Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time. Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal. 3 Applies after the power-up sequence is complete. Subsequent resets require RESET to be held low a minimum of four CLKIN cycles in order to properly initialize and propagate default states at all I/O pins. 4 The 4096 cycle count depends on tsrst specification in Table 15. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles maximum. RESET tRSTVDD VDDINT tIVDDEVDD VDDEXT tCLKVDD CLKIN tCLKRST CLK_CFG1-0 tPLLRST RSTOUT tCORERST Figure 5. Power-Up Sequencing Rev. A | Page 21 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Clock Input Table 14. Clock Input 333 MHz Max 1002 452 452 3 10 +250 Parameter Timing Requirements tCK CLKIN Period tCKL CLKIN Width Low tCKH CLKIN Width High tCKRF CLKIN Rise/Fall (0.4 V to 2.0 V) tCCLK3 CCLK Period CLKIN Jitter Tolerance tCKJ4, 5 1 2 Min 181 81 81 3.01 –250 Unit ns ns ns ns ns ps Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL. Applies only for CLK_CFG1–0 = 10 and default values for PLL control bits in PMCTL. 3 Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK. 4 Actual input jitter should be combined with ac specifications for accurate timing analysis. 5 Jitter specification is maximum peak-to-peak time interval error (TIE) jitter. tCK CLKIN tCKH tCKL Figure 6. Clock Input Clock Signals The processors can use an external clock or a crystal. See the CLKIN pin description in Table 5. Programs can configure the processor to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. Figure 7 shows the component connections used for a crystal operating in fundamental mode. Note that the clock rate is achieved using a 20.81 MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock speed of 333 MHz). To achieve the full core clock rate, programs need to configure the multiplier bits in the PMCTL register. ADSP-2136x CLKIN 1M R1 (TYPICAL) XTAL R2 (TYPICAL) 47 C1 22pF C2 22pF Y1 24.576MHz R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL DRIVE POWER. REFER TO CRYSTAL MANUFACTURER’S SPECIFICATIONS Figure 7. 333 MHz Operation (Fundamental Mode Crystal) Rev. A | Page 22 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Reset Table 15. Reset Parameter Timing Requirements tWRST1 RESET Pulse Width Low tSRST RESET Setup Before CLKIN Low 1 Min 4tCK 8 Max Unit ns ns Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable VDD and CLKIN (not including startup time of external clock oscillator). CLKIN tWRST RESET tSRST Figure 8. Reset Interrupts The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts. Table 16. Interrupts Parameter Timing Requirement tIPW IRQx Pulse Width Min 2 × tPCLK + 2 Max Unit ns DAI_P20-1 DPI_14-1 FLAG2 -0 (IRQ2-0) tIPW Figure 9. Interrupts Rev. A | Page 23 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer (CTIMER). Table 17. Core Timer Parameter Switching Characteristic tWCTIM CTIMER Pulse Width Min 4 × tPCLK – 1 Max Unit ns FLAG3 (CTIMER) tWCTIM Figure 10. Core Timer Timer PWM_OUT Cycle Timing The following timing specification applies to Timer0, Timer1, and Timer2 in PWM_OUT (pulse-width modulation) mode. Timer signals are routed to the DPI_P14–1 pins through the DPI SRU. Therefore, the timing specifications provided below are valid at the DPI_P14–1 pins. Table 18. Timer PWM_OUT Timing Parameter Switching Characteristic tPWMO Timer Pulse Width Output Min 2 × tPCLK – 2 Max 2 × (231 – 1) × tPCLK Unit ns DPI_P14-1 (TIMER2 -0) tPWMO Figure 11. Timer PWM_OUT Timing Rev. A | Page 24 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Timer WDTH_CAP Timing The following timing specification applies to Timer0, Timer1, and Timer2 in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DPI_P14–1 pins through the DPI SRU. Therefore, the timing specification provided below are valid at the DPI_P14–1 pins. Table 19. Timer Width Capture Timing Parameter Switching Characteristic tPWI Timer Pulse Width Min 2 × tPCLK Max 2 × (231 – 1) × tPCLK Unit ns tPWI DPI_P14- 1 (TIMER2 -0) Figure 12. Timer Width Capture Timing Pin to Pin Direct Routing (DAI and DPI) For direct pin connections only (for example, DAI_PB01_I to DAI_PB02_O). Table 20. DAI Pin to Pin Routing Parameter Timing Requirement tDPIO Delay DAI Pin Input Valid to DAI Output Valid Min 1.5 Max 10 Unit ns DAI_Pn DPI_Pn DAI_pm DPI_Pm tDPIO Figure 13. DAI Pin to Pin Direct Routing Rev. A | Page 25 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Precision Clock Generator (Direct Pin Routing) This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG’s Table 21. Precision Clock Generator (Direct Pin Routing) Parameter Min Max Unit Timing Requirements tPCGIP Input Clock Period 24 ns tSTRIG PCG Trigger Setup Before Falling 4.5 ns Edge of PCG Input Clock tHTRIG PCG Trigger Hold After Falling 3 ns Edge of PCG Input Clock Switching Characteristics tDPCGIO PCG Output Clock and Frame Sync Active Edge Delay After PCG Input Clock 2.5 10 ns tDTRIGCLK PCG Output Clock Delay After PCG Trigger 2.5 + ((2.5 + D) × tPCGIP) 10 + ((2.5 + D) × tPCGIP) ns tDTRIGFS PCG Frame Sync Delay After PCG Trigger 2.5 + ((2.5 + D – PH) × tPCGIP) 10 + ((2.5 + D – PH) × tPCGIP) ns tPCGOW1 Output Clock Period 2 × tPCGIP – 1 ns D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-2136x SHARC Processor Hardware Reference for the ADSP-21368 Processor, “Precision Clock Generators” chapter. 1 inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is no timing data available. All timing parameters and switching characteristics apply to external DAI pins (DAI_P01 – DAI_P20). In normal mode. tSTRIG DAI_Pn DPI_Pn PCG_TRIGx_I tHTRIG tPCGIP DAI_Pm DPI_Pm PCG_EXTx_I (CLKIN) tDPCGIO DAI_Py DPI_Py PCG_CLKx_O tDTRIGCLK tDPCGIO tPCGOW DAI_Pz DPI_Pz PCG_FSx_O tDTRIGFS Figure 14. Precision Clock Generator (Direct Pin Routing) Rev. A | Page 26 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Flags The timing specifications provided below apply to the FLAG3–0 and DPI_P14–1 pins, and the serial peripheral interface (SPI). See Table 5 on Page 12 for more information on flag use. Table 22. Flags Parameter Timing Requirement FLAG3–0 IN Pulse Width tFIPW Switching Characteristic tFOPW FLAG3–0 OUT Pulse Width Min 2 × tPCLK + 3 2 × tPCLK – 1.5 Max Unit ns ns DPI_P14-1 (FLAG3-0IN) (DATA31-0) tFIPW DPI_P14-1 (FLAG3- 0OUT) (DATA31-0) tFOPW Figure 15. Flags Rev. A | Page 27 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 SDRAM Interface Timing (133 MHz SDCLK) The 133 MHz access speed is for a single processor. When multiple ADSP-21368 processors are connected in a shared memory system, the access speed is 100 MHz. Table 23. SDRAM Interface Timing1 Parameter Timing Requirements DATA Setup Before SDCLK tSSDAT tHSDAT DATA Hold After SDCLK Switching Characteristics tSDCLK SDCLK Period tSDCLKH SDCLK Width High tSDCLKL SDCLK Width Low Command, ADDR, Data Delay After SDCLK2 tDCAD tHCAD Command, ADDR, Data Hold After SDCLK2 tDSDAT Data Disable After SDCLK tENSDAT Data Enable After SDCLK 1 Min 0.58 1.23 7.5 3.65 3.65 Max Unit ns ns ns ns ns ns ns ns ns 4.8 1.5 5.3 1.6 For FCCLK = 333 MHz (SDCLK ratio = 1:2.5). 2 Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE. tSDCLK SDCLK tSDCLKH tSSDAT tHSDAT DATA (IN) tSDCLKL tDCAD tENSDAT DATA(OUT) tDSDAT tHCAD tDCAD CMND ADDR (OUT) tHCAD Figure 16. SDRAM Interface Timing Rev. A | Page 28 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 SDRAM Interface Enable/Disable Timing (133 MHz SDCLK) Table 24. SDRAM Interface Enable/Disable Timing1 Parameter Switching Characteristics tDSDC Command Disable After CLKIN Rise tENSDC Command Enable After CLKIN Rise tDSDCC SDCLK Disable After CLKIN Rise tENSDCC SDCLK Enable After CLKIN Rise tDSDCA Address Disable After CLKIN Rise tENSDCA Address Enable After CLKIN Rise 1 Min Max 2 × tPCLK + 1 Unit ns ns ns ns ns ns 4.0 8.5 3.8 2 × tPCLK – 4 9.2 4 × tPCLK For FCCLK = 333 MHz (SDCLK ratio = 1:2.5). CLKIN tDSDC tDSDCC tDSDCA COMMAND SDCLK ADDR COMMAND SDCLK ADDR tENSDC tENSDCC tENSDCA Figure 17. SDRAM Interface Enable/Disable Timing Rev. A | Page 29 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Memory Read—Bus Master Use these specifications for asynchronous interfacing to memories. These specifications apply when the processors are the bus master accessing external memory space in asynchronous access mode. Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode. Table 25. Memory Read—Bus Master Parameter Timing Requirements tDAD Address, Selects Delay to Data Valid1, 2 tDRLD RD Low to Data Valid1 tSDS Data Setup to RD High tHDRH Data Hold from RD High3, 4 tDAAK ACK Delay from Address, Selects2, 5 tDSAK ACK Delay from RD Low4 Min Max W+tSDCLK – 5.12 W– 2.9 2.2 0 tSDCLK –9.5+ W W – 7.0 Unit ns ns ns ns ns ns ns ns ns ns Switching Characteristics tDRHA Address Selects Hold After RD High RH + 0.38 tDARL Address Selects to RD Low2 tSDCLK – 3.3 tRW RD Pulse Width W – 1.2 tRWR RD High to WR, RD Low HI +tSDCLK – 0.8 W = (number of wait states specified in AMICTLx register) × tSDCLK. HI =RHC + IC (RHC = number of read hold cycles specified in AMICTLx register) × tSDCLK IC = (number of idle cycles specified in AMICTLx register) × tSDCLK. H = (number of hold cycles specified in AMICTLx register) × tSDCLK. 1 2 Data delay/setup: system must meet tDAD, tDRLD, or tSDS. The falling edge of MSx is referenced. 3 Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode. 4 Data hold: User must meet tHDA or tHDRH in asynchronous access mode. See Test Conditions on Page 47 for the calculation of hold times given capacitive and dc loads. 5 ACK Delay/Setup: User must meet tDAAK, or tDSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet tDAAK or tDSAK. ADDRESS MSx RD tDARL tDRHA tRW tDRLD tDAD DATA tSDS tHDRH tDSAK tDAAK ACK tRWR WR Figure 18. Memory Read—Bus Master Rev. A | Page 30 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Memory Write—Bus Master Use these specifications for asynchronous interfacing to memories. These specifications apply when the processors are the bus master accessing external memory space in asynchronous access mode. Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode. Table 26. Memory Write—Bus Master Parameter Timing Requirements tDAAK ACK Delay from Address, Selects1, 2 tDSAK ACK Delay from WR Low 1, 3 Switching Characteristics tDAWH Address, Selects to WR Deasserted2 Address, Selects to WR Low2 tDAWL tWW WR Pulse Width tDDWH Data Setup Before WR High tDWHA Address Hold After WR Deasserted tDWHD Data Hold After WR Deasserted tWWR WR High to WR, RD Low Data Disable Before RD Low tDDWR tWDE WR Low to Data Enabled W = (number of wait states specified in AMICTLx register) × tSDCLK. H = (number of hold cycles specified in AMICTLx register) x tSDCLK. 1 2 Min Max tSDCLK – 9.7 + W W – 4.9 Unit ns ns ns ns ns ns ns ns ns ns ns tSDCLK – 3.1+ W tSDCLK – 2.7 W – 1.3 tSDCLK – 3.0+ W H + 0.15 H + 0.02 tSDCLK – 1.5+ H 2tSDCLK – 4.11 tSDCLK – 3.5 ACK Delay/Setup: System must meet tDAAK, or tDSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet tDAAK or tDSAK. The falling edge of MSx is referenced. 3 Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode. ADDRESS MSx tDAWH tDAWL WR tDWHA tWW tWWR tWDE tDDWH DATA tDDWR tDSAK tDAAK ACK tDWHD RD Figure 19. Memory Write—Bus Master Rev. A | Page 31 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Asynchronous Memory Interface (AMI) Enable/Disable Use these specifications for passing bus mastership between ADSP-21368 processors (BRx). Table 27. AMI Enable/Disable Parameter Switching Characteristics tENAMIAC Address/Control Enable After Clock Rise tENAMID Data Enable After Clock Rise tDISAMIAC Address/Control Disable After Clock Rise tDISAMID Data Disable After Clock Rise Min 4 tSCLK + 4 8.7 0 Max Unit ns ns ns ns CLKIN tDISAMIAC tDISAMID ADDR, WR, RD, MS1-0, DATA tENAMIAC tENAMID ADDR, WR, RD, MS1-0, DATA Figure 20. AMI Enable/Disable Rev. A | Page 32 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Shared Memory Bus Request Use these specifications for passing bus mastership between ADSP-21368 processors (BRx). Table 28. Multiprocessor Bus Request Parameter Timing Requirements tSBRI BRx, Setup Before CLKIN High tHBRI BRx, Hold After CLKIN High Switching Characteristics tDBRO BRx Delay After CLKIN High BRx Hold After CLKIN High tHBRO Min 9 0.5 9 1.0 Max Unit ns ns ns ns CLKIN tDBRO tHBRO BRX (OUT) tSBRI BR X (IN) tHBRI Figure 21. Shared Memory Bus Request Rev. A | Page 33 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width. Table 29. Serial Ports—External Clock Parameter Timing Requirements tSFSE1 FS Setup Before SCLK (Externally Generated FS in Either Transmit or Receive Mode) tHFSE1 FS Hold After SCLK (Externally Generated FS in Either Transmit or Receive Mode) 1 tSDRE Receive Data Setup Before Receive SCLK tHDRE1 Receive Data Hold After SCLK tSCLKW SCLK Width tSCLK SCLK Period Switching Characteristics tDFSE2 FS Delay After SCLK (Internally Generated FS in Either Transmit or Receive Mode) FS Hold After SCLK tHOFSE2 (Internally Generated FS in Either Transmit or Receive Mode) tDDTE2 Transmit Data Delay After Transmit SCLK 2 Transmit Data Hold After Transmit SCLK tHDTE 1 Serial port signals (SCLK, FS, data channel A, data channel B) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Min Max Unit 2.5 2.5 2.5 2.5 10 20 ns ns ns ns ns ns 9.5 2 9.6 2 ns ns ns ns Referenced to sample edge. 2 Referenced to drive edge. Table 30. Serial Ports—Internal Clock Parameter Timing Requirements tSFSI1 FS Setup Before SCLK (Externally Generated FS in Either Transmit or Receive Mode) 1 tHFSI FS Hold After SCLK (Externally Generated FS in Either Transmit or Receive Mode) 1 Receive Data Setup Before SCLK tSDRI tHDRI1 Receive Data Hold After SCLK Switching Characteristics tDFSI2 FS Delay After SCLK (Internally Generated FS in Transmit Mode) tHOFSI2 FS Hold After SCLK (Internally Generated FS in Transmit Mode) tDFSIR2 FS Delay After SCLK (Internally Generated FS in Receive Mode) 2 FS Hold After SCLK (Internally Generated FS in Receive Mode) tHOFSIR tDDTI2 Transmit Data Delay After SCLK tHDTI2 Transmit Data Hold After SCLK 3 tSCLKIW Transmit or Receive SCLK Width 1 Min Max Unit 7 2.5 7 2.5 4 –1.0 9 –1.0 3 –1.0 2 × tPCLK – 1.5 2 × tPCLK ns ns ns ns ns ns ns ns ns ns ns Referenced to the sample edge. 2 Referenced to drive edge. 3 Minimum SPORT divisor register value. Rev. A | Page 34 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Table 31. Serial Ports—Enable and Three-State Parameter Switching Characteristics tDDTEN1 Data Enable from External Transmit SCLK Data Disable from External Transmit SCLK tDDTTE1 tDDTIN1 Data Enable from Internal Transmit SCLK 1 Min 2 Max Unit ns ns ns 10 –1 Referenced to drive edge. Table 32. Serial Ports—External Late Frame Sync Parameter Switching Characteristics tDDTLFSE1 Data Delay from Late External Transmit FS or External Receive FS with MCE = 1, MFD = 0 tDDTENFS1 Data Enable for MCE = 1, MFD = 0 1 Min Max Unit 7.75 0.5 ns ns The tDDTLFSE and tDDTENFS parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0. EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0 DAI_P20-1 (SCLK) DRIVE SAMPLE DRIVE tSFSE/I DAI_P20- 1 (FS) tHFSE/I tDDTENFS DAI_P20-1 (DATA CHANNEL A/B) tDDTE/I tHDTE/I 1ST BIT 2ND BIT tDDTLFSE LATE EXTERNAL TRANSMIT FS DRIVE SAMPLE DRIVE DAI_P20- 1 (SCLK) tSFSE/I DAI_P20-1 (FS) tHFSE/I tDDTENFS DAI_P20- 1 (DATA CHANNEL A/B) tDDTE/I tHDTE/I 1ST BIT 2ND BIT tDDTLFSE NOTE: SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20- 1 PINS USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20-1 PINS. Figure 22. External Late Frame Sync1 1 This figure reflects changes made to support left-justified sample pair mode. Rev. A | Page 35 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DATA RECEIVE—EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE tSCLKIW DAI_P20-1 (SCLK) DAI_P20- 1 (SCLK) tSCLKW tDFSIR tHOFSIR DAI_P20-1 (FS) tSFSI tHFSI DAI_P20-1 (FS) tDFSE tHOFSE tSFSE tHFSE tSDRI DAI_P20-1 (DATA CHANNEL A/B) tHDRI DAI_P20-1 (DATA CHANNEL A/B) tSDRE tHDRE NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DATA TRANSMIT—EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE tSCLKIW DAI_P20-1 (SCLK) DAI_P20-1 (SCLK) tSCLKW tDFSI tHOFSI DAI_P20- 1 (FS) tDFSE tSFSI tHFSI DAI_P20-1 (FS) tHOFSE tSFSE tHFSE tHDTI DAI_P20-1 (DATA CHANNEL A/B) tDDTI DAI_P20- 1 (DATA CHANNEL A/B) tHDTE tDDTE NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. DRIVE EDGE DAI_P20-1 SCLK (EXT) SCLK DRIVE EDGE tDDTEN DAI_P20- 1 (DATA CHANNEL A/B) DRIVE EDGE DAI_P20-1 SCLK (INT) tDDTTE tDDTIN DAI_P20- 1 (DATA CHANNEL A/B) Figure 23. Serial Ports Rev. A | Page 36 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Input Data Port The timing requirements for the IDP are given in Table 33. IDP signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 33. IDP Parameter Timing Requirements tSISFS1 FS Setup Before SCLK Rising Edge 1 tSIHFS FS Hold After SCLK Rising Edge SDATA Setup Before SCLK Rising Edge tSISD1 tSIHD1 SDATA Hold After SCLK Rising Edge tIDPCLKW Clock Width tIDPCLK Clock Period 1 Min 3.8 2.5 2.5 2.5 9 24 Max Unit ns ns ns ns ns ns DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE tIDPCLK DAI_P20-1 (SCLK) tIDPCLKW tSISFS DAI_P20-1 (FS) tSIHFS tSISD DAI_P20-1 (SDATA) tSIHD Figure 24. IDP Master Timing Rev. A | Page 37 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Parallel Data Acquisition Port (PDAP) The timing requirements for the PDAP are provided in Table 34. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the IDP, see the IDP chapter of the ADSP-21368 SHARC Processor Hardware Table 34. Parallel Data Acquisition Port (PDAP) Parameter Timing Requirements tSPCLKEN1 PDAP_CLKEN Setup Before PDAP_CLK Sample Edge 1 tHPCLKEN PDAP_CLKEN Hold After PDAP_CLK Sample Edge PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge tPDSD1 tPDHD1 PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge tPDCLKW Clock Width tPDCLK Clock Period Switching Characteristics tPDHLDD Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word PDAP Strobe Pulse Width tPDSTRB 1 Reference. Note that the most significant 16 bits of external PDAP data can be provided through the DATA31–16 pins. The remaining four bits can only be sourced through DAI_P4–1. The timing below is valid at the DATA31–16 pins. Min 2.5 2.5 3.85 2.5 7.0 24 2 × tPCLK + 3 2 × tPCLK – 1 Max Unit ns ns ns ns ns ns ns ns Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG. SAMPLE EDGE t PDCLK t PDCLKW DAI_P20 -1 (PDAP_CLK) t SPCLKEN DAI_P20- 1 (PDAP_CLKEN) t HPCLKEN t PDSD DATA t PDHD DAI_P20-1 (PDAP_STROBE) tPDSTRB t PDHLDD Figure 25. PDAP Timing Rev. A | Page 38 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Pulse-Width Modulation Generators Table 35. PWM Timing Parameter Switching Characteristics tPWMW PWM Output Pulse Width tPWMP PWM Output Period Min tPCLK – 2 2 × tPCLK – 1.5 Max (216 – 2) × tPCLK – 2 (216 – 1) × tPCLK – 1.5 Unit ns ns tPWMW PWM OUTPUTS tPWMP Figure 26. PWM Timing Sample Rate Converter—Serial Input Port The SRC input signals (SCLK, FS, and SDATA) are routed from the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided in Table 36 are valid at the DAI_P20–1 pins. Table 36. SRC, Serial Input Port Parameter Timing Requirements tSRCSFS1 FS Setup Before SCLK Rising Edge tSRCHFS1 FS Hold After SCLK Rising Edge tSRCSD1 SDATA Setup Before SCLK Rising Edge tSRCHD1 SDATA Hold After SCLK Rising Edge tSRCCLKW Clock Width Clock Period tSRCCLK 1 Min 4 5.5 4 5.5 9 24 Max Unit ns ns ns ns ns ns DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE tSRCCLK DAI_P20-1 (SCLK) tSRCCLKW tSRCSFS DAI_P20-1 (FS) tSRCHFS tSRCSD DAI_P20- 1 (SDATA) tSRCHD Figure 27. SRC Serial Input Port Timing Rev. A | Page 39 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Sample Rate Converter—Serial Output Port For the serial output port, the frame-sync is an input and it should meet setup and hold times with regard to SCLK on the output port. The serial data output, SDATA, has a hold time Table 37. SRC, Serial Output Port Parameter Timing Requirements FS Setup Before SCLK Rising Edge tSRCSFS1 tSRCHFS1 FS Hold After SCLK Rising Edge tSRCCLKW Clock Width tSRCCLK Clock Period Switching Characteristics tSRCTDD1 Transmit Data Delay After SCLK Falling Edge 1 Transmit Data Hold After SCLK Falling Edge tSRCTDH 1 and delay specification with regard to SCLK. Note that SCLK rising edge is the sampling edge and the falling edge is the drive edge. Min 4 5.5 9 24 Max Unit ns ns ns ns 8.9 1 ns ns DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE tSRCCLK DAI_P20-1 (SCLK) tSRCCLKW tSRCSFS DAI_P20-1 (FS) tSRCHFS tSRCTDD DAI_P20-1 (SDATA) tSRCTDH Figure 28. SRC Serial Output Port Timing Rev. A | Page 40 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 SPDIF Transmitter Serial data input to the SPDIF transmitter can be formatted as left justified, I2S, or right justified with word widths of 16, 18, 20, or 24 bits. The following sections provide timing for the transmitter. SPDIF Transmitter—Serial Input Waveforms Figure 29 shows the right-justified mode. LRCLK is HI for the left channel and LO for the right channel. Data is valid on the rising edge of SCLK. The MSB is delayed 12-bit clock periods (in 20-bit output mode) or 16-bit clock periods (in 16-bit output mode) from an LRCLK transition, so that when there are 64 SCLK periods per LRCLK period, the LSB of the data is rightjustified to the next LRCLK transition. DAI_P20- 1 LRCLK DAI_P20- 1 SCLK DAI_P20- 1 SDATA LSB LEFT CHANNEL RIGHT CHANNEL MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB Figure 29. Right-Justified Mode Figure 30 shows the default I2S-justified mode. LRCLK is LO for the left channel and HI for the right channel. Data is valid on the rising edge of SCLK. The MSB is left-justified to an LRCLK transition but with a single SCLK period delay. RIGHT CHANNEL DAI_P20-1 LRCLK DAI_P20-1 SCLK DAI_P20-1 SDATA MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB LEFT CHANNEL Figure 30. I2S-Justified Mode Figure 31 shows the left-justified mode. LRCLK is HI for the left channel and LO for the right channel. Data is valid on the rising edge of SCLK. The MSB is left-justified to an LRCLK transition with no MSB delay. DAI_P20 -1 LRCLK DAI_P20 -1 SCLK DAI_P20 -1 SDATA MSB MSB-1 MSB-2 LEFT CHANNEL RIGHT CHANNEL LSB+2 LSB+1 LSB MSB MSB-1 MSB-2 LS B+2 LSB+1 LSB MSB MSB+1 Figure 31. Left-Justified Mode Rev. A | Page 41 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 SPDIF Transmitter Input Data Timing The timing requirements for the input port are given in Table 38. Input signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 38. SPDIF Transmitter Input Data Timing Parameter Timing Requirements tSISFS1 FS Setup Before SCLK Rising Edge tSIHFS1 FS Hold After SCLK Rising Edge tSISD1 SData Setup Before SCLK Rising Edge tSIHD1 SData Hold After SCLK Rising Edge Clock Width tSISCLKW tSISCLK Clock Period tSITXCLKW Transmit Clock Width tSITXCLK Transmit Clock Period 1 Min 3 3 3 3 36 80 9 20 Max Unit ns ns ns ns ns ns ns ns DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE tSITXCLKW DAI_P20-1 (TXCLK) tSITXCLK DAI_P20-1 (SCLK) tSISCLKW tSISFS DAI_P20-1 (FS) tSIHFS tSISD DAI_P20-1 (SDATA) tSIHD Figure 32. SPDIF Transmitter Input Timing Oversampling Clock (TxCLK) Switching Characteristics The SPDIF transmitter has an oversampling clock. This TxCLK input is divided down to generate the biphase clock. Table 39. Oversampling Clock (TxCLK) Switching Characteristics Parameter TxCLK Frequency for TxCLK = 768 × FS TxCLK Frequency for TxCLK = 512 × FS TxCLK Frequency for TxCLK = 384 × FS TxCLK Frequency for TxCLK = 256 × FS Frame Rate Min Max 147.5 98.4 73.8 49.2 192.0 Unit MHz MHz MHz MHz kHz Rev. A | Page 42 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 SPDIF Receiver The following section describes timing as it relates to the SPDIF receiver. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × FS clock. Table 40. SPDIF Receiver Internal Digital PLL Mode Timing Parameter Switching Characteristics LRCLK Delay After SCLK tDFSI tHOFSI LRCLK Hold After SCLK tDDTI Transmit Data Delay After SCLK tHDTI Transmit Data Hold After SCLK tSCLKIW1 Transmit SCLK Width 1 Min Max 5 Unit ns ns ns ns ns –2 5 –2 40 SCLK frequency is 64 × FS where FS = the frequency of LRCLK. DRIVE EDGE tSCLKIW DAI_P20-1 (SCLK) SAMPLE EDGE tDFSI tHOFSI DAI_P20-1 (FS) tHDTI DAI_P20-1 (DATA CHANNEL A/B) tDDTI Figure 33. SPDIF Receiver Internal Digital PLL Mode Timing Rev. A | Page 43 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 SPI Interface—Master The processors contain two SPI ports. The primary has dedicated pins and the secondary is available through the DPI. The timing provided in Table 41 and Table 42 on Page 45 applies to both. Table 41. SPI Interface Protocol—Master Switching and Timing Specifications Parameter Timing Requirements tSSPIDM Data Input Valid to SPICLK Edge (Data Input Setup Time) tHSPIDM SPICLK Last Sampling Edge to Data Input Not Valid Switching Characteristics tSPICLKM Serial Clock Cycle tSPICHM Serial Clock High Period tSPICLM Serial Clock Low Period tDDSPIDM SPICLK Edge to Data Out Valid (Data Out Delay Time) tHDSPIDM SPICLK Edge to Data Out Not Valid (Data Out Hold Time) FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge tSDSCIM tHDSM Last SPICLK Edge to FLAG3–0IN High tSPITDM Sequential Transfer Delay Min 8.2 2 8 × TPCLK – 2 4 × tPCLK – 2 4 × tPCLK – 2 2.5 2 4 × tPCLK – 2 4 × tPCLK – 2 4 × tPCLK – 1 Max Unit ns ns ns ns ns ns ns ns ns ns FLAG3-0 (OUTPUT) t SDSCIM SPICLK (CP = 0) (OUTPUT) t SPICHM t SPICLM t SPI CLKM t HDSM t SPIT DM t SPICL M SPICLK (CP = 1) (OUTPUT) t SPICHM t D DSPIDM MOSI (OUTPUT) MSB t HDSPIDM LSB t SSPIDM CPHASE = 1 MISO (INPUT) MSB VALID t SSPIDM t HSPIDM LSB VALID tHSPIDM t DDSPIDM MOSI (OUTPUT) CPHASE = 0 MISO (INPUT) MSB t HDSPIDM LSB t SSPIDM MSB VALID t HSPIDM LSB VALID Figure 34. SPI Master Timing Rev. A | Page 44 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 SPI Interface—Slave Table 42. SPI Interface Protocol—Slave Switching and Timing Specifications Serial Clock Cycle Serial Clock High Period Serial Clock Low Period SPIDS Assertion to First SPICLK Edge CPHASE = 0 CPHASE = 1 tHDS Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 tSSPIDS Data Input Valid to SPICLK Edge (Data Input Setup Time) tHSPIDS SPICLK Last Sampling Edge to Data Input Not Valid tSDPPW SPIDS Deassertion Pulse Width (CPHASE = 0) Switching Characteristics tDSOE SPIDS Assertion to Data Out Active tDSDHI SPIDS Deassertion to Data High Impedance tDDSPIDS SPICLK Edge to Data Out Valid (Data Out Delay Time) tHDSPIDS SPICLK Edge to Data Out Not Valid (Data Out Hold Time) tDSOV SPIDS Assertion to Data Out Valid (CPHASE = 0) Parameter Timing Requirements tSPICLKS tSPICHS tSPICLS tSDSCO Min 4 × tPCLK – 2 2 × tPCLK – 2 2 × tPCLK – 2 2 × tPCLK 2 × tPCLK 2 × tPCLK 2 2 2 × tPCLK 0 0 2 × tPCLK Max Unit ns ns ns ns ns ns ns ns ns 6.8 6.8 9.5 5 × tPCLK ns ns ns ns ns SPIDS (INPUT) tSPICHS SPICLK (CP = 0) (INPUT) tSPICLS tS P I C L K S tHDS tS D P P W tS D S C O SPICLK (CP = 1) (INPUT) tSPICLS tSPICHS tDSOE tDDSPIDS tD D S P I D S MSB LSB tDSD HI t H D S P ID S MISO (OUTPUT) CPHASE = 1 MOSI (INPUT) t H S P ID S tSSPIDS MSB VALID tSSPIDS LSB VALID tDSOV tDSOE MISO (OUTPUT) CPHASE = 0 MOSI (INPUT) MSB tDDSPIDS t H D S P ID S tDSDHI LSB tSSPIDS MSB VALID LSB VALID t H S P ID S Figure 35. SPI Slave Timing Rev. A | Page 45 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 JTAG Test Access Port and Emulation Table 43. JTAG Test Access Port and Emulation Parameter Timing Requirements tTCK TCK Period tSTAP TDI, TMS Setup Before TCK High tHTAP TDI, TMS Hold After TCK High tSSYS1 System Inputs Setup Before TCK High 1 tHSYS System Inputs Hold After TCK High tTRSTW TRST Pulse Width Switching Characteristics tDTDO TDO Delay from TCK Low 2 tDSYS System Outputs Delay After TCK Low 1 2 Min tCK 5 6 7 18 4tCK Max Unit ns ns ns ns ns ns 7 tCK ÷ 2 + 7 ns ns System Inputs = AD15–0, SPIDS, CLK_CFG1–0, RESET, BOOT_CFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0. System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU. tTCK TCK tSTAP TMS TDI tDTDO TDO tSSYS SYSTEM INPUTS tDSYS SYSTEM OUTPUTS tHSYS tHTAP Figure 36. IEEE 1149.1 JTAG Test Access Port Rev. A | Page 46 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 OUTPUT DRIVE CURRENTS Figure 37 shows typical I-V characteristics for the output drivers of the ADSP-21367/ADSP-21368/ADSP-21369. The curves represent the current drive capability of the output drivers as a function of output voltage. INPUT 1.5V OR OUTPUT 1.5V Figure 39. Voltage Reference Levels for AC Measurements 40 30 SOURCE (VDDEXT) CURRENT (mA) CAPACITIVE LOADING VOH 3.3V, 25°C 3.47V, -45°C 20 10 0 -10 3.11V, 125°C Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 38). Figure 42 shows graphically how output delays and holds vary with load capacitance. The graphs of Figure 40, Figure 41, and Figure 42 may not be linear outside the ranges shown for Typical Output Delay vs. Load Capacitance and Typical Output Rise Time (20% to 80%, V = Min) vs. Load Capacitance. 3.11V, 125°C -20 3.3V, 25°C -30 -40 VOL 3.47V, -45°C 0 0.5 12 RISE AND FALL TIMES (ns) 1.0 1.5 2.0 2.5 SWEEP (VDDEXT ) VOLTAGE (V) 3.0 3.5 10 y = 0.0467x + 1.6323 8 RISE FALL Figure 37. Typical Drive at Junction temperature 6 TEST CONDITIONS The ac signal specifications (timing parameters) appear in Table 15 on Page 23 through Table 43 on Page 46. These include output disable time, output enable time, and capacitive loading. The timing specifications for the SHARC apply for the voltage reference levels in Figure 39. Timing is measured on signals when they cross the 1.5 V level as described in Figure 39. All delays (in nanoseconds) are measured between the point that the first signal reaches 1.5 V and the point that the second signal reaches 1.5 V. 4 y = 0.045x + 1.524 2 0 0 50 100 150 200 250 LOAD CAPACITANCE (pF) Figure 40. Typical Output Rise/Fall Time (20% to 80%, VDDEXT = Max) 12 IOL RISE 10 RISE AND FALL TIMES (ns) y = 0.049x + 1.5105 8 FALL 50 1.5V + TO OUTPUT PIN 6 y = 0.0482x + 1.4604 4 30pF IOH 2 0 Figure 38. Equivalent Device Loading for AC Measurements (Includes All Fixtures) 0 50 100 150 200 250 LOAD CAPACITANCE (pF) Figure 41. Typical Output Rise/Fall Time (20% to 80%, VDDEXT = Min) Rev. A | Page 47 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 10 8 OUTPUT DELAY OR HOLD (ns) Values of θJB are provided for package comparison and PCB design considerations. Note that the thermal characteristics values provided in Table 44 and Table 45 are modeled values. Y = 0.0488x - 1.5923 Table 44. Thermal Characteristics for 256-Ball SBGA Parameter θJA θJMA θJMA θJC θJB ΨJT ΨJMT ΨJMT Condition Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Typical 12.5 10.6 9.9 0.7 5.3 0.3 0.3 0.3 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W 6 4 2 0 -2 -4 0 50 100 150 200 LOAD CAPACITANCE (pF) Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Figure 42. Typical Output Delay or Hold vs. Load Capacitance (at Junction Temperature) Table 45. Thermal Characteristics for 208-Lead MQFP Parameter θJA θJMA θJMA θJC ΨJT ΨJMT ΨJMT Condition Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Typical 25.0 22.5 21.6 9.6 0.7 0.8 0.9 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W THERMAL CHARACTERISTICS The ADSP-21367/ADSP-21368/ADSP-21369 processors are rated for performance over the temperature range specified in Operating Conditions on Page 16. Table 44 and Table 45 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-toboard measurement complies with JESD51-8. Test board design complies with JEDEC standard JESD51-9 (SBGA) and JESD51-7 (MQFP). The junction-to-case measurement complies with MIL-STD-883. All measurements use a 2S2P JEDEC test board. To determine the junction temperature of the device while on the application PCB, use: T J = T TOP + ( Ψ JT × P D ) where: TJ = junction temperature (°C) TTOP = case temperature (°C) measured at the top center of the package ΨJT = junction-to-top (of package) characterization parameter is the typical value from Table 44 and Table 45. PD = power dissipation (see EE Note EE-299) Values of θJA are provided for package comparison and PCB design considerations. θJA can be used for a first-order approximation of TJ by the equation: T J = T A + ( θ JA × P D ) where: TA = ambient temperature (°C) Values of θJC are provided for package comparison and PCB design considerations when an external heat sink is required. This is only applicable when a heat sink is used. Rev. A | Page 48 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 256-BALL SBGA PINOUT Table 46. 256-Ball SBGA Pin Assignment (Numerically by Ball Number) Ball No. A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 E01 E02 E03 E04 E17 E18 E19 E20 J01 J02 J03 J04 Signal NC TDI TMS CLK_CFG0 CLK_CFG1 EMU DAI4 DAI1 DPI14 DPI12 DPI10 DPI9 DPI7 DPI6 DPI3 DPI2 CLKOUT DATA31 NC NC DAI11 DAI8 VDDINT VDDINT GND GND DATA25 DATA23 DAI19 DAI18 GND GND Ball No. B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 F01 F02 F03 F04 F17 F18 F19 F20 K01 K02 K03 K04 Signal DAI5 SDCLK1 TRST TCK BOOT_CFG_0 BOOT_CFG_1 TDO DAI3 DAI2 DPI13 DPI11 DPI8 DPI5 DPI4 DPI1 RESET DATA30 DATA29 DATA28 NC DAI14 DAI12 GND GND VDDEXT GND GND/ID21 DATA21 FLAG0 DAI20 GND VDDEXT Ball No. C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 G01 G02 G03 G04 G17 G18 G19 G20 L01 L02 L03 L04 Signal DAI9 DAI7 GND VDDEXT GND GND VDDINT GND GND VDDINT GND GND VDDINT GND GND VDDINT VDDINT VDDINT DATA27 NC/RPBA1 DAI15 DAI13 GND VDDEXT VDDINT VDDINT DATA22 DATA20 FLAG2 FLAG1 VDDINT VDDINT Ball No. D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 H01 H02 H03 H04 H17 H18 H19 H20 M01 M02 M03 M04 Signal DAI10 DAI6 GND VDDEXT GND VDDEXT VDDINT GND VDDEXT VDDINT GND VDDEXT VDDINT GND VDDEXT GND VDDEXT GND DATA26 DATA24 DAI17 DAI16 VDDINT VDDINT VDDEXT GND DATA19 DATA18 ACK FLAG3 GND GND Rev. A | Page 49 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Table 46. 256-Ball SBGA Pin Assignment (Numerically by Ball Number) (Continued) Ball No. J17 J18 J19 J20 N01 N02 N03 N04 N17 N18 N19 N20 U01 U02 U03 U04 U05 U06 U07 U08 U09 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 1 Signal GND GND GND/ID11 DATA17 RD SDCLK0 GND VDDEXT GND GND DATA11 DATA10 MS0 MS1 VDDINT GND VDDEXT GND VDDEXT VDDINT VDDEXT GND VDDEXT VDDINT VDDEXT VDDEXT VDDINT VDDEXT VDDINT VDDINT DATA0 DATA2 Ball No. K17 K18 K19 K20 P01 P02 P03 P04 P17 P18 P19 P20 V01 V02 V03 V04 V05 V06 V07 V08 V09 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 Signal VDDINT VDDINT GND/ID01 DATA16 SDA10 WR VDDINT VDDINT VDDINT VDDINT DATA8 DATA9 ADDR22 ADDR23 VDDINT GND GND GND GND VDDINT GND GND GND VDDINT VDDEXT GND VDDINT GND GND GND DATA1 DATA3 Ball No. L17 L18 L19 L20 R01 R02 R03 R04 R17 R18 R19 R20 W01 W02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Signal VDDINT VDDINT DATA15 DATA14 SDWE SDRAS GND GND VDDEXT GND DATA6 DATA7 GND ADDR21 ADDR19 ADDR20 ADDR17 ADDR16 ADDR15 ADDR14 AVDD AVSS ADDR13 ADDR12 ADDR10 ADDR8 ADDR5 ADDR4 ADDR1 ADDR2 ADDR0 NC Ball No. M17 M18 M19 M20 T01 T02 T03 T04 T17 T18 T19 T20 Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Signal VDDEXT GND DATA12 DATA13 SDCKE SDCAS GND VDDEXT GND GND DATA5 DATA4 GND NC NC ADDR18 NC/BR11 NC/BR21 XTAL2 CLKIN NC NC NC/BR31 NC/BR41 ADDR11 ADDR9 ADDR7 ADDR6 ADDR3 GND GND NC Applies to ADSP-21368 models only. Rev. A | Page 50 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Figure 43 shows the bottom view of the SBGA ball configuration. Figure 44 shows the top view of the SBGA ball configuration. 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A B C D E F G H J 20 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y TOP VIEW BOTTOM VIEW K L M N P R T U V W Y KEY VDDINT I/O SIGNALS VDDEXT GND AVDD AVSS NO CONNECT KEY VDDINT I/O SIGNALS VDDEXT GND AVDD AVSS NO CONNECT Figure 44. 256-Ball SBGA Ball Configuration (Top View) Figure 43. 256-Ball SBGA Ball Configuration (Bottom View) Rev. A | Page 51 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 208-LEAD MQFP PINOUT Table 47. 208-Lead MQFP Pin Assignment (Numerically by Lead Number) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Signal VDD DATA28 DATA27 GND VDDEXT DATA26 DATA25 DATA24 DATA23 GND VDD DATA22 DATA21 DATA20 VDDEXT GND DATA19 DATA18 VDD GND DATA17 VDD GND VDD GND DATA16 DATA15 DATA14 DATA13 DATA12 VDDEXT GND VDD GND DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 VDDEXT GND VDD DATA4 Pin No. 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Signal VDD GND VDDEXT ADDR0 ADDR2 ADDR1 ADDR4 ADDR3 ADDR5 GND VDD GND VDDEXT ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 GND VDD GND VDDEXT ADDR11 ADDR12 ADDR13 GND VDD AVSS AVDD GND CLKIN XTAL2 VDDEXT GND VDD ADDR14 GND VDDEXT ADDR15 ADDR16 ADDR17 ADDR18 GND VDDEXT Pin No. 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 Signal VDD GND VDDEXT SDCAS SDRAS SDCKE SDWE WR SDA10 GND VDDEXT SDCLK0 GND VDD RD ACK FLAG3 FLAG2 FLAG1 FLAG0 DAI20 GND VDD GND VDDEXT DAI19 DAI18 DAI17 DAI16 DAI15 DAI14 DAI13 DAI12 VDD VDDEXT GND VDD GND DAI11 DAI10 DAI8 DAI9 DAI6 DAI7 Pin No. 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Signal VDD VDD GND VDD VDD VDD TDI TRST TCK GND VDD TMS CLK_CFG0 BOOT_CFG0 CLK_CFG1 EMU BOOT_CFG1 TDO DAI4 DAI2 DAI3 DAI1 VDDEXT GND VDD GND DPI14 DPI13 DPI12 DPI11 DPI10 DPI9 DPI8 DPI7 VDDEXT GND VDD GND DPI6 DPI5 DPI4 DPI3 DPI1 DPI2 Rev. A | Page 52 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Table 47. 208-Lead MQFP Pin Assignment (Numerically by Lead Number) (Continued) Pin No. 45 46 47 48 49 50 51 52 Signal DATA5 DATA2 DATA3 DATA0 DATA1 VDDEXT GND VDD Pin No. 97 98 99 100 101 102 103 104 Signal ADDR19 ADDR20 ADDR21 ADDR23 ADDR22 MS1 MS0 VDD Pin No. 149 150 151 152 153 154 155 156 Signal DAI5 VDDEXT GND VDD GND VDD GND VDD Pin No. 201 202 203 204 205 206 207 208 Signal CLKOUT RESET VDDEXT GND DATA30 DATA31 DATA29 VDD Rev. A | Page 53 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 PACKAGE DIMENSIONS The ADSP-21367/ADSP-21368/ADSP-21369 processors are available in 256-ball lead-free and leaded SBGA, and 208-lead lead-free MQFP packages. 0.75 0.60 0.45 4.10 MAX 208 1 30.85 30.60 SQ 30.35 157 156 SEATING PLANE PIN 1 INDICATOR TOP VIEW (PINS DOWN) 28.20 28.00 SQ 27.80 3.60 3.40 3.20 VIEW A 0.20 0.09 0.08 MAX (LEAD COPLANARITY) VIEW A ROTATED 90° CCW 52 53 105 104 0.50 0.25 0.50 BSC (LEAD PITCH) 0.27 0.17 (LEAD WIDTH) NOTES: 1. THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 FROM ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION. 2. CENTER DIMENSIONS ARE NOMINAL. 3. DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH JEDEC STANDARD MS-029, FA-1. Figure 45. 208-Lead MQFP (S-208-2) Rev. A | Page 54 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 A1 CORNER INDEX AREA 20 18 16 14 12 10 8 64 2 19 17 15 13 11 9 7 5 3 1 A1 BALL INDICATOR A B C D E F G H J K L M N P R T U V W Y BOTTOM VIEW T OP VIEW 27.00 BSC SQ DETAIL A 24.13 REF SQ 1.27 NOM 0.70 0.60 0.50 1.00 0.80 0.60 DETAIL A 1.70 MAX 0.10 MIN 0.20 COPLANARITY DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH JEDEC STANDARDS MO-192-BAL-2. BALL DIAMETER 0.90 0.75 0.60 0.25 MIN 4 SEATING PLANE Figure 46. 256-Ball SBGA, Thermally Enhanced (BP-256) SURFACE-MOUNT DESIGN Table 48 is provided as an aide to PCB design. For industrystandard design recommendations, refer to IPC-7351, Generic Requirements for Surface-Mount Design and Land Pattern Standard. Table 48. SBGA Data for Use with Surface-Mount Design Package 256-Lead Ball Grid Array SBGA (BP-256) Ball Attach Type Solder Mask Defined (SMD) Solder Mask Opening 0.63 Ball Pad Size 0.73 Rev. A | Page 55 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 ORDERING GUIDE Operating Voltage Package Internal/External Description 1.2 V/3.3 V 1.3 V/3.3 V 1.3 V/3.3 V 1.3 V/3.3 V 1.3 V/3.3 V 1.3 V/3.3 V 1.3 V/3.3 V 1.3 V/3.3 V 1.3 V/3.3 V 1.2 V/3.3 V 1.3 V/3.3 V 1.3 V/3.3 V 1.3 V/3.3 V 1.3 V/3.3 V 208-Lead MQFP 256-Ball SBGA 256-Ball SBGA 256-Ball SBGA 256-Ball SBGA 256-Ball SBGA 256-Ball SBGA 256-Ball SBGA 256-Ball SBGA 208-Lead MQFP 256-Ball SBGA 256-Ball SBGA 256-Ball SBGA 256-Ball SBGA Part Number ADSP-21367KSZ-1A2, 3 ADSP-21367KBP-2A ADSP-21367BBP-2A ADSP-21367BBPZ-2A ADSP-21368KBP-2A ADSP-21368KBPZ-2A ADSP-21368BBP-2A ADSP-21368BBPZ-2A ADSP-21369KSZ-1A2 ADSP-21369KBP-2A ADSP-21369KBPZ-2A ADSP-21369BBP-2A ADSP-21369BBPZ-2A 1 Temperature Range 1 0°C to +70°C 0°C to +70°C 0°C to +70°C –40°C to +85°C 2 3 Instruction On-Chip Rate SRAM 266 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 266 MHz 333 MHz 333 MHz 333 MHz 333 MHz 2M bit 2M bit 2M bit 2M bit 2M bit 2M bit 2M bit 2M bit 2M bit 2M bit 2M bit 2M bit 2M bit 2M bit ROM 6M bit 6M bit 6M bit 6M bit 6M bit 6M bit 6M bit 6M bit 6M bit 6M bit 6M bit 6M bit 6M bit 6M bit Package Option S-208-2 BP-256 BP-256 BP-256 BP-256 BP-256 BP-256 BP-256 BP-256 S-208-2 BP-256 BP-256 BP-256 BP-256 ADSP-21367KBPZ-2A2, 3 –40°C to +85°C 0°C to +70°C 0°C to +70°C –40°C to +85°C –40°C to +85°C 0°C to +70°C 0°C to +70°C 2 2 2 0°C to +70°C –40°C to +85°C –40°C to +85°C 2 Referenced temperature is ambient temperature. 2 Z = Pb-free part. 3 Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at www.analog.com/SHARC. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05267-0-8/06(A) Rev. A | Page 56 of 56 | August 2006