SHARC Processor
ADSP-21369
SUMMARY
DEDICATED AUDIO COMPONENTS
High performance 32-bit/40-bit floating-point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—2M bits of on-chip SRAM and 6M bits of
on-chip mask programmable ROM
Code compatible with all other members of the SHARC family
400 MHz core instruction rate with unique audiocentric
peripherals such as the digital applications interface,
S/PDIF transceiver, serial ports, 8-channel asynchronous
sample rate converter, precision clock generators, and
more. For complete ordering information, see Ordering
Guide.
S/PDIF-compatible digital audio receiver/transmitter
4 independent asynchronous sample rate converters (SRC)
16 PWM outputs configured as four groups of four outputs
ROM-based security features include
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multiplier/divider ratios
Available in 256-ball BGA_ED and 208-lead LQFP_EP
packages
Internal Memory
SIMD Core
Instruction
Cache
Block 0
RAM/ROM
Block 2
RAM
Block 3
RAM
5 stage
Sequencer
DAG1/2
Timer
PEx
PEy
S
DMD
64-BIT
B0D
64-BIT
B1D
64-BIT
B2D
64-BIT
B3D
64-BIT
DMD 64-BIT
Core Bus
Cross Bar
PMD
64-BIT
FLAGx/IRQx/
TMREXP
Block 1
RAM/ROM
Internal Memory I/F
PMD 64-BIT
IOD0 32-BIT
EPD BUS 32-BIT
JTAG
PERIPHERAL BUS
32-BIT
IOD1
32-BIT
IOD0 BUS
MTM
PERIPHERAL BUS
CORE PCG
FLAGS C-D
TIMER
2-0
TWI
EP
SPI/B
UART
1-0
DPI Routing/Pins
S/PDIF PCG
Tx/Rx A-D
ASRC IDP/ SPORT
7-0
3-0 PDAP
7-0
DAI Routing/Pins
DPI Peripherals
DAI Peripherals
CORE PWM
FLAGS 3-0
AMI
SDRAM
External Port Pin MUX
Peripherals
External
Port
Figure 1. Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. H
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ADSP-21369
TABLE OF CONTENTS
General Description ................................................. 3
Maximum Power Dissipation ................................. 17
SHARC Family Core Architecture ............................ 4
Absolute Maximum Ratings ................................... 18
Family Peripheral Architecture ................................ 7
Timing Specifications ........................................... 18
I/O Processor Features ......................................... 10
Output Drive Currents ......................................... 50
System Design .................................................... 10
Test Conditions .................................................. 50
Development Tools ............................................. 11
Capacitive Loading .............................................. 50
Additional Information ........................................ 12
Thermal Characteristics ........................................ 52
Related Signal Chains .......................................... 12
256-Ball BGA_ED Pinout ......................................... 53
Pin Function Descriptions ....................................... 13
208-Lead LQFP_EP Pinout ....................................... 56
Specifications ........................................................ 16
Package Dimensions ............................................... 58
Operating Conditions .......................................... 16
Surface-Mount Design .......................................... 59
Electrical Characteristics ....................................... 17
Ordering Guide ..................................................... 60
ESD Caution ...................................................... 17
REVISION HISTORY
3/2019—Rev. G to Rev. H
Deleted obsolete models ADSP-21367 and ADSP-21368
throughout data sheet.
Reorganized layout of data sheet.
Rev. H |
Page 2 of 60 |
March 2019
ADSP-21369
GENERAL DESCRIPTION
The ADSP-21369 SHARC® processor is a member of the SIMD
SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. These processors are source code-compatible
with the ADSP-2126x and ADSP-2116x DSPs as well as with
first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. The processors are 32bit/40-bit floating-point processors optimized for high performance automotive audio applications with its large on-chip
SRAM, mask programmable ROM, multiple internal buses to
eliminate I/O bottlenecks, and an innovative digital applications
interface (DAI).
As shown in the functional block diagram on Page 1, the
processor uses two computational units to deliver a significant
performance increase over the previous SHARC processors on a
range of DSP algorithms. Fabricated in a state-of-the-art, high
speed, CMOS process, the processor achieves an instruction
cycle time of up to 2.5 ns at 400 MHz. With its SIMD computational hardware, the processor can perform 2.4 GFLOPS
running at 400 MHz.
Table 2. Product Features (Continued)
ADSP-21369
DPI
Yes
S/PDIF Transceiver
1
AMI Interface Bus Width
32 bits/16 bits/8 bits
SPI
2
TWI
Yes
SRC Performance
128 dB
Shared Memory Support
256-Ball BGA only
Package
256-Ball BGA, 208-Lead LQFP_EP
The diagram on Page 1 shows the two clock domains. The core
clock domain contains the following features.
• Two processing elements (PEx, PEy), each of which comprises an ALU, multiplier, shifter, and data register file
Table 1 shows performance benchmarks for the ADSP-21369
processor.
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
Table 1. Processor Benchmarks (at 400 MHz)
Speed
Benchmark Algorithm
(at 400 MHz)
1024 Point Complex FFT (Radix 4, with Reversal) 23.2 s
FIR Filter (per Tap)1
1.25 ns
5.0 ns
IIR Filter (per Biquad)1
Matrix Multiply (Pipelined)
[3×3] × [3×1]
11.25 ns
[4×4] × [4×1]
20.0 ns
Divide (y/x)
8.75 ns
Inverse Square Root
13.5 ns
1
Feature
• PM and DM buses capable of supporting two 64-bit data
transfers between memory and the core at every core processor cycle
• One periodic interval timer with pinout
• On-chip SRAM (2M bit)
• JTAG test access port for emulation and boundary scan.
The JTAG provides software debug through user breakpoints which allows flexible exception handling.
The block diagram on Page 1 also shows the peripheral clock
domain (also known as the I/O processor) and contains the following features:
Assumes two files in multichannel SIMD mode.
• IOD0 (peripheral DMA) and IOD1 (external port DMA)
buses for 32-bit data transfers
Table 2. Product Features
• Peripheral and external port buses for core connection
Feature
ADSP-21369
Frequency
400 MHz
RAM
2M bits
ROM
6M bits
Pulse-Width Modulation
Yes
S/PDIF
Yes
• External port with an AMI and SDRAM controller
• 4 units for PWM control
• 1 MTM unit for internal-to-internal memory transfers
• Digital applications interface that includes four precision
clock generators (PCG), a input data port (IDP) for serial
and parallel interconnect, an S/PDIF receiver/transmitter,
four asynchronous sample rate converters, eight serial
ports, a flexible signal routing unit (DAI SRU).
SDRAM Memory Bus Width 32 bits/16 bits
Serial Ports
8
IDP
Yes
DAI
Yes
UART
2
• Digital peripheral interface that includes three timers, a 2wire interface, two UARTs, two serial peripheral interfaces
(SPI), 2 precision clock generators (PCG) and a flexible signal routing unit (DPI SRU).
Rev. H |
Page 3 of 60 |
March 2019
ADSP-21369
SHARC FAMILY CORE ARCHITECTURE
shares architectural features with the ADSP-2126x and
ADSP-2116x SIMD SHARC processors, as shown in Figure 2
and detailed in the following sections.
The processor is code compatible at the assembly level with the
ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first
generation ADSP-2106x SHARC processors. The processor
S
JTAG
FLAG
TIMER INTERRUPT CACHE
SIMD Core
PM ADDRESS 24
DMD/PMD 64
5 STAGE
PROGRAM SEQUENCER
PM DATA 48
DAG1
16x32
DAG2
16x32
PM ADDRESS 32
SYSTEM
I/F
DM ADDRESS 32
USTAT
4x32-BIT
PM DATA 64
PX
64-BIT
DM DATA 64
MULTIPLIER
MRF
80-BIT
MRB
80-BIT
SHIFTER
ALU
RF
Rx/Fx
PEx
16x40-BIT
DATA
SWAP
RF
Sx/SFx
PEy
16x40-BIT
ASTATx
ASTATy
STYKx
STYKy
Figure 2. SHARC Core Block Diagram
Rev. H |
Page 4 of 60 |
March 2019
ALU
SHIFTER
MULTIPLIER
MSB
80-BIT
MSF
80-BIT
ADSP-21369
SIMD Computational Engine
The processor contains two computational processing elements
that operate as a single-instruction, multiple-data (SIMD)
engine. The processing elements are referred to as PEX and PEY
and each contains an ALU, multiplier, shifter, and register file.
PEX is always active, and PEY may be enabled by setting the
PEYEN mode bit in the MODE1 register. When this mode is
enabled, the same instruction is executed in both processing elements, but each processing element operates on different data.
This architecture is efficient at executing math intensive DSP
algorithms.
Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all operations in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing
elements. These computation units support IEEE 32-bit singleprecision floating-point, 40-bit extended precision floatingpoint, and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is contained in each processing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the enhanced Harvard architecture
of the ADSP-21369 processor, allow unconstrained data flow
between computation units and internal memory. The registers
in PEX are referred to as R0–R15 and in PEY as S0–S15.
Context Switch
Many of the processor’s registers have secondary registers that
can be activated during interrupt servicing for a fast context
switch. The data registers in the register file, the DAG registers,
and the multiplier result registers all have secondary registers.
The primary registers are active at reset, while the secondary
registers are activated by control bits in a mode control register.
The data bus exchange register (PX) permits data to be passed
between the 64-bit PM data bus and the 64-bit DM data bus, or
between the 40-bit register file and the PM data bus. These registers contain hardware to handle the data width difference.
Timer
A core timer that can generate periodic software Interrupts. The
core timer can be configured to use FLAG3 as a timer expired
signal.
Single-Cycle Fetch of Instruction and Four Operands
The processor features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data
(see Figure 2). With separate program and data memory buses
and on-chip instruction cache, the processors can simultaneously fetch four operands (two over each data bus) and one
instruction (from the cache), all in a single cycle.
Instruction Cache
The processors include an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
Data Address Generators with Zero-Overhead Hardware
Circular Buffer Support
The processor has two data address generators (DAGs). The
DAGs are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient
programming of delay lines and other data structures required
in digital signal processing, and are commonly used in digital
filters and Fourier transforms. The two DAGs contain sufficient
registers to allow the creation of up to 32 circular buffers
(16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reduce overhead,
increase performance, and simplify implementation. Circular
buffers can start and end at any memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations for concise programming. For example, the
ADSP-21369 processor can conditionally execute a multiply, an
add, and a subtract in both processing elements while branching
and fetching up to four 32-bit values from memory—all in a single instruction.
Universal Registers
These registers can be used for general-purpose tasks. The
USTAT (4) registers allow easy bit manipulations (Set, Clear,
Toggle, Test, XOR) for all system registers (control/status) of
the core.
Rev. H |
Page 5 of 60 |
March 2019
ADSP-21369
On-Chip Memory
The processors contain two megabits of internal RAM and six
megabits of internal mask-programmable ROM. Each block can
be configured for different combinations of code and data storage (see Table 3). Each memory block supports single-cycle,
independent accesses by the core processor and I/O processor.
The memory architecture, in combination with its separate onchip buses, allows two data transfers from the core and one
from the I/O processor, in a single cycle.
The SRAM can be configured as a maximum of 64k words of
32-bit data, 128k words of 16-bit data, 42k words of 48-bit
instructions (or 40-bit data), or combinations of different word
sizes up to two megabits. All of the memory can be accessed as
16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point
storage format is supported that effectively doubles the amount
of data that can be stored on-chip. Conversion between the
32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each memory block can
store combinations of code and data, accesses are most efficient
when one block stores data using the DM bus for transfers, and
the other block stores instructions and data using the PM bus
for transfers.
Table 3. Internal Memory Space
Using the DM bus and PM buses, with one bus dedicated to
each memory block, assures single-cycle execution with two
data transfers. In this case, the instruction must be available in
the cache.
On-Chip Memory Bandwidth
The internal memory architecture allows programs to have four
accesses at the same time to any of the four blocks (assuming
there are no block conflicts). The total bandwidth is realized
using the DMD and PMD buses (2 × 64-bit, core CLK) and the
IOD0/1 buses (2 × 32-bit, PCLK).
ROM-Based Security
The processor has a ROM security feature that provides hardware support for securing user software code by preventing
unauthorized reading from the internal code when enabled.
When using this feature, the processor does not boot-load any
external code, executing exclusively from internal ROM. Additionally, the processor is not freely accessible via the JTAG port.
Instead, a unique 64-bit key, which must be scanned in through
the JTAG or test access port will be assigned to each customer.
The device will ignore a wrong key. Emulation features and
external boot modes are only available after the correct key is
scanned.
1
IOP Registers 0x0000 0000–0x0003 FFFF
1
Long Word (64 Bits)
Extended Precision Normal or
Instruction Word (48 Bits)
Normal Word (32 Bits)
Short Word (16 Bits)
Block 0 ROM (Reserved)
0x0004 0000–0x0004 BFFF
Block 0 ROM (Reserved)
0x0008 0000–0x0008 FFFF
Block 0 ROM (Reserved)
0x0008 0000–0x0009 7FFF
Block 0 ROM (Reserved)
0x0010 0000–0x0012 FFFF
Reserved
0x0004 F000–0x0004 FFFF
Reserved
0x0009 4000–0x0009 FFFF
Reserved
0x0009 E000–0x0009 FFFF
Reserved
0x0013 C000–0x0013 FFFF
Block 0 SRAM
0x0004 C000–0x0004 EFFF
Block 0 SRAM
0x0009 0000–0x0009 3FFF
Block 0 SRAM
0x0009 8000–0x0009 DFFF
Block 0 SRAM
0x0013 0000–0x0013 BFFF
Block 1 ROM (Reserved)
0x0005 0000–0x0005 BFFF
Block 1 ROM (Reserved)
0x000A 0000–0x000A FFFF
Block 1 ROM (Reserved)
0x000A 0000–0x000B 7FFF
Block 1 ROM (Reserved)
0x0014 0000–0x0016 FFFF
Reserved
0x0005 F000–0x0005 FFFF
Reserved
0x000B 4000–0x000B FFFF
Reserved
0x000B E000–0x000B FFFF
Reserved
0x0017 C000–0x0017 FFFF
Block 1 SRAM
0x0005 C000–0x0005 EFFF
Block 1 SRAM
0x000B 0000–0x000B 3FFF
Block 1 SRAM
0x000B 8000–0x000B DFFF
Block 1 SRAM
0x0017 0000–0x0017 BFFF
Block 2 SRAM
0x0006 0000–0x0006 0FFF
Block 2 SRAM
0x000C 0000–0x000C 1554
Block 2 SRAM
0x000C 0000–0x000C 1FFF
Block 2 SRAM
0x0018 0000–0x0018 3FFF
Reserved
0x0006 1000– 0x0006 FFFF
Reserved
0x000C 1555–0x000C 3FFF
Reserved
0x000C 2000–0x000D FFFF
Reserved
0x0018 4000–0x001B FFFF
Block 3 SRAM
0x0007 0000–0x0007 0FFF
Block 3 SRAM
0x000E 0000–0x000E 1554
Block 3 SRAM
0x000E 0000–0x000E 1FFF
Block 3 SRAM
0x001C 0000–0x001C 3FFF
Reserved
0x0007 1000–0x0007 FFFF
Reserved
0x000E 1555–0x000F FFFF
Reserved
0x000E 2000–0x000F FFFF
Reserved
0x001C 4000–0x001F FFFF
The processor includes a customer-definable ROM block. Please contact your Analog Devices sales representative for additional details.
Rev. H |
Page 6 of 60 |
March 2019
ADSP-21369
FAMILY PERIPHERAL ARCHITECTURE
Table 4. External Memory for SDRAM Addresses
The processor contains a rich set of peripherals that support a
wide variety of applications including high quality audio, medical imaging, communications, military, test equipment, 3D
graphics, speech recognition, motor control, imaging, and other
applications.
Bank
Size in
Words
Address Range
Bank 0
62M
0x0020 0000–0x03FF FFFF
Bank 1
64M
0x0400 0000–0x07FF FFFF
External Port
Bank 2
64M
0x0800 0000–0x0BFF FFFF
The external port interface supports access to the external memory through core and DMA accesses. The external memory
address space is divided into four banks. Any bank can be programmed as either asynchronous or synchronous memory. The
external ports of the processor are comprised of the following
modules.
Bank 3
64M
0x0C00 0000–0x0FFF FFFF
• An Asynchronous Memory Interface which communicates
with SRAM, FLASH, and other devices that meet the standard asynchronous SRAM access protocol. The AMI
supports 14M words of external memory in bank 0 and
16M words of external memory in bank 1, bank 2, and
bank 3.
devices and DIMMs (dual inline memory module), while the
second is an asynchronous memory controller intended to
interface to a variety of memory devices. Four memory select
pins enable up to four separate devices to coexist, supporting
any desired combination of synchronous and asynchronous
device types. Non-SDRAM external memory address space is
shown in Table 5.
Table 5. External Memory for Non-SDRAM Addresses
• An SDRAM controller that supports a glueless interface
with any of the standard SDRAMs. The SDC supports 62M
words of external memory in bank 0, and 64M words of
external memory in bank 1, bank 2, and bank 3.
• Arbitration Logic to coordinate core and DMA transfers
between internal and external memory over the external
port.
• A Shared Memory Interface that allows the connection of
up to four processors to create shared external bus systems.
SDRAM Controller
The SDRAM controller provides an interface of up to four separate banks of industry-standard SDRAM devices or DIMMs, at
speeds up to fSCLK. Fully compliant with the SDRAM standard,
each bank has its own memory select line (MS0–MS3), and can
be configured to contain between 16M bytes and 128M bytes of
memory. SDRAM external memory address space is shown in
Table 4.
A set of programmable timing parameters is available to configure the SDRAM banks to support slower memory devices. The
memory banks can be configured as either 32 bits wide for maximum performance and bandwidth or 16 bits wide for
minimum device count and lower system cost.
The SDRAM controller address, data, clock, and control pins
can drive loads up to distributed 30 pF loads. For larger memory
systems, the SDRAM controller external buffer timing should
be selected and external buffering should be provided so that the
load on the SDRAM controller pins does not exceed 30 pF.
External Memory
The external port provides a high performance, glueless interface to a wide variety of industry-standard memory devices. The
32-bit wide bus can be used to interface to synchronous and/or
asynchronous memory devices through the use of its separate
internal memory controllers. The first is an SDRAM controller
for connection of industry-standard synchronous DRAM
Rev. H |
Bank
Size in
Words
Address Range
Bank 0
14M
0x0020 0000–0x00FF FFFF
Bank 1
16M
0x0400 0000–0x04FF FFFF
Bank 2
16M
0x0800 0000–0x08FF FFFF
Bank 3
16M
0x0C00 0000–0x0CFF FFFF
Shared External Memory
The ADSP-21369 processor supports connecting to common
shared external memory with other ADSP-21369 processors to
create shared external bus processor systems. This support
includes:
• Distributed, on-chip arbitration for the shared external bus
• Fixed and rotating priority bus arbitration
• Bus time-out logic
• Bus lock
Multiple processors can share the external bus with no additional arbitration logic. Arbitration logic is included on-chip to
allow the connection of up to four processors.
Bus arbitration is accomplished through the BR1–4 signals and
the priority scheme for bus arbitration is determined by the setting of the RPBA pin. Table 8 provides descriptions of the pins
used in multiprocessor systems.
External Port Throughput
The throughput for the external port, based on 166 MHz clock
and 32-bit data bus, is 221M bytes/s for the AMI and 664M
bytes/s for SDRAM.
Page 7 of 60 |
March 2019
ADSP-21369
Asynchronous Memory Controller
The asynchronous memory controller provides a configurable
interface for up to four separate banks of memory or I/O
devices. Each bank can be independently programmed with different timing parameters, enabling connection to a wide variety
of memory devices including SRAM, ROM, flash, and EPROM,
as well as I/O devices that interface with standard memory
control lines. Bank 0 occupies a 14M word window and Banks 1,
2, and 3 occupy a 16M word window in the processor’s address
space but, if not fully populated, these windows are not made
contiguous by the memory controller logic. The banks can also
be configured as 8-bit, 16-bit, or 32-bit wide buses for ease of
interfacing to a range of memories and I/O devices tailored
either to high performance or to low cost and power.
Pulse-Width Modulation
The PWM module is a flexible, programmable, PWM waveform
generator that can be programmed to generate the required
switching patterns for various applications related to motor and
engine control or audio power control. The PWM generator can
generate either center-aligned or edge-aligned PWM waveforms. In addition, it can generate complementary signals on
two outputs in paired mode or independent signals in nonpaired mode (applicable to a single group of four PWM
waveforms).
The entire PWM module has four groups of four PWM outputs
each. Therefore, this module generates 16 PWM outputs in
total. Each PWM group produces two pairs of PWM signals on
the four PWM outputs.
The PWM generator is capable of operating in two distinct
modes while generating center-aligned PWM waveforms: single
update mode or double update mode. In single update mode,
the duty cycle values are programmable only once per PWM
period. This results in PWM patterns that are symmetrical
about the midpoint of the PWM period. In double update
mode, a second updating of the PWM registers is implemented
at the midpoint of the PWM period. In this mode, it is possible
to produce asymmetrical PWM patterns that produce lower
harmonic distortion in 2-phase PWM inverters.
Digital Applications Interface (DAI)
The digital applications interface (DAI) provides the ability to
connect various peripherals to any of the DAI pins of the DSP
(DAI_P20–1). Programs make these connections using the signal routing unit (SRU1), shown in Figure 1.
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be interconnected under software control. This allows easy use of the
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with nonconfigurable signal paths.
The DAI includes eight serial ports, an S/PDIF receiver/transmitter, four precision clock generators (PCG), eight channels of
synchronous sample rate converters, and an input data port
(IDP). The IDP provides an additional input path to the
processor core, configurable as either eight channels of I2S serial
Rev. H |
data or as seven channels plus a single 20-bit wide synchronous
parallel data acquisition port. Each data channel has its own
DMA channel that is independent from the processor’s serial
ports.
For complete information on using the DAI, see the
ADSP-2137x SHARC Processor Hardware Reference.
Serial Ports
The processors feature eight synchronous serial ports (SPORTs)
that provide an inexpensive interface to a wide variety of digital
and mixed-signal peripheral devices such as Analog Devices’
AD183x family of audio codecs, ADCs, and DACs. The serial
ports are made up of two data lines, a clock, and frame sync. The
data lines can be programmed to either transmit or receive and
each data line has a dedicated DMA channel.
Serial ports are enabled via 16 programmable and simultaneous
receive or transmit pins that support up to 32 transmit or 32
receive channels of audio data when all eight SPORTs are
enabled, or eight full duplex TDM streams of 128 channels
per frame.
The serial ports operate at a maximum data rate of 50 Mbps.
Serial port data can be automatically transferred to and from
on-chip memory via dedicated DMA channels. Each of the
serial ports can work in conjunction with another serial port to
provide TDM support. One SPORT provides two transmit signals while the other SPORT provides the two receive signals.
The frame sync and clock are shared.
Serial ports operate in five modes:
• Standard DSP serial mode
• Multichannel (TDM) mode with support for packed I2S
mode
• I2S mode
• Packed I2S mode
• Left-justified sample pair mode
Left-justified sample pair mode is a mode where in each frame
sync cycle two samples of data are transmitted/received—one
sample on the high segment of the frame sync, the other on the
low segment of the frame sync. Programs have control over various attributes of this mode.
Each of the serial ports supports the left-justified sample pair
and I2S protocols (I2S is an industry-standard interface commonly used by audio codecs, ADCs, and DACs such as the
Analog Devices AD183x family), with two data pins, allowing
four left-justified sample pair or I2S channels (using two stereo
devices) per serial port, with a maximum of up to 32 I2S channels. The serial ports permit little-endian or big-endian
transmission formats and word lengths selectable from 3 bits to
32 bits. For the left-justified sample pair and I2S modes, dataword lengths are selectable between 8 bits and 32 bits. Serial
ports offer selectable synchronization and transmit modes as
well as optional -law or A-law companding selection on a per
channel basis. Serial port clocks and frame syncs can be internally or externally generated.
Page 8 of 60 |
March 2019
ADSP-21369
The serial ports also contain frame sync error detection logic
where the serial ports detect frame syncs that arrive early (for
example, frame syncs that arrive while the transmission/reception of the previous word is occurring). All the serial ports also
share one dedicated error interrupt.
S/PDIF-Compatible Digital Audio Receiver/Transmitter
The S/PDIF receiver/transmitter has no separate DMA channels. It receives audio data in serial format and converts it into a
biphase encoded signal. The serial data input to the
receiver/transmitter can be formatted as left-justified, I2S, or
right-justified with word widths of 16, 18, 20, or 24 bits.
The serial data, clock, and frame sync inputs to the S/PDIF
receiver/transmitter are routed through the signal routing unit
(SRU). They can come from a variety of sources such as the
SPORTs, external pins, the precision clock generators (PCGs),
or the sample rate converters (SRC) and are controlled by the
SRU control registers.
Synchronous/Asynchronous Sample Rate Converter
The sample rate converter (SRC) contains four SRC blocks and
is the same core as that used in the AD1896 192 kHz stereo
asynchronous sample rate converter and provides up to 128 dB
SNR. The SRC block is used to perform synchronous or asynchronous sample rate conversion across independent stereo
channels, without using internal processor resources. The four
SRC blocks can also be configured to operate together to convert multichannel audio data without phase mismatches.
Finally, the SRC can be used to clean up audio data from jittery
clock sources such as the S/PDIF receiver.
Serial Peripheral (Compatible) Interface
The processors contain two serial peripheral interface ports
(SPIs). The SPI is an industry-standard synchronous serial link,
enabling the SPI-compatible port to communicate with other
SPI-compatible devices. The SPI consists of two data pins, one
device select pin, and one clock pin. It is a full-duplex
synchronous serial interface, supporting both master and slave
modes. The SPI port can operate in a multimaster environment
by interfacing with up to four other SPI-compatible devices,
either acting as a master or slave device. The SPI-compatible
peripheral implementation also features programmable baud
rate and clock phase and polarities. The SPI-compatible port
uses open-drain drivers to support a multimaster configuration
and to avoid data contention.
UART Port
The processors provide a full-duplex universal asynchronous
receiver/transmitter (UART) port, which is fully compatible
with PC-standard UARTs. The UART port provides a simplified UART interface to other peripherals or hosts, supporting
full-duplex, DMA-supported, asynchronous transfers of serial
data. The UART also has multiprocessor communication capability using 9-bit address detection. This allows it to be used in
multidrop networks through the RS-485 data interface
standard. The UART port also includes support for five data bits
to eight data bits, one stop bit or two stop bits, and none, even,
or odd parity. The UART port supports two modes of
operation:
• PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
Input Data Port
The IDP provides up to eight serial input channels—each with
its own clock, frame sync, and data inputs. The eight channels
are automatically multiplexed into a single 32-bit by eight-deep
FIFO. Data is always formatted as a 64-bit frame and divided
into two 32-bit words. The serial protocol is designed to receive
audio channels in I2S, left-justified sample pair, or right-justified mode. One frame sync cycle indicates one 64-bit left/right
pair, but data is sent to the FIFO as 32-bit words (that is, onehalf of a frame at a time). The processor supports 24- and 32-bit
I2S, 24- and 32-bit left-justified, and 24-, 20-, 18- and 16-bit
right-justified formats.
• DMA (direct memory access) – The DMA controller transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
The UART port’s baud rate, serial data format, error code generation and status, and interrupts are programmable:
• Supporting bit rates ranging from (fSCLK/1,048,576) to
(fSCLK/16) bits per second.
Precision Clock Generators
• Supporting data formats from 7 bits to 12 bits per frame.
The precision clock generators (PCG) consist of four units, each
of which generates a pair of signals (clock and frame sync)
derived from a clock input signal. The units, A B, C, and D, are
identical in functionality and operate independently of each
other. The two signals generated by each unit are normally used
as a serial bit clock/frame sync pair.
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
Where the 16-bit UART_Divisor comes from the DLH register
(most significant eight bits) and DLL register (least significant
eight bits).
In conjunction with the general-purpose timer functions, autobaud detection is supported.
Digital Peripheral Interface (DPI)
The digital peripheral interface provides connections to two
serial peripheral interface ports (SPI), two universal asynchronous receiver-transmitters (UARTs), a 2-wire interface (TWI),
12 flags, and three general-purpose timers.
Rev. H |
Page 9 of 60 |
March 2019
ADSP-21369
Peripheral Timers
Delay Line DMA
Three general-purpose timers can generate periodic interrupts
and be independently set to operate in one of three modes:
The processor provides delay line DMA functionality. This
allows processor reads and writes to external delay line buffers
(in external memory, SRAM, or SDRAM) with limited core
interaction.
• Pulse waveform generation mode
• Pulse width count/capture mode
SYSTEM DESIGN
• External event watchdog mode
Each general-purpose timer has one bidirectional pin and four
registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register,
and a 32-bit pulse width register. A single control and status
register enables or disables all three general-purpose timers
independently.
2-Wire Interface Port (TWI)
The TWI is a bidirectional 2-wire serial bus used to move 8-bit
data while maintaining compliance with the I2C bus protocol.
The TWI master incorporates the following features:
• Simultaneous master and slave operation on multiple
device systems with support for multimaster data
arbitration
The following sections provide an introduction to system design
options and power supply issues.
Program Booting
The internal memory of the processors can be booted up at system power-up from an 8-bit EPROM via the external port, an
SPI master or slave, or an internal boot. Booting is determined
by the boot configuration (BOOT_CFG1–0) pins (see Table 7
and the processor hardware reference). Selection of the boot
source is controlled via the SPI as either a master or slave device,
or it can immediately begin executing from ROM.
Table 7. Boot Mode Selection
BOOT_CFG1–0
00
01
10
11
• Digital filtering and timed event processing
• 7-bit and 10-bit addressing
• 100 kbps and 400 kbps data rates
• Low interrupt rate
Booting Mode
SPI Slave Boot
SPI Master Boot
EPROM/FLASH Boot
No boot (processor executes from
internal ROM after reset)
I/O PROCESSOR FEATURES
The I/O processor provides many channels of DMA, and controls the extensive set of peripherals described in the previous
sections.
DMA Controller
The processor’s on-chip DMA controller allows data transfers
without processor intervention. The DMA controller operates
independently and invisibly to the processor core, allowing
DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur
between the processor’s internal memory and its serial ports, the
SPI-compatible (serial peripheral interface) ports, the IDP
(input data port), the parallel data acquisition port (PDAP), or
the UART.
Thirty four channels of DMA are available on the ADSP-2136x
processors as shown in Table 6.
Table 6. DMA Channels
Peripheral
SPORTs
PDAP
SPI
UART
External Port
Memory-to-Memory
DMA Channels
16
8
2
4
2
2
Rev. H |
Power Supplies
The processors have separate power supply connections for the
internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS) power
supplies. The internal and analog supplies must meet the 1.3 V
requirement for the 400 MHz device and 1.2 V for the
333 MHz and 266 MHz devices. The external supply must meet
the 3.3 V requirement. All external supply pins must be connected to the same power supply.
Note that the analog supply pin (AVDD) powers the processor’s
internal clock generator PLL. To produce a stable clock, it is recommended that PCB designs use an external filter circuit for the
AVDD pin. Place the filter components as close as possible to the
AVDD/AVSS pins. For an example circuit, see Figure 3. (A recommended ferrite chip is the muRata BLM18AG102SN1D). To
reduce noise coupling, the PCB should use a parallel pair of
power and ground planes for VDDINT and GND. Use wide traces
to connect the bypass capacitors to the analog power (AVDD) and
ground (AVSS) pins. Note that the AVDD and AVSS pins specified in
Figure 3 are inputs to the processor and not the analog ground
plane on the board—the AVSS pin should connect directly to digital ground (GND) at the chip.
Page 10 of 60 |
March 2019
ADSP-21369
100nF
10nF
1nF
ADSP-213xx
AVDD
VDDINT
HI-Z FERRITE
BEAD CHIP
emulation capabilities and other evaluation and development
features. Also available are various EZ-Extenders®, which are
daughter cards delivering additional specialized functionality,
including audio and video processing. For more information
visit www.analog.com and search on “ezkit” or “ezextender”.
EZ-KIT Lite Evaluation Kits
AVSS
LOCATE ALL COMPONENTS
CLOSE TO AVDD AND AVSS PINS
Figure 3. Analog Power (AVDD) Filter Circuit
Target Board JTAG Emulator Connector
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the processor to monitor and control the target board processor during emulation.
Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and
modification of memory, registers, and processor stacks. The
processor’s JTAG interface ensures that the emulator will not
affect target system loading or timing.
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appropriate “Emulator Hardware User’s Guide.”
DEVELOPMENT TOOLS
Analog Devices supports its processors with a complete line of
software and hardware development tools, including integrated
development environments (which include CrossCore® Embedded Studio and/or VisualDSP++®), evaluation products,
emulators, and a wide variety of software add-ins.
Integrated Development Environments (IDEs)
For a cost-effective way to learn more about developing with
Analog Devices processors, Analog Devices offer a range of EZKIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT
Lite evaluation board, directions for downloading an evaluation
version of the available IDE(s), a USB cable, and a power supply.
The USB controller on the EZ-KIT Lite board connects to the
USB port of the user’s PC, enabling the chosen IDE evaluation
suite to emulate the on-board processor in-circuit. This permits
the customer to download, execute, and debug programs for the
EZ-KIT Lite system. It also supports in-circuit programming of
the on-board Flash device to store user-specific boot code,
enabling standalone operation. With the full version of CrossCore Embedded Studio or VisualDSP++ installed (sold
separately), engineers can develop software for supported EZKITs or any custom system utilizing supported Analog Devices
processors.
Software Add-Ins for CrossCore Embedded Studio
Analog Devices offers software add-ins which seamlessly integrate with CrossCore Embedded Studio to extend its capabilities
and reduce development time. Add-ins include board support
packages for evaluation hardware, various middleware packages, and algorithmic modules. Documentation, help,
configuration dialogs, and coding examples present in these
add-ins are viewable through the CrossCore Embedded Studio
IDE once the add-in is installed.
Board Support Packages for Evaluation Hardware
For C/C++ software writing and editing, code generation, and
debug support, Analog Devices offers two IDEs.
The newest IDE, CrossCore Embedded Studio, is based on the
EclipseTM framework. Supporting most Analog Devices processor families, it is the IDE of choice for future processors,
including multicore devices. CrossCore Embedded Studio
seamlessly integrates available software add-ins to support real
time operating systems, file systems, TCP/IP stacks, USB stacks,
algorithmic software modules, and evaluation hardware board
support packages. For more information visit
www.analog.com/cces.
Software support for the EZ-KIT Lite evaluation boards and EZExtender daughter cards is provided by software add-ins called
Board Support Packages (BSPs). The BSPs contain the required
drivers, pertinent release notes, and select example code for the
given evaluation hardware. A download link for a specific BSP is
located on the web page for the associated EZ-KIT or EZExtender product. The link is found in the Product Download
area of the product web page.
The other Analog Devices IDE, VisualDSP++, supports processor families introduced prior to the release of CrossCore
Embedded Studio. This IDE includes the Analog Devices VDK
real time operating system and an open source TCP/IP stack.
For more information visit www.analog.com/visualdsp. Note
that VisualDSP++ will not support future Analog Devices
processors.
EZ-KIT Lite Evaluation Board
For processor evaluation, Analog Devices provides wide range
of EZ-KIT Lite® evaluation boards. Including the processor and
key peripherals, the evaluation board also supports on-chip
Rev. H |
Page 11 of 60 |
March 2019
ADSP-21369
Middleware Packages
RELATED SIGNAL CHAINS
Analog Devices separately offers middleware add-ins such as
real time operating systems, file systems, USB stacks, and
TCP/IP stacks. For more information see the following web
pages:
A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena.
• www.analog.com/ucos2
• www.analog.com/ucos3
• www.analog.com/ucfs
Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together well. A tool for viewing relationships between
specific applications and related components is available on the
www.analog.com website.
• www.analog.com/ucusbd
• www.analog.com/ucusbh
• www.analog.com/lwip
Algorithmic Modules
To speed development, Analog Devices offers add-ins that perform popular audio and video processing algorithms. These are
available for use with both CrossCore Embedded Studio and
VisualDSP++. For more information visit www.analog.com and
search on “Blackfin software modules” or “SHARC software
modules”.
The application signal chains page in the Circuits from the Lab®
site (http:\\www.analog.com\circuits) provides:
• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
• Drill down links for components in each chain to selection
guides and application information
• Reference designs applying best practice design techniques
Designing an Emulator-Compatible DSP Board (Target)
For embedded system test and debug, Analog Devices provides
a family of emulators. On each JTAG DSP, Analog Devices supplies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit
emulation is facilitated by use of this JTAG interface. The emulator accesses the processor’s internal features via the
processor’s TAP, allowing the developer to load code, set breakpoints, and view variables, memory, and registers. The
processor must be halted to send data and commands, but once
an operation is completed by the emulator, the DSP system is set
to run at full speed with no impact on system timing. The emulators require the target board to include a header that supports
connection of the JTAG port of the DSP to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal termination, and emulator pod logic, see “Analog Devices JTAG
Emulation Technical Reference” (EE-68). This document is
updated regularly to keep pace with improvements to emulator
support.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the
architecture and functionality of the ADSP-21369 processor.
For detailed information on the ADSP-2136x family core architecture and instruction set, refer to the ADSP-2137x SHARC
Processor Hardware Reference and the SHARC Processor Programming Reference.
Rev. H |
Page 12 of 60 |
March 2019
ADSP-21369
PIN FUNCTION DESCRIPTIONS
The following symbols appear in the Type column of Table 8:
A = asynchronous, G = ground, I = input, O = output,
O/T = output three-state, P = power supply, S = synchronous,
(A/D) = active drive, (O/D) = open-drain, (pd) = pull-down
resistor, (pu) = pull-up resistor.
The ADSP-21369 SHARC processors use extensive pin multiplexing to achieve a lower pin count. For complete information
on the multiplexing scheme, see the ADSP-2137x SHARC Processor Hardware Reference, “System Design” chapter.
Table 8. Pin Descriptions
State During/
After Reset
(ID = 00x)
Description
Name
Type
ADDR23–0
O/T (pu)1
Pulled high/
driven low
External Address. The processors output addresses for external memory and peripherals on these pins.
DATA31–0
I/O (pu)1
Pulled high/
pulled high
External Data. Data pins can be multiplexed to support external memory interface data
(I/O), the PDAP (I), FLAGS (I/O), and PWM (O). After reset, all DATA pins are in EMIF mode
and FLAG(0-3) pins are in FLAGS mode (default). When configured using the IDP_PDAP_CTL register, IDP Channel 0 scans the external port data pins for parallel input data.
ACK
I (pu)1
MS0–1
O/T (pu)1
Pulled high/
driven high
Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corresponding banks of external memory. The MS3-0 lines are decoded memory address lines
that change at the same time as the other address lines. When no external memory access
is occurring, the MS3-0 lines are inactive; they are active, however, when a conditional
memory access instruction is executed, whether or not the condition is true.
The MS1 pin can be used in EPORT/FLASH boot mode. See the processor hardware
reference for more information.
RD
O/T (pu)1
Pulled high/
driven high
External Port Read Enable. RD is asserted whenever the processors read a word from
external memory.
WR
O/T (pu)1
Pulled high/
driven high
External Port Write Enable. WR is asserted when the processors write a word to external
memory.
FLAG[0]/IRQ0
I/O
FLAG[0] INPUT
FLAG0/Interrupt Request 0.
FLAG[1]/IRQ1
I/O
FLAG[1] INPUT
FLAG1/Interrupt Request 1.
FLAG[2]/IRQ2/
MS2
I/O with programmable pu
(for MS mode)
FLAG[2] INPUT
FLAG2/Interrupt Request 2/Memory Select 2.
FLAG[3]/
TMREXP/MS3
I/O with programmable pu
(for MS mode)
FLAG[3] INPUT
FLAG3/Timer Expired/Memory Select 3.
Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an
external memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access.
Rev. H |
Page 13 of 60 |
March 2019
ADSP-21369
Table 8. Pin Descriptions (Continued)
State During/
After Reset
(ID = 00x)
Description
Name
Type
SDRAS
O/T (pu)1
Pulled high/
driven high
SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other
SDRAM command pins, defines the operation for the SDRAM to perform.
SDCAS
O/T (pu)1
Pulled high/
driven high
SDRAM Column Address Select. Connect to SDRAM’s CAS pin. In conjunction with other
SDRAM command pins, defines the operation for the SDRAM to perform.
SDWE
O/T (pu)1
Pulled high/
driven high
SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin.
SDCKE
O/T (pu)1
Pulled high/
driven high
SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK signal.
For details, see the data sheet supplied with the SDRAM device.
SDA10
O/T (pu)1
Pulled high/
driven low
SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with nonSDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.
SDCLK0
O/T
High-Z/driving
SDRAM Clock Output 0. Clock driver for this pin differs from all other clock drivers. See
Figure 39.
SDCLK1
O/T
DAI _P20–1
I/O with programmable
pu2
Pulled high/
pulled high
Digital Applications Interface. These pins provide the physical interface to the DAI SRU.
The DAI SRU configuration registers define the combination of on-chip audiocentric
peripheral inputs or outputs connected to the pin, and to the pin’s output enable. The
configuration registers then determines the exact behavior of the pin. Any input or
output signal present in the DAI SRU may be routed to any of these pins. The DAI SRU
provides the connection from the serial ports (8), the SRC module, the S/PDIF module,
input data ports (2), and the precision clock generators (4), to the DAI_P20–1 pins. Pullups can be disabled via the DAI_PIN_PULLUP register.
DPI _P14–1
I/O with programmable
pu2
Pulled high/
pulled high
Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU.
The DPI SRU configuration registers define the combination of on-chip peripheral inputs
or outputs connected to the pin and to the pin’s output enable. The configuration
registers of these peripherals then determines the exact behavior of the pin. Any input
or output signal present in the DPI SRU may be routed to any of these pins. The DPI SRU
provides the connection from the timers (3), SPIs (2), UARTs (2), flags (12) TWI (1), and
general-purpose I/O (9) to the DPI_P14–1 pins. The TWI output is an open-drain output—
so the pins used for I2C data and clock should be connected to logic level 0. Pull-ups can
be disabled via the DPI_PIN_PULLUP register.
TDI
I (pu)
Test Data Input (JTAG). Provides serial data for the boundary scan logic.
TDO
O/T
Test Data Output (JTAG). Serial scan output of the boundary scan path.
TMS
I (pu)
Test Mode Select (JTAG). Used to control the test state machine.
TCK
I
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed
low) after power-up, or held low for proper operation of the processor
TRST
I (pu)
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after
power-up or held low for proper operation of the processor.
SDRAM Clock Output 1. Additional clock for SDRAM devices. For systems with multiple
SDRAM devices, handles the increased clock load requirements, eliminating need of offchip clock buffers. Either SDCLK1 or both SDCLKx pins can be three-stated. Clock driver
for this pin differs from all other clock drivers. See Figure 39.
The SDCLK1 signal is only available on the FCBGA package. SDCLK1 is not available on
the LQFP_EP package.
Rev. H |
Page 14 of 60 |
March 2019
ADSP-21369
Table 8. Pin Descriptions (Continued)
1
2
State During/
After Reset
(ID = 00x)
Name
Type
EMU
O (O/D, pu)
Emulation Status. Must be connected to the processor Analog Devices DSP Tools
product line of JTAG emulator target board connectors only.
CLK_CFG1–0
I
Core/CLKIN Ratio Control. These pins set the start-up clock frequency. See the processor
hardware reference for a description of the clock configuration modes.
Note that the operating frequency can be changed by programming the PLL multiplier
and divider in the PMCTL register at any time after the core comes out of reset.
CLKIN
I
Local Clock In. Used with XTAL. CLKIN is the processor’s clock input. It configures the
processors to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator.
Connecting the external clock to CLKIN while leaving XTAL unconnected configures the
processor to use an external clock such as an external clock oscillator. CLKIN may not be
halted, changed, or operated below the specified frequency.
XTAL
O
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal.
RESET
I
Processor Reset. Resets the processor to a known state. Upon deassertion, there is a 4096
CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution
from the hardware reset vector address. The RESET input must be asserted (low) at powerup.
RESETOUT
O
BOOT_CFG1–0
I
BR4–1
I/O (pu)1
ID2–0
I (pd)
Processor ID. Determines which bus request (BR4–1) is used by the processor. ID = 001
corresponds to BR1, ID = 010 corresponds to BR2, and so on. Use ID = 000 or 001 in singleprocessor systems. These lines are a system configuration selection that should be
hardwired or only changed at reset. ID = 101,110, and 111 are reserved.
RPBA
I (pu)1
Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for
external bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal
is a system configuration selection which must be set to the same value on every
processor in the system.
Driven low/
driven high
Description
Reset Out. Drives out the core reset signal to an external device.
Boot Configuration Select. These pins select the boot mode for the processor. The
BOOT_CFG pins must be valid before reset is asserted. See the processor hardware
reference for a description of the boot modes.
Pulled high/
pulled high
External Bus Request. Used to arbitrate for bus mastership. A processor only drives its
own BRx line (corresponding to the value of its ID2-0 inputs) and monitors all others. In a
system with less than four processors, the unused BRx pins should be tied high; the processor’s own BRx line must not be tied high or low because it is an output.
The pull-up is always enabled.
Pull-up can be enabled/disabled, value of pull-up cannot be programmed.
Rev. H |
Page 15 of 60 |
March 2019
ADSP-21369
SPECIFICATIONS
OPERATING CONDITIONS
366 MHz
350 MHz
400 MHz
Parameter1 Description
333 MHz
266 MHz
Min
Max
Min
Max
Min
Max
Unit
1.25
1.35
1.235
1.365
1.14
1.26
V
VDDINT
Internal (Core) Supply Voltage
AVDD
Analog (PLL) Supply Voltage
1.25
1.35
1.235
1.365
1.14
1.26
V
VDDEXT
External (I/O) Supply Voltage
3.13
3.47
3.13
3.47
3.13
3.47
V
High Level Input Voltage @ VDDEXT = Max
2.0
VDDEXT + 0.5
2.0
VDDEXT + 0.5
2.0
VDDEXT + 0.5
V
Low Level Input Voltage @ VDDEXT = Min
–0.5
+0.8
–0.5
+0.8
–0.5
+0.8
V
VIH
VIL
2
2
3
High Level Input Voltage @ VDDEXT = Max
1.74
VDDEXT + 0.5
1.74
VDDEXT + 0.5
1.74
VDDEXT + 0.5
V
VIL_CLKIN3
Low Level Input Voltage @ VDDEXT = Min
–0.5
+1.1
–0.5
+1.1
–0.5
+1.1
V
TJ
Junction Temperature 208-Lead LQFP_EP @
TAMBIENT 0C to 70C
0
95
0
110
0
110
C
Junction Temperature 208-Lead LQFP_EP @
TAMBIENT –40C to +85C
N/A
N/A
N/A
N/A
–40
+120
C
TJ
Junction Temperature 256-Ball BGA_ED @
TAMBIENT 0C to 70C
0
95
N/A
N/A
0
105
C
TJ
Junction Temperature 256-Ball BGA_ED @
TAMBIENT –40C to +85C
N/A
N/A
N/A
N/A
–40
+105
C
VIH_CLKIN
TJ
1
Specifications subject to change without notice.
Applies to input and bidirectional pins: DATAx, ACK, RPBA, BRx, IDx, FLAGx, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RESET, TCK, TMS, TDI, TRST.
3
Applies to input pin CLKIN.
2
Rev. H |
Page 16 of 60 |
March 2019
ADSP-21369
ELECTRICAL CHARACTERISTICS
Parameter
Description
Test Conditions
Min
VOH1
Max
Unit
High Level Output Voltage
@ VDDEXT = Min, IOH = –1.0 mA2
2.4
Low Level Output Voltage
@ VDDEXT = Min, IOL = 1.0 mA2
0.4
V
High Level Input Current
@ VDDEXT = Max, VIN = VDDEXT Max
10
μA
Low Level Input Current
@ VDDEXT = Max, VIN = 0 V
10
μA
High Level Input Current Pull-Down
@ VDDEXT = Max, VIN = 0 V
250
μA
Low Level Input Current Pull-Up
@ VDDEXT = Max, VIN = 0 V
200
μA
7, 8
Three-State Leakage Current
@ VDDEXT = Max, VIN = VDDEXT Max
10
μA
7, 9
Three-State Leakage Current
@ VDDEXT = Max, VIN = 0 V
10
μA
VOL
1
IIH3, 4
IIL
3, 5, 6
IIHPD
5
IILPU4
IOZH
IOZL
8
Typ
V
Three-State Leakage Current Pull-Up
@ VDDEXT = Max, VIN = 0 V
IDD-INTYP10
Supply Current (Internal)
tCCLK = 3.75 ns, VDDINT = 1.2 V, 25°C
tCCLK = 3.00 ns, VDDINT = 1.2 V, 25°C
tCCLK = 2.85 ns, VDDINT = 1.3 V, 25°C
tCCLK = 2.73 ns, VDDINT = 1.3 V, 25°C
tCCLK = 2.50 ns, VDDINT = 1.3 V, 25°C
AIDD11
Supply Current (Analog)
AVDD = Max
11
mA
Input Capacitance
fIN = 1 MHz, TCASE = 25°C, VIN = 1.3 V
4.7
pF
IOZLPU
CIN
12
200
μA
mA
mA
mA
mA
mA
700
900
1050
1080
1100
1
Applies to output and bidirectional pins: ADDRx, DATAx, RD, WR, MSx, BRx, FLAGx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDCLKx, EMU, TDO.
See Output Drive Currents for typical drive current capabilities.
3
Applies to input pins without internal pull-ups: BOOT_CFGx, CLK_CFGx, CLKIN, RESET, TCK.
4
Applies to input pins with internal pull-ups: ACK, RPBA, TMS, TDI, TRST.
5
Applies to input pins with internal pull-downs: IDx.
6
Applies to input pins with internal pull-ups disabled: ACK, RPBA.
7
Applies to three-statable pins without internal pull-ups: FLAGx, SDCLKx, TDO.
8
Applies to three-statable pins with internal pull-ups: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, EMU.
9
Applies to three-statable pins with internal pull-ups disabled: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10
10
See the Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-21368 SHARC Processors” (EE-299) for further information.
11
Characterized, but not tested.
12
Applies to all signal pins.
2
ESD CAUTION
MAXIMUM POWER DISSIPATION
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
Rev. H |
See the Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-21368 SHARC Processors” (EE-299) for detailed
thermal and power information regarding maximum power dissipation. For information on package thermal specifications, see
Thermal Characteristics.
Page 17 of 60 |
March 2019
ADSP-21369
ABSOLUTE MAXIMUM RATINGS
Voltage Controlled Oscillator
Stresses at or above those listed in Table 9 may cause permanent
damage to the product. This is a stress rating only; functional
operation of the product at these or any other conditions above
those indicated in the operational section of this specification is
not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
In application designs, the PLL multiplier value should be
selected in such a way that the VCO frequency never exceeds
fVCO specified in Table 12.
• The product of CLKIN and PLLM must never exceed 1/2 of
fVCO (max) in Table 12 if the input divider is not enabled
(INDIV = 0).
• The product of CLKIN and PLLM must never exceed fVCO
(max) in Table 12 if the input divider is enabled
(INDIV = 1).
Table 9. Absolute Maximum Ratings
Parameter
Internal (Core) Supply Voltage (VDDINT)
Analog (PLL) Supply Voltage (AVDD)
External (I/O) Supply Voltage (VDDEXT)
Input Voltage
Output Voltage Swing
Load Capacitance
Storage Temperature Range
Junction Temperature Under Bias
Rating
–0.3 V to +1.5 V
–0.3 V to +1.5 V
–0.3 V to +4.6 V
–0.5 V to +3.8 V
–0.5 V to VDDEXT + 0.5 V
200 pF
–65C to +150C
125C
The VCO frequency is calculated as follows:
fVCO = 2 PLLM fINPUT
fCCLK = (2 PLLM fINPUT) (2 PLLD)
where:
fVCO = VCO output
PLLM = Multiplier value programmed in the PMCTL register.
During reset, the PLLM value is derived from the ratio selected
using the CLK_CFG pins in hardware.
PLLD = Divider value 1, 2, 4, or 8 based on the PLLD value programmed on the PMCTL register. During reset this value is 1.
TIMING SPECIFICATIONS
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 40 under Test Conditions for voltage reference levels.
fINPUT = CLKIN 2 when the input divider is enabled
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Table 10. Clock Periods
Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Core Clock Requirements
The processor’s internal clock (a multiple of CLKIN) provides
the clock signal for timing internal memory, processor core, and
serial ports. During reset, program the ratio between the processor’s internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG1–0 pins.
fINPUT = Input frequency to the PLL.
fINPUT = CLKIN when the input divider is disabled or
Note the definitions of the clock periods that are a function of
CLKIN and the appropriate ratio control shown in and
Table 10. All of the timing specifications for the ADSP-2136x
peripherals are defined in relation to tPCLK. See the peripheral specific timing section for timing information for each peripheral.
Timing
Requirements
tCK
tCCLK
tPCLK
Figure 4 shows core to CLKIN relationships with external oscillator or crystal. The shaded divider/multiplier blocks denote
where clock ratios can be set through hardware or software
using the power management control register (PMCTL). For
more information, see the processor hardware reference.
The processor’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL,
see Figure 4). This PLL-based clocking minimizes the skew
between the system clock (CLKIN) signal and the processor’s
internal clock.
Rev. H |
Description
CLKIN Clock Period
Processor Core Clock Period
Peripheral Clock Period = 2 × tCCLK
Page 18 of 60 |
March 2019
ADSP-21369
PMCTL
(SDCKR)
PMCTL
(PLLBP)
CLKIN
DIVIDER
fINPUT
LOOP
FILTER
fVCO
VCO
PLL
DIVIDER
fCCLK
XTAL
CCLK
SDRAM
DIVIDER
BYPASS
MUX
CLKIN
BYPASS
MUX
PLL
PMCTL
(2xPLLD)
BUF
PMCTL
(INDIV)
PLL
MULTIPLIER
DIVIDE
BY 2
PMCTL
(PLLBP)
SDCLK
PCLK
PCLK
CLK_CFGx/PMCTL (2xPLLM)
CCLK
PIN MUX
CLKOUT (TEST ONLY)
DELAY OF
4096 CLKIN
CYCLES
Figure 4. Core Clock and System Clock Relationship to CLKIN
Rev. H |
Page 19 of 60 |
March 2019
BUF
ADSP-21369
Power-Up Sequencing
driven low before power up is complete. This leakage current
results from the weak internal pull-up resistor on this pin being
enabled during power-up.
The timing requirements for processor start-up are given in
Table 11. Note that during power-up, a leakage current of
approximately 200μA may be observed on the RESET pin if it is
Table 11. Power-Up Sequencing Timing Requirements (Processor Start-up)
Parameter
Timing Requirements
tRSTVDD
tIVDDEVDD
tCLKVDD1
tCLKRST
tPLLRST
Switching Characteristic
tCORERST
Min
RESET Low Before VDDINT/VDDEXT On
VDDINT On Before VDDEXT
CLKIN Valid After VDDINT/VDDEXT Valid
CLKIN Valid Before RESET Deasserted
PLL Control Setup Before RESET Deasserted
0
–50
0
102
20
Core Reset Deasserted After RESET Deasserted
4096tCK + 2 tCCLK 3, 4
1
Max
+200
200
Unit
ns
ms
ms
μs
μs
Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.2 V rails and 3.3 V rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time.
Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3
Applies after the power-up sequence is complete. Subsequent resets require RESET to be held low a minimum of four CLKIN cycles in order to properly initialize and propagate
default states at all I/O pins.
4
The 4096 cycle count depends on tsrst specification in Table 13. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles
maximum.
RESET
VDDINT
VDDEXT
tRSTVDD
tIVDDEVDD
tCLKVDD
CLKIN
tCLKRST
CLK_CFG1–0
tPLLRST
tCORERST
RESETOUT
Figure 5. Power-Up Sequencing
Rev. H |
Page 20 of 60 |
March 2019
ADSP-21369
Clock Input
Table 12. Clock Input
Parameter
Timing Requirements
tCK
CLKIN Period
tCKL
CLKIN Width Low
tCKH
CLKIN Width High
tCKRF
CLKIN Rise/Fall (0.4 V to 2.0 V)
tCCLK7 CCLK Period
VCO Frequency
fVCO8
tCKJ9, 10 CLKIN Jitter Tolerance
400 MHz1
Min
Max
366 MHz2
Min
Max
350 MHz3
Min
Max
333 MHz4
Min
Max
266 MHz5
Min
Max
156
7.51
7.51
16.396
8.11
8.11
17.146
8.51
8.51
186
91
91
22.56
11.251
11.251
2.56
100
–250
100
45
45
3
10
800
+250
2.736
100
–250
100
45
45
3
10
800
+250
2.856
100
–250
100
45
45
3
10
800
+250
1
Applies to all 400 MHz models. See Ordering Guide.
Applies to all 366 MHz models. See Ordering Guide.
3
Applies to all 350 MHz models. See Ordering Guide.
4
Applies to all 333 MHz models. See Ordering Guide.
5
Applies to all 266 MHz models. See Ordering Guide.
6
Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL.
7
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK.
8
See Figure 4 for VCO diagram.
9
Actual input jitter should be combined with ac specifications for accurate timing analysis.
10
Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
2
tCKJ
tCK
CLKIN
tCKH
tCKL
Figure 6. Clock Input
Rev. H |
Page 21 of 60 |
March 2019
3.06
100
–250
100
45
45
3
10
800
+250
3.756
100
–250
100
45
45
3
10
600
+250
Unit
ns
ns
ns
ns
ns
MHz
ps
ADSP-21369
Clock Signals
The processors can use an external clock or a crystal. See the
CLKIN pin description in Table 8. Programs can configure the
processor to use its internal clock generator by connecting the
necessary components to CLKIN and XTAL. Figure 7 shows the
component connections used for a crystal operating in fundamental mode.
Note that the clock rate is achieved using a 25 MHz crystal and a
PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock speed
of 400 MHz). To achieve the full core clock rate, programs need
to configure the multiplier bits in the PMCTL register.
ADSP-21369
CLKIN
R1
1MV *
XTAL
R2
47V *
C1
22pF
Y1
C2
22pF
25.00 MHz
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’S SPECIFICATIONS
Figure 7. 400 MHz Operation (Fundamental Mode Crystal)
Rev. H |
Page 22 of 60 |
March 2019
ADSP-21369
Reset
Table 13. Reset
Parameter
Timing Requirements
tWRST1
RESET Pulse Width Low
tSRST
RESET Setup Before CLKIN Low
1
Min
Max
Unit
4tCK
8
ns
ns
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 s while RESET is low, assuming stable
VDD and CLKIN (not including start-up time of external clock oscillator).
CLKIN
tWRST
tSRST
RESET
Figure 8. Reset
Interrupts
The following timing specification applies to the FLAG0,
FLAG1, and FLAG2 pins when they are configured as IRQ0,
IRQ1, and IRQ2 interrupts.
Table 14. Interrupts
Parameter
Timing Requirement
tIPW
IRQx Pulse Width
Min
2 × tPCLK +2
INTERRUPT
INPUTS
tIPW
Figure 9. Interrupts
Rev. H |
Page 23 of 60 |
March 2019
Max
Unit
ns
ADSP-21369
Core Timer
The following timing specification applies to FLAG3 when it is
configured as the core timer (TMREXP).
Table 15. Core Timer
Parameter
Switching Characteristic
tWCTIM
TMREXP Pulse Width
Min
Max
4 × tPCLK – 1
Unit
ns
tWCTIM
FLAG3
(TMREXP)
Figure 10. Core Timer
Timer PWM_OUT Cycle Timing
The following timing specification applies to Timer0, Timer1,
and Timer2 in PWM_OUT (pulse-width modulation) mode.
Timer signals are routed to the DPI_P14–1 pins through the
DPI SRU. Therefore, the timing specifications provided below
are valid at the DPI_P14–1 pins.
Table 16. Timer PWM_OUT Timing
Parameter
Switching Characteristic
tPWMO
Timer Pulse Width Output
Min
Max
Unit
2 × tPCLK – 1.2
2 × (231 – 1) × tPCLK
ns
tPWMO
PWM
OUTPUTS
Figure 11. Timer PWM_OUT Timing
Rev. H |
Page 24 of 60 |
March 2019
ADSP-21369
Timer WDTH_CAP Timing
The following specification applies to Timer0, Timer1, and
Timer2 in WDTH_CAP (pulse width count and capture) mode.
Timer signals are routed to the DPI_P14–1 pins through the
DPI SRU. Therefore, the specification provided in Table 17 is
valid at the DPI_P14–1 pins.
Table 17. Timer Width Capture Timing
Parameter
Switching Characteristic
tPWI
Timer Pulse Width
Min
Max
Unit
2 × tPCLK
2 × (231 – 1) × tPCLK
ns
tPWI
TIMER
CAPTURE
INPUTS
Figure 12. Timer Width Capture Timing
Pin to Pin Direct Routing (DAI and DPI)
For direct pin connections only (for example, DAI_PB01_I to
DAI_PB02_O).
Table 18. DAI/DPI Pin to Pin Routing
Parameter
Timing Requirement
tDPIO
Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid
Min
Max
Unit
1.5
12
ns
DAI_Pn
DPI_Pn
tDPIO
DAI_Pm
DPI_Pm
Figure 13. DAI/DPI Pin to Pin Direct Routing
Rev. H |
Page 25 of 60 |
March 2019
ADSP-21369
Precision Clock Generator (Direct Pin Routing)
This timing is only valid when the SRU is configured such that
the precision clock generator (PCG) takes its inputs directly
from the DAI pins (via pin buffers) and sends its outputs
directly to the DAI pins. For the other cases, where the PCG’s
inputs and outputs are not directly routed to/from DAI pins (via
pin buffers) there is no timing data available. All timing parameters and switching characteristics apply to external DAI pins
(DAI_P01–20).
Table 19. Precision Clock Generator (Direct Pin Routing)
Parameter
Min
Max
Unit
Timing Requirements
tPCGIP
Input Clock Period
tPCLK × 4
ns
tSTRIG
PCG Trigger Setup Before Falling
4.5
ns
Edge of PCG Input Clock
tHTRIG
PCG Trigger Hold After Falling
3
ns
Edge of PCG Input Clock
Switching Characteristics
tDPCGIO
PCG Output Clock and Frame Sync Active Edge
2.5
10
ns
Delay After PCG Input Clock
tDTRIGCLK
PCG Output Clock Delay After PCG Trigger
2.5 + (2.5 × tPCGIP)
10 + (2.5 × tPCGIP)
ns
tDTRIGFS
PCG Frame Sync Delay After PCG Trigger
2.5 + ((2.5 + D – PH) × tPCGIP)
10 + ((2.5 + D – PH) × tPCGIP)
ns
tPCGOW1
Output Clock Period
2 × tPCGIP – 1
ns
D = FSxDIV, and PH = FSxPHASE. For more information, see the ADSP-2137x SHARC Processor Hardware Reference, “Precision Clock Generators” chapter.
1
In normal mode.
tSTRIG
tHTRIG
DAI_Pn
DPI_Pn
PCG_TRIGx_I
DAI_Pm
DPI_Pm
PCG_EXTx_I
(CLKIN)
tPCGIP
tDPCGIO
DAI_Py
DPI_Py
PCG_CLKx_O
tDTRIGCLK
tDPCGIO
DAI_Pz
DPI_Pz
PCG_FSx_O
tDTRIGFS
Figure 14. Precision Clock Generator (Direct Pin Routing)
Rev. H |
Page 26 of 60 |
March 2019
tPCGOW
ADSP-21369
Flags
The timing specifications provided below apply to the FLAG3–0
and DPI_P14–1 pins, and the serial peripheral interface (SPI).
See Table 8 for more information on flag use.
Table 20. Flags
Parameter
Timing Requirement
FLAG3–0 IN Pulse Width
tFIPW
Switching Characteristic
tFOPW
FLAG3–0 OUT Pulse Width
Min
ns
2 × tPCLK – 1.5
ns
tFIPW
FLAG
OUTPUTS
tFOPW
Figure 15. Flags
Page 27 of 60 |
Unit
2 × tPCLK + 3
FLAG
INPUTS
Rev. H |
Max
March 2019
ADSP-21369
SDRAM Interface Timing (166 MHz SDCLK)
The 166 MHz access speed is for a single processor. When multiple ADSP-21369 processors are connected in a shared memory
system, the access speed is 100 MHz.
Table 21. SDRAM Interface Timing1
Parameter
Timing Requirements
tSSDAT
DATA Setup Before SDCLK
DATA Hold After SDCLK
tHSDAT
Switching Characteristics
tSDCLK
SDCLK Period
tSDCLKH
SDCLK Width High
tSDCLKL
SDCLK Width Low
tDCAD
Command, ADDR, Data Delay After SDCLK2
Command, ADDR, Data Hold After SDCLK2
tHCAD
tDSDAT
Data Disable After SDCLK
tENSDAT
Data Enable After SDCLK
366 MHz
Min
Max
350 MHz
Min
Max
All Other Speed
Grades
Min
Max
Unit
500
1.23
500
1.23
500
1.23
ps
ns
6.83
3
3
7.14
3
3
6.0
2.6
2.6
ns
ns
ns
ns
ns
ns
ns
4.8
1.2
4.8
1.2
5.3
1.3
4.8
1.2
5.3
1.3
5.3
1.3
The processor needs to be programmed in tSDCLK = 2.5 tCCLK mode when operated at 350 MHz, 366 MHz, and 400 MHz.
2
Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE.
1
tSDCLKH
tSDCLK
SDCLK
tSSDAT
tHSDAT
tSDCLKL
DATA (IN)
tDCAD
tENSDAT
tHCAD
DATA (OUT)
tDCAD
tHCAD
COMMAND/ADDR
(OUT)
Figure 16. SDRAM Interface Timing
Rev. H |
Page 28 of 60 |
March 2019
tDSDAT
ADSP-21369
SDRAM Interface Enable/Disable Timing (166 MHz SDCLK)
Table 22. SDRAM Interface Enable/Disable Timing1
Parameter
Switching Characteristics
tDSDC
Command Disable After CLKIN Rise
tENSDC
Command Enable After CLKIN Rise
tDSDCC
SDCLK Disable After CLKIN Rise
tENSDCC
SDCLK Enable After CLKIN Rise
tDSDCA
Address Disable After CLKIN Rise
tENSDCA
Address Enable After CLKIN Rise
1
Min
Max
Unit
2 × tPCLK + 3
ns
ns
ns
ns
ns
ns
4.0
8.5
3.8
2 × tPCLK – 4
For fCCLK = 400 MHz (SDCLK ratio = 1:2.5).
CLKIN
tDSDC
tDSDCC
tDSDCA
COMMAND
SDCLK
ADDR
tENSDC
tENSDCA
tENSDCC
COMMAND
SDCLK
ADDR
Figure 17. SDRAM Interface Enable/Disable Timing
Rev. H |
Page 29 of 60 |
March 2019
9.2
4 × tPCLK
ADSP-21369
Memory Read
Use these specifications for asynchronous interfacing to memories. These specifications apply when the processors are the bus
master accessing external memory space in asynchronous access
mode. Note that timing for ACK, DATA, RD, WR, and strobe
timing parameters only apply to asynchronous access mode.
Table 23. Memory Read
Parameter
Timing Requirements
tDAD
Address, Selects Delay to Data Valid1, 2
tDRLD
RD Low to Data Valid2
tSDS
Data Setup to RD High
tHDRH
Data Hold from RD High3, 4
tDAAK
ACK Delay from Address, Selects1, 5
tDSAK
ACK Delay from RD Low5
Min
Max
Unit
W + tSDCLK – 5.12
W – 3.2
tSDCLK – 9.5 + W
ns
ns
ns
ns
ns
W – 7.0
ns
2.5
0
Switching Characteristics
tDRHA
Address Selects Hold After RD High
RH + 0.20
tDARL
Address Selects to RD Low1
tSDCLK – 3.3
tRW
RD Pulse Width
W – 1.4
tRWR
RD High to WR, RD Low
HI + tSDCLK – 0.8
W = (number of wait states specified in AMICTLx register) × tSDCLK
RHC = (number of Read Hold Cycles specified in AMICTLx register) × tSDCLK
Where PREDIS = 0
HI = RHC (if IC = 0): Read to Read from same bank
HI = RHC+ tSDCLK (if IC > 0): Read to Read from same bank
HI = RHC + IC: Read to Read from different bank
HI = RHC + Max (IC, (4 × tSDCLK)): Read to Write from same or different bank
Where PREDIS = 1
HI = RHC + Max (IC, (4 × tSDCLK)): Read to Write from same or different bank
HI = RHC + (3 × tSDCLK): Read to Read from same bank
HI = RHC + Max (IC, (3 × tSDCLK)): Read to Read from different bank
IC = (number of idle cycles specified in AMICTLx register) × tSDCLK
H = (number of hold cycles specified in AMICTLx register) × tSDCLK
1
ns
ns
ns
ns
The falling edge of MSx is referenced.
The maximum limit of timing requirement values for tDAD and tDRLD parameters are applicable for the case where AMI_ACK is always high and when the ACK feature is not used.
3
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.
4
Data hold: User must meet tHDA or tHDRH in asynchronous access mode. See Test Conditions for the calculation of hold times given capacitive and dc loads.
5
ACK delay/setup: User must meet tDAAK, or tDSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high), user must meet tDAAK or tDSAK.
2
Rev. H |
Page 30 of 60 |
March 2019
ADSP-21369
ADDR
MSx
tDARL
tRW
tDRHA
RD
tDRLD
tSDS
tDAD
tHDRH
DATA
tRWR
tDSAK
tDAAK
ACK
WR
Figure 18. Memory Read
Rev. H |
Page 31 of 60 |
March 2019
ADSP-21369
access mode. Note that timing for ACK, DATA, RD, WR, and
strobe timing parameters only applies to asynchronous access
mode.
Memory Write
Use these specifications for asynchronous interfacing to memories. These specifications apply when the processor is the bus
master, accessing external memory space in asynchronous
Table 24. Memory Write
Parameter
Timing Requirements
ACK Delay from Address, Selects1, 2
tDAAK
tDSAK
ACK Delay from WR Low 1, 3
Switching Characteristics
tDAWH
Address, Selects to WR Deasserted2
tDAWL
Address, Selects to WR Low2
tWW
WR Pulse Width
Data Setup Before WR High
tDDWH
tDWHA
Address Hold After WR Deasserted
tDWHD
Data Hold After WR Deasserted
tWWR
WR High to WR, RD Low
tDDWR
Data Disable Before RD Low
tWDE
Data Enabled to WR Low
W = (number of wait states specified in AMICTLx register) × tSDCLK.
H = (number of hold cycles specified in AMICTLx register) × tSDCLK.
Min
Max
Unit
tSDCLK – 9.7 + W
W – 4.9
ns
ns
tSDCLK – 3.1+ W
tSDCLK – 2.7
W – 1.3
tSDCLK – 3.0+ W
H + 0.15
H + 0.02
tSDCLK – 1.5+ H
2tSDCLK – 4.11
tSDCLK – 3.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
ACK delay/setup: System must meet tDAAK, or tDSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high), user must meet tDAAK or tDSAK.
The falling edge of MSx is referenced.
3
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.
2
ADDR
MSx
tDWHA
tDAWH
tDAWL
tWW
WR
tWWR
tWDE
tDATRWH
tDDWH
DATA
tDSAK
tDWHD
tDAAK
ACK
RD
Figure 19. Memory Write
Rev. H |
Page 32 of 60 |
March 2019
tDDWR
ADSP-21369
Asynchronous Memory Interface (AMI) Enable/Disable
Use these specifications for passing bus mastership between
ADSP-21369 processors (BRx).
Table 25. AMI Enable/Disable
Parameter
Switching Characteristics
tENAMIAC
Address/Control Enable After Clock Rise
tENAMID
Data Enable After Clock Rise
tDISAMIAC
Address/Control Disable After Clock Rise
tDISAMID
Data Disable After Clock Rise
Min
tDISAMIAC
tDISAMID
ADDR, WR , RD,
MS1–0, DATA
tENAMIAC
tENAMID
Figure 20. AMI Enable/Disable
Rev. H |
Unit
8.7
0
ns
ns
ns
ns
4
tSDCLK + 4
CLKIN
ADDR , WR , RD,
MS1–0, DATA
Max
Page 33 of 60 |
March 2019
ADSP-21369
Shared Memory Bus Request
Use these specifications for passing bus mastership between
ADSP-21369 processors (BRx).
Table 26. Multiprocessor Bus Request
Parameter
Timing Requirements
tSBRI
BRx, Setup Before CLKIN High
tHBRI
BRx, Hold After CLKIN High
Switching Characteristics
tDBRO
BRx Delay After CLKIN High
BRx Hold After CLKIN High
tHBRO
Min
Max
9
0.5
ns
ns
9
1.0
CLKIN
tDBRO
tHBRO
BRX(OUT)
tSBRI
BRX(IN)
Figure 21. Shared Memory Bus Request
Rev. H |
Page 34 of 60 |
March 2019
Unit
tHBRI
ns
ns
ADSP-21369
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Serial port signals SCLK, frame sync (FS), data channel A, and
data channel B are routed to the DAI_P20–1 pins using the
SRU. Therefore, the timing specifications provided in Table 27
are valid at the DAI_P20–1 pins.
Table 27. Serial Ports—External Clock
400 MHz
366 MHz
350 MHz
Parameter
Timing Requirements
tSFSE1
FS Setup Before SCLK
(Externally Generated FS in Either
Transmit or Receive Mode)
FS Hold After SCLK
tHFSE1
(Externally Generated FS in Either
Transmit or Receive Mode)
tSDRE1
Receive Data Setup Before Receive
SCLK
tHDRE1
Receive Data Hold After SCLK
tSCLKW
SCLK Width
tSCLK
SCLK Period
Switching Characteristics
tDFSE2
FS Delay After SCLK
(Internally Generated FS in Either
Transmit or Receive Mode)
tHOFSE2
FS Hold After SCLK
(Internally Generated FS in Either
Transmit or Receive Mode)
tDDTE2
Transmit Data Delay After Transmit
SCLK
tHDTE2
Transmit Data Hold After Transmit
SCLK
1
2
Min
333 MHz
Max
Min
266 MHz
Max
Min
Max
Unit
2.5
2.5
2.5
ns
2.5
2.5
2.5
ns
1.9
2.0
2.5
ns
2.5
(tPCLK × 4) ÷ 2 – 0.5
tPCLK × 4
2.5
(tPCLK × 4) ÷ 2 – 0.5
tPCLK × 4
2.5
(tPCLK × 4) ÷ 2 – 0.5
tPCLK × 4
ns
ns
ns
10.25
2
10.25
2
7.8
2
Referenced to sample edge.
Referenced to drive edge.
Page 35 of 60 |
2
9.6
2
Rev. H |
10.25
March 2019
ns
9.8
2
ns
ns
ns
ADSP-21369
Table 28. Serial Ports—Internal Clock
Parameter
Timing Requirements
tSFSI1
FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
tHFSI1
FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
tSDRI1
Receive Data Setup Before SCLK
tHDRI1
Receive Data Hold After SCLK
Switching Characteristics
tDFSI2
FS Delay After SCLK (Internally Generated FS in Transmit Mode)
FS Hold After SCLK (Internally Generated FS in Transmit Mode)
tHOFSI2
tDFSIR2
FS Delay After SCLK (Internally Generated FS in Receive Mode)
2
tHOFSIR
FS Hold After SCLK (Internally Generated FS in Receive Mode)
tDDTI2
Transmit Data Delay After SCLK
tHDTI2
Transmit Data Hold After SCLK
3
tSCLKIW
Transmit or Receive SCLK Width
Min
Max
Unit
7
ns
2.5
ns
7
2.5
ns
ns
4
–1.0
9.75
–1.0
3.25
–1.0
2 × tPCLK – 1.5
2 × tPCLK + 1.5
ns
ns
ns
ns
ns
ns
ns
1
Referenced to the sample edge.
2
Referenced to drive edge.
3
Minimum SPORT divisor register value.
Table 29. Serial Ports—Enable and Three-State
Parameter
Switching Characteristics
tDDTEN1
Data Enable from External Transmit SCLK
tDDTTE1
Data Disable from External Transmit SCLK
1
tDDTIN
Data Enable from Internal Transmit SCLK
1
Min
Max
Unit
10
ns
ns
ns
Max
Unit
7.75
ns
2
–1
Referenced to drive edge.
Table 30. Serial Ports—External Late Frame Sync
Parameter
Switching Characteristics
Data Delay from Late External Transmit FS or External Receive
tDDTLFSE1
FS with MCE = 1, MFD = 0
1
tDDTENFS
Data Enable for MCE = 1, MFD = 0
1
Min
0.5
The tDDTLFSE and tDDTENFS parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.
Rev. H |
Page 36 of 60 |
March 2019
ns
ADSP-21369
DATA RECEIVE—INTERNAL CLOCK
DRIVE EDGE
tSCLKIW
DATA RECEIVE—EXTERNAL CLOCK
SAMPLE EDGE
DRIVE EDGE
DAI_P20–1
(SCLK)
SAMPLE EDGE
tSCLKW
DAI_P20–1
(SCLK)
tDFSI
tDFSE
tSFSI
tHOFSI
tHFSI
DAI_P20–1
(FS)
tSFSE
tHFSE
tSDRE
tHDRE
tHOFSE
DAI_P20–1
(FS)
tSDRI
tHDRI
DAI_P20–1
(DATA
CHANNEL A/B)
DAI_P20–1
(DATA
CHANNEL A/B)
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE
tSCLKIW
DATA TRANSMIT—EXTERNAL CLOCK
SAMPLE EDGE
DRIVE EDGE
DAI_P20–1
(SCLK)
tSCLKW
SAMPLE EDGE
DAI_P20–1
(SCLK)
tDFSI
tDFSE
tHOFSI
tSFSI
tHFSI
DAI_P20–1
(FS)
tSFSE
tHOFSE
DAI_P20–1
(FS)
tHDTI
tDDTI
tDDTE
tHDTE
DAI_P20–1
(DATA
CHANNEL A/B)
DAI_P20–1
(DATA
CHANNEL A/B)
Figure 22. Serial Ports
DRIVE EDGE
DRIVE EDGE
DAI_P20–1
(SCLK, EXT)
tDDTEN
tDDTTE
DAI_P20–1
(DATA
CHANNEL A/B)
DRIVE EDGE
DAI_P20–1
(SCLK, INT)
tDDTIN
DAI_P20–1
(DATA
CHANNEL A/B)
Figure 23. Enable and Three-State
Rev. H |
Page 37 of 60 |
March 2019
tHFSE
ADSP-21369
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
DAI_P20–1
(SCLK)
tSFSE/I
tHFSE/I
DAI_P20–1
(FS)
tDDTE/I
tDDTENFS
tHDTE/I
DAI_P20–1
(DATA CHANNEL
A/B)
2ND BIT
1ST BIT
tDDTLFSE
LATE EXTERNAL TRANSMIT FS
DRIVE
SAMPLE
DRIVE
DAI_P20–1
(SCLK)
tSFSE/I
tHFSE/I
DAI_P20–1
(FS)
tDDTE/I
tDDTENFS
tHDTE/I
DAI_P20–1
(DATA CHANNEL
A/B)
2ND BIT
1ST BIT
tDDTLFSE
Figure 24. External Late Frame Sync1
1
This figure reflects changes made to support left-justified sample pair mode.
Rev. H |
Page 38 of 60 |
March 2019
ADSP-21369
Input Data Port
The timing requirements for the IDP are given in Table 31. IDP
signals SCLK, frame sync (FS), and SDATA are routed to the
DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided in Table 31 are valid at the DAI_P20–1 pins.
Table 31. IDP
Parameter
Timing Requirements
tSISFS1
FS Setup Before SCLK Rising Edge
1
tSIHFS
FS Hold After SCLK Rising Edge
SDATA Setup Before SCLK Rising Edge
tSISD1
tSIHD1
SDATA Hold After SCLK Rising Edge
tIDPCLKW
Clock Width
tIDPCLK
Clock Period
1
Min
4
2.5
2.5
2.5
(tPCLK × 4) ÷ 2 – 1
tPCLK × 4
Max
Unit
ns
ns
ns
ns
ns
ns
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
tIDPCLK
SAMPLE EDGE
DAI_P20–1
(SCLK)
tIDPCLKW
tSISFS
tSIHFS
DAI_P20–1
(FS)
tSISD
tSIHD
DAI_P20–1
(SDATA)
Figure 25. IDP Master Timing
Rev. H |
Page 39 of 60 |
March 2019
ADSP-21369
For details on the operation of the IDP, see the “Input Data
Port” chapter of the ADSP-2137x SHARC Processor Hardware
Reference. Note that the 20 bits of external PDAP data can be
provided through the external port DATA31–12 pins or the
DAI pins.
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 32. PDAP is the parallel mode operation of Channel 0 of
the input data port (IDP).
Table 32. Parallel Data Acquisition Port (PDAP)
Parameter
Timing Requirements
PDAP_HOLD Setup Before PDAP_CLK Sample Edge
tSPHOLD1
tHPHOLD1
PDAP_HOLD Hold After PDAP_CLK Sample Edge
1
tPDSD
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge
tPDHD1
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge
tPDCLKW
Clock Width
tPDCLK
Clock Period
Switching Characteristics
tPDHLDD
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word
tPDSTRB
PDAP Strobe Pulse Width
1
Min
ns
ns
ns
ns
ns
ns
2 × tPCLK + 3
2 × tPCLK – 1
ns
ns
tPDCLK
tPDCLKW
DAI_P20–1
(PDAP_CLK)
tHPHOLD
tSPHOLD
DAI_P20–1
(PDAP_HOLD)
tPDHD
tPDSD
DAI_P20–1/
ADDR23–4
(PDAP_DATA)
tPDHLDD
DAI_P20–1
(PDAP_STROBE)
Figure 26. PDAP Timing
Rev. H |
Page 40 of 60 |
March 2019
Unit
2.5
2.5
3.85
2.5
(tPCLK × 4) ÷ 2 – 3
tPCLK × 4
Data Source pins are DATA31–12, or DAI pins. Source pins for SCLK and FS are: 1) DATA11–10 pins, 2) DAI pins.
SAMPLE EDGE
Max
tPDSTRB
ADSP-21369
Pulse-Width Modulation Generators
Table 33. PWM Timing
Parameter
Switching Characteristics
tPWMW
PWM Output Pulse Width
tPWMP
PWM Output Period
Min
Max
Unit
tPCLK – 2
2 × tPCLK – 1.5
(216 – 2) × tPCLK
(216 – 1) × tPCLK
ns
ns
tPWMW
PWM
OUTPUTS
tPWMP
Figure 27. PWM Timing
Sample Rate Converter—Serial Input Port
The SRC input signals SCLK, frame sync (FS), and SDATA are
routed from the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided in Table 34 are valid at the
DAI_P20–1 pins.
Table 34. SRC, Serial Input Port
Parameter
Timing Requirements
tSRCSFS1
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
tSRCHFS1
tSRCSD1
SDATA Setup Before SCLK Rising Edge
1
tSRCHD
SDATA Hold After SCLK Rising Edge
tSRCCLKW
Clock Width
tSRCCLK
Clock Period
1
Min
4
5.5
4
5.5
(tPCLK × 4) ÷ 2 – 1
tPCLK × 4
Max
Unit
ns
ns
ns
ns
ns
ns
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
Rev. H |
Page 41 of 60 |
March 2019
ADSP-21369
SAMPLE EDGE
DAI_P20–1
(SCLK)
tSRCCLK
tSRCCLKW
tSRCSFS
tSRCHFS
DAI_P20–1
(FS)
tSRCSD
tSRCHD
DAI_P20–1
(SDATA)
Figure 28. SRC Serial Input Port Timing
Rev. H |
Page 42 of 60 |
March 2019
ADSP-21369
and delay specification with regard to SCLK. Note that SCLK
rising edge is the sampling edge and the falling edge is the
drive edge.
Sample Rate Converter—Serial Output Port
For the serial output port, the frame-sync is an input and it
should meet setup and hold times with regard to SCLK on the
output port. The serial data output, SDATA, has a hold time
Table 35. SRC, Serial Output Port
Parameter
Timing Requirements
FS Setup Before SCLK Rising Edge
tSRCSFS1
tSRCHFS1
FS Hold After SCLK Rising Edge
tSRCCLKW
Clock Width
tSRCCLK
Clock Period
Switching Characteristics
tSRCTDD1
Transmit Data Delay After SCLK Falling Edge
1
Transmit Data Hold After SCLK Falling Edge
tSRCTDH
1
Min
Max
4
5.5
(tPCLK × 4) ÷ 2 – 1
tPCLK × 4
ns
ns
ns
ns
9.9
1
Unit
ns
ns
DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
SAMPLE EDGE
tSRCCLK
tSRCCLKW
DAI_P20–1
(SCLK)
tSRCSFS
tSRCHFS
DAI_P20–1
(FS)
tSRCTDD
tSRCTDH
DAI_P20–1
(SDATA)
Figure 29. SRC Serial Output Port Timing
Rev. H |
Page 43 of 60 |
March 2019
ADSP-21369
mode) from an LRCLK transition, so that when there are 64
SCLK periods per LRCLK period, the LSB of the data is rightjustified to the next LRCLK transition.
S/PDIF Transmitter
Serial data input to the S/PDIF transmitter can be formatted as
left justified, I2S, or right justified with word widths of 16, 18, 20,
or 24 bits. The following sections provide timing for the
transmitter.
Figure 31 shows the default I2S-justified mode. LRCLK is low
for the left channel and high for the right channel. Data is valid
on the rising edge of SCLK. The MSB is left-justified to an
LRCLK transition but with a single SCLK period delay.
S/PDIF Transmitter—Serial Input Waveforms
Figure 30 shows the right-justified mode. LRCLK is high for the
left channel and low for the right channel. Data is valid on the
rising edge of SCLK. The MSB is delayed 12-bit clock periods
(in 20-bit output mode) or 16-bit clock periods (in 16-bit output
LEFT/RIGHT CHANNEL
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
tRJD
LSB
MSB
MSB–1
MSB–2
LSB+2
Figure 30. Right-Justified Mode
LEFT/RIGHT CHANNEL
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
tI2SD
MSB
MSB–1
MSB–2
LSB+2
LSB+1
LSB
Figure 31. I2S-Justified Mode
Rev. H |
Page 44 of 60 |
March 2019
LSB+1
LSB
ADSP-21369
Figure 32 shows the left-justified mode. LRCLK is high for the
left channel and low for the right channel. Data is valid on the
rising edge of SCLK. The MSB is left-justified to an LRCLK
transition with no MSB delay.
S/PDIF Transmitter Input Data Timing
The timing requirements for the input port are given in
Table 36. Input signals SCLK, frame sync (FS), and SDATA are
routed to the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided in Table 36 are valid at the
DAI_P20–1 pins.
DAI_P20–1
FS
LEFT/RIGHT CHANNEL
DAI_P20–1
SCLK
tLJD
DAI_P20–1
SDATA
MSB
MSB–1
MSB–2
LSB+2
LSB+1
LSB
Figure 32. Left-Justified Mode
Table 36. S/PDIF Transmitter Input Data Timing
Parameter
Timing Requirements
tSISFS1
FS Setup Before SCLK Rising Edge
1
tSIHFS
FS Hold After SCLK Rising Edge
tSISD1
SDATA Setup Before SCLK Rising Edge
tSIHD1
SDATA Hold After SCLK Rising Edge
Clock Width
tSISCLKW
tSISCLK
Clock Period
tSITXCLKW
Transmit Clock Width
tSITXCLK
Transmit Clock Period
1
Min
3
3
3
3
36
80
9
20
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
tSITXCLKW
SAMPLE EDGE
tSITXCLK
DAI_P20–1
(TxCLK)
tSISCLK
tSISCLKW
DAI_P20–1
(SCLK)
tSISFS
tSIHFS
DAI_P20–1
(FS)
tSISD
tSIHD
DAI_P20–1
(SDATA)
Figure 33. S/PDIF Transmitter Input Timing
Rev. H |
Page 45 of 60 |
March 2019
ADSP-21369
Oversampling Clock (TxCLK) Switching Characteristics
The S/PDIF transmitter has an oversampling clock. This TxCLK
input is divided down to generate the biphase clock.
Table 37. Oversampling Clock (TxCLK) Switching Characteristics
Parameter
TxCLK Frequency for TxCLK = 384 × FS
TxCLK Frequency for TxCLK = 256 × FS
Frame Rate (FS)
Min
Max
Oversampling Ratio × FS
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