ADSP-21469

Preliminary Technical Data SUMMARY Note: This datasheet is preliminary. This document contains material that is subject to change without notice. High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Single-instruction, multiple-data (SIMD) computational architecture On-chip memory—5 Mbits of on-chip RAM SHARC Processor ADSP-21469/ADSP-21469W Code compatible with all other members of the SHARC family The ADSP-21469 is available with a 450 MHz core instruction rate with unique audiocentric peripherals such as the digital applications interface, serial ports, precision clock generators, S/PDIF transceiver, asynchronous sample rate converters, input data port, and more. For complete ordering information, see Ordering Guide on Page 56. CORE PROCESSOR PLL THERMAL DIODE TIMER INSTRUCTION CACHE 32 x 48-BIT 4 BLOCKS OF ON-CHIP MEMORY 5M BIT RAM JTAG TEST & EMULATION EXTERNAL PORT 8 DATA FLAGS PWM DAG1 8 x 4 x 32 DAG2 8 x 4 x 32 PROGRAM SEQUENCER ADDR 32 DATA 48 ASYNCHRONOUS MEMORY INTERFACE (AMI) 24 ADDRESS 3 7 AMI CONTROL DDR2 CONTROL DATA ADDRESS PM ADDRESS BUS DM ADDRESS BUS 32 32 PM DATA BUS 64 DDR2 DRAM CONTROLLER 16 19 DM DATA BUS 64 IOA(19) IOD(32) ACCELERATORS FFT FIR IIR PROCESSING ELEMENT (PEX) PROCESSING ELEMENT (PEY) PX REGISTER IOP REGISTER CONTROL STATUS, & DATA BUFFERS DMA ARBITER LINK PORTS 20 4 DAI ROUTING UNIT PRECISION CLOCK GENERATORS (4) SERIAL PORTS (8) INPUT DATA PORT/ PDAP ASRC TWO WIRE INTERFACE GPIO DPI PINS (14) DPI ROUTING UNIT GPIO IRQ/FLAGS SPI PORT (2) UART S S/PDIF (RX/TX) GP TIMERS (2) DAI PINS (20) DIGITAL APPLICATIONS INTERFACE 20 DIGITAL PERIPHERAL INTERFACE 14 I/O PROCESSOR Figure 1. Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. PrB Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.3113 ©2008 Analog Devices, Inc. All rights reserved. ADSP-21469/ADSP-21469W KEY FEATURES—PROCESSOR CORE At 450 MHz core instruction rate, the ADSP-21469 performs at 2.7 GFLOPS/900 MMACs 5 Mbits on-chip, RAM for simultaneous access by the core processor and DMA DDR2 DRAM interface (16-bit) operating at maximum frequency of half the core clock frequency Dual data address generators (DAGs) with modulo and bitreverse addressing Zero-overhead looping with single-cycle loop setup, providing efficient program sequencing VISA (variable instruction set) execution support Single instruction multiple data (SIMD) architecture provides: Two computational processing elements Concurrent execution Code compatibility with other SHARC family members at the assembly level Parallelism in buses and computational units allows: Single cycle executions (with or without SIMD) of a multiply operation, an ALU operation, a dual memory read or write, and an instruction fetch Transfers between memory and core at a sustained 7.2 Gbytes/second bandwidth FFT accelerator implements radix-2 complex/real input, complex output FFT with no core intervention IIR accelerators perform dedicated IIR filtering with high-performance, fixed- and floating-point processing capabilities with no core intervention FIR accelerators perform dedicated FIR filtering with highperformance, fixed- and floating-point processing capabilities with no core intervention In the ADSP-21469, the program sequencer can execute code directly from external memory bank 0 (SRAM, as well as DDR2 DRAM). This allows more options to a user in terms of code and data storage. New opcodes of 16 and 32 bits are supported in addition to the existing 48 bit opcodes. Variable Instruction Set Architecture (VISA) execution from external DDR2 DRAM memory is also supported. Preliminary Technical Data Programmable wait state options (for AMI): 2 to 31 DDR2_CLK cycles Delay-line DMA engine maintains circular buffers in external memory with tap/offset based reads 16-bit data access for synchronous DDR2 DRAM 8-bit data access for asynchronous memory 4 memory select lines allows multiple external memory devices Digital audio interface (DAI) includes eight serial ports, four precision clock generators, an input data port, an S/PDIF transceiver, and a signal routing unit Digital peripheral interface (DPI) includes, two timers, one UART, and two SPI ports, and a two-wire interface port Outputs of PCG’s A and B can be routed through DAI pins Outputs of PCG's C and D can be driven on to DAI as well as DPI pins Eight dual data line serial ports— each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair TDM support for telecommunications interfaces including 128 TDM channel support for newer telephony interfaces such as H.100/H.110 Up to 16 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port (IDP), configurable as eight channels of serial data or seven channels of serial data and up to a 20-bit wide parallel data channel Signal routing unit provides configurable and flexible connections between the various peripherals and the DAI/DPI components 4 independent asynchronous sample rate converters (ASRC). Each converter has separate serial input and output ports, a de-emphasis filter providing up to –128 dB SNR performance, stereo sample rate converter and supports leftjustified, I2S, TDM, and right-justified modes and 24-, 20-, 18-, and 16-audio data word lengths. 2 muxed flag/IRQ lines 1 muxed flag/IRQ /AMI_MS pin 1 muxed flag/Timer expired line /AMI_MS pin S/PDIF-compatible digital audio receiver/transmitter supports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards Left-justified, I2S or right-justified serial data input with 16-, 18-, 20- or 24-bit word widths (transmitter) Pulse-width modulation provides: 16 PWM outputs configured as four groups of four outputs supports center-aligned or edge-aligned PWM waveforms PLL has a wide variety of software and hardware multiplier/divider ratios Thermal diode to monitor die temperature Available in 19 mm by 19 mm PBGA package (see Ordering Guide on Page 56) INPUT/OUTPUT FEATURES Two 8-bit wide link ports can connect to the link ports of other SHARCs or peripherals. Link ports are bidirectional programmable ports having eight data lines, an acknowledge line and a clock line. Link ports can operate at a maximum frequency of 166 MHz. DMA controller supports: 36 DMA channels for transfers between ADSP-21469 internal memory and a variety of peripherals DMA transfers at peripheral clock speed, in parallel with full-speed processor execution External port provides glueless connection to 16-bit wide synchronous DDR2 DRAM using a dedicated DDR2 DRAM controller, and 8-bit wide asynchronous memory devices using asynchronous memory interface (AMI) Rev. PrB | Page 2 of 56 | November 2008 Preliminary Technical Data TABLE OF CONTENTS Summary ............................................................... 1 Key Features—Processor Core ................................. 2 Input/Output Features ........................................... 2 Table Of Contents .................................................... 3 Revision History ...................................................... 3 General Description ................................................. 4 Family Core Architecture ....................................... 5 Memory ............................................................. 6 External Memory .................................................. 6 Input/Output Features ........................................... 7 System Design ..................................................... 10 Development Tools .............................................. 10 Additional Information ......................................... 11 Pin Function Descriptions ........................................ 12 Data Modes ........................................................ 15 Boot Modes ........................................................ 15 Core Instruction Rate to CLKIN Ratio Modes ............. 15 Specifications ......................................................... 16 Operating Conditions ........................................... 16 Electrical Characteristics ........................................ 17 Maximum Power Dissipation ................................. 18 Absolute Maximum Ratings ................................... 18 ESD Sensitivity .................................................... 18 Timing Specifications ........................................... 19 Output Drive Currents .......................................... 50 Test Conditions ................................................... 50 Capacitive Loading ............................................... 50 Thermal Characteristics ........................................ 51 Ball configuration - ADSP-21469 ............................. 52 PBGA Pinout ......................................................... 53 Outline Dimensions ................................................ 55 Automotive Products ............................................... 56 Ordering Guide ...................................................... 56 ADSP-21469/ADSP-21469W REVISION HISTORY 11/08—Revision PrB Rev. PrB | Page 3 of 56 | November 2008 ADSP-21469/ADSP-21469W GENERAL DESCRIPTION The ADSP-21469 SHARC® processor is a member of the SIMD SHARC family of DSPs that feature Analog Devices' Super Harvard Architecture. The ADSP-21469 is source code compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x, and ADSP2116x DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. The ADSP-21469 is a 32-bit/40-bit floating point processors optimized for high performance audio applications with its large on-chip SRAM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital applications interface (DAI). Table 1. SHARC Features Feature Frequency Core Internal RAM DDR2 Memory Interface DDR2 Memory Bus Width Direct DMA from SPORTs to external memory FFT accelerator FIR accelerator IIR accelerator IDP Serial Ports ASRC (channels) UART DAI and DPI Link Ports S/PDIF transceiver AMI interface with 8-bit support SPI TWI Package Description 1 Preliminary Technical Data Table 2 shows performance benchmarks for the ADSP-21469. Table 2. Processor Benchmarks Benchmark Algorithm 1024 Point Complex FFT (Radix 4, With Reversal) FIR Filter (per Tap)1 IIR Filter (per Biquad)1 Matrix Multiply (Pipelined) [3 × 3] × [3 × 1] [4 × 4] × [4 × 1] Divide (y/×) Inverse Square Root Assumes two files in multichannel SIMD mode Speed (at 450 MHz) 20.44 μs 1.11 ns 4.43 ns 10.0 ns 17.78 ns 6.67 ns 10.0 ns 450 MHz 5-stage pipeline 5 Mbits 1/2 CCLK Max 16-bits Yes Yes Yes Yes Yes 8 8 1 20/14 pins 2 1 Yes 2 1 324-ball, 19 mm x 19 mm PBGA The ADSP-21469 continues SHARC’s industry-leading standards of integration for DSPs, combining a high performance 32-bit DSP core with integrated, on-chip system features. The block diagram of the ADSP-21469 on Page 1 illustrates the following architectural features: • Two processing elements, each of which comprises an ALU, multiplier, shifter, and data register file • Data address generators (DAG1, DAG2) • Program sequencer with instruction cache • PM and DM buses capable of supporting four 32-bit data transfers between memory and the core at every core processor cycle • Two programmable interval timers with external event counter capabilities • On-chip SRAM • JTAG test access port The block diagram of the ADSP-21469 on Page 1 also illustrates the following architectural features: • DMA controller • Digital applications interface that includes four precision clock generators (PCG), an S/PDIF-compatible digital audio receiver/transmitter with four independent asynchronous sample rate converters, an input data port (IDP) with eight serial ports, eight serial interfaces, a 20-bit parallel input port (PDAP), and a flexible signal routing unit (DAI SRU). • Digital peripheral interface that includes two timers, one UART, two serial peripheral interfaces (SPI), a 2-wire interface (TWI), and a flexible signal routing unit (DPI SRU). As shown in the functional block diagram on Page 1, the ADSP-21469 uses two computational units to deliver a significant performance increase over the previous SHARC processors on a range of DSP algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the ADSP-21469 processor achieves an instruction cycle time of 2.22 ns at 450 MHz. With its SIMD computational hardware, the ADSP-21469 can perform 2.7 GFLOPS. Rev. PrB | Page 4 of 56 | November 2008 Preliminary Technical Data FAMILY CORE ARCHITECTURE The ADSP-21469 is code compatible at the assembly level with the ADSP-2137x, ADSP-2136x, ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-21469 shares architectural features with the ADSP-2126x, ADSP-2136x, ADSP-2137x, and ADSP-2116x SIMD SHARC processors, as detailed in the following sections. ADSP-21469/ADSP-21469W gram and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. Instruction Cache The ADSP-21469 includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full speed execution of core, looped operations such as digital filter multiply-accumulates, and FFT butterfly processing. SIMD Computational Engine The ADSP-21469 contains two computational processing elements that operate as a single-instruction, multiple-data (SIMD) engine. The processing elements are referred to as PEX and PEY and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY may be enabled by setting the PEYEN mode bit in the MODE1 register. When this mode is enabled, the same instruction is executed in both processing elements, but each processing element operates on different data. This architecture is efficient at executing math intensive DSP algorithms. Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each access of memory or the register file. Data Address Generators With Zero-Overhead Hardware Circular Buffer Support The ADSP-21469’s two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs of the ADSP-21469 contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any memory location. Flexible Instruction Set The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the ADSP-21469 can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetching up to four 32-bit values from memory—all in a single instruction. Independent, Parallel Computation Units Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all operations in a single cycle. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit singleprecision floating-point, 40-bit extended precision floatingpoint, and 32-bit fixed-point data formats. Variable Instruction Set Architecture In addition to supporting the standard 48-bit instructions from previously existing SHARC family of processors, the ADSP21469 will support new instructions of 16 and 32 bits in addition to the existing 48 bit instructions. This feature, called Variable Instruction Set Architecture (VISA), is based on dropping redundant/unused bits within the 48-bit instruction to create more efficient and compact code. The program sequencer will now support fetching these 16-bit and 32-bit instructions as well in addition to the standard 48-bit instructions, both from internal as well as external memory. Source modules will need to be built using the VISA option, in order to allow code generation tools to create these more efficient opcodes. Data Register File A general-purpose data register file is contained in each processing element. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the ADSP-21469 enhanced Harvard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0-R15 and in PEY as S0-S15. FFT Accelerator FFT accelerator implements radix-2 complex/real input, complex output FFT with no core intervention. Single-Cycle Fetch of Instruction and Four Operands The ADSP-21469 features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data (see Figure 1 on page 1). With the ADSP-21469’s separate pro- Rev. PrB | Page 5 of 56 | November 2008 ADSP-21469/ADSP-21469W FIR Accelerators The FIR (finite impulse response) accelerator consists of a 1024 word coefficient memory, a 1024 word deep delay line for the data, and four MAC units. A controller manages the accelerator. The FIR accelerator runs at the peripheral clock frequency. Preliminary Technical Data MEMORY The ADSP-21469 adds the following architectural features to the SIMD SHARC family core. On-Chip Memory The ADSP-21469 contains 5 Mbits of internal RAM. Each block can be configured for different combinations of code and data storage (see Table 3). Each memory block supports single-cycle, independent accesses by the core processor and I/O processor. The ADSP-21469 memory architecture, in combination with its separate on-chip buses, allow two data transfers from the core and one from the I/O processor, in a single cycle. IIR Accelerators The IIR (infinite impulse response) accelerator consists of a 1440 word coefficient memory for storage of biquad coefficients, a data memory for storing the intermediate data and one MAC unit. A controller manages the accelerator. The IIR accelerator runs at the peripheral clock frequency. Table 3. ADSP-21469 Internal Memory Space IOP Registers 0x0000 0000–0x0003 FFFF Long Word (64 bits) BLOCK 0 RAM 0x0004 9000–0x0004 EFFF Reserved 0x0004 F000–0x0005 8FFF BLOCK 1 RAM 0x0005 9000–0x0005 EFFF Reserved 0x0005 F000–0x0005 FFFF BLOCK 2 RAM 0x0006 0000–0x0006 3FFF Reserved 0x0006 4000–0x0006 FFFF BLOCK 3 RAM 0x0007 0000–0x0007 3FFF Reserved 0x0007 4000–0x0007 FFFF Extended Precision Normal or Instruction Word (48 bits) BLOCK 0 RAM 0x0008 C000-0x0009 3FFF Reserved 0x0009 E000–0x000B 1FFF BLOCK 1 RAM 0x000A C000-0x000B 3FFF Reserved 0x000B E000–0x000B FFFF BLOCK 2 RAM 0x000C 0000–0x000C 5554 Reserved 0x000C 8000–0x000D FFFF BLOCK 3 RAM 0x000E 0000–0x000E 5554 Reserved 0x000E 8000–0x000F FFFF Normal Word (32 bits) BLOCK 0 RAM 0x0009 2000-0x0009 DFFF Reserved 0x0009 E000–0x000B 1FFF BLOCK 1 RAM 0x000B 2000-0x000B DFFF Reserved 0x000B E000–0x000B FFFF BLOCK 2 RAM 0x000C 0000-0x000C 7FFF Reserved 0x000C 8000–0x000D FFFF BLOCK 3 RAM 0x000E 0000–0x000E 7FFF Reserved 0x000E 8000–0x000F FFFF Short Word (16 bits) BLOCK 0 RAM 0x0012 4000–0x0013 BFFF Reserved 0x0013 C000–0x0016 3FFF BLOCK 1 RAM 0x0016 4000-0x0017 BFFF Reserved 0x0017 C000–0x0017 FFFF BLOCK 2 RAM 0x0018 0000–0x0018 FFFF Reserved 0x0019 0000–0x001B FFFF BLOCK 3 RAM 0x001C 0000–0x001C FFFF Reserved 0x001D 0000–0x001F FFFF The ADSP-21469’s SRAM can be configured as a maximum of 160k words of 32-bit data, 320k words of 16-bit data, 106.7k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 5 megabit. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Using the DM bus and PM buses, with one bus dedicated to a memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. The memory map in Table 3 displays the internal memory address space of the ADSP-21469. The 48-bit space section describes what this address range looks like to an instruction that retrieves 48-bit memory. The 32-bit section describes what this address range looks like to an instruction that retrieves 32-bit memory. EXTERNAL MEMORY The external port on the ADSP-21469 SHARC provides a high performance, glueless interface to a wide variety of industrystandard memory devices. The external port may be used to interface to synchronous and/or asynchronous memory devices through the use of its separate internal memory controllers: the 16-bit DDR2 DRAM controller for connection of industry-standard synchronous DRAM devices, while the second is an 8-bit asynchronous memory controller intended to interface to a variety of memory devices. Four memory select pins enable up Rev. PrB | Page 6 of 56 | November 2008 Preliminary Technical Data to four separate devices to coexist, supporting any desired combination of synchronous and asynchronous device types. Non DDR2 DRAM external memory address space is shown in Table 4. ADSP-21469/ADSP-21469W Note that the external memory bank addresses shown are for normal-word (32-bit) accesses. If 48-bit instructions as well as 32-bit data are both placed in the same external memory bank, care must be taken while mapping them to avoid overlap. In case of 32-bit wide external memory, two 48-bit instructions will be stored in three 32-bit wide memory locations. For example, if 2k instructions are placed in 32-bit wide external memory starting at the bank 0 normal-word base address 0x0030 0000 (corresponding to instruction address 0x0020 0000) and ending at address 0x0030 0BFF (corresponding to instruction address 0x0020 07FF), then data buffers can be placed starting at an address that is offset by 3k 32-bit words (for example, starting at 0x0030 0C00). External Memory Execution In the ADSP-21469, the program sequencer can execute code directly from external memory bank 0 (SRAM, as well as DDR2 DRAM). This allows more options to a user in terms of code and data storage. With external execution, programs run at slower speeds since 48-bit instructions are fetched in parts from a 16-bit external bus coupled with the inherent latency of fetching instructions from DDR2 DRAM. VISA mode and SIMD mode accesses are supported for DDR2 space. However, external memory execution from DDR2 space is different for VISA and non-VISA mode. Asynchronous Memory Controller The asynchronous memory controller provides a configurable interface for up to four separate banks of memory or I/O devices. Each bank can be independently programmed with different timing parameters, enabling connection to a wide variety of memory devices including SRAM, flash, and EPROM, as well as I/O devices that interface with standard memory control lines. Bank 0 occupies a 14M word window and banks 1, 2, and 3 occupy a 16M word window in the processor’s address space but, if not fully populated, these windows are not made contiguous by the memory controller logic. The asynchronous memory controller is capable of a maximum throughput of TBD Mbps using a TBD MHz external bus speed. Other features include 8 to 32-bit packing and unpacking, booting from bank select 1, and support for delay line DMA. DDR2 Support The ADSP-21469 supports a 16-bit DDR interface operating at a maximum frequency of half the core clock. Execution from external memory is supported. External memory up to 2 Gbits can be supported. Delay line DMA functionality supported. DDR2 DRAM Controller The DDR2 DRAM controller provides an 16-bit interface to up to four separate banks of industry-standard DDR2 DRAM devices. Fully compliant with the DDR2 DRAM standard, each bank can has its own memory select line (DDR2_CS3DDR2_CS0), and can be configured to contain between 32M bytes and 256M bytes of memory. DDR2 DRAM external memory address space is shown in Table 5 A set of programmable timing parameters is available to configure the DDR2 DRAM banks to support memory devices. Table 4. External Memory for Non DDR2 DRAM Addresses Size in Words 14M 16M 16M 16M Shared External Memory The ADSP-21469 processor supports connecting to common shared external DDR2 memory with other ADSP-21469 processors to create shared external bus processor systems. This support includes: • Distributed, on-chip arbitration for the shared external bus • Fixed and rotating priority bus arbitration • Bus time-out logic • Bus lock Multiple processors can share the external bus with no additional arbitration logic. Arbitration logic is included on-chip to allow the connection of up to TBD processors. Bus arbitration is accomplished through the BR6-1 signals and the priority scheme for bus arbitration is determined by the setting of the RPBA pin. Table 6 on Page 12 provides descriptions of the pins used in multiprocessor systems. Bank Bank 0 Bank 1 Bank 2 Bank 3 Address Range 0x0020 0000 – 0x00FF FFFF 0x0400 0000 – 0x04FF FFFF 0x0800 0000 – 0x08FF FFFF 0x0C00 0000 – 0x0CFF FFFF Table 5. External Memory for DDR2 DRAM Addresses Size in Words 62M 64M 64M 64M Bank Bank 0 Bank 1 Bank 2 Bank 3 Address Range 0x0020 0000 – 0x03FF FFFF 0x0400 0000 – 0x07FF FFFF 0x0800 0000 – 0x0BFF FFFF 0x0C00 0000 – 0x0FFF FFFF INPUT/OUTPUT FEATURES The ADSP-21469 I/O processor provides 36 channels of DMA, as well as an extensive set of peripherals. These include a 20 lead digital applications interface, which controls: • Eight serial ports • S/PDIF receiver/transmitter Rev. PrB | Page 7 of 56 | November 2008 ADSP-21469/ADSP-21469W • Four precision clock generators • Input data port/parallel data acquisition port • Four stereo asynchronous sample rate converters The ADSP-21469 processor also contains a 14 lead digital peripheral interface, which controls: • Two general-purpose timers • Two serial peripheral interfaces • One universal asynchronous receiver/transmitter (UART) • An I2C®-compatible 2-wire interface • Two PCGs (C and D) can also be routed through DPI Preliminary Technical Data associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with nonconfigurable signal paths. The DAI also includes eight serial ports, four precision clock generators (PCG), S/PDIF transceiver, four ASRCs, and an input data port (IDP). The IDP provides an additional input path to the ADSP-21469 core, configurable as either eight channels of serial data, or a single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the ADSP-21469’s serial ports. Serial Ports The ADSP-21469 features eight synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as Analog Devices’ AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and frame sync. The data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel. Serial ports can support up to 16 transmit or 16 receive channels of audio data when all eight SPORTs are enabled, or four full duplex TDM streams of 128 channels per frame. The serial ports operate at a maximum data rate of 56.25 Mbps. Serial port data can be automatically transferred to and from on-chip memory/external memory via dedicated DMA channels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. One SPORT provides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared. Serial ports operate in five modes: • Standard DSP serial mode • Multichannel (TDM) mode • I2S mode • Packed I2S mode • Left-justified sample pair mode Left-justified sample pair mode is a mode where in each frame sync cycle two samples of data are transmitted/received—one sample on the high segment of the frame sync, the other on the low segment of the frame sync. Programs have control over various attributes of this mode. Each of the serial ports supports the left-justified sample pair and I2S protocols (I2S is an industry-standard interface commonly used by audio codecs, ADCs, and DACs such as the Analog Devices AD183x family), with two data pins, allowing four left-justified sample pair or I2S channels (using two stereo devices) per serial port, with a maximum of up to 32 I2S channels. The serial ports permit little-endian or big-endian transmission formats and word lengths selectable from 3 bits to 32 bits. For the left-justified sample pair and I2S modes, dataword lengths are selectable between 8 bits and 32 bits. Serial ports offer selectable synchronization and transmit modes as well as optional μ-law or A-law companding selection on a per channel basis. Serial port clocks and frame syncs can be internally or externally generated. DMA Controller The ADSP-21469’s on-chip DMA controller allows data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur between the ADSP-21469’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) ports, the IDP (input data port), the parallel data acquisition port (PDAP) or the UART. Thirty-six channels of DMA are available on the ADSP-21469, 16 via the serial ports, eight via the input data port, two for the UART, two for the SPI interface, two for the external port, two for memory-to-memory transfers, two for the link port, two for the FFT/IIR/FIR accelerator. Programs can be downloaded to the ADSP-21469 using DMA transfers. Other DMA features include interrupt generation upon completion of DMA transfers, and DMA chaining for automatic linked DMA transfers. Delay Line DMA The ADSP-21469 processor provides delay line DMA functionality. This allows processor reads and writes to external delay line buffers (and hence to external memory) with limited core interaction. Scatter/Gather DMA The ADSP-21469 processor provides scatter/gather DMA functionality. This allows processor DMA reads/writes to/from non-contingeous memory blocks. Digital Applications Interface (DAI) The digital applications interface (DAI) provides the ability to connect various peripherals to any of the DSP DAI pins (DAI_P20–1). Programs make these connections using the signal routing unit (SRU), shown in Figure 1. The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to be interconnected under software control. This allows easy use of the DAI Rev. PrB | Page 8 of 56 | November 2008 Preliminary Technical Data The serial ports also contain frame sync error detection logic where the serial ports detect frame syncs that arrive early (for example frame syncs that arrive while the transmission/reception of the previous word is occurring). All the serial ports also share one dedicated error interrupt. ADSP-21469/ADSP-21469W transfers of serial data. The UART also has multiprocessor communication capability using 9-bit address detection. This allows it to be used in multidrop networks through the RS-485 data interface standard. The UART port also includes support for 5 to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The UART port supports two modes of operation: • PIO (programmed I/O) – The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive. • DMA (direct memory access) – The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates. The UART port's baud rate, serial data format, error code generation and status, and interrupts are programmable: • Supporting bit rates ranging from (fPCLK/ 1,048,576) to (fPCLK/16) bits per second. • Supporting data formats from 7 to 12 bits per frame. • Both transmit and receive operations can be configured to generate maskable interrupts to the processor. In conjunction with the general-purpose timer functions, autobaud detection is supported. S/PDIF-Compatible Digital Audio Receiver/Transmitter and Synchronous/Asynchronous Sample Rate Converter The S/PDIF receiver/transmitter has no separate DMA channels. It receives audio data in serial format and converts it into a biphase encoded signal. The serial data input to the receiver/transmitter can be formatted as left justified, I2S or right justified with word widths of 16, 18, 20, or 24 bits. The serial data, clock, and frame sync inputs to the S/PDIF receiver/transmitter are routed through the signal routing unit (SRU). They can come from a variety of sources such as the SPORTs, external pins, the precision clock generators (PCGs), and are controlled by the SRU control registers. The sample rate converter (ASRC) contains four ASRC blocks and is the same core as that used in the AD1896 192 kHz stereo asynchronous sample rate converter and provides up to 128 dB SNR. The ASRC block is used to perform synchronous or asynchronous sample rate conversion across independent stereo channels, without using internal processor resources. The four SRC blocks can also be configured to operate together to convert multichannel audio data without phase mismatches. Finally, the ASRC can be used to clean up audio data from jittery clock sources such as the S/PDIF receiver. Timers The ADSP-21469 has a total of three timers: a core timer that can generate periodic software interrupts and two general purpose timers that can generate periodic interrupts and be independently set to operate in one of three modes: • Pulse waveform generation mode • Pulse width count/capture mode • External event watchdog mode The core timer can be configured to use FLAG3 as a timer expired signal, and each general-purpose timer has one bidirectional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A single control and status register enables or disables both generalpurpose timers independently. Digital Peripheral Interface (DPI) The digital peripheral interface provides connections to two serial peripheral interface ports (SPI), one universal asynchronous receiver-transmitter (UART), 12 flags, a 2-wire interface (TWI), and two general-purpose timers. Serial Peripheral (Compatible) Interface The ADSP-21469 SHARC processor contains two serial peripheral interface ports (SPIs). The SPI is an industry-standard synchronous serial link, enabling the ADSP-21469 SPI-compatible port to communicate with other SPI compatible devices. The SPI consists of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The ADSP-21469 SPI-compatible peripheral implementation also features programmable baud rate and clock phase and polarities. The ADSP-21469 SPI-compatible port uses open drain drivers to support a multimaster configuration and to avoid data contention. 2-Wire Interface Port (TWI) The TWI is a bidirectional 2-wire, serial bus used to move 8-bit data while maintaining compliance with the I2C bus protocol. The TWI master incorporates the following features: • 7-bit addressing • Simultaneous master and slave operation on multiple device systems with support for multi master data arbitration • Digital filtering and timed event processing • 100 kbps and 400 kbps data rates • Low interrupt rate November 2008 UART Port The ADSP-21469 processor provides a full-duplex Universal Asynchronous Receiver/Transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous Rev. PrB | Page 9 of 56 | ADSP-21469/ADSP-21469W Pulse-Width Modulation The PWM module is a flexible, programmable, PWM waveform generator that can be programmed to generate the required switching patterns for various applications related to motor and engine control or audio power control. The PWM generator can generate either center-aligned or edge-aligned PWM waveforms. In addition, it can generate complementary signals on two outputs in paired mode or independent signals in nonpaired mode (applicable to a single group of four PWM waveforms). The entire PWM module has four groups of four PWM outputs each. Therefore, this module generates 16 PWM outputs in total. Each PWM group produces two pairs of PWM signals on the four PWM outputs. The PWM generator is capable of operating in two distinct modes while generating center-aligned PWM waveforms: single update mode or double update mode. In single update mode the duty cycle values are programmable only once per PWM period. This results in PWM patterns that are symmetrical about the mid-point of the PWM period. In double update mode, a second updating of the PWM registers is implemented at the midpoint of the PWM period. In this mode, it is possible to produce asymmetrical PWM patterns that produce lower harmonic distortion in three-phase PWM inverters. Preliminary Technical Data Note that the analog supply pin (VDD_A) powers the processor’s internal clock generator PLL. To produce a stable clock, it is recommended that PCB designs use an external filter circuit for the VDD_A pin. Place the filter components as close as possible to the VDD_A/VSS_A pins. For an example circuit, see Figure 2. (A recommended ferrite chip is the muRata BLM18AG102SN1D). 100nF VDDINT 10nF 1nF ADSP-21469 VDD_A HI Z FERRITE BEAD CHIP VSS_A LOCATE ALL COMPONENTS CLOSE TO VDD_A AND VSS_A PINS Figure 2. Analog Power (VDD_A) Filter Circuit Link Ports Two 8-bit wide link ports can connect to the link ports of other DSPs or peripherals. Link ports are bidirectional ports having eight data lines, an acknowledge line and a clock line. Link ports can operate at a maximum frequency of 166 MHz. To reduce noise coupling, the PCB should use a parallel pair of power and ground planes for VDD_INT and VSS. Use wide traces to connect the bypass capacitors to the analog power (VDD_A) and ground (VSS_A) pins. Note that the VDD_A and VSS_A pins specified in Figure 2 are inputs to the processor and not the analog ground plane on the board—the VSS_A pin should connect directly to digital ground (VSS) at the chip Target Board JTAG Emulator Connector Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21469 processor to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor's JTAG interface ensures that the emulator will not affect target system loading or timing. For complete information on Analog Devices’ SHARC DSP Tools product line of JTAG emulator operation, see the appropriate “Emulator Hardware User's Guide”. SYSTEM DESIGN The following sections provide an introduction to system design options and power supply issues. Program Booting The internal memory of the ADSP-21469 boots at system power-up from an 8-bit EPROM via the external port, link port, an SPI master, or an SPI slave. Booting is determined by the boot configuration (BOOTCFG2–0) pins (see Table 8 on Page 15). The “Running Reset” feature allows a user to perform a reset of the processor core and peripherals, but without resetting the PLL and DDR2 DRAM controller, or performing a Boot. The functionality of the CLKOUT/RESETOUT/RUNRSTIN pin has now been extended to also act as the input for initiating a Running Reset. For more information, see the ADSP-2146x SHARC Processor Hardware Reference. DEVELOPMENT TOOLS The ADSP-21469 processor is supported with a complete set of CROSSCORE® software and hardware development tools, including Analog Devices emulators and VisualDSP++® development environment. The same emulator hardware that supports other SHARC processors also fully emulates the ADSP-21469 processor. EZ-KIT Lite Evaluation Board For evaluation of the processors, use the EZ-KIT Lite® board being developed by Analog Devices. The board comes with onchip emulation capabilities and is equipped to enable software development. Multiple daughter cards are available. Power Supplies The processors have separate power supply connections for the internal (VDD_INT), external (VDD_EXT), and analog (VDD_A/VSS_A) power supplies. The internal and analog supplies must meet the VDD_INT specifications. The external supply must meet the VDD_EXT specification. All external supply pins must be connected to the same power supply. Rev. PrB | Page 10 of 56 | November 2008 Preliminary Technical Data Designing an Emulator-Compatible DSP Board (Target) The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on each JTAG DSP. Nonintrusive incircuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing. To use these emulators, the target board must include a header that connects the DSP’s JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)—use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support. ADSP-21469/ADSP-21469W Evaluation Kit Analog Devices offers a range of EZ-KIT Lite® evaluation platforms to use as a cost effective method to learn more about developing or prototyping applications with Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite includes an evaluation board along with an evaluation suite of the VisualDSP++® development and debugging environment with the C/C++ compiler, assembler, and linker. Also included are sample application programs, power supply, and a USB cable. All evaluation versions of the software tools are limited for use only with the EZ-KIT Lite product. The USB controller on the EZ-KIT Lite board connects the board to the USB port of the user’s PC, enabling the VisualDSP++ evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also allows in-circuit programming of the on-board Flash device to store user-specific boot code, enabling the board to run as a standalone unit without being connected to the PC. With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any custom defined system. Connecting one of Analog Devices JTAG emulators to the EZ-KIT Lite board enables high speed, nonintrusive emulation. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-21469 architecture and functionality. For detailed information on the ADSP-21469 family core architecture and instruction set, refer to the ADSP-2136x/ADSP-2146x SHARC Processor Programming Reference. Rev. PrB | Page 11 of 56 | November 2008 ADSP-21469/ADSP-21469W PIN FUNCTION DESCRIPTIONS The following symbols appear in the Type column of Table 6: A = asynchronous, I = input, O = output, S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state, (pd) = pull-down resistor, (pu) = pull-up resistor. Table 6. Pin List State During and After LVTTL SSTL18 Reset High-Z/ driven low (boot) Preliminary Technical Data Name AMI_ADDR23–0 Type O/T AMI_DATA7–0 I/O/T High-Z DAI _P20–1 I/O with fixed weak pull-up on input path 1, 2 High-Z DPI _P14–1 I/O with fixed weak pull-up only on input path1, 2 High-Z AMI_ACK I (pu) O/T AMI_RD O/T AMI_WR DDR2_ADDR15-0 DDR2_BA2-0 O/T O/T High-Z High-Z O/T DDR2_CAS High-Z/ Driven low High-Z/ DDR2 Bank Address Input pins. Define which bank an ACTIVATE, Driven low READ, WRITE, or PRECHARGE command is being applied. BA2–0 define which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command. High-Z/ DDR2 Column Address Strobe. Connect to DDR2_CAS pin, in conjunction Driven with other DDR2 command pins, defines the operation for the DDR2 to high perform. Description External Address. The ADSP-21469 outputs addresses for external memory and peripherals on these pins. The data pins can be multiplexed to support the PDAP (I) and PWM (O). After reset, all AMI_ADDR23-0 pins are in EMIF mode and FLAG(0-3) pins will be in FLAGS mode (default). When configured in the IDP_PDAP_CTL register, IDP channel 0 scans the AMI_ADDR23–0 pins for parallel input data. External Data. The data pins can be multiplexed to support the external memory interface data (I/O), the PDAP (I), FLAGS (I/O) and PWM (O). After reset, all AMI_DATA pins are in EMIF mode and FLAG(0-3) pins will be in FLAGS mode (default). Digital Applications Interface Pins. These pins provide the physical interface to the DAI SRU. The DAI SRU configuration registers define the combination of on-chip audiocentric peripheral inputs or outputs connected to the pin and to the pin’s output enable. The configuration registers of these peripherals then determine the exact behavior of the pin. Any input or output signal present in the DAI SRU may be routed to any of these pins. The DAI SRU provides the connection from the serial ports, the S/PDIF module, input data ports (2), and the precision clock generators (4), to the DAI_P20–1 pins. Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU. The DPI SRU configuration registers define the combination of onchip peripheral inputs or outputs connected to the pin and to the pin’s output enable. The configuration registers of these peripherals then determines the exact behavior of the pin. Any input or output signal present in the DPI SRU may be routed to any of these pins. The DPI SRU provides the connection from the timers (2), SPIs (2), UART (1), flags (12), and general-purpose I/O (9) to the DPI_P14–1 pins. Memory Acknowledge (AMI_ACK). External devices can deassert AMI_ACK (low) to add wait states to an external memory access. AMI_ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access. AMI Port Read Enable. AMI_RD is asserted whenever the ADSP-21469 reads a word from external memory. AMI_RD has fixed internal pull-up resistor1, 2. External Port Write Enable. AMI_WR is asserted when the ADSP-21469 writes a word to external memory. AMI_WR has fixed internal pull-up resistor1, 2 . DDR2 Address pins. DDR2 address pins. Rev. PrB | Page 12 of 56 | November 2008 Preliminary Technical Data Table 6. Pin List (Continued) State During and After LVTTL SSTL18 Reset High-Z/ Driven low High-Z/ Driven high High-Z High-Z/ Driven high High-Z ADSP-21469/ADSP-21469W Name DDR2_CKE Type O/T O/T DDR2_CS3-0 DDR2_DATA15-0 DDR2_DM1-0 I/O/T O/T DDR2_DQS1-0 DDR2_DQS1-0 DDR2_RAS DDR2_WE I/O/T (Differential) O/T O/T DDR2_CLK0, DDR2_CLK0, DDR2_CLK1, DDR2_CLK1 DDR2_ODT AMI_MS0–1 O/T (Differential) High-Z/ Driven high High-Z/ DDR2 Write Enable. Connect to DDR2_WE pin, in conjunction with other Driven DDR2 command pins, defines the operation for the DDR2 to perform high High-Z/ DDR2 Clock. Free running, minimum frequency not guaranteed during reset. driven low Description DDR2 Clock Enable Output to DDR2. Active high signal. Connect to DDR2 CKE signal. DDR2 Chip Select. All commands are masked when DDR2_CS3-0 is driven high. DDR2_CS3-0 are decoded emory address lines. Each DDR2_CS3-0lines select the corresponding bank. DDR2 Data In/Out. Connect to corresponding DDR2_DATA pins. DDR2 Input Data Mask. Mask for the DDR2 write data if driven high. Sampled on both edges of DDR2_DQS at DDR2 side. DM0 corresponds to DDR2_DATA 7–0 and DM1 corresponds to DDR2_DATA 15–8. Data Strobe. Output with Write Data. Input with Read Data. DQS0 corresponds to DDR2_DATA 7–0 and DQS1 corresponds to DDR2_DATA 15–8. DDR2 Row Address Strobe. Connect to DDR2_RAS pin, in conjunction with other DDR2 command pins, defines the operation for the DDR2 to perform. O/T O/T FLAG[0]/IRQ0 FLAG[1]/IRQ1 FLAG[2]/IRQ2/ AMI_MS2 FLAG[3]/TIMEX P/ AMI_MS3 LDAT07–0 LDAT17-0 LCLK0 LCLK1 LACK0 LACK1 THD_P THD_M TDI TDO TMS I/O I/O I/O I/O I/0 I/O I/O I O I (pu) O /T I (pu) High-Z/ DDR2 On Die Termination. ODT pin when driven high (along with other Driven low requirements) enables the DDR2 termination resistances. High-Z Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corresponding banks of external memory on the AMI interface. The MS10 lines are decoded memory address lines that change at the same time as the other address lines. When no external memory access is occurring the MS1-0 lines are inactive; they are active however when a conditional memory access instruction is executed, whether or not the condition is true. The MS1 pin can be used in EPORT/FLASH boot mode. For more information, see the ADSP-2146x SHARC Processor Hardware Reference. High-Z FLAG0/Interrupt Request0. High-Z FLAG1/Interrupt Request1. High-Z FLAG2/Interrupt Request2/Async Memory Select2. High-Z High-Z High-Z High-Z FLAG3/Timer Expired/Async Memory Select3. Link Port Data (Link Ports 0-1). Link Port Clock (Link Ports 0–1). Link Port Acknowledge (Link Port 0-1). Thermal Diode Anode Thermal Diode Cathode Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a fixed internal pull-up resistor1, 2. Test Data Output (JTAG). Serial scan output of the boundary scan path. Test Mode Select (JTAG). Used to control the test state machine. TMS has a fixed internal pull-up resistor1, 2. High-Z Rev. PrB | Page 13 of 56 | November 2008 ADSP-21469/ADSP-21469W Table 6. Pin List (Continued) Preliminary Technical Data Name TCK Type I (pu) TRST I (pu) EMU O/T (pu) CLK_CFG1–0 I BOOT_CFG2–0 I RESET I (pu) XTAL CLKIN O I CLKOUT/ RESETOUT/ RUNRSTIN I/O (pu) BR6-1 RPBA ID2-0 1 2 I/O I I State During and After LVTTL SSTL18 Reset Description Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-21469. Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP21469. TRST has a fixed internal pull-up resistor1, 2. High-Z Emulation Status. Must be connected to the ADSP-21469 Analog Devices DSP Tools product line of JTAG emulators target board connector only. EMU has a fixed internal pull-up resistor1, 2. Core to CLKIN Ratio Control. These pins set the start up clock frequency. See Table 9 for a description of the clock configuration modes. Note that the operating frequency can be changed by programming the PLL multiplier and divider in the PMCTL register at any time after the core comes out of reset. Boot Configuration Select. These pins select the boot mode for the processor. The BOOTCFG pins must be valid before reset is asserted. See Table 8 for a description of the boot modes. Processor Reset. Resets the ADSP-21469 to a known state. Upon deassertion, there is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution from the hardware reset vector address. The RESET input must be asserted (low) at power-up. Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal. Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21469 clock input. It configures the ADSP-21469 to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the ADSP-21469 to use the external clock source such as an external clock oscillator. CLKIN may not be halted, changed, or operated below the specified frequency. Clock Out/Reset Out/Running Reset In. The functionality can be switched between the PLL output clock and reset out by setting Bit 12 of the PMCTL register. The default is reset out. This pin also has a third function as RUNRSTIN. The functionality of which is enabled by setting bit 0 of the RUNRSTCTL register. For more information, see the ADSP-2146x SHARC Processor Hardware Reference. High-Z/ Bus request. Bus request pins for external DDR2 bus arbitration. Driven low Rotating priority bus arbitration. Chip ID Pull-up/pull-down resistor can not be enabled/disabled and the value of the pull-up/pull-down resistor cannot be programmed. Range of fixed pull-up resistor can be between 26k-63kΩ. Range of fixed pull-down resistor can be between 31k-85kΩ. Rev. PrB | Page 14 of 56 | November 2008 Preliminary Technical Data DATA MODES The address and data pins of the external memory interface are muxed (using bits in the SYSCTL register) to support the external memory interface data (input/output), the PDAP (input only), and the FLAGS (input/output). Table 7 provides the pin settings. Table 7. Function of Data Pins DATA PIN MODE 000 001 010 011 100 101 110 111 AMI_ADDR [23:8] AMI_ADDR [23:0] ADSP-21469/ADSP-21469W AMI_ADDR [7:0] Reserved Reserved AMI_DATA [7:0] AMI_DATA [7:0] FLAGS/PWM [15–0] Reserved PDAP (DATA + CTRL) Reserved Three-state all pins FLAGS [15–0] FLAGS [7–0] BOOT MODES Table 8. Boot Mode Selection BOOTCFG2–0 000 001 010 011 100 101 110 111 Booting Mode SPI Slave Boot SPI Master Boot AMI user boot (for 8-bit Flash boot) Reserved Link Port 0 Boot Reserved Reserved Reserved CORE INSTRUCTION RATE TO CLKIN RATIO MODES For details on processor timing, see Timing Specifications and Figure 3 on Page 19. Table 9. Core Instruction Rate/ CLKIN Ratio Selection CLKCFG1–0 00 01 11 10 Core to CLKIN Ratio 6:1 32:1 Reserved 16:1 Rev. PrB | Page 15 of 56 | November 2008 ADSP-21469/ADSP-21469W SPECIFICATIONS OPERATING CONDITIONS Parameter1 VDD_INT VDD_EXT VDD_DDR23 VREF VIH4 VIL4 VIH_CLKIN5 VIL_CLKIN5 VIL_DDR2 VIH_DDR2 TJUNCTION 1 2 Preliminary Technical Data Description Internal (Core) Supply Voltage External (I/O) Supply Voltage DDR2 Controller Supply Voltage DDR2 Reference Voltage High Level Input Voltage @ VDD_EXT = max Low Level Input Voltage @ VDD_EXT = min High Level Input Voltage @ VDD_EXT = max Low Level Input Voltage @ VDD_EXT = min Low Level Input Voltage High Level Input Voltage Junction Temperature 208-Lead PBGA @ TAMBIENT 08C to +708C Min TBD2 3.14 1.71 0.84 2.0 -0.3 TBD TBD -0.3 VREF + 0.13 0 Max TBD2 3.46 1.89 0.96 3.6 0.8 TBD TBD VREF - 0.12 VDD_DDR2 + 0.3 125 Unit V V V V V V V V V V C Specifications subject to change without notice. The expected value is 1.1V and initial customer designs should design with a programmable regulator that can be adjusted from 0.95V to 1.15V +/-50mV 3 Applies to DDR2 signals. 4 Applies to input and bidirectional pins: AMI_ADDR23–0, AMI_DATA7–0, FLAG3–0, DAI_Px, DPI_Px, SPIDS, BOOTCFGx, CLKCFGx, CLKOUT (RUNRSTIN), RESET, TCK, TMS, TDI, TRST. 5 Applies to input pin CLKIN. Rev. PrB | Page 16 of 56 | November 2008 Preliminary Technical Data ELECTRICAL CHARACTERISTICS Parameter1 VOH2 VOL2 IOH_DDR24 IOL_DDR2 IIH 5, 6 4 ADSP-21469 Description High Level Output Voltage Low Level Output Voltage Output Source DC Current Output Sink DC Current High Level Input Current Low Level Input Current Test Conditions @ VDD_EXT = min, IOH = –1.0 mA3 @ VDD_EXT = min, IOL = 1.0 mA3 @ VOH_DDR2 (DC) = VDD_DDR2 -0.28 V @ VOL_DDR2 (DC)=0.28 @ VDD_EXT = max, VIN = VDD_EXT max @ VDD_EXT = max, VIN = 0 V @ VDD_EXT = max, VIN = 0 V @ VDD_EXT = max, VIN = VDD_EXT max @ VDD_EXT = max, VIN = 0 V Min 2.4 Typical Max Unit V 0.4 TBD TBD 10 10 TBD 10 10 TBD TBD TBD V mA mA μA μA μA μA μA μA mA pF IIL5 IILPU 6 7, 8 Low Level Input Current Pull-up Three-State Leakage Current Three-State Leakage Current IOZH IOZL 7 IOZLPU8 IDD-INTYP CIN 1 2 Three-State Leakage Current Pull-up @ VDD_EXT = max, VIN = 0 V 9, 10 Supply Current (Internal) Input Capacitance TBD TBD 11, 12 Specifications subject to change without notice. Applies to output and bidirectional pins: AMI_ADDR23-0, AMI_DATA7-0, AMI_RD, AMI_WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO, CLKOUT. 3 See Output Drive Currents on Page 50 for typical drive current capabilities. 4 Applies to DDR2_ADDR18-0, DDR2_CAS, DDR2_CS3-0, DDR2_DQ1-0, DDR2_DM1-0, DDR2_DQS1-0, DDR2_DATA15-0, DDR2_RAS, DDR2_WE, DDR2_CLK0, DDR2_CLK0, DDR2_CLK1 and, DDR2_CLK1. 5 Applies to input pins: BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN. 6 Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI. 7 Applies to three-statable pins: FLAG3–0. 8 Applies to three-statable pins with 22.5 kΩ pull-ups: DAI_Px, DPI_Px, EMU. 9 Typical internal current data reflects nominal operating conditions. 10 See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-21469 SHARC Processors” for further information. 11 Applies to all signal pins. 12 Guaranteed, but not tested. Rev. PrB | Page 17 of 56 | November 2008 ADSP-21469/ADSP-21469W MAXIMUM POWER DISSIPATION See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-21469 SHARC Processors” for detailed thermal and power information regarding maximum power dissipation. For information on package thermal specifications, see Thermal Characteristics on Page 51. Preliminary Technical Data ESD SENSITIVITY ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in Table 10 may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 10. Absolute Maximum Ratings Parameter Internal (Core) Supply Voltage (VDD_INT) Analog (PLL) Supply Voltage (VDD_A) External (I/O) Supply Voltage (VDD_EXT) DDR2 Controller Supply Voltage (VDD_DDR2) Input Voltage Output Voltage Swing Load Capacitance Storage Temperature Range Junction Temperature under Bias Rating –0.3 V to +1.32V TBD –0.3 V to +4.6V –0.5 V to +2.7V –0.5 V to +3.8V –0.5 V to VDD_EXT +0.5V 200 pF –65°C to +150°C 125°C Rev. PrB | Page 18 of 56 | November 2008 Preliminary Technical Data TIMING SPECIFICATIONS The ADSP-21469’s internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor core, and serial ports. During reset, program the ratio between the processor’s internal clock frequency and external (CLKIN) clock frequency with the CLKCFG1–0 pins (see Table 9 on ADSP-21469/ADSP-21469W Page 15). To determine switching frequencies for the serial ports, divide down the internal clock, using the programmable divider control of each port (DIVx for the serial ports). Figure 3 shows core to CLKIN ratios of 6:1, 16:1, and 32:1 with external oscillator or crystal. Note that more ratios are possible and can be set through software using the power management control register (PMCTL). For more information, see the ADSP-2136x SHARC Processor Programming Reference. PMCTL CLK_CFGx/ PMCTL LINKPORT CLOCK DIVIDER BYPASS MUX LCLK PMCTL PLL CLKIN BYPA SS MUX CLK_CFGx/ PMCTL PLL DIVIDER DDR2 DIVIDER CCLK BYPASS MUX PLLI CLKIN CLK DIVIDER LOOP FILTER VCO DDR2_CLK XTAL BUF PMCTL PLL MULTIPLIER CLK_CFGx/ PMCTL DIVIDE BY 2 PCLK CLK_CFGx/PMCTL PMCTL CLKOUT PIN MUX PCLK CCLK RESET DELAY OF 4096 CLKIN CYCLES RESETOUT BUF RESETOUT/ CLKOUT CORERST Figure 3. Core Clock and System Clock Relationship to CLKIN The ADSP-21469’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the processor uses an internal phase-locked loop (PLL). This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the processor’s internal clock. Core clock frequency can be calculated as: fCCLK = (2 × PLLM × fINPUT) ÷ (2 × PLLN) Note that in the user application, the PLL multiplier value should be selected in such a way that the VCO frequency falls in between 160 MHz and 800 MHz. The VCO frequency is calculated as follows: fVCO = 2 × PLLM × fINPUT where: fVCO is the VCO frequency PLLM is the multiplier value programmed fINPUT is the input frequency to the PLL in MHz. fINPUT = CLKIN when the input divider is disabled fINPUT = CLKIN ÷ 2 when the input divider is enabled Note the definitions of various clock periods shown in Table 12 which are a function of CLKIN and the appropriate ratio control shown in Table 11. Table 11. CLKOUT and CCLK Clock Generation Operation Timing Requirements CLKIN CCLK Description Input Clock Core Clock Calculation 1/tCK 1/tCCLK Rev. PrB | Page 19 of 56 | November 2008 ADSP-21469/ADSP-21469W Table 12. Clock Periods Timing Requirements tCK tCCLK tLCLK tPCLK tSCLK tDDR2_CLK tSPICLK 1 Preliminary Technical Data Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times. See Figure 41 on Page 50 under Test Conditions for voltage reference levels. Switching Characteristics specify how the processor changes its signals. Circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given circumstance. Use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices. Description1 CLKIN Clock Period (Processor) Core Clock Period (Link Port) Core Clock Period (Peripheral) Clock Period = 2 × tCCLK Serial Port Clock Period = (tPCLK) × SR DDR2 DRAM Clock Period = (tCCLK) × SDR SPI Clock Period = (tPCLLK) × SPIR where: SR = serial port-to-core clock ratio (wide range, determined by SPORT CLKDIV bits in DIVx register) SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register setting) SDR=DDR2 DRAM-to-Core Clock Ratio (Values determined by bits 20-18 of the PMCTL register) Rev. PrB | Page 20 of 56 | November 2008 Preliminary Technical Data Power-Up Sequencing The timing requirements for processor startup are given in Table 13. Table 13. Power Up Sequencing Timing Requirements (Processor Startup) Parameter Timing Requirements tRSTVDD RESET Low Before VDDEXT or VDDDDR2 On tEVDD-DDR2VDD VDD_EXT on Before VDD_DDR2 tDDR2VDD_IVDD VDD_DDR2 on Before VDD_INT tCLKVDD1 CLKIN Valid After VDD_INT Valid CLKIN Valid Before RESET Deasserted tCLKRST tPLLRST PLL Control Setup Before RESET Deasserted Switching Characteristic tCORERST Core Reset Deasserted After RESET Deasserted 1 2 ADSP-21469/ADSP-21469W Min 0 TBD TBD 0 102 203 4096 × tCK + 2 × tCCLK 4, 5 Max Unit ms ms ms ms ms ms ms 200 Valid VDD_INT assumes that the supply is fully ramped to its 1 volt rail. Voltage ramp rates can vary from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem. Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's datasheet for startup time. Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal. 3 Based on CLKIN cycles. 4 Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and propagate default states at all I/O pins. 5 The 4096 cycle count depends on tSRST specification in Table 15. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles maximum. tR S T V D D RESET V DDEXT t E V D D -D D R 2V D D V DD_DDR2 tD D R 2V D D _IVD D V DDINT tC L K V D D CLKIN tC L K R S T CLK_CFG 1-0 t PL L R S T RESETOUT tC O R E R S T Figure 4. Power-Up Sequencing Rev. PrB | Page 21 of 56 | November 2008 ADSP-21469/ADSP-21469W Clock Input Table 14. Clock Input 450 MHz Min TBD1 TBD1 TBD1 2.221 Preliminary Technical Data Parameter Timing Requirements tCK CLKIN Period tCKL CLKIN Width Low tCKH CLKIN Width High tCKRF CLKIN Rise/Fall (0.4 V to 2.0 V) tCCLK3 CCLK Period 1 2 Max TBD2 TBD2 TBD2 TBD TBD Unit ns ns ns ns ns Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL. Applies only for CLKCFG1–0 = 01 and default values for PLL control bits in PMCTL. 3 Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK. tCK CLKIN tCKH tCKL Figure 5. Clock Input Clock Signals The ADSP-21469 can use an external clock or a crystal. See the CLKIN pin description in Table 6. The programmer can configure the ADSP-21469 to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. Figure 6 shows the component connections used for a crystal operating in fundamental mode. Note that the clock rate is achieved using a 28.125 MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock speed of 450 MHz). To achieve the full core clock rate, programs need to configure the multiplier bits in the PMCTL register. ADSP-21469 CLKIN R1 1M * XTAL R2 47 * C1 22pF Y1 28.125 MHz C2 22pF R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL DRIVE POWER. REFER TO CRYSTAL MANUFACTURER’S SPECIFICATIONS *TYPICAL VALUES Figure 6. 450 MHz Operation (Fundamental Mode Crystal) Rev. PrB | Page 22 of 56 | November 2008 Preliminary Technical Data Reset Table 15. Reset Parameter Timing Requirements tWRST1 RESET Pulse Width Low tSRST RESET Setup Before CLKIN Low 1 ADSP-21469/ADSP-21469W Min TBD TBD Max TBD TBD Unit ns ns Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μσ while RESET is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator). CLKIN tWR S T RESET tS R ST Figure 7. Reset Running Reset The following timing specification applies to CLKOUT/ RESETOUT/RUNRSTIN pin when it is configured as RUNRSTIN. Table 16. Running Reset Parameter Timing Requirements tWRUNRST Running RESET Pulse Width Low tSRUNRST Running RESET Setup Before CLKIN High Min TBD TBD Max TBD TBD Unit ns ns CLKIN tWRUNRST RUNRSTIN tSRUNRST Figure 8. Running Reset Rev. PrB | Page 23 of 56 | November 2008 ADSP-21469/ADSP-21469W Interrupts The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts as well as the DAI_P20-1 and DPI_P14-1 pins when they are configured as interrupts. Table 17. Interrupts Parameter Timing Requirement tIPW IRQx Pulse Width Min TBD Preliminary Technical Data Max TBD Unit ns DAI_P20-1 DPI_P14-1 FLAG2 -0 (IRQ2-0) tIPW Figure 9. Interrupts Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer (CTIMER). Table 18. Core Timer Parameter Switching Characteristic tWCTIM CTIMER Pulse Width Min TBD Max TBD Unit ns FLAG 3 (CTIMER) tWCTIM Figure 10. Core Timer Timer PWM_OUT Cycle Timing The following timing specification applies to Timer0 and Timer1 in PWM_OUT (pulse-width modulation) mode. Timer signals are routed to the DPI_P14–1 pins through the DPI SRU. Therefore, the timing specifications provided below are valid at the DPI_P14–1 pins. Table 19. Timer PWM_OUT Timing Parameter Switching Characteristic tPWMO Timer Pulse Width Output Min TBD Max TBD Unit ns DPI_P14-1 (TIMER1 -0) tPWMO Figure 11. Timer PWM_OUT Timing Rev. PrB | Page 24 of 56 | November 2008 Preliminary Technical Data Timer WDTH_CAP Timing The following timing specification applies to timer0 and timer1, and in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DPI_P14–1 pins through the SRU. Therefore, the timing specification provided below is valid at the DPI_P14–1 pins. Table 20. Timer Width Capture Timing Parameter Timing Requirement tPWI Timer Pulse Width Min TBD Max TBD ADSP-21469/ADSP-21469W Unit ns tPWI DPI_P14-1 (TIMER1-0) Figure 12. Timer Width Capture Timing Pin to Pin Direct Routing (DAI and DPI) For direct pin connections only (for example DAI_PB01_I to DAI_PB02_O). Table 21. DAI Pin to Pin Routing Parameter Timing Requirement tDPIO Delay DAI/DPI Pin Input Valid to DAI Output Valid Min TBD Max TBD Unit ns DAI_Pn DPI_Pn DAI_Pm DPI_Pm tDPIO Figure 13. DAI Pin to Pin Direct Routing Rev. PrB | Page 25 of 56 | November 2008 ADSP-21469/ADSP-21469W Precision Clock Generator (Direct Pin Routing) This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG’s Table 22. Precision Clock Generator (Direct Pin Routing) Preliminary Technical Data inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is no timing data available. All timing parameters and switching characteristics apply to external DAI pins (DAI_P01 – DAI_P20). Parameter Min Max Unit Timing Requirements tPCGIW Input Clock Period TBD TBD ns tSTRIG PCG Trigger Setup Before Falling Edge of PCG Input TBD TBD ns Clock tHTRIG PCG Trigger Hold After Falling Edge of PCG Input TBD TBD ns Clock Switching Characteristics tDPCGIO PCG Output Clock and Frame Sync Active Edge Delay After PCG Input Clock TBD TBD ns tDTRIGCLK PCG Output Clock Delay After PCG Trigger TBD TBD ns tDTRIGFS PCG Frame Sync Delay After PCG Trigger TBD TBD ns tPCGOW1 Output Clock Period TBD TBD ns D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-2146x SHARC Processor Hardware Reference, “Precision Clock Generators” chapter. 1 Normal mode of operation. tSTRIG DAI_Pn DPI_Pn PCG_TRIGx_I tHTRIG tPCGIW DAI_Pm DPI_Pm PCG_EXTx_I (CLKIN) tDPCGIO DAI_Py DPI_Py PCG_CLKx_O tDTRIGCLK tDPCGIO tPCGOW DAI_Pz DPI_Pz PCG_FSx_O tDTRIGF S Figure 14. Precision Clock Generator (Direct Pin Routing) Rev. PrB | Page 26 of 56 | November 2008 Preliminary Technical Data Flags The timing specifications provided below apply to AMI_ADDR23-0 and AMI_DATA7-0 when configured as FLAGS. See Table 6 on page 12 for more information on flag use. Table 23. Flags Parameter Min Timing Requirement tFIPW DPI_P14-1, AMI_ADDR23-0, AMI_DATA7-0, FLAG3–0 IN Pulse Width TBD Switching Characteristic DPI_P14-1, AMI_ADDR23-0, AMI_DATA7-0, FLAG3–0 OUT Pulse Width TBD tFOPW ADSP-21469/ADSP-21469W Max TBD TBD Unit ns ns DPI_P14-1 (FLAG3- 0IN) (AMI_DATA7- 0) (AMI_ADDR23-0) tFIPW DPI_P14-1 (FLAG3-0OUT) (AMI_DATA7- 0) AMI_ADDR23-0) tFOPW Figure 15. Flags Rev. PrB | Page 27 of 56 | November 2008 ADSP-21469/ADSP-21469W DDR2 SDRAM Read Cycle Timing Table 24. DDR2 SDRAM Read Cycle Timing, VDD-DDR2 nominal 1.8V Parameter Timing Requirements TBD TBD Figure 16. DDR2 SDRAM Controller Input AC Timing Preliminary Technical Data Symbol TBD Minimum TBD Maximum TBD Unit TBD Rev. PrB | Page 28 of 56 | November 2008 Preliminary Technical Data DDR2 SDRAM Write Cycle Timing Table 25. DDR2 SDRAM Write Cycle Timing, VDD-DDR2 nominal 1.8V Parameter Switching Characteristics TBD TBD Symbol TBD ADSP-21469/ADSP-21469W Minimum TBD Maximum TBD Unit TBD Figure 17. DDR2 SDRAM Controller Output AC Timing Rev. PrB | Page 29 of 56 | November 2008 ADSP-21469/ADSP-21469W Memory Read—Bus Master Use these specifications for asynchronous interfacing to memories. Note that timing for AMI_ACK, AMI_DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode. Table 26. Memory Read—Bus Master Parameter Min Timing Requirements tDAD Address, Selects Delay to Data Valid1, 2 TBD tDRLD AMI_RD Low to Data Valid1 TBD tSDS Data Setup to AMI_RD High TBD tHDRH Data Hold from AMI_RD High3, 4 TBD tDAAK AMI_ACK Delay from Address, Selects2, 5 TBD tDSAK AMI_ACK Delay from AMI_RD Low4 TBD Switching Characteristics TBD tDRHA Address Selects Hold After AMI_RD High TBD tDARL Address Selects to AMI_RD Low2 TBD tRW AMI_RD Pulse Width TBD tRWR AMI_RD High to AMI_WR, AMI_RD, Low TBD W = (number of wait states specified in AMICTLx register) × tDDR2_CLK. HI = RHC + IC (RHC = (number of Read Hold Cycles specified in AMICTLx register) x tDDR2_CLK IC = (number of idle cycles specified in AMICTLx register) x tDDR2_CLK). H = (number of hold cycles specified in AMICTLx register) x tDDR2_CLK. 1 2 Preliminary Technical Data Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Unit ns ns ns ns ns ns ns ns ns ns Data delay/setup: System must meet tDAD, tDRLD, or tSDS. The falling edge of AMI_MSx, is referenced. 3 Note that timing for AMI_ACK, AMI_DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode. 4 Data hold: User must meet tHDRH in asynchronous access mode. See Test Conditions on Page 50 for the calculation of hold times given capacitive and dc loads. 5 AMI_ACK delay/setup: User must meet tDAAK, or tDSAK, for deassertion of AMI_ACK (low). For asynchronous assertion of AMI_ACK (high) user must meet tDAAK or tDSAK. AMI_ADDR MSx AMI_RD tDARL tDRHA tRW tDRLD tDAD AMI_DATA tSDS tHDRH tDSAK tDAAK AMI_ACK tRWR AMI_WR Figure 18. Memory Read—Bus Master Rev. PrB | Page 30 of 56 | November 2008 Preliminary Technical Data Memory Write—Bus Master Use these specifications for asynchronous interfacing to memories. Note that timing for AMI_ACK, AMI_DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode. ADSP-21469/ADSP-21469W Table 27. Memory Write—Bus Master Parameter Min Max Unit Timing Requirements tDAAK AMI_ACK Delay from Address, Selects1, 2 TBD TBD ns 1, 3 tDSAK AMI_ACK Delay from AMI_WR Low TBD TBD ns Switching Characteristics TBD TBD tDAWH Address, Selects to AMI_WR Deasserted2 TBD TBD ns 2 tDAWL Address, Selects to AMI_WR Low TBD TBD ns tWW AMI_WR Pulse Width TBD TBD ns tDDWH Data Setup Before AMI_WR High TBD TBD ns tDWHA Address Hold After AMI_WR Deasserted TBD TBD ns Data Hold After AMI_WR Deasserted TBD TBD ns tDWHD tDATRWH Data Disable After AMI_WR Deasserted4 TBD TBD ns tWWR AMI_WR High to AMI_WR, AMI_RD Low TBD TBD ns tDDWR Data Disable Before AMI_RD Low TBD TBD ns tWDE AMI_WR Low to Data Enabled TBD TBD ns W = (number of wait states specified in AMICTLx register) × tSDDR2_CLKH = (number of hold cycles specified in AMICTLx register) x tDDR2_CLK 1 2 AMI_ACK delay/setup: System must meet tDAAK, or tDSAK, for deassertion of AMI_ACK (low). For asynchronous assertion of AMI_ACK (high) user must meet tDAAK or tDSAK. The falling edge of AMI_MSx is referenced. 3 Note that timing for AMI_ACK, AMI_DATA, AMI_RD, AMI_WR, and strobe timing parameters only applies to asynchronous access mode. 4 See Test Conditions on Page 50 for calculation of hold times given capacitive and dc loads. AMI_ADDR MSx tDAWH tDAWL AMI_WR tDWHA tWW tWWR tWDE tDDWH AMI_DATA tDATRWH tDDWR tDSAK tDAAK AMI_ACK tDWHD AMI_RD Figure 19. Memory Write—Bus Master Rev. PrB | Page 31 of 56 | November 2008 ADSP-21469/ADSP-21469W Link Ports Calculation of link receiver data setup and hold relative to link clock is required to determine the maximum allowable skew that can be introduced in the transmission path between LDATA and LCLK. Setup skew is the maximum delay that can be introduced in LDATA relative to LCLK, (setup skew = tLCLKTWH min– tDLDCH – tSLDCL). Hold skew is the maximum delay that can be introduced in LCLK relative to LDATA, (hold skew = tLCLKTWL min – tHLDCH – tHLDCL). Calculations made directly Table 28. Link Ports – Receive Parameter Timing Requirements tSLDCL Data Setup Before LCLK Low tHLDCL Data Hold After LCLK Low tLCLKIW LCLK Period tLCLKRWL LCLK Width Low LCLK Width High tLCLKRWH Switching Characteristics tDLALC LACK Low Delay After LCLK High1 1 Preliminary Technical Data from speed specifications will result in unrealistically small skew times because they include multiple tester guardbands. The setup and hold skew times shown below are calculated to include only one tester guardband. ADSP-21469 Setup Skew = TBD ns max ADSP-21469 Hold Skew = TBD ns max Note that there is a two-cycle effect latency between the link port enable instruction and the DSP enabling the link port. Min TBD TBD TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD TBD TBD Unit ns ns ns ns ns ns LACK goes low with tDLALC relative to rise of LCLK after first byte, but does not go low if the receiver's link buffer is not about to fill. tLCLKIW tLCLKRWH LCLK tLCLKRWL tSLDCL LDAT7-0 IN tHLDCL tDLALC LACK (OUT) Figure 20. Link Ports—Receive Rev. PrB | Page 32 of 56 | November 2008 Preliminary Technical Data Table 29. Link Ports – Transmit Parameter Timing Requirements tSLACH LACK Setup Before LCLK High LACK Hold After LCLK High tHLACH Switching Characteristics tDLDCH Data Delay After LCLK High tHLDCH Data Hold After LCLK High tLCLKTWL LCLK Width Low tLCLKTWH LCLK Width High tDLACLK LCLK Low Delay After LACK High Min TBD TBD TBD TBD TBD TBD TBD TBD ADSP-21469/ADSP-21469W Max TBD TBD TBD TBD TBD TBD TBD TBD Unit ns ns ns ns ns ns ns tLCLKTWH LCLK tLCLKTWL LAST BYTE TRANSMITTED FIRST BYTE TRANSMITTED LCLK INACTIVE (HIGH) tDLDCH tHLDCH LDAT7-0 OUT tSLACH LACK (IN) tHLACH tDLACLK THE tSLACH REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST BYTE TRANSMITTED. Figure 21. Link Ports—Transmit Rev. PrB | Page 33 of 56 | November 2008 ADSP-21469/ADSP-21469W Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width. Table 30. Serial Ports—External Clock Parameter Timing Requirements tSFSE1 FS Setup Before SCLK (Externally Generated FS in either Transmit or Receive Mode) tHFSE1 FS Hold After SCLK (Externally Generated FS in either Transmit or Receive Mode) 1 tSDRE Receive Data Setup Before Receive SCLK tHDRE1 Receive Data Hold After SCLK tSCLKW SCLK Width tSCLK SCLK Period Switching Characteristics tDFSE2 FS Delay After SCLK (Internally Generated FS in either Transmit or Receive Mode) FS Hold After SCLK tHOFSE2 (Internally Generated FS in either Transmit or Receive Mode) tDDTE2 Transmit Data Delay After Transmit SCLK 2 Transmit Data Hold After Transmit SCLK tHDTE 1 2 Preliminary Technical Data Serial port signals (SCLK, FS, Data Channel A, Data Channel B) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Min Max Unit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD ns ns ns ns ns ns ns ns ns ns TBD TBD TBD TBD TBD TBD Referenced to sample edge. Referenced to drive edge. Table 31. Serial Ports—Internal Clock Parameter Timing Requirements tSFSI1 FS Setup Before SCLK (Externally Generated FS in either Transmit or Receive Mode) tHFSI1 FS Hold After SCLK (Externally Generated FS in either Transmit or Receive Mode) tSDRI1 Receive Data Setup Before SCLK 1 tHDRI Receive Data Hold After SCLK Switching Characteristics tDFSI2 FS Delay After SCLK (Internally Generated FS in Transmit Mode) tHOFSI2 FS Hold After SCLK (Internally Generated FS in Transmit Mode) 2 tDFSIR FS Delay After SCLK (Internally Generated FS in Receive Mode) tHOFSIR2 FS Hold After SCLK (Internally Generated FS in Receive Mode) tDDTI2 Transmit Data Delay After SCLK 2 tHDTI Transmit Data Hold After SCLK tSCKLIW Transmit or Receive SCLK Width 1 2 Min Max Unit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD ns ns ns ns ns ns ns ns ns ns ns Referenced to the sample edge. Referenced to drive edge. Rev. PrB | Page 34 of 56 | November 2008 Preliminary Technical Data Table 32. Serial Ports—Enable and Three-State Parameter Switching Characteristics tDDTEN1 Data Enable from External Transmit SCLK Data Disable from External Transmit SCLK tDDTTE1 tDDTIN1 Data Enable from Internal Transmit SCLK 1 ADSP-21469/ADSP-21469W Min TBD TBD TBD Max TBD TBD TBD Unit ns ns ns Referenced to drive edge. Table 33. Serial Ports—External Late Frame Sync Parameter Min Switching Characteristics tDDTLFSE1 Data Delay from Late External Transmit FS or External Receive FS with MCE = 1, MFD = 0 TBD tDDTENFS1 Data Enable for MCE = 1, MFD = 0 TBD 1 Max Unit TBD TBD ns ns The tDDTLFSE and tDDTENFS parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0. EXTERNAL RECEIVE F S WITH MCE = 1, MFD = 0 DRIVE S AMPLE DRIVE DAI_P20 -1 ( SCLK) tS F SE/I DAI_P20 -1 (FS ) tHF S E/I tDDTENFS DAI_P20 -1 (DATA CHANNEL A/B) tDDTE/I tHDTE/I 1S T BIT 2ND BIT tD DTLF S E LATE EXTERNAL TRAN S MIT FS DAI_P20-1 (S CLK) DRIVE S AMPLE DRIVE tS F S E/I DAI_P20 -1 (FS ) tHF S E/I tDDTENF S DAI_P20 -1 (DATA CHANNEL A/B) tDDTE/I tHDTE/I 1 S T BIT 2ND BIT tDDTLF S E NOTE: S ERIAL PORT S IGNALS (S CLK, F S, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20 -1 PIN S US ING THE S RU. THE TIMING S PECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20 -1 PINS . THE CHARACTERIZED AC S PORT TIMINGS ARE APPLICABLE WHEN INTERNAL CLOCK S AND FRAME S ARE LOOPED BACK FROM THE PIN, NOT ROUTED DIRECTLY THROUGH S AU. Figure 22. External Late Frame Sync1 1 This figure reflects changes made to support left-justified sample pair mode. Rev. PrB | Page 35 of 56 | November 2008 ADSP-21469/ADSP-21469W Preliminary Technical Data DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DATA RECEIVE—EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE tSCLKIW DAI_P20-1 (SCLK) DAI_P20- 1 (SCLK) tSCLKW tDF SIR tHOF SIR DAI_P20-1 (F S) tSFSI tHF SI DAI_P20-1 (FS) tDFS E tHOFSE tSFSE tHFSE tSDRI DAI_P20-1 (DATA CHANNEL A/B) tHDRI DAI_P20-1 (DATA CHANNEL A/B) tSDRE tHDRE NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL) OR SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DATA TRANSMIT—EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE tSCLKIW DAI_P20- 1 (SCLK) DAI_P20- 1 (SCLK) tSCLKW tDFSI tHOFSI DAI_P20- 1 (FS) tDFSE tS F S I tHFSI DAI_P20-1 (FS) tHOFSE tSFSE tHFSE tHDTI DAI_P20-1 (DATA CHANNEL A/B) tDDTI DAI_P20- 1 (DATA CHANNEL A/B) tHDTE tDDTE NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL) OR SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. DRIVE EDGE DAI_P20-1 SCLK (EXT) SCLK DRIVE EDGE tDDTEN DAI_P20-1 (DATA CHANNEL A/B) DRIVE EDGE DAI_P20-1 SCLK (INT) tDDTTE tDDTIN DAI_P20-1 (DATA CHANNEL A/B) Figure 23. Serial Ports Rev. PrB | Page 36 of 56 | November 2008 Preliminary Technical Data Input Data Port (IDP) The timing requirements for the IDP are given in Table 34. IDP signals (SCLK, FS, and SDATA) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 34. Input Data Port (IDP) Parameter Timing Requirements tSISFS1 FS Setup Before SCLK Rising Edge 1 tSIHFS FS Hold After SCLK Rising Edge SData Setup Before SCLK Rising Edge tSISD1 tSIHD1 SData Hold After SCLK Rising Edge tIDPCLKW Clock Width tIDPCLK Clock Period 1 ADSP-21469/ADSP-21469W Min TBD TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD TBD Unit ns ns ns ns ns ns AMI_DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins. SAMPLE EDGE tIPDCLK DAI_P20-1 (SCLK) tIPDCLKW tSISFS DAI_P20-1 (FS) tSIHFS tSISD DAI_P20-1 (SDATA) tSIHD Figure 24. IDP Master Timing Sample Rate Converter—Serial Input Port The ASRC input signals (SCLK, FS, and SDATA) are routed from the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided in Table 35 are valid at the DAI_P20–1 pins. Table 35. ASRC, Serial Input Port Parameter Timing Requirements FS Setup Before SCLK Rising Edge tSRCSFS1 1 tSRCHFS FS Hold After SCLK Rising Edge tSRCSD1 SDATA Setup Before SCLK Rising Edge tSRCHD1 SDATA Hold After SCLK Rising Edge tSRCCLKW Clock Width tSRCCLK Clock Period 1 Min TBD TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD TBD Unit ns ns ns ns ns ns AMI_DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. Rev. PrB | Page 37 of 56 | November 2008 ADSP-21469/ADSP-21469W SAMPLE EDGE tSRCCLK DAI_P20-1 ( SCLK) Preliminary Technical Data tSRCCLKW tSRCSFS tSRCHF S DAI_P20-1 (FS) tSRCSD DAI_P20-1 (SDATA) tSRCHD Figure 25. ASRC Serial Input Port Timing Rev. PrB | Page 38 of 56 | November 2008 Preliminary Technical Data Sample Rate Converter—Serial Output Port For the serial output port, the frame-sync is an input and it should meet setup and hold times with regard to SCLK on the output port. The serial data output, SDATA, has a hold time Table 36. ASRC, Serial Output Port Parameter Timing Requirements FS Setup Before SCLK Rising Edge tSRCSFS1 tSRCHFS1 FS Hold After SCLK Rising Edge tSRCCLKW Clock Width tSRCCLK Clock Period Switching Characteristics tSRCTDD1 Transmit Data Delay After SCLK Falling Edge 1 Transmit Data Hold After SCLK Falling Edge tSRCTDH 1 ADSP-21469/ADSP-21469W and delay specification with regard to SCLK. Note that SCLK rising edge is the sampling edge and the falling edge is the drive edge. Min TBD TBD TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD TBD TBD Unit ns ns ns ns ns ns AMI_DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE tSRCCLK DAI_P20- 1 (SCLK) tSRCCLKW tSRCSF S DAI_P20- 1 (F S) tSRCHFS tSRCTDD DAI_P20-1 (SDATA) tSRCTDH Figure 26. ASRC Serial Output Port Timing Rev. PrB | Page 39 of 56 | November 2008 ADSP-21469/ADSP-21469W Parallel Data Acquisition Port (PDAP) The timing requirements for the PDAP are provided in Table 37. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the PDAP, see the PDAP chapter of the ADSP-2146x SHARC Processor Hardware Table 37. Parallel Data Acquisition Port (PDAP) Parameter Timing Requirements tSPCLKEN1 PDAP_CLKEN Setup Before PDAP_CLK Sample Edge 1 tHPCLKEN PDAP_CLKEN Hold After PDAP_CLK Sample Edge PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge tPDSD1 tPDHD1 PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge tPDCLKW Clock Width tPDCLK Clock Period Switching Characteristics tPDHLDD Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word PDAP Strobe Pulse Width tPDSTRB 1 Preliminary Technical Data Reference. Note that the most significant 16 bits of external PDAP data can be provided through the DATA7-0 pins. The remaining four bits can only be sourced through DAI_P4–1. The timing below is valid at the DATA7–0 pins. Min TBD TBD TBD TBD TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD TBD TBD TBD TBD Unit ns ns ns ns ns ns ns ns Source pins of AMI_DATA are DATA7–0 or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG. S AMPLE EDGE t PDCLK t PDCLKW DAI_P20 -1 (PDAP_CLK) t S PCLKEN DAI_P20- 1 (PDAP_CLKEN) t HPCLKEN t PD S D DATA t PDHD DAI_P20-1 (PDAP_S TROBE) tPD S TRB t PDHLDD Figure 27. PDAP Timing Rev. PrB | Page 40 of 56 | November 2008 Preliminary Technical Data Pulse-Width Modulation Generators (PWM) The following timing specifications apply when the AMI_ADDR23-8 pins are configured as PWM. Table 38. Pulse-Width Modulation (PWM) Timing Parameter Switching Characteristics tPWMW PWM Output Pulse Width tPWMP PWM Output Period Min TBD TBD ADSP-21469/ADSP-21469W Max TBD TBD Unit ns ns tPWMW PWM OUTPUTS tPWMP Figure 28. PWM Timing Rev. PrB | Page 41 of 56 | November 2008 ADSP-21469/ADSP-21469W S/PDIF Transmitter Serial data input to the S/PDIF transmitter can be formatted as left justified, I2S, or right justified with word widths of 16-, 18-, 20-, or 24-bits. The following sections provide timing for the transmitter. S/PDIF Transmitter-Serial Input Waveforms Figure 29 shows the right-justified mode. LRCLK is high for the left channel and low for the right channel. Data is valid on the rising edge of SCLK. The MSB is delayed 12-bit clock periods (in 20-bit output mode) or 16-bit clock periods (in 16-bit output Preliminary Technical Data mode) from an LRCLK transition, so that when there are 64 SCLK periods per LRCLK period, the LSB of the data will be right-justified to the next LRCLK transition. DAI_P20-1 LRCLK DAI_P20-1 SCLK DAI_P20-1 SDATA L SB LEFT CHANNEL RIGHT CHANNEL M SB MS B-1 M S B-2 L S B+2 L S B+1 LS B M SB M S B-1 M S B-2 LS B+2 L S B+1 LSB Figure 29. Right-Justified Mode Figure 30 shows the default I2S-justified mode. LRCLK is low for the left channel and HI for the right channel. Data is valid on the rising edge of SCLK. The MSB is left-justified to an LRCLK transition but with a single SCLK period delay. RIGHT CHANNEL DAI_P20-1 LRCLK DAI_P20-1 SCLK DAI_P20-1 SDATA M SB M S B-1 MS B-2 LS B+2 LS B+1 L SB M SB MS B-1 MS B-2 LS B+2 LS B+1 LSB M SB LEFT CHANNEL Figure 30. I2S-Justified Mode Figure 31 shows the left-justified mode. LRCLK is high for the left channel and LO for the right channel. Data is valid on the rising edge of SCLK. The MSB is left-justified to an LRCLK transition with no MSB delay. DAI_P20-1 LRCLK DAI_P20-1 SCLK DAI_P20-1 SDATA M SB M S B-1 M S B-2 LEFT CHANNEL RIGHT CHANNEL LS B+2 L S B+1 LS B M SB M S B-1 M S B-2 LS B+2 L SB +1 L SB M SB M S B+1 Figure 31. Left-Justified Mode Rev. PrB | Page 42 of 56 | November 2008 Preliminary Technical Data S/PDIF Transmitter Input Data Timing The timing requirements for the S/PDIF transmitter are given in Table 39. Input signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 39. S/PDIF Transmitter Input Data Timing Parameter Timing Requirements tSISFS1 FS Setup Before SCLK Rising Edge tSIHFS1 FS Hold After SCLK Rising Edge tSISD1 SData Setup Before SCLK Rising Edge tSIHD1 SData Hold After SCLK Rising Edge Transmit Clock Width tSITXCLKW tSITXCLK Transmit Clock Period tSISCLKW Clock Width tSISCLK Clock Period 1 ADSP-21469/ADSP-21469W Min TBD TBD TBD TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD TBD TBD TBD Unit ns ns ns ns ns ns ns ns AMI_DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. tSITXCLKW SAMPLE EDGE DAI_P20-1 (TXCLK) tSITXCLK DAI_P20-1 (SCLK) tSISCLKW tSISCLK tSISFS DAI_P20-1 (FS) tSIHF S tSISD DAI_P20-1 (SDATA) tSIHD Figure 32. S/PDIF Transmitter Input Timing Oversampling Clock (TxCLK) Switching Characteristics The S/PDIF transmitter has an oversampling clock. This TxCLK input is divided down to generate the biphase clock. Table 40. Over Sampling Clock (TxCLK) Switching Characteristics Parameter TxCLK Frequency for TxCLK = 384 × FS TxCLK Frequency for TxCLK = 256 × FS Frame Rate Min TBD TBD TBD Max TBD TBD TBD Unit MHz MHz kHz Rev. PrB | Page 43 of 56 | November 2008 ADSP-21469/ADSP-21469W S/PDIF Receiver The following section describes timing as it relates to the S/PDIF receiver. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the TBD × FS clock. Table 41. S/PDIF Receiver Internal Digital PLL Mode Timing Parameter Switching Characteristics LRCLK Delay After SCLK tDFSI tHOFSI LRCLK Hold After SCLK tDDTI Transmit Data Delay After SCLK tHDTI Transmit Data Hold After SCLK tSCLKIW1 Transmit SCLK Width 1 Preliminary Technical Data Min TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD Unit ns ns ns ns ns SCLK frequency is TBD x FS where FS = the frequency of LRCLK. DRIVE EDGE tSCLKIW DAI_P20-1 (SCLK) SAMPLE EDGE tDFSI tHOFSI DAI_P20-1 (FS) tHDTI DAI_P20-1 (DATA CHANNEL A/B) tDDTI Figure 33. S/PDIF Receiver Internal Digital PLL Mode Timing Rev. PrB | Page 44 of 56 | November 2008 Preliminary Technical Data SPI Interface—Master The ADSP-21469 contains two SPI ports. Both primary and secondary are available through DPI only. The timing provided in Table 42 and Table 43 applies to both. Table 42. SPI Interface Protocol—Master Switching and Timing Specifications Parameter Timing Requirements Data Input Valid To SPICLK Edge (Data Input Setup Time) tSSPIDM tHSPIDM SPICLK Last Sampling Edge To Data Input Not Valid Switching Characteristics tSPICLKM Serial Clock Cycle tSPICHM Serial Clock High Period tSPICLM Serial Clock Low Period SPICLK Edge to Data Out Valid (Data Out Delay Time) tDDSPIDM tHDSPIDM SPICLK Edge to Data Out Not Valid (Data Out Hold Time) tSDSCIM FLAG3–0IN (SPI device select) Low to First SPICLK Edge tHDSM Last SPICLK Edge to FLAG3–0IN High tSPITDM Sequential Transfer Delay Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD ADSP-21469/ADSP-21469W Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Unit ns ns ns ns ns ns ns ns ns FLAG3-0 (OUTPUT) t S D S CIM SPICLK (CP = 0) (OUTPUT) t S PICHM t S PICLM t S PI CLKM t HD S M t S PIT DM t S PICL M SPICLK (CP = 1) (OUTPUT) t S PICHM t D D S PIDM MOSI (OUTPUT) MSB t HDSPIDM LSB t SS PIDM CPHASE = 1 MISO (INPUT) MSB VALID t SS PIDM t H S PIDM LSB VALID tH S PIDM t DD S PIDM MOSI (OUTPUT) CPHASE = 0 MISO (INPUT) MSB t HD S PIDM LSB t SS PIDM MSB VALID t H S PIDM LSB VALID Figure 34. SPI Master Timing Rev. PrB | Page 45 of 56 | November 2008 ADSP-21469/ADSP-21469W SPI Interface—Slave Table 43. SPI Interface Protocol—Slave Switching and Timing Specifications Parameter Timing Requirements tSPICLKS tSPICHS tSPICLS tSDSCO Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Preliminary Technical Data Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Serial Clock Cycle Serial Clock High Period Serial Clock Low Period SPIDS Assertion to First SPICLK Edge CPHASE = 0 CPHASE = 1 Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 tHDS tSSPIDS Data Input Valid to SPICLK edge (Data Input Set-up Time) tHSPIDS SPICLK Last Sampling Edge to Data Input Not Valid tSDPPW SPIDS Deassertion Pulse Width (CPHASE=0) Switching Characteristics tDSOE SPIDS Assertion to Data Out Active SPIDS Deassertion to Data High Impedance tDSDHI tDDSPIDS SPICLK Edge to Data Out Valid (Data Out Delay Time) tHDSPIDS SPICLK Edge to Data Out Not Valid (Data Out Hold Time) tDSOV SPIDS Assertion to Data Out Valid (CPHAS E = 0) SPIDS (INPUT) t S P IC H S SPICLK (CP = 0) (INPUT) tSPICLS tSPICLKS tHDS tSDPPW tSDSCO SPICLK (CP = 1) (INPUT) tSPICLS tSPICHS tDSOE tDDSPIDS tDDSPIDS MSB LSB tDSDHI tHDSPIDS MISO (OUTPUT) CPHASE = 1 MOSI (INPUT) tHSPIDS tSSPIDS MSB VALID tSSPIDS LSB VALID tDDSPIDS MISO (OUTPUT) t DSOV CPHASE = 0 MOSI (INPUT) M SB tHDSPIDS tDSDHI L SB tSSPIDS MSB VALID LSB VALID tHSPIDS Figure 35. SPI Slave Timing Rev. PrB | Page 46 of 56 | November 2008 Preliminary Technical Data Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing Figure 36 describes UART port receive and transmit operations. The maximum baud rate is PCLK/16 where PCLK = 1/tPCLK. As shown in Figure 36 there is some latency between the generTable 44. UART Port Parameter Timing Requirement Incoming Data Pulse Width tRXD1 Switching Characteristic tTXD1 Outgoing Data Pulse Width 1 ADSP-21469/ADSP-21469W ation of internal UART interrupts and the external data operations. These latencies are negligible at the data transmission rates for the UART. Min TBD TBD TBD Max TBD TBD TBD Unit ns ns UART signals RXD and TXD are routed through DPI P14-1 pins using the SRU. DPI_P14-1 [RXD] RECEIVE INTERNAL UART RECEIVE INTERRUPT DATA(5- 8) STOP tRXD UART RECEIVE BIT SET BY DATA STOP; CLEARED BY FIFO READ START DPI_P14-1 [TXD] TRANSMIT INTERNAL UART TRANSMIT INTERRUPT DATA(5- 8) STOP(1-2) tTXD UART TRANSMIT BIT SET BY PROGRAM; CLEARED BY WRITE TO TRANSMIT Figure 36. UART Port—Receive and Transmit Timing Rev. PrB | Page 47 of 56 | November 2008 ADSP-21469/ADSP-21469W TWI Controller Timing Table 45 and Figure 37 provide timing information for the TWI interface. Input Signals (SCL, SDA) are routed to the DPI_P14–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DPI_P14–1 pins. Preliminary Technical Data Table 45. Characteristics of the SDA and SCL Bus Lines for F/S-Mode TWI Bus Devices1 Parameter fSCL tHDSTA tLOW tHIGH tSUSTA tHDDAT tSUDAT tSUSTO tBUF tSP 1 SCL Clock Frequency Hold Time (repeated) Start Condition. After This Period, the First Clock Pulse is Generated. Low Period of the SCL Clock High Period of the SCL Clock Setup Time for a Repeated Start Condition Data Hold Time for TWI-bus Devices Data Setup Time Setup Time for Stop Condition Bus Free Time Between a Stop and Start Condition Pulse Width of Spikes Suppressed By the Input Filter Standard Mode Min Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD n/a Fast Mode Min TBD TBD TBD TBD TBD TBD TBD TBD TBD Max TBD Unit kHz μs μs μs μs μs ns μs μs ns n/a TBD All values referred to VIHmin and VILmax levels. For more information, see Electrical Characteristics on page 17. DPI_P14-1 SDA tSUDA T tLOW tHD S TA t SP tBUF DPI_P14-1 S CL tHDS TA S tH DDA T tHIGH tSU S TA Sr t SU STO P S Figure 37. Fast and Standard Mode Timing on the TWI Bus Rev. PrB | Page 48 of 56 | November 2008 Preliminary Technical Data JTAG Test Access Port and Emulation Table 46. JTAG Test Access Port and Emulation Parameter Timing Requirements tTCK TCK Period tSTAP TDI, TMS Setup Before TCK High tHTAP TDI, TMS Hold After TCK High tSSYS1 System Inputs Setup Before TCK High 1 tHSYS System Inputs Hold After TCK High tTRSTW TRST Pulse Width Switching Characteristics tDTDO TDO Delay from TCK Low 2 tDSYS System Outputs Delay After TCK Low 1 2 ADSP-21469/ADSP-21469W Min TBD TBD TBD TBD TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD TBD TBD TBD TBD Unit ns ns ns ns ns ns ns ns System Inputs = AD15–0, CLKCFG1–0, RESET, BOOTCFG1–0, DAI_Px, and FLAG3–0. System Outputs = DAI_Px, AD15–0, AMI_RD, AMI_WR, FLAG3–0, CLKOUT, EMU, and ALE. tTCK TCK tSTAP TMS TDI tDTDO TDO tSSYS SYSTEM INPUTS tD S Y S SYSTEM OUTPUTS tHS Y S tHTAP Figure 38. IEEE 1149.1 JTAG Test Access Port Rev. PrB | Page 49 of 56 | November 2008 ADSP-21469/ADSP-21469W OUTPUT DRIVE CURRENTS Figure 39 shows typical I-V characteristics for the output drivers of the ADSP-21469. The curves represent the current drive capability of the output drivers as a function of output voltage. Preliminary Technical Data INPUT 1.5V OR OUTPUT 1.5V Figure 41. Voltage Reference Levels for AC Measurements 12 CAPACITIVE LOADING Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 40). Figure 44 shows graphically how output delays and holds vary with load capacitance. The graphs of Figure 42, Figure 43, and Figure 44 may not be linear outside the ranges shown for Typical Output Delay vs. Load Capacitance and Typical Output Rise Time (20% to 80%, V = Min) vs. Load Capacitance. 10 8 6 TBD 4 2 12 0 0 50 100 150 200 250 10 Figure 39. ADSP-21469 Typical Drive at Junction Temperature 8 TEST CONDITIONS 6 The ac signal specifications (timing parameters) appear in Table 15 on Page 23 through Table 46 on Page 49. These include output disable time, output enable time, and capacitive loading. The timing specifications for the SHARC apply for the voltage reference levels in Figure 40. Timing is measured on signals when they cross the 1.5 V level as described in Figure 41. All delays (in nanoseconds) are measured between the point that the first signal reaches 1.5 V and the point that the second signal reaches 1.5 V. TBD 4 2 0 0 50 100 150 200 250 Figure 42. Typical Output Rise/Fall Time (20% to 80%, VDD_EXT = Max) TESTER PIN ELECTRONICS 50 VLOAD 45 70 ZO = 50 (impedance) TD = 4.04 1.18 ns 0.5pF 2pF 400 T1 DUT OUTPUT 12 10 50 4pF 8 6 TBD 4 NOTES: THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS. ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES. 2 0 0 50 100 150 200 250 Figure 40. Equivalent Device Loading for AC Measurements (Includes All Fixtures) Figure 43. Typical Output Rise/Fall Time (20% to 80%, VDD_EXT = Min) Rev. PrB | Page 50 of 56 | November 2008 Preliminary Technical Data 12 ADSP-21469/ADSP-21469W Values of θJB are provided for package comparison and PCB design considerations. Note that the thermal characteristics values provided in Table 47 are modeled values. Table 47. Thermal Characteristics for 324-Lead PBGA Parameter θJA θJMA θJMA θJC ΨJT ΨJMT ΨJMT Condition Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Typical TBD TBD TBD TBD TBD TBD TBD Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W 10 8 6 TBD 4 2 0 0 50 100 150 200 250 Figure 44. Typical Output Delay or Hold vs. Load Capacitance (at Ambient Temperature) THERMAL CHARACTERISTICS The ADSP-21469 processor is rated for performance over the temperature range specified in Operating Conditions on Page 16. Table 47 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-to-board measurement complies with JESD51-8. Test board design complies with JEDEC standards JESD51-7 (PBGA). The junction-to-case measurement complies with MIL- STD-883. All measurements use a 2S2P JEDEC test board. To determine the junction temperature of the device while on the application PCB, use: T J = T CASE + ( Ψ JT × P D ) where: TJ = junction temperature °C TCASE = case temperature (°C) measured at the top center of the package ΨJT = junction-to-top (of package) characterization parameter is the Typical value from Table 47. PD = power dissipation Values of θJA are provided for package comparison and PCB design considerations. θJA can be used for a first order approximation of TJ by the equation: T J = T A + ( θ JA × P D ) where: TA = ambient temperature °C Values of θJC are provided for package comparison and PCB design considerations when an external heatsink is required. Rev. PrB | Page 51 of 56 | November 2008 ADSP-21469/ADSP-21469W BALL CONFIGURATION - ADSP-21469 Figure 45 shows the ball configuration for the ASDP-21469. Preliminary Technical Data A1 CORNER INDEX AREA 1 A B C D E F G H J K L M N P R T U V VDDINT VDDEXT VSS NC I/O SIGNALS D R T A S T A S D D D R D D D D D D D D R D D D D D D 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 VDD_DDR2 VREF VDD_THD VDD_A VSS_A Figure 45. ADSP-21469 Ball Configuration - Pin Out Rev. PrB | Page 52 of 56 | November 2008 Preliminary Technical Data PBGA PINOUT Table 48 lists the pin assignments of the ADSP-21469 SHARC processor. Table 48. 19 mm by 19 mm PBGA Pin Assignment (Alphabetically by Signal) Signal AMI_ACK AMI_ADDR0 AMI_ADDR1 AMI_ADDR2 AMI_ADDR3 AMI_ADDR4 AMI_ADDR5 AMI_ADDR6 AMI_ADDR7 AMI_ADDR8 AMI_ADDR9 AMI_ADDR10 AMI_ADDR11 AMI_ADDR12 AMI_ADDR13 AMI_ADDR14 AMI_ADDR15 AMI_ADDR16 AMI_ADDR17 AMI_ADDR18 AMI_ADDR19 AMI_ADDR20 AMI_ADDR21 AMI_ADDR22 AMI_ADDR23 AMI_DATA0 AMI_DATA1 AMI_DATA2 AMI_DATA3 AMI_DATA4 AMI_DATA5 AMI_DATA6 AMI_DATA7 AMI_MS0 AMI_MS1 AMI_RD AMI_WR BOOT_CFG0 BOOT_CFG1 BOOT_CFG2 BR1 BR2 Ball R10 V16 U16 T16 R16 V15 U15 T15 R15 V14 U14 T14 R14 V13 U13 T13 R13 V12 U12 T12 R12 V11 U11 T11 R11 U18 T18 R18 P18 V17 U17 T17 R17 T10 U10 J4 V10 J2 J3 H3 V8 U8 Signal BR3 BR4 BR5 BR6 CLK_CFG0 CLK_CFG1 CLKIN CLKOUT/RESETOUT/RUNRSTIN DAI_P1 DAI_P2 DAI_P3 DAI_P4 DAI_P5 DAI_P6 DAI_P7 DAI_P8 DAI_P9 DAI_P10 DAI_P11 DAI_P12 DAI_P13 DAI_P14 DAI_P15 DAI_P16 DAI_P17 DAI_P18 DAI_P19 DAI_P20 DDR2_ADDR0 DDR2_ADDR1 DDR2_ADDR2 DDR2_ADDR3 DDR2_ADDR4 DDR2_ADDR5 DDR2_ADDR6 DDR2_ADDR7 DDR2_ADDR8 DDR2_ADDR9 DDR2_ADDR10 DDR2_ADDR11 DDR2_ADDR12 DDR2_ADDR13 Ball T8 V9 U9 T9 G1 G2 L1 M2 R7 V6 U6 T6 R6 V5 U5 T5 R5 V4 U4 T4 R4 V3 U3 T3 R3 V2 U2 T2 D13 C13 D14 C14 B14 A14 D15 C15 B15 A15 D16 C16 B16 A16 ADSP-21469/ADSP-21469W Signal DDR2_ADDR14 DDR2_ADDR15 DDR2_BA0 DDR2_BA1 DDR2_BA2 DDR2_CAS DDR2_CKE DDR2_CLK0 DDR2_CLK0 DDR2_CLK1 DDR2_CLK1 DDR2_CS0 DDR2_CS1 DDR2_CS2 DDR2_CS3 DDR2_DATA0 DDR2_DATA1 DDR2_DATA2 DDR2_DATA3 DDR2_DATA4 DDR2_DATA5 DDR2_DATA6 DDR2_DATA7 DDR2_DATA8 DDR2_DATA9 DDR2_DATA10 DDR2_DATA11 DDR2_DATA12 DDR2_DATA13 DDR2_DATA14 DDR2_DATA15 DDR2_DM0 DDR2_DM1 DDR2_DQS0 DDR2_DQS0 DDR2_DQS1 DDR2_DQS1 DDR2_ODT DDR2_RAS DDR2_WE DPI_P1 DPI_P2 Ball B17 A17 C18 C17 B18 C7 E1 B7 A7 B13 A13 C1 D1 C2 D2 B2 A2 B3 A3 B5 A5 B6 A6 B8 A8 B9 A9 A11 B11 A12 B12 C3 C11 A4 B4 A10 B10 B1 C9 C10 R2 U1 Signal DPI_P3 DPI_P4 DPI_P5 DPI_P6 DPI_P7 DPI_P8 DPI_P9 DPI_P10 DPI_P11 DPI_P12 DPI_P13 DPI_P14 EMU FLAG0 FLAG1 FLAG2 FLAG3 ID_0 ID_1 ID_2 LACK_0 LACK_1 LCLK_0 LCLK_1 LDAT0_0 LDAT0_1 LDAT0_2 LDAT0_3 LDAT0_4 LDAT0_5 LDAT0_6 LDAT0_7 LDAT1_0 LDAT1_1 LDAT1_2 LDAT1_3 LDAT1_4 LDAT1_5 LDAT1_6 LDAT1_7 NC NC Ball T1 R1 P1 P2 P3 P4 N1 N2 N3 N4 M3 M4 K2 R8 V7 U7 T7 G3 G4 G5 K17 P17 J18 N18 E18 F17 F18 G17 G18 H16 H17 J16 K18 L16 L17 L18 M16 M17 N16 P16 F1 K3 Rev. PrB | Page 53 of 56 | November 2008 ADSP-21469/ADSP-21469W Table 48. 19 mm by 19 mm PBGA Pin Assignment (Alphabetically by Signal) Signal NC NC NC NC RESET RPBA TCK TDI TDO THD_M THD_P TMS TRST VDD_A VDD_DDR2 VDD_DDR2 VDD_DDR2 VDD_DDR2 VDD_DDR2 VDD_DDR2 VDD_DDR2 VDD_DDR2 VDD_DDR2 VDD_DDR2 VDD_DDR2 VDD_DDR2 VDD_DDR2 VDD_DDR2 VDD_DDR2 VDD_DDR2 VDD_DDR2 VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT Ball K4 L2 L3 L4 M1 R9 K15 L15 M15 N12 N11 K16 N15 H1 C5 C12 D3 D6 D8 D18 E2 E4 E7 E10 E11 E17 F3 F5 F15 G14 G16 H15 H18 J5 J15 K14 L5 M14 M18 N5 P6 P8 P10 P12 Signal VDD_EXT VDD_EXT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_THD VSS_A VSS VSS VSS VSS VSS VSS VSS Ball P14 P15 D12 E6 E8 E9 E14 E15 F6 F7 F8 F9 F10 F11 F12 F13 G6 G13 H5 H6 H13 H14 J6 J13 K6 K13 L6 L13 M6 M13 N6 N7 N8 N9 N13 N10 H2 A1 A18 C4 C6 C8 D5 D7 Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Preliminary Technical Data Ball D9 D10 D17 E3 E5 E12 E13 E16 F2 F4 F14 F16 G7 G8 G9 G10 G11 G12 G15 H4 H7 H8 H9 H10 H11 H12 J1 J7 J8 J9 J10 J11 J12 J14 J17 K5 K7 K8 K9 K10 K11 K12 L7 L8 Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VREF VREF XTAL Ball L9 L10 L11 L12 L14 M5 M7 M8 M9 M10 M11 M12 N14 N17 P5 P7 P9 P11 P13 V1 V18 D4 D11 K1 Rev. PrB | Page 54 of 56 | November 2008 Preliminary Technical Data OUTLINE DIMENSIONS The ADSP-21469 is available in a 19 mm by 19 mm PBGA leadfree package. ADSP-21469/ADSP-21469W BALL A1 PAD CORNER 19.20 19.00 SQ 18.80 18 16 14 12 10 8 6 4 2 17 15 13 11 9 7 5 3 1 A B C D E F G H J K L M N P R T U V BALL A1 PAD CORNER 17.05 16.95 SQ 16.85 17.00 BSC SQ 1.00 BSC TOP VIEW 2.40 2.28 2.16 DETAIL A 1.00 REF BOTTOM VIEW DETAIL A 0.61 NOM 1.22 1.17 1.12 0.50 NOM 0.40 MIN SEATING PLANE 0.70 0.60 0.50 BALL DIAMETER 0.20 COPLANARITY COMPLIANT TO JEDEC STANDARDS MS-034-BAR-2 Figure 46. 324-Ball Plastic Ball Grid Array [PBGA] (B-324) Dimensions shown in millimeters Rev. PrB | Page 55 of 56 | November 2008 ADSP-21469/ADSP-21469W AUTOMOTIVE PRODUCTS Preliminary Technical Data The ADSP-21469 is available for automotive applications with controlled manufacturing. Note that this special model may have specifications that differ from the general release models. The automotive grade product shown in Table 49 is available for use in automotive applications. Contact your local ADI account representative or authorized ADI product distributor for specific product ordering information. Note that all automotive products are RoHS compliant. Table 49. Automotive Products Model AD21469WBBZ3xx 1 Temperature Range1 –40°C to +85°C On-Chip SRAM Package Description 5M bit 324-Ball Plastic Ball Grid Array (PBGA) Package Option B-324-2 Referenced temperature is ambient temperature. ORDERING GUIDE Model ADSP-21469KBZ-ENG2, 3, 4 1 2 3 4 Temperature Range1 0 °C to +70 °C On-Chip SRAM Package Description 5 Mbit 324-Ball Plastic Ball Grid Array (PBGA) Package Option B-324-2 Referenced temperature is ambient temperature. Z =Part number subject to change. Z =RoHS Compliant Part Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at www.analog.com/SHARC ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07809-0-11/08(PrB) Rev. PrB | Page 56 of 56 | November 2008