ADSP-BF561

a FEATURES Dual symmetric 600 MHz high performance Blackfin cores 328K bytes of on-chip memory (see memory information on Page 4) Each Blackfin core includes: Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of programming and compiler-friendly support Advanced debug, trace, and performance monitoring 0.8 V to 1.35 V core VDD with on-chip voltage regulator 3.3 V and 2.5 V compliant I/O 256-ball mini-BGA and 297-ball PBGA package options Blackfin® Embedded Symmetric Multiprocessor ADSP-BF561 PERIPHERALS Two parallel input/output peripheral interface units supporting ITU-R 656 video and glueless interface to analog front end ADCs Two dual channel, full duplex synchronous serial ports supporting eight stereo I2S channels Dual 16-channel DMA controllers and one internal memory DMA controller 12 general-purpose 32-bit timers/counters, with PWM capability SPI®-compatible port UART with support for IrDA® Dual watchdog timers 48 programmable flags On-chip phase-locked loop capable of 0.5× to 64× frequency multiplication IRQ CONTROL/ WATCHDOG TIMER VOLTAGE REGULATOR B L1 INSTRUCTION MEMORY MMU L1 DATA MEMORY B L1 INSTRUCTION MEMORY MMU L1 DATA MEMORY IRQ CONTROL/ WATCHDOG TIMER JTAG TEST EMULATION UART IrDA SPI L2 SRAM 128K BYTES SPORT0 CORE SYSTEM/BUS INTERFACE IMDMA CONTROLLER SPORT1 EAB DMA CONTROLLER1 32 DEB BOOT ROM 32 DAB EXTERNAL PORT FLASH/SDRAM CONTROL PPI0 PPI1 DMA CONTROLLER2 DAB PAB 16 16 GPIO TIMERS Figure 1. Functional Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2006 Analog Devices, Inc. All rights reserved. ADSP-BF561 TABLE OF CONTENTS General Description ................................................. 4 Portable Low Power Architecture ............................. 4 Blackfin Processor Core .......................................... 4 Memory Architecture ............................................ 5 DMA Controllers .................................................. 9 Watchdog Timer .................................................. 9 Timers ............................................................. 10 Serial Ports (SPORTs) .......................................... 10 Serial Peripheral Interface (SPI) Port ....................... 10 UART Port ........................................................ 10 Programmable Flags (PFx) .................................... 11 Parallel Peripheral Interface ................................... 11 Dynamic Power Management ................................ 12 Voltage Regulation .............................................. 13 Clock Signals ..................................................... 13 Booting Modes ................................................... 14 Instruction Set Description ................................... 14 Development Tools ............................................. 15 Designing an Emulator-Compatible Processor Board (Target) ................................... 16 Related Documents ............................................. 16 Pin Descriptions .................................................... 17 Specifications ........................................................ 20 Recommended Operating Conditions ...................... 20 Electrical Characteristics ....................................... 20 Absolute Maximum Ratings .................................. 21 Package Information ........................................... 21 ESD Sensitivity ................................................... 21 Timing Specifications .......................................... 22 Clock and Reset Timing .................................... 23 Asynchronous Memory Read Cycle Timing ........... 24 Asynchronous Memory Write Cycle Timing .......... 25 SDRAM Interface Timing .................................. 26 External Port Bus Request and Grant Cycle Timing .. 27 Parallel Peripheral Interface Timing ..................... 28 Serial Ports ..................................................... 31 Serial Peripheral Interface (SPI) Port— Master Timing ............................................. 35 Serial Peripheral Interface (SPI) Port— Slave Timing ............................................... 36 Universal Asynchronous Receiver Transmitter (UART) Port—Receive and Transmit Timing ................. 37 Programmable Flags Cycle Timing ....................... 38 Timer Cycle Timing .......................................... 39 JTAG Test and Emulation Port Timing .................. 40 Output Drive Currents ......................................... 41 Power Dissipation ............................................... 42 Test Conditions .................................................. 43 Environmental Conditions .................................... 45 256-Ball MBGA Pinout ............................................ 46 297-Ball PBGA Pinout ............................................. 51 Outline Dimensions ................................................ 56 Ordering Guide ..................................................... 58 Rev. A | Page 2 of 60 | May 2006 ADSP-BF561 REVISION HISTORY 5/06—Changes from Rev. 0 to Rev. A Minor format and wording changes throughout the docunment. Changed voltage range in Features.................................1 Changed PLL multiplier range in Peripherals ...................1 Changed figure Blackfin Processor Core..........................5 Changed title of Table 2 ..............................................8 Moved section Timers .............................................. 10 Replaced section Parallel Peripheral Interface ................. 11 Replaced figure Frequency Modification Methods ........... 13 Added section EZ-KIT Lite Evaluation Board ................. 16 Added section Related Documents............................... 16 Reformated table Pin Descriptions............................... 17 Changed Recommended Operating Conditions .............. 20 Changed CIN in Electrical Characteristics....................... 20 Changed Absolute Maximum Ratings........................... 21 Added Maximum Duty Cycle for Input Transient Voltage. 21 Added Package Information....................................... 21 Changed Core Clock Requirements ............................. 22 Added Maximum SCLK Conditions............................. 22 Changed figure Clock and Reset Timing ....................... 23 Changed SDRAM Interface Timing ............................. 26 Changed Parallel Peripheral Interface Timing................. 28 Changed figures in Parallel Peripheral Interface Timing.... 28 Changed figure Serial Ports ........................................ 32 Rewrote/Changed values in Power Dissipation ............... 42 Rewrote section Test Conditions ................................. 43 Changed title of Figure 37 through Figure 44.................. 44 Reordered Table 36 .................................................. 46 Added Table 37....................................................... 48 Added Figure 47 and Figure 48 ................................... 50 Added Figure 45 and Figure 46 ................................... 50 Reordered Table 38 .................................................. 51 Added Table 39....................................................... 53 Added Section for Surface Mount Design ...................... 57 Changed Ordering Guide .......................................... 58 1/05—Initial version Rev. A | Page 3 of 60 | May 2006 ADSP-BF561 GENERAL DESCRIPTION The ADSP-BF561 processor is a high performance member of the Blackfin family of products targeting a variety of multimedia, industrial, and telecommunications applications. At the heart of this device are two independent Analog Devices Blackfin processors. These Blackfin processors combine a dualMAC state-of-the-art signal processing engine, the advantage of a clean, orthogonal RISC-like microprocessor instruction set, and single instruction, multiple data (SIMD) multimedia capabilities in a single instruction set architecture. The ADSP-BF561 processor has 328K bytes of on-chip memory. Each Blackfin core includes: • 16K bytes of instruction SRAM/cache • 16K bytes of instruction SRAM • 32K bytes of data SRAM/cache • 32K bytes of data SRAM • 4K bytes of scratchpad SRAM Additional on-chip memory peripherals include: • 128K bytes of low latency on-chip L2 SRAM • Four-channel internal memory DMA controller • External memory controller with glueless support for SDRAM, mobile SDRAM, SRAM, and flash. The powerful 40-bit shifter has extensive capabilities for performing shifting, rotating, normalization, extraction, and depositing of data. The data for the computational units is found in a multiported register file of sixteen 16-bit entries or eight 32-bit entries. A powerful program sequencer controls the flow of instruction execution, including instruction alignment and decoding. The sequencer supports conditional jumps and subroutine calls, as well as zero overhead looping. A loop buffer stores instructions locally, eliminating instruction memory accesses for tight looped code. Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches from memory. The DAGs share a register file containing four sets of 32-bit Index, Modify, Length, and Base registers. Eight additional 32-bit registers provide pointers for general indexing of variables and stack locations. Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. Level 2 (L2) memories are other memories, on-chip or off-chip, that may take multiple processor cycles to access. At the L1 level, the instruction memory holds instructions only. The two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. At the L2 level, there is a single unified memory space, holding both instructions and data. In addition, half of L1 instruction memory and half of L1 data memory may be configured as either Static RAMs (SRAMs) or caches. The Memory Management Unit (MMU) provides memory protection for individual tasks that may be operating on the core and may protect system registers from unintended access. The architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources. The Blackfin instruction set has been optimized so that 16-bit op-codes represent the most frequently used instructions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit op-codes, representing fully featured multifunction instructions. Blackfin processors support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle. The Blackfin assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been optimized for use in conjunction with the VisualDSP C/C++ compiler, resulting in fast and efficient software implementations. PORTABLE LOW POWER ARCHITECTURE Blackfin processors provide world-class power management and performance. Blackfin processors are designed in a low power and low voltage design methodology and feature dynamic power management, the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. Varying the voltage and frequency can result in a substantial reduction in power consumption, compared with just varying the frequency of operation. This translates into longer battery life for portable appliances. BLACKFIN PROCESSOR CORE As shown in Figure 2, each Blackfin core contains two multiplier/accumulators (MACs), two 40-bit ALUs, four video ALUs, and a single shifter. The computational units process 8-bit, 16-bit, or 32-bit data from the register file. Each MAC performs a 16-bit by 16-bit multiply in every cycle, with accumulation to a 40-bit result, providing eight bits of extended precision. The ALUs perform a standard set of arithmetic and logical operations. With two ALUs capable of operating on 16-bit or 32-bit data, the flexibility of the computation units covers the signal processing requirements of a varied set of application needs. Each of the two 32-bit input registers can be regarded as two 16-bit halves, so each ALU can accomplish very flexible single 16-bit arithmetic operations. By viewing the registers as pairs of 16-bit operands, dual 16-bit or single 32-bit operations can be accomplished in a single cycle. By further taking advantage of the second ALU, quad 16-bit operations can be accomplished simply, accelerating the per cycle throughput. Rev. A | Page 4 of 60 | May 2006 ADSP-BF561 ADDRESS ARITHMETIC UNIT I3 I2 I1 I0 DA1 DA0 TO MEMORY 32 32 L3 L2 L1 L0 B3 B2 B1 B0 M3 M2 M1 M0 DAG1 DAG0 SP FP P5 P4 P3 P2 P1 P0 32 RAB 32 PREG SD LD1 LD0 32 32 32 32 32 ASTAT SEQUENCER R7.H R6.H R5.H R4.H R3.H R2.H R1.H R0.H R7.L R6.L R5.L R4.L R3.L R2.L R1.H R0.L BARREL SHIFTER 16 8 8 8 16 8 DECODE ALIGN 40 40 40 40 LOOP BUFFER A0 A1 CONTROL UNIT 32 32 DATA ARITHMETIC UNIT Figure 2. Blackfin Processor Core MEMORY ARCHITECTURE The ADSP-BF561 views memory as a single unified 4G byte address space, using 32-bit addresses. All resources including internal memory, external memory, and I/O control registers occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low latency memory as cache or SRAM very close to the processor, and larger, lower cost and performance memory systems farther away from the processor. The ADSP-BF561 memory map is shown in Figure 3. The L1 memory system in each core is the highest performance memory available to each Blackfin core. The L2 memory provides additional capacity with lower performance. Lastly, the off-chip memory system, accessed through the External Bus Interface Unit (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing more than 768M bytes of physical memory. The memory DMA controllers provide high bandwidth data movement capability. They can perform block transfers of code or data between the internal L1/L2 memories and the external memory spaces. Internal (On-Chip) Memory The ADSP-BF561 has four blocks of on-chip memory providing high bandwidth access to the core. The first is the L1 instruction memory of each Blackfin core consisting of 16K bytes of four-way set-associative cache memory and 16K bytes of SRAM. The cache memory may also be configured as an SRAM. This memory is accessed at full processor speed. When configured as SRAM, each of the two 16K banks of memory is broken into 4K sub-banks which can be independently accessed by the processor and DMA. The second on-chip memory block is the L1 data memory of each Blackfin core which consists of four banks of 16K bytes each. Two of the L1 data memory banks can be configured as one way of a two-way set-associative cache or as an SRAM. The other two banks are configured as SRAM. All banks are accessed at full processor speed. When configured as SRAM, each of the four 16K banks of memory is broken into 4K sub-banks which can be independently accessed by the processor and DMA. The third memory block associated with each core is a 4K byte scratchpad SRAM which runs at the same speed as the L1 memories, but is only accessible as data SRAM (it cannot be configured as cache memory and is not accessible via DMA). Rev. A | Page 5 of 60 | May 2006 ADSP-BF561 CORE A MEMORY MAP 0xFFFF FFFF 0xFFE0 0000 0xFFC0 0000 0xFFB0 1000 0xFFB0 0000 0xFFA1 4000 0xFFA1 0000 0xFFA0 4000 0xFFA0 0000 0xFF90 8000 0xFF90 4000 0xFF90 0000 0xFF80 8000 0xFF80 4000 0xFF80 0000 RESERVED L1 SCRATCHPAD SRAM (4K) RESERVED L1 INSTRUCTION SRAM/CACHE (16K) RESERVED L1 INSTRUCTION SRAM (16K) RESERVED L1 DATA BANK B SRAM/CACHE (16K) L1 DATA BANK B SRAM (16K) RESERVED L1 DATA BANK A SRAM/CACHE (16K) L1 DATA BANK A SRAM (16K) RESERVED L1 SCRATCHPAD SRAM (4K) RESERVED L1 INSTRUCTION SRAM/CACHE (16K) RESERVED RESERVED L1 INSTRUCTION SRAM (16K) RESERVED L1 DATA BANK B SRAM/CACHE (16K) L1 DATA BANK B SRAM (16K) RESERVED L1 DATA BANK A SRAM/CACHE (16K) L1 DATA BANK A SRAM (16K) 0xFEB2 0000 0xFEB0 0000 0xEF00 4000 0xEF00 0000 0x3000 0000 0x2C00 0000 0x2800 0000 0x2400 0000 0x2000 0000 Top of last SDRAM page RESERVED L2 SRAM (128K) RESERVED BOOT ROM RESERVED ASYNC MEMORY BANK 3 ASYNC MEMORY BANK 2 ASYNC MEMORY BANK 1 ASYNC MEMORY BANK 0 RESERVED SDRAM BANK 3 SDRAM BANK 2 SDRAM BANK 1 0x0000 0000 SDRAM BANK 0 EXTERNAL MEMORY 0xFF80 0000 0xFF70 1000 0xFF70 0000 0xFF61 4000 0xFF61 0000 0xFF60 4000 0xFF60 0000 0xFF50 8000 0xFF50 4000 0xFF50 0000 0xFF40 8000 0xFF40 4000 0xFF40 0000 INTERNAL MEMORY RESERVED CORE MMR REGISTERS CORE MMR REGISTERS SYSTEM MMR REGISTERS CORE B MEMORY MAP Figure 3. Memory Map The fourth on-chip memory system is the L2 SRAM memory array which provides 128K bytes of high speed SRAM operating at one half the frequency of the core, and slightly longer latency than the L1 memory banks. The L2 memory is a unified instruction and data memory and can hold any mixture of code and data required by the system design. The Blackfin cores share a dedicated low latency 64-bit wide data path port into the L2 SRAM memory. Each Blackfin core processor has its own set of core Memory Mapped Registers (MMRs) but share the same system MMR registers and 128K bytes L2 SRAM memory. (SDRAM) as well as up to four banks of asynchronous memory devices, including flash, EPROM, ROM, SRAM, and memory mapped I/O devices. The PC133-compliant SDRAM controller can be programmed to interface to up to four banks of SDRAM, with each bank containing between 16M bytes and 128M bytes providing access to up to 512M bytes of SDRAM. Each bank is independently programmable and is contiguous with adjacent banks regardless of the sizes of the different banks or their placement. This allows flexible configuration and upgradability of system memory while allowing the core to view all SDRAM as a single, contiguous, physical address space. The asynchronous memory controller can also be programmed to control up to four banks of devices with very flexible timing parameters for a wide variety of devices. Each bank occupies a External (Off-Chip) Memory The ADSP-BF561 external memory is accessed via the External Bus Interface Unit (EBIU). This interface provides a glueless connection to up to four banks of synchronous DRAM Rev. A | Page 6 of 60 | May 2006 ADSP-BF561 64M byte segment regardless of the size of the devices used so that these banks will only be contiguous if fully populated with 64M bytes of memory. The ADSP-BF561 event controller consists of two stages: the Core Event Controller (CEC) and the System Interrupt Controller (SIC). The Core Event Controller works with the System Interrupt Controller to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into the SIC, and are then routed directly into the general-purpose interrupts of the CEC. I/O Memory Space Blackfin processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. Onchip I/O devices have their control registers mapped into memory mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks, one which contains the control MMRs for all core functions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. The core MMRs are accessible only by the core and only in supervisor mode and appear as reserved space by on-chip peripherals. The system MMRs are accessible by the core in supervisor mode and can be mapped as either visible or reserved to other devices, depending on the system protection model desired. Core Event Controller (CEC) The CEC supports nine general-purpose interrupts (IVG15–7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest priority interrupts (IVG15–14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the ADSP-BF561. Table 1 describes the inputs to the CEC, identifies their names in the Event Vector Table (EVT), and lists their priorities. Table 1. Core Event Controller (CEC) Priority (0 is Highest) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Event Class Emulation/Test Control Reset Nonmaskable Interrupt Exceptions Global Enable Hardware Error Core Timer General Interrupt 7 General Interrupt 8 General Interrupt 9 General Interrupt 10 General Interrupt 11 General Interrupt 12 General Interrupt 13 General Interrupt 14 General Interrupt 15 EVT Entry EMU RST NMI EVX IVHW IVTMR IVG7 IVG8 IVG9 IVG10 IVG11 IVG12 IVG13 IVG14 IVG15 Booting The ADSP-BF561 contains a small boot kernel, which configures the appropriate peripheral for booting. If the ADSP-BF561 is configured to boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. Event Handling The event controller on the ADSP-BF561 handles all asynchronous and synchronous events to the processor. The ADSP-BF561 provides event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher priority event takes precedence over servicing of a lower priority event. The controller provides support for five different types of events: • Emulation – An emulation event causes the processor to enter emulation mode, allowing command and control of the processor via the JTAG interface. • Reset – This event resets the processor. • Nonmaskable Interrupt (NMI) – The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shutdown of the system. • Exceptions – Events that occur synchronously to program flow, i.e., the exception will be taken before the instruction is allowed to complete. Conditions such as data alignment violations or undefined instructions cause exceptions. • Interrupts – Events that occur asynchronously to program flow. They are caused by timers, peripherals, input pins, and an explicit software instruction. Each event has an associated register to hold the return address and an associated “return from event” instruction. When an event is triggered, the state of the processor is saved on the supervisor stack. System Interrupt Controller (SIC) The System Interrupt Controller provides the mapping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the ADSP-BF561 provides a default mapping, the user can alter the mappings and priorities of interrupt events by writ- Rev. A | Page 7 of 60 | May 2006 ADSP-BF561 ing the appropriate values into the Interrupt Assignment Registers (SIC_IAR7–0). Table 2 describes the inputs into the SIC and the default mappings into the CEC. Table 2. System Interrupt Controller (SIC) Peripheral Interrupt Event PLL wakeup DMA1 Error (generic) DMA2 Error (generic) IMDMA Error PPI0 Error PPI1 Error SPORT0 Error SPORT1 Error SPI Error UART Error Reserved DMA1 Channel 0 Interrupt (PPI0) DMA1 Channel 1 Interrupt (PPI1) DMA1 Channel 2 Interrupt DMA1 Channel 3 Interrupt DMA1 Channel 4 Interrupt DMA1 Channel 5 Interrupt DMA1 Channel 6 Interrupt DMA1 Channel 7 Interrupt DMA1 Channel 8 Interrupt DMA1 Channel 9 Interrupt DMA1 Channel 10 Interrupt DMA1 Channel 11 Interrupt DMA2 Channel 0 Interrupt (SPORT0 RX) DMA2 Channel 1 Interrupt (SPORT0 TX) DMA2 Channel 2 Interrupt (SPORT1 RX) DMA2 Channel 3 Interrupt (SPORT1 TX) DMA2 Channel 4 Interrupt (SPI) DMA2 Channel 5 Interrupt (UART RX) DMA2 Channel 6 Interrupt (UART TX) DMA2 Channel 7 Interrupt DMA2 Channel 8 Interrupt DMA2 Channel 9 Interrupt DMA2 Channel 10 Interrupt DMA2 Channel 11 Interrupt Timer0 Interrupt Timer1 Interrupt Timer2 Interrupt Timer3 Interrupt Timer4 Interrupt Timer5 Interrupt Timer6 Interrupt Default Mapping IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG8 IVG8 IVG8 IVG8 IVG8 IVG8 IVG8 IVG8 IVG8 IVG8 IVG8 IVG8 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 Table 2. System Interrupt Controller (SIC) (Continued) Peripheral Interrupt Event Timer7 Interrupt Timer8 Interrupt Timer9 Interrupt Timer10 Interrupt Timer11 Interrupt Programmable Flags 15–0 Interrupt A Programmable Flags 15–0 Interrupt B Programmable Flags 31–16 Interrupt A Programmable Flags 31–16 Interrupt B Programmable Flags 47–32 Interrupt A Programmable Flags 47–32 Interrupt B DMA1 Channel 12/13 Interrupt (Memory DMA/Stream 0) DMA1 Channel 14/15 Interrupt (Memory DMA/Stream 1) DMA2 Channel 12/13 Interrupt (Memory DMA/Stream 0) DMA2 Channel 14/15 Interrupt (Memory DMA/Stream 1) IMDMA Stream 0 Interrupt IMDMA Stream 1 Interrupt Watchdog Timer Interrupt Reserved Reserved Supplemental Interrupt 0 Supplemental Interrupt 1 Default Mapping IVG10 IVG10 IVG10 IVG10 IVG10 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG8 IVG8 IVG9 IVG9 IVG12 IVG12 IVG13 IVG7 IVG7 IVG7 IVG7 Event Control The ADSP-BF561 provides the user with a very flexible mechanism to control the processing of events. In the CEC, three registers are used to coordinate and control events. Each of the registers is 16 bits wide, while each bit represents a particular event class. • CEC Interrupt Latch Register (ILAT) – The ILAT register indicates when events have been latched. The appropriate bit is set when the processor has latched the event and cleared when the event has been accepted into the system. This register is updated automatically by the controller, but may be written only when its corresponding IMASK bit is cleared. • CEC Interrupt Mask Register (IMASK) – The IMASK register controls the masking and unmasking of individual events. When a bit is set in the IMASK register, that event is unmasked and will be processed by the CEC when asserted. A cleared bit in the IMASK register masks the event thereby preventing the processor from servicing the event even though the event may be latched in the ILAT register. This register may be read from or written to while in super- Rev. A | Page 8 of 60 | May 2006 ADSP-BF561 visor mode. (Note that general-purpose interrupts can be globally enabled and disabled with the STI and CLI instructions.) • CEC Interrupt Pending Register (IPEND) – The IPEND register keeps track of all nested events. A set bit in the IPEND register indicates the event is currently active or nested at some level. This register is updated automatically by the controller but may be read while in supervisor mode. The SIC allows further control of event processing by providing six 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events shown in Table 2. • SIC Interrupt Mask Register (SIC_IMASK0, SIC_IMASK1) – This register controls the masking and unmasking of each peripheral interrupt event. When a bit is set in the register, that peripheral event is unmasked and will be processed by the system when asserted. A cleared bit in the register masks the peripheral event thereby preventing the processor from servicing the event. • SIC Interrupt Status Register (SIC_ISR0, SIC_ISR1)– As multiple peripherals can be mapped to a single event, this register allows the software to determine which peripheral event source triggered the interrupt. A set bit indicates the peripheral is asserting the interrupt; a cleared bit indicates the peripheral is not asserting the event. • SIC Interrupt Wakeup Enable Register (SIC_IWR0, SIC_IWR1) – By enabling the corresponding bit in this register, each peripheral can be configured to wake up the processor, should the processor be in a powered-down mode when the event is generated. Because multiple interrupt sources can map to a single generalpurpose interrupt, multiple pulse assertions can occur simultaneously, before or during interrupt processing for an interrupt event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt acknowledgement. The appropriate ILAT register bit is set when an interrupt rising edge is detected (detection requires two core clock cycles). The bit is cleared when the respective IPEND register bit is set. The IPEND bit indicates that the event has entered into the processor pipeline. At this point the CEC will recognize and queue the next rising edge event on the corresponding event input. The minimum latency from the rising edge transition of the generalpurpose interrupt to the IPEND output asserted is three core clock cycles; however, the latency can be much higher, depending on the activity within and the mode of the processor. ler. DMA-capable peripherals include the SPORTs, SPI port, UART, and PPI. Each individual DMA-capable peripheral has at least one dedicated DMA channel. The ADSP-BF561 DMA controllers support both 1-dimensional (1-D) and 2-dimensional (2-D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks. The 2-D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to ± 32K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved data streams. This feature is especially useful in video applications where data can be deinterleaved on the fly. Examples of DMA types supported by the ADSP-BF561 DMA controllers include: • A single linear buffer that stops upon completion. • A circular autorefreshing buffer that interrupts on each full or fractionally full buffer. • 1-D or 2-D DMA using a linked list of descriptors. • 2-D DMA using an array of descriptors, specifying only the base DMA address within a common page. In addition to the dedicated peripheral DMA channels, each DMA Controller has four memory DMA channels provided for transfers between the various memories of the ADSP-BF561 system. These enable transfers of blocks of data between any of the memories—including external SDRAM, ROM, SRAM, and flash memory—with minimal processor intervention. Memory DMA transfers can be controlled by a very flexible descriptorbased methodology or by a standard register-based autobuffer mechanism. Further, the ADSP-BF561 has a four channel Internal Memory DMA (IMDMA) Controller. The IMDMA Controller allows data transfers between any of the internal L1 and L2 memories. WATCHDOG TIMER Each ADSP-BF561 core includes a 32-bit timer, which can be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known state, via generation of a hardware reset, nonmaskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the timer control register, which is set only upon a watchdog generated reset. DMA CONTROLLERS The ADSP-BF561 has multiple, independent DMA controllers that support automated data transfers with minimal overhead for the DSP core. DMA transfers can occur between the ADSP-BF561 internal memories and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory controlRev. A | Page 9 of 60 | May 2006 ADSP-BF561 The timer is clocked by the system clock (SCLK) at a maximum frequency of fSCLK. • Interrupts – Each transmit and receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer or buffers through DMA. • Multichannel capability – Each SPORT supports 128 channels out of a 1,024-channel window and is compatible with the H.100, H.110, MVIP-90, and HMVIP standards. TIMERS There are 14 programmable timer units in the ADSP-BF561. Each of the 12 general-purpose timer units can be independently programmed as a Pulse-Width Modulator (PWM), internally or externally clocked timer, or pulse-width counter. The general-purpose timer units can be used in conjunction with the UART to measure the width of the pulses in the data stream to provide an autobaud detect function for a serial channel. The general-purpose timers can generate interrupts to the processor core providing periodic events for synchronization, either to the processor clock or to a count of external signals. In addition to the 12 general-purpose programmable timers, another timer is also provided for each core. These extra timers are clocked by the internal processor clock (CCLK) and are typically used as a system tick clock for generation of operating system periodic interrupts. SERIAL PERIPHERAL INTERFACE (SPI) PORT The ADSP-BF561 processor has an SPI-compatible port that enables the processor to communicate with multiple SPI-compatible devices. The SPI interface uses three pins for transferring data: two data pins (master output-slave input, MOSI, and master input-slave output, MISO) and a clock pin (serial clock, SCK). An SPI chip select input pin (SPISS) lets other SPI devices select the processor, and seven SPI chip select output pins (SPISEL7–1) let the processor select other SPI devices. The SPI select pins are reconfigured programmable flag pins. Using these pins, the SPI port provides a full-duplex, synchronous serial interface which supports both master/slave modes and multimaster environments. The baud rate and clock phase/polarities for the SPI port are programmable, and it has an integrated DMA controller, configurable to support transmit or receive data streams. The SPI DMA controller can only service unidirectional accesses at any given time. The SPI port clock rate is calculated as: f SCLK SPI Clock Rate = -------------------------------2 × SPI_Baud Where the 16-bit SPI_Baud register contains a value of 2 to 65,535. During transfers, the SPI port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines. SERIAL PORTS (SPORTs) The ADSP-BF561 incorporates two dual-channel synchronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support the following features: • I2S capable operation. • Bidirectional operation – Each SPORT has two sets of independent transmit and receive pins, enabling eight channels of I2S stereo audio. • Buffered (8-deep) transmit and receive ports – Each port has a data register for transferring data words to and from other DSP components and shift registers for shifting data in and out of the data registers. • Clocking – Each transmit and receive port can either use an external serial clock or generate its own, in frequencies ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz. • Word length – Each SPORT supports serial data words from 3 bits to 32 bits in length, transferred most significant bit first or least significant bit first. • Framing – Each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulse-widths and early or late frame sync. • Companding in hardware – Each SPORT can perform A-law or µ-law companding according to ITU recommendation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional latencies. • DMA operations with single-cycle overhead – Each SPORT can automatically receive and transmit multiple buffers of memory data. The DSP can link or chain sequences of DMA transfers between a SPORT and memory. UART PORT The ADSP-BF561 processor provides a full-duplex universal asynchronous receiver/transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. The UART port includes support for 5 data bits to 8 data bits, 1 stop bit or 2 stop bits, and none, even, or odd parity. The UART port supports two modes of operation: • PIO (programmed I/O) – The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive. • DMA (direct memory access) – The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated Rev. A | Page 10 of 60 | May 2006 ADSP-BF561 DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates. The baud rate, serial data format, error code generation and status, and interrupts for the UART port are programmable. The UART programmable features include: • Supporting bit rates ranging from (fSCLK/1,048,576) bits per second to (fSCLK/16) bits per second. • Supporting data formats from seven bits to 12 bits per frame. • Both transmit and receive operations can be configured to generate maskable interrupts to the processor. The UART port’s clock rate is calculated as: f SCLK UART Clock Rate = ----------------------------------------------16 × UART_Divisor Where the 16-bit UART_Divisor comes from the DLH register (most significant 8 bits) and DLL register (least significant 8 bits). In conjunction with the general-purpose timer functions, autobaud detection is supported. The capabilities of the UART are further extended with support for the Infrared Data Association (IrDA) serial infrared physical layer link specification (SIR) protocol. defined as inputs can be configured to generate hardware interrupts, while output PFx pins can be configured to generate software interrupts. • Flag Interrupt Sensitivity Registers – The Flag Interrupt Sensitivity Registers specify whether individual PFx pins are level- or edge-sensitive and specify, if edge-sensitive, whether just the rising edge or both the rising and falling edges of the signal are significant. One register selects the type of sensitivity, and one register selects which edges are significant for edge sensitivity. PARALLEL PERIPHERAL INTERFACE The ADSP-BF561 processor provides two parallel peripheral interfaces (PPI0, PPI1) that can connect directly to parallel A/D and D/A converters, ITU-R 601/656 video encoders and decoders, and other general-purpose peripherals. Each PPI consists of a dedicated input clock pin, up to three frame synchronization pins, and up to 16 data pins. The input clock supports parallel data rates up to half the system clock rate. In ITU-R 656 modes, the PPI receives and parses a data stream of 8-bit or 10-bit data elements. On-chip decode of embedded preamble control and synchronization information is supported. Three distinct ITU-R 656 modes are supported: • Active video only – The PPI does not read in any data between the end of active video (EAV) and start of active video (SAV) preamble symbols, or any data present during the vertical blanking intervals. In this mode, the control byte sequences are not stored to memory; they are filtered by the PPI. • Vertical blanking only – The PPI only transfers vertical blanking interval (VBI) data, as well as horizontal blanking information and control byte sequences on VBI lines. • Entire field – The entire incoming bitstream is read in through the PPI. This includes active video, control preamble sequences, and ancillary data that may be embedded in horizontal and vertical blanking intervals. Though not explicitly supported, ITU-R 656 output functionality can be achieved by setting up the entire frame structure (including active video, blanking, and control information) in memory and streaming the data out the PPI in a frame sync-less mode. The processor’s 2-D DMA features facilitate this transfer by allowing the static frame buffer (blanking and control codes) to be placed in memory once, and simply updating the active video information on a per-frame basis. The general-purpose modes of the PPI are intended to suit a wide variety of data capture and transmission applications. The modes are divided into four main categories, each allowing up to 16 bits of data transfer per PPI_CLK cycle: • Data receive with internally generated frame syncs • Data receive with externally generated frame syncs • Data transmit with internally generated frame syncs • Data transmit with externally generated frame syncs PROGRAMMABLE FLAGS (PFx) The ADSP-BF561 has 48 bidirectional, general-purpose I/O, programmable flag (PF47–0) pins. The programmable flag pins have special functions for SPI port operation. Each programmable flag can be individually controlled by manipulation of the flag control, status, and interrupt registers as follows: • Flag Direction Control Register – Specifies the direction of each individual PFx pin as input or output. • Flag Control and Status Registers – Rather than forcing the software to use a read-modify-write process to control the setting of individual flags, the ADSP-BF561 employs a “write one to set” and “write one to clear” mechanism that allows any combination of individual flags to be set or cleared in a single instruction, without affecting the level of any other flags. Two control registers are provided, one register is written-to in order to set flag values, while another register is written-to in order to clear flag values. Reading the flag status register allows software to interrogate the sense of the flags. • Flag Interrupt Mask Registers – The Flag Interrupt Mask Registers allow each individual PFx pin to function as an interrupt to the processor. Similar to the Flag Control Registers that are used to set and clear individual flag values, one Flag Interrupt Mask Register sets bits to enable an interrupt function, and the other Flag Interrupt Mask Register clears bits to disable an interrupt function. PFx pins Rev. A | Page 11 of 60 | May 2006 ADSP-BF561 These modes support ADC/DAC connections, as well as video communication with hardware signaling. Many of the modes support more than one level of frame synchronization. If desired, a programmable delay can be inserted between assertion of a frame sync and reception/transmission of data. Deep Sleep Operating Mode—Maximum Dynamic Power Savings The Deep Sleep mode maximizes power savings by disabling the clocks to the processor cores (CCLK) and to all synchronous peripherals (SCLK). Asynchronous peripherals will not be able to access internal resources or external memory. This powereddown mode can only be exited by assertion of the reset interrupt (RESET). If BYPASS is disabled, the processor will transition to the Full-On mode. If BYPASS is enabled, the processor will transition to the Active mode. DYNAMIC POWER MANAGEMENT The ADSP-BF561 provides four power management modes and one power management state, each with a different performance/power profile. In addition, Dynamic Power Management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation. Control of clocking to each of the ADSP-BF561 peripherals also reduces power consumption. See Table 3 for a summary of the power settings for each mode. Table 3. Power Settings PLL Mode PLL Bypassed Full-On Enabled No Active Enabled/ Yes Disabled Sleep Enabled – Deep Sleep Disabled – Hibernate Disabled – Core Clock (CCLK) Enabled Enabled System Clock (SCLK) Enabled Enabled Core Power On On Hibernate Operating State—Maximum Static Power Savings The Hibernate state maximizes static power savings by disabling the voltage and clocks to the processor core (CCLK) and to all the synchronous peripherals (SCLK). The internal voltage regulator for the processor can be shut off by writing b#00 to the FREQ bits of the VR_CTL register. This disables both CCLK and SCLK. Furthermore, it sets the internal power supply voltage (VDDINT) to 0 V to provide the lowest static power dissipation. Any critical information stored internally (memory contents, register contents, etc.) must be written to a nonvolatile storage device prior to removing power if the processor state is to be preserved. Since VDDEXT is still supplied in this mode, all of the external pins three-state, unless otherwise specified. This allows other devices that may be connected to the processor to have power still applied without drawing unwanted current. The internal supply regulator can be woken up by asserting the RESET pin. Disabled Enabled On Disabled Disabled On Disabled Disabled Off Full-On Operating Mode—Maximum Performance In the Full-On mode, the PLL is enabled and is not bypassed, providing capability for maximum operational frequency. This is the default execution state in which maximum performance can be achieved. The processor cores and all enabled peripherals run at full speed. Power Savings As shown in Table 4, the ADSP-BF561 supports two different power domains. The use of multiple power domains maximizes flexibility, while maintaining compliance with industry standards and conventions. By isolating the internal logic of the ADSP-BF561 into its own power domain, separate from the I/O, the processor can take advantage of Dynamic Power Management, without affecting the I/O devices. There are no sequencing requirements for the various power domains. Table 4. ADSP-BF561 Power Domains Power Domain All internal logic I/O VDD Range VDDINT VDDEXT Active Operating Mode—Moderate Power Savings In the Active mode, the PLL is enabled but bypassed. Because the PLL is bypassed, the processor’s core clock (CCLK) and system clock (SCLK) run at the input clock (CLKIN) frequency. In this mode, the CLKIN to CCLK multiplier ratio can be changed, although the changes are not realized until the Full-On mode is entered. DMA access is available to appropriately configured L1 and L2 memories. In the Active mode, it is possible to disable the PLL through the PLL Control Register (PLL_CTL). If disabled, the PLL must be re-enabled before transitioning to the Full-On or Sleep modes. Sleep Operating Mode—High Dynamic Power Savings The Sleep mode reduces power dissipation by disabling the clock to the processor core (CCLK). The PLL and system clock (SCLK), however, continue to operate in this mode. Typically an external event will wake up the processor. When in the Sleep mode, assertion of wakeup will cause the processor to sense the value of the BYPASS bit in the PLL Control register (PLL_CTL). When in the Sleep mode, system DMA access is only available to external memory, not to L1 or on-chip L2 memory. The power dissipated by a processor is largely a function of the clock frequency of the processor and the square of the operating voltage. For example, reducing the clock frequency by 25% results in a 25% reduction in dynamic power dissipation, while reducing the voltage by 25% reduces dynamic power dissipation by more than 40%. Further, these power savings are additive, in that if the clock frequency and supply voltage are both reduced, the power savings can be dramatic. The Dynamic Power Management feature of the ADSP-BF561 allows both the processor’s input voltage (VDDINT) and clock frequency (fCCLK) to be dynamically controlled. Rev. A | Page 12 of 60 | May 2006 ADSP-BF561 The savings in power dissipation can be modeled using the power savings factor and % power savings calculations. The power savings factor is calculated as: power savings factor f CCLKRED V DDINTRED 2 T RED = -------------------- × ⎛ ------------------------- ⎞ × ⎛ ------------ ⎞ ⎝ T NOM ⎠ f CCLKNOM ⎝ V DDINTNOM⎠ where the variables in the equations are: fCCLKNOM is the nominal core clock frequency fCCLKRED is the reduced core clock frequency VDDINTNOM is the nominal internal supply voltage VDDINTRED is the reduced internal supply voltage TNOM is the duration running at fCCLKNOM TRED is the duration running at fCCLKRED The percent power savings is calculated as: % power savings = ( 1 – power savings factor ) × 100% CLOCK SIGNALS The ADSP-BF561 can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. If an external clock is used, it should be a TTL-compatible signal and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is connected to the processor CLKIN pin. When an external clock is used, the XTAL pin must be left unconnected. Alternatively, because the ADSP-BF561 includes an on-chip oscillator circuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 5. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used. VOLTAGE REGULATION The ADSP-BF561 processor provides an on-chip voltage regulator that can generate processor core voltage levels 0.85 V to 1.25 V from an external 2.25 V to 3.6 V supply. Figure 4 shows the typical external components required to complete the power management system. The regulator controls the internal logic voltage levels and is programmable with the Voltage Regulator Control Register (VR_CTL) in increments of 50 mV. To reduce standby power consumption, the internal voltage regulator can be programmed to remove power to the processor core while keeping I/O power (VDDEXT) supplied. While in the hibernate state VDDEXT can still be applied, eliminating the need for external buffers. The voltage regulator can be activated from this powerdown state by asserting RESET, which will then initiate a boot sequence. The regulator can also be disabled and bypassed at the user’s discretion. CLKIN XTAL CLKOUT Figure 5. External Crystal Connections As shown in Figure 6, the core clock (CCLK) and system peripheral clock (SCLK) are derived from the input clock (CLKIN) signal. An on-chip PLL is capable of multiplying the CLKIN signal by a user-programmable 0.5× to 64× multiplication factor. The default multiplier is 10×, but it can be modified by a software instruction sequence. On the fly frequency changes can be effected by simply writing to the PLL_DIV register. “FI NE” ADJUSTMENT REQUI RES PLL SEQ UENCING “CO ARSE” ADJUSTMENT ON-THE-FLY VDDEXT 100µF 10µH 0.1µF 100µF 1µF ZHCS1000 2.25V TO 3.6V INPUT VOLTAGE RANGE VDDINT ÷ 1, 2, 4, 8 FDS9431A CCLK CLKIN PLL 0.5 × to 64 × VCO ÷ 1 to 15 SCLK VROUT1–0 EXTERNAL COMPONENTS NOTE: VROUT1–0 SHOULD BE TIED TOGETHER EXTERNALLY AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO FDS9431A. SCLK ≤ CCLK SCLK ≤ 133 MHz Figure 6. Frequency Modification Methods Figure 4. Voltage Regulator Circuit All on-chip peripherals are clocked by the system clock (SCLK). The system clock frequency is programmable by means of the SSEL3–0 bits of the PLL_DIV register. The values programmed Rev. A | Page 13 of 60 | May 2006 ADSP-BF561 into the SSEL fields define a divide ratio between the PLL output (VCO) and the system clock. SCLK divider values are 1 through 15. Table 5 illustrates typical system clock ratios. Table 5. Example System Clock Ratios Signal Name SSEL3–0 0001 0110 1010 Divider Ratio VCO/SCLK 1:1 6:1 10:1 Example Frequency Ratios (MHz) VCO SCLK 100 100 300 50 500 50 BOOTING MODES The ADSP-BF561 has three mechanisms (listed in Table 7) for automatically loading internal L1 instruction memory or L2 after a reset. A fourth mode is provided to execute from external memory, bypassing the boot sequence. Table 7. Booting Modes BMODE1–0 00 01 10 11 Description Execute from 16-bit external memory (Bypass Boot ROM) Boot from 8-bit/16-bit flash Reserved Boot from SPI serial EEPROM (16-bit address range) The maximum frequency of the system clock is fSCLK. Note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of fSCLK. The SSEL value can be changed dynamically without any PLL lock latencies by writing the appropriate values to the PLL divisor register (PLL_DIV). The core clock (CCLK) frequency can also be dynamically changed by means of the CSEL1–0 bits of the PLL_DIV register. Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in Table 6. This programmable core clock capability is useful for fast core frequency modifications. Table 6. Core Clock Ratios Signal Name CSEL1–0 00 01 10 11 Divider Ratio VCO/CCLK 1:1 2:1 4:1 8:1 Example Frequency Ratios (MHz) VCO CCLK 500 500 500 250 200 50 200 25 The BMODE pins of the Reset Configuration Register, sampled during power-on resets and software initiated resets, implement the following modes: • Execute from 16-bit external memory – Execution starts from address 0x2000 0000 with 16-bit packing. The boot ROM is bypassed in this mode. All configuration settings are set for the slowest device possible (3-cycle hold time, 15-cycle R/W access times, 4-cycle setup). • Boot from 8-bit/16-bit external flash memory – The 8-bit/16-bit flash boot routine located in boot ROM memory space is set up using Asynchronous Memory Bank 0. All configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle R/W access times; 4-cycle setup). • Boot from SPI serial EEPROM (16-bit addressable) – The SPI uses the PF2 output pin to select a single SPI EPROM device, submits a read command at address 0x0000, and begins clocking data into the beginning of L1 instruction memory. A 16-bit addressable SPI-compatible EPROM must be used. For each of the boot modes, a boot loading protocol is used to transfer program and data blocks from an external memory device to their specified memory locations. Multiple memory blocks may be loaded by any boot sequence. Once all blocks are loaded, Core A program execution commences from the start of L1 instruction SRAM (0xFFA0 0000). Core B remains in a heldoff state until Bit 5 of SICA_SYSCR is cleared. After that, Core B will start execution at address 0xFF60 0000. In addition, Bit 4 of the Reset Configuration Register can be set by application code to bypass the normal boot sequence during a software reset. For this case, the processor jumps directly to the beginning of L1 instruction memory. The maximum PLL clock time when a change is programmed via the PLL_CTL register is 40 µs. The maximum time to change the internal voltage via the internal voltage regulator is also 40 µs. The reset value for the PLL_LOCKCNT register is 0x200. This value should be programmed to ensure a 40 µs wakeup time when either the voltage is changed or a new MSEL value is programmed. The value should be programmed to ensure an 80 µs wakeup time when both voltage and the MSEL value are changed. The time base for the PLL_LOCKCNT register is the period of CLKIN. INSTRUCTION SET DESCRIPTION The Blackfin processor family assembly language instruction set employs an algebraic syntax that was designed for ease of coding and readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to a very small final memory size. The instruction set also pro- Rev. A | Page 14 of 60 | May 2006 ADSP-BF561 vides fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single instruction. Coupled with many features more often seen on microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture supports both a user (algorithm/application code) and a supervisor (O/S kernel, device drivers, debuggers, ISRs) mode of operation—allowing multiple levels of access to core processor resources. The assembly language, which takes advantage of the processor’s unique architecture, offers the following advantages: • Seamlessly integrated DSP/CPU features are optimized for both 8-bit and 16-bit operations. • A multi-issue load/store modified Harvard architecture, which supports two 16-bit MAC or four 8-bit ALU plus two load/store plus two pointer updates per cycle. • All registers, I/O, and memory are mapped into a unified 4G byte memory space providing a simplified programming model. • Microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data types; and separate user and kernel stack pointers. • Code density enhancements, which include intermixing of 16-bit and 32-bit instructions (no mode switching, no code segregation). Frequently used instructions are encoded as 16-bits. designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action. Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can: • View mixed C/C++ and assembly code (interleaved source and object information). • Insert breakpoints. • Set conditional breakpoints on registers, memory, and stacks. • Trace instruction execution. • Perform linear or statistical profiling of program execution. • Fill, dump, and graphically plot the contents of memory. • Perform source level debugging. • Create custom debugger windows. The VisualDSP++ IDE lets programmers define and manage software development. Its dialog boxes and property pages let programmers configure and manage all development tools, including Color Syntax Highlighting in the VisualDSP++ editor. These capabilities permit programmers to: • Control how the development tools process inputs and generate outputs. • Maintain a one-to-one correspondence with the tool’s command line switches. The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of embedded, real-time programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, pre-emptive, cooperative, and time-sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system. Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used with standard command line tools. When the VDK is used, the development environment assists the developer with many error prone tasks and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the system state when debugging an application that uses the VDK. DEVELOPMENT TOOLS The ADSP-BF561 is supported with a complete set of CROSSCORE®† software and hardware development tools, including Analog Devices emulators and the VisualDSP++®‡ development environment. The same emulator hardware that supports other Analog Devices processors also fully emulates the ADSP-BF561. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy to use assembler that is based on an algebraic syntax, an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to Blackfin assembly. The Blackfin processor has architectural features that improve the efficiency of compiled C/C++ code. The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the † ‡ CROSSCORE is a registered trademark of Analog Devices, Inc. VisualDSP++ is a registered trademark of Analog Devices, Inc. Rev. A | Page 15 of 60 | May 2006 ADSP-BF561 VCSE is Analog Devices’ technology for creating, using, and reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software applications. Components can be downloaded from the Web and dropped into the application. Component archives can be published from within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language. The Expert Linker can be used to visually manipulate the placement of code and data in the embedded system. Memory utilization can be viewed in a color-coded graphical form. Code and data can be easily moved to different areas of the processor or external memory with the drag of the mouse. Runtime stack and heap usage can be examined. The Expert Linker is fully compatible with existing Linker Definition File (LDF), allowing the developer to move between the graphical and textual environments. Analog Devices emulators use the IEEE 1149.1 JTAG test access port of the ADSP-BF561 to monitor and control the target board processor during emulation. The emulator provides fullspeed emulation, allowing inspection and modification of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect the loading or timing of the target system. In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the Blackfin processor family. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools. Reference on the Analog Devices website (www.analog.com)— use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support. RELATED DOCUMENTS The following publications that describe the ADSP-BF561 processors (and related processors) can be ordered from any Analog Devices sales office or accessed electronically on our website: • Getting Started With Blackfin Processors • ADSP-BF561 Blackfin Processor Hardware Reference • ADSP-BF53x/BF56x Blackfin Processor Programming Reference • ADSP-BF561 Blackfin Processor Anomaly List EZ-KIT Lite Evaluation Board For evaluation of ADSP-BF561 processors, use the ADSP-BF561 EZ-KIT Lite® board available from Analog Devices. Order part number ADDS-BF561-EZLITE. The board comes with on-chip emulation capabilities and is equipped to enable software development. Multiple daughter cards are available. DESIGNING AN EMULATOR-COMPATIBLE PROCESSOR BOARD (TARGET) The Analog Devices family of emulators are tools that every system developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on the ADSP-BF561. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the processor is set running at full speed with no impact on system timing. To use these emulators, the target board must include a header that connects the processor’s JTAG port to the emulator. For details on target board design issues, including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see EE-68: Analog Devices JTAG Emulation Technical Rev. A | Page 16 of 60 | May 2006 ADSP-BF561 PIN DESCRIPTIONS ADSP-BF561 pin definitions are listed in Table 8. Unused inputs should be tied or pulled to VDDEXT or GND. Output drive currents for each driver type are shown in Figure 26 through Figure 33. Table 8. Pin Descriptions Pin Name EBIU ADDR25–2 DATA31–0 ABE3–0/SDQM3–0 BR BG BGH EBIU (ASYNC) AMS3–0 ARDY AOE AWE ARE EBIU (SDRAM) SRAS SCAS SWE SCKE SCLK0/CLKOUT SCLK1 SA10 SMS3–0 PF/TIMER PF0/SPISS/TMR0 PF1/SPISEL1/TMR1 PF2/SPISEL2/TMR2 PF3/SPISEL3/TMR3 PF4/SPISEL4/TMR4 PF5/SPISEL5/TMR5 PF6/SPISEL6/TMR6 PF7/SPISEL7/TMR7 PF8 PF9 PF10 PF11 PF12 PF13 PF14 PF15/EXT CLK Type Function O I/O O I O O O I O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Address Bus for Async/Sync Access Data Bus for Async/Sync Access Byte Enables/Data Masks for Async/Sync Access Bus Request Bus Grant Bus Grant Hang Bank Select Hardware Ready Control Output Enable Write Enable Read Enable Row Address Strobe Column Address Strobe Write Enable Clock Enable Clock Output Pin 0 Clock Output Pin 1 SDRAM A10 Pin Bank Select Programmable Flag/Slave SPI Select/Timer Programmable Flag/SPI Select/Timer Programmable Flag/SPI Select/Timer Programmable Flag/SPI Select/Timer Programmable Flag/SPI Select/Timer Programmable Flag/SPI Select/Timer Programmable Flag/SPI Select/Timer Programmable Flag/SPI Select/Timer Programmable Flag Programmable Flag Programmable Flag Programmable Flag Programmable Flag Programmable Flag Programmable Flag Programmable Flag/External Timer Clock Input Driver Type1 Pull-Up/Down Requirement A A A A A A A A A A A A A B B A A C C C C C C C C C C C C C C C C None None None Pull-up Required If Function Not Used None None None Pull-up Required If Function Not Used None None None None None None None None None None None None None None None None None None None None None None None None None None None Rev. A | Page 17 of 60 | May 2006 ADSP-BF561 Table 8. Pin Descriptions (Continued) Pin Name PPI0 PPI0D15–8/PF47–40 PPI0D7–0 PPI0CLK PPI0SYNC1/TMR8 PPI0SYNC2/TMR9 PPI0SYNC3 PPI1 PPI1D15–8/PF39–32 PPI1D7–0 PPI1CLK PPI1SYNC1/TMR10 PPI1SYNC2/TMR11 PPI1SYNC3 SPORT0 RSCLK0/PF28 RFS0/PF19 DR0PRI DR0SEC/PF20 TSCLK0/PF29 TFS0/PF16 DT0PRI/PF18 DT0SEC/PF17 SPORT1 RSCLK1/PF30 RFS1/PF24 DR1PRI DR1SEC/PF25 TSCLK1/PF31 TFS1/PF21 DT1PRI/PF23 DT1SEC/PF22 SPI MOSI MISO SCK UART RX/PF27 TX/PF26 Type Function I/O I/O I I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PPI Data/Programmable Flag Pins PPI Data Pins PPI Clock PPI Sync/Timer PPI Sync/Timer PPI Sync PPI Data/Programmable Flag Pins PPI Data Pins PPI Clock PPI Sync/Timer PPI Sync/Timer PPI Sync Sport0/Programmable Flag Sport0 Receive Frame Sync/Programmable Flag Sport0 Receive Data Primary Sport0 Receive Data Secondary/Programmable Flag Sport0 Transmit Serial Clock/Programmable Flag Sport0 Transmit Frame Sync/Programmable Flag Sport0 Transmit Data Primary/Programmable Flag Sport0 Transmit Data Secondary/Programmable Flag Sport1/Programmable Flag Sport1 Receive Frame Sync/Programmable Flag Sport1 Receive Data Primary Sport1 Receive Data Secondary/Programmable Flag Sport1 Transmit Serial Clock/Programmable Flag Sport1 Transmit Frame Sync/Programmable Flag Sport1 Transmit Data Primary/Programmable Flag Sport1 Transmit Data Secondary/Programmable Flag Master Out Slave In Master In Slave Out SPI Clock UART Receive/Programmable Flag UART Transmit/Programmable Flag Driver Type1 Pull-Up/Down Requirement C C C C C C C C C C D C C D C C C D C C D C C C C C D C C None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Pull-up is Necessary if Booting via SPI None None None Rev. A | Page 18 of 60 | May 2006 ADSP-BF561 Table 8. Pin Descriptions (Continued) Pin Name JTAG EMU TCK TDO TDI TMS TRST Clock CLKIN XTAL Mode Controls RESET NMI0 NMI1 BMODE1–0 SLEEP BYPASS Voltage Regulator VROUT1–0 Supplies VDDEXT VDDINT GND No Connection 1 Type Function O I O I I I I O I I I I O I O P P G NC Emulation Output JTAG Clock JTAG Serial Data Out JTAG Serial Data In JTAG Mode Select JTAG Reset Clock input Crystal connection Chip reset signal Nonmaskable Interrupt Core A Nonmaskable Interrupt Core B Dedicated Mode Pin, Configures the Boot Mode that Follows a Hardware or Software Reset Sleep PLL BYPASS Control Regulation Output Power Supply Power Supply Power Supply Return NC Driver Type1 Pull-Up/Down Requirement C C None Internal Pull-down None Internal Pull-down Internal Pull-down External Pull-down Necessary If JTAG Not Used Needs to be at a Level or Clocking None Always Active if Core Power On Pull-down Required If Function Not Used Pull-down Required If Function Not Used Pull-up or Pull-down Required C None Pull-up or Pull-down Required N/A N/A N/A N/A N/A Refer to Figure 27 on Page 41 to Figure 31 on Page 42. Rev. A | Page 19 of 60 | May 2006 ADSP-BF561 SPECIFICATIONS Component specifications are subject to change without notice. RECOMMENDED OPERATING CONDITIONS Parameter VDDINT1 VDDINT1 VDDINT2 VDDINT3 VDDINT VDDEXT VDDEXT VIH VIL 1 Internal Supply Voltage ADSP-BF561SKBCZ500 Internal Supply Voltage ADSP-BF561SKBCZ600 Internal Supply Voltage ADSP-BF561SBB600 Internal Supply Voltage ADSP-BF561SBB500 Internal Supply Voltage ADSP-BF561WBBZ-5A External Supply Voltage External Supply Voltage ADSP-BF561WBBZ-5A High Level Input Voltage4, 5 Low Level Input Voltage5 Min 0.8 0.8 0.8 0.8 0.95 2.25 2.7 2.0 –0.3 Nominal 1.25 1.25 1.35 1.25 1.25 2.5 or 3.3 3.3 Max 1.375 1.375 1.4185 1.375 1.312 3.6 3.6 3.6 +0.6 Unit V V V V V V V V V Internal voltage regulator tolerance: ADSP-BF561SKBCZ500, ADSP-BF561SKBCZ600: VDDINT = –5% to +10% 2 Internal voltage regulator tolerance: ADSP-BF561SBB600: VDDINT = –7% to +12% 3 Internal voltage regulator tolerance: ADSP-BF561SBB500: VDDINT = –7% to +12% except at 1.25 V: VDDINT = –5% to +10% 4 The ADSP-BF561 is 3.3 V tolerant (always accepts up to 3.6 V maximum VIH), but voltage compliance (on outputs, VOH) depends on the input VDDEXT, because VOH (maximum) approximately equals VDDEXT (maximum). This 3.3 V tolerance applies to bidirectional and input only pins. 5 Applies to all signal pins. ELECTRICAL CHARACTERISTICS Parameter VOH VOL IIH IIHP IIL4 IOZH IOZL4 CIN 1 2 High Level Output Voltage1 Low Level Output Voltage1 High Level Input Current2 High Level Input Current JTAG3 Low Level Input Current2 Three-State Leakage Current5 Three-State Leakage Current5 Input Capacitance6 Test Conditions @ VDDEXT = 3.0 V, IOH = –0.5 mA @ VDDEXT = 3.0 V, IOL = 2.0 mA @ VDDEXT = Maximum, VIN = VDD Maximum @ VDDEXT = Maximum, VIN = VDD Maximum @ VDDEXT = Maximum, VIN = 0 V @ VDDEXT = Maximum, VIN = VDD Maximum @ VDDEXT = Maximum, VIN = 0 V fIN = 1 MHz, TAMBIENT = 25°C, VIN = 2.5 V Min 2.4 Typical Max 0.4 10.0 50.0 10.0 10.0 10.0 87 4 Unit V V µA µA µA µA µA pF Applies to output and bidirectional pins. Applies to input pins except JTAG inputs. 3 Applies to JTAG input pins (TCK, TDI, TMS, TRST). 4 Absolute value. 5 Applies to three-statable pins. 6 Applies to all signal pins. 7 Guaranteed, but not tested. Rev. A | Page 20 of 60 | May 2006 ADSP-BF561 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in the table may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameter Internal (Core) Supply Voltage (VDDINT) External (I/O) Supply Voltage (VDDEXT) Input Voltage1 Output Voltage Swing Load Capacitance Storage Temperature Range Junction Temperature Under Bias 1 PACKAGE INFORMATION The information presented in Figure 7 and Table 10 provides information about how to read the package brand and relate it to specific product features. For a complete listing of product offerings, see the Ordering Guide on Page 58. Value –0.3 V to +1.42 V –0.5 V to +3.8 V – 0.5 V to +3.8 V –0.5 V to VDDEXT + 0.5 V 200 pF –65 C to +150 C 125 C Brand Key t pp Z ccc vvvvvv.x n.n yyww a ADSP-BF561 StppZccc vvvvvv.x n.n yyww country_of_origin B Figure 7. Product Information on Package Applies to 100% transient duty cycle. For other duty cycles see Table 9. Table 10. Package Brand Information Field Description Temperature Range Package Type Lead Free Option (Optional) See Ordering Guide Assembly Lot Code Silicon Revision Date Code Table 9. Maximum Duty Cycle for Input Transient Voltage1 VIN Min (V) –0.50 –0.70 –0.80 –0.90 –1.00 1 VIN Max (V) 3.80 4.00 4.10 4.20 4.30 Maximum Duty Cycle 100% 40% 25% 15% 10% Applies to all signal pins with the exception of CLKIN, XTAL, VROUT1–0. ESD SENSITIVITY CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-BF561 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. p Rev. A | Page 21 of 60 | May 2006 ADSP-BF561 TIMING SPECIFICATIONS Table 11 through Table 13 describe the timing requirements for the ADSP-BF561 clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock, system clock, and Voltage Controlled Oscillator (VCO) operating frequencies, as described in Absolute Maximum Ratings on Page 21. Table 14 describes phase-locked loop operating conditions. Table 11. Core Clock Requirements—ADSP-BF561SKBCZ500, ADSP-BF561SKB500, ADSP-BF561SKBZ500, ADSP-BF561SBB500, ADSP-BF561SBBZ500, and ADSP-BF561WBBZ-5A Parameter tCCLK Core Cycle Period (VDDINT =1.1875 Vminimum) Core Cycle Period (VDDINT =1.045 Vminimum) tCCLK tCCLK Core Cycle Period (VDDINT =0.95 Vminimum) tCCLK Core Cycle Period (VDDINT =0.855 Vminimum)1 tCCLK Core Cycle Period (VDDINT =0.8 V minimum)1 1 Min 2.00 2.25 2.86 3.33 4.00 Max Unit ns ns ns ns ns Not applicable to ADSP-BF561WBBZ-5A. Table 12. Core Clock Requirements—ADSP-BF561SKBCZ600 Parameter tCCLK Core Cycle Period (VDDINT =1.1875 Vminimum) tCCLK Core Cycle Period (VDDINT =1.045 Vminimum) tCCLK Core Cycle Period (VDDINT =0.95 Vminimum) tCCLK Core Cycle Period (VDDINT =0.855 Vminimum) tCCLK Core Cycle Period (VDDINT =0.8 V minimum) Min 1.66 2.10 2.35 2.66 4.00 Max Unit ns ns ns ns ns Table 13. Core Clock Requirements—ADSP-BF561SBB600, ADSP-BF561SBBZ600, ADSP-BF561SKB600 and ADSP-BF561SKBZ600 Parameter tCCLK Core Cycle Period (VDDINT =1.2825 Vminimum)1 tCCLK Core Cycle Period (VDDINT =1.1875 Vminimum) tCCLK Core Cycle Period (VDDINT =1.045 Vminimum) tCCLK Core Cycle Period (VDDINT =0.95 Vminimum) Core Cycle Period (VDDINT =0.855 V minimum) tCCLK tCCLK Core Cycle Period (VDDINT =0.8 Vminimum) 1 Min 1.66 2.00 2.25 2.86 3.33 4.00 Max Unit ns ns ns ns ns ns External voltage regulator required to ensure proper operation at 600 MHz 1.35 V nominal. Table 14. Phase-Locked Loop Operating Conditions Parameter Voltage Controlled Oscillator (VCO) Frequency Min 50 Max Maximum fCCLK Unit MHz Table 15. Maximum SCLK Conditions Parameter1 fSCLK fSCLK 1 CLKOUT/SCLK Frequency (VDDINT ≥ 1.14 V) CLKOUT/SCLK Frequency (VDDINT < 1.14 V) VDDEXT = 3.3 V 133 100 VDDEXT = 2.5 V 133 100 Unit MHz MHz tSCLK (= 1/fSCLK) must be greater than or equal to tCCLK. Rev. A | Page 22 of 60 | May 2006 ADSP-BF561 Clock and Reset Timing Table 16 and Figure 8 describe clock and reset operations. Per Absolute Maximum Ratings on Page 21, combinations of CLKIN and clock multipliers must not select core/peripheral clocks in excess of 600 MHz/133 MHz. Table 16. Clock and Reset Timing Parameter Timing Requirements CLKIN Period tCKIN tCKINL CLKIN Low Pulse2 tCKINH CLKIN High Pulse2 tWRST RESET Asserted Pulse Width Low3 1 2 Min 25.0 10.0 10.0 11 × tCKIN Max 100.01 Unit ns ns ns ns If DF bit in PLL_CTL register is set, then the maximum tCKIN period is 50 ns. Applies to bypass mode and nonbypass mode. 3 Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2,000 CLKIN cycles, while RESET is asserted, assuming stable power supplies and CLKIN (not including startup time of external clock oscillator). tCKIN CLKIN tCKINL RESET tCKINH tWRST Figure 8. Clock and Reset Timing Rev. A | Page 23 of 60 | May 2006 ADSP-BF561 Asynchronous Memory Read Cycle Timing Table 17. Asynchronous Memory Read Cycle Timing Parameter Timing Requirements tSDAT DATA31–0 Setup Before CLKOUT tHDAT DATA31–0 Hold After CLKOUT tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristics tDO Output Delay After CLKOUT1 tHO Output Hold After CLKOUT 1 1 Min 2.1 0.8 4.0 0.0 Max Unit ns ns ns ns 6.0 0.8 ns ns Output pins include AMS3–0, ABE3–0, ADDR25–2, AOE, ARE. SETUP 2 CYCLES PROGRAMMED READ ACCESS 4 CYCLES ACCESS EXTENDED 3 CYCLES HOLD 1 CYCLE CLKOUT t DO AMSx t HO ABE3–0 ADDR25–2 BE, ADDRESS AOE t DO ARE t HO t SARDY ARDY tHARDY t HARDY tSARDY tSDAT t HDAT DATA31–0 READ Figure 9. Asynchronous Memory Read Cycle Timing Rev. A | Page 24 of 60 | May 2006 ADSP-BF561 Asynchronous Memory Write Cycle Timing Table 18. Asynchronous Memory Write Cycle Timing Parameter Timing Requirements tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristics tDDAT DATA31–0 Disable After CLKOUT DATA31–0 Enable After CLKOUT tENDAT tDO Output Delay After CLKOUT1 tHO Output Hold After CLKOUT 1 1 Min 4.0 0.0 Max Unit ns ns 6.0 1.0 6.0 0.8 ns ns ns ns Output pins include AMS3–0, ABE3–0, ADDR25–2, DATA31–0, AOE, AWE. SETUP 2 CYCLES PROGRAMMED WRITE ACCESS 2 CYCLES ACCESS EXTENDED 1 CYCLE HOLD 1 CYCLE CLKOUT t DO AMSx t HO ABE3–0 ADDR25–2 BE, ADDRESS tDO AWE tHO t SARDY ARDY t HARDY t END AT DATA31–0 WRITE DATA tSARDY t DD AT Figure 10. Asynchronous Memory Write Cycle Timing Rev. A | Page 25 of 60 | May 2006 ADSP-BF561 SDRAM Interface Timing Table 19. SDRAM Interface Timing Parameter Timing Requirements tSSDAT DATA Setup Before CLKOUT tHSDAT DATA Hold After CLKOUT Switching Characteristics tSCLK CLKOUT Period1 CLKOUT Width High tSCLKH tSCLKL CLKOUT Width Low tDCAD Command, ADDR, Data Delay After CLKOUT2 tHCAD Command, ADDR, Data Hold After CLKOUT2 tDSDAT Data Disable After CLKOUT tENSDAT Data Enable After CLKOUT 1 2 Min 2.1 0 7.5 2.5 2.5 Max Unit ns ns ns ns ns ns ns ns ns 4.0 0.8 4.0 1.0 Refer to Table 15 on Page 22 for maximum fSCLK at various VDDINT. Command pins include: SRAS, SCAS, SWE, SDQM, SMS3–0, SA10, SCKE. tSCLK CLKOUT tSCLKH t SSDAT tHSDAT DATA (IN) t SCLKL t DCAD tENSDAT DATA(OUT) tD SDA T tHCAD tDCAD CMND ADDR (OUT) tHCAD NOTE: COMMAND = SRAS, SCAS , SWE , SDQM, SMS, SA10, SCKE. Figure 11. SDRAM Interface Timing Rev. A | Page 26 of 60 | May 2006 ADSP-BF561 External Port Bus Request and Grant Cycle Timing Table 20 and Figure 12 describe external port bus request and bus grant operations. Table 20. External Port Bus Request and Grant Cycle Timing Parameter1, 2 Timing Requirements tBS BR Asserted to CLKOUT High Setup tBH CLKOUT High to BR Deasserted Hold Time Switching Characteristics tSD CLKOUT Low to SMS, Address and RD/WR Disable tSE CLKOUT Low to SMS, Address and RD/WR Enable tDBG CLKOUT High to BG Asserted Setup tEBG CLKOUT High to BG Deasserted Hold Time tDBH CLKOUT High to BGH Asserted Setup CLKOUT High to BGH Deasserted Hold Time tEBH 1 2 Min 4.6 0.0 Max Unit ns ns 4.5 4.5 3.6 3.6 3.6 3.6 ns ns ns ns ns ns These are preliminary timing parameters that are based on worst-case operating conditions. The pad loads for these timing parameters are 20 pF. CLKOUT tBS BR tBH tSD tSE AMSx tSD tSE ADDR25-2 ABE3-0 tSD tSE AWE ARE tDBG BG tEBG tDBH BGH tEBH Figure 12. External Port Bus Request and Grant Cycle Timing Rev. A | Page 27 of 60 | May 2006 ADSP-BF561 Parallel Peripheral Interface Timing Table 21, and Figure 13 through Figure 16 , describe Parallel Peripheral Interface operations. Table 21. Parallel Peripheral Interface Timing Parameter Timing Requirements tPCLKW PPI_CLK Width1 tPCLK PPI_CLK Period1 External Frame Sync Setup Before PPI_CLK tSFSPE tHFSPE External Frame Sync Hold After PPI_CLK tSDRPE Receive Data Setup Before PPI_CLK tHDRPE Receive Data Hold After PPI_CLK Switching Characteristics tDFSPE Internal Frame Sync Delay After PPI_CLK Internal Frame Sync Hold After PPI_CLK tHOFSPE tDDTPE Transmit Data Delay After PPI_CLK tHDTPE Transmit Data Hold After PPI_CLK 1 Min 5.0 13.3 4.0 1.0 3.5 2.0 Max Unit ns ns ns ns ns ns 8.0 1.7 8.0 2.0 ns ns ns ns For PPI modes that use an internally generated frame sync, the PPI_CLK frequency cannot exceed fSCLK/2. For modes with no frame syncs or external frame syncs, PPI_CLK cannot exceed 75MHz and fSCLK should be equal to or greater than PPI_CLK. FRAME SYNC IS DRIVEN OUT POLC = 0 PPI_CLK DATA0 IS SAMPLED PPI_CLK POLC = 1 t tHOFSPE POLS = 1 PPI_FS1 POLS = 0 DFSPE POLS = 1 PPI_FS2 POLS = 0 tSDRPE tHDRPE PPI_DATA Figure 13. PPI GP Rx Mode with Internal Frame Sync Timing Rev. A | Page 28 of 60 | May 2006 ADSP-BF561 FRAME SYNC IS SAMPLED FOR DATA0 DATA0 IS SAMPLED PPI_CLK POLC = 0 PPI_CLK POLC = 1 DATA1 IS SAMPLED t tSFSPE POLS = 1 PPI_FS1 POLS = 0 HFSPE POLS = 1 PPI_FS2 POLS = 0 t SDRPE t HDRPE PPI_DATA Figure 14. PPI GP Rx Mode with External Frame Sync Timing FRAME SYNC IS SAMPLED PPI_CLK POLC = 0 PPI_CLK POLC = 1 t t POLS = 1 PPI_FS1 POLS = 0 SFSPE HFSPE DATA0 IS DRIVEN OUT POLS = 1 PPI_FS2 POLS = 0 tHDTPE PPI_DATA DATA0 tDDTPE Figure 15. PPI GP Tx Mode with External Frame Sync Timing Rev. A | Page 29 of 60 | May 2006 ADSP-BF561 FRAME SYNC IS DRIVEN OUT DATA0 IS DRIVEN OUT PPI_CLK POLC = 0 PPI_CLK POLC = 1 t tHOFSPE POLS = 1 PPI_FS1 POLS = 0 DFSPE POLS = 1 PPI_FS2 POLS = 0 tDDTPE t HDTPE PPI_DATA DATA0 Figure 16. PPI GP Tx Mode with Internal Frame Sync Timing Rev. A | Page 30 of 60 | May 2006 ADSP-BF561 Serial Ports Table 22 on Page 31 through Table 25 on Page 33 and Figure 17 on Page 32 through Figure 19 on Page 34 describe Serial Port operations. Table 22. Serial Ports—External Clock Parameter Timing Requirements tSFSE TFS/RFS Setup Before TSCLK/RSCLK1 tHFSE TFS/RFS Hold After TSCLK/RSCLK1 tSDRE Receive Data Setup Before RSCLK1 tHDRE Receive Data Hold After RSCLK1 tSCLKW TSCLK/RSCLK Width tSCLK TSCLK/RSCLK Period Switching Characteristics tDFSE TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)2 tHOFSE TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)1 tDDTE Transmit Data Delay After TSCLK1 tHDTE Transmit Data Hold After TSCLK1 1 2 Min 3.0 3.0 3.0 3.0 4.5 15.0 Max Unit ns ns ns ns ns ns 10.0 0.0 10.0 0.0 ns ns ns ns Referenced to sample edge. Referenced to drive edge. Table 23. Serial Ports—Internal Clock Parameter Timing Requirements tSFSI TFS/RFS Setup Before TSCLK/RSCLK1 tHFSI TFS/RFS Hold After TSCLK/RSCLK1 tSDRI Receive Data Setup Before RSCLK1 tHDRI Receive Data Hold After RSCLK1 tSCLKW TSCLK/RSCLK Width tSCLK TSCLK/RSCLK Period Switching Characteristics tDFSI TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)2 tHOFSI TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)1 tDDTI Transmit Data Delay After TSCLK1 Transmit Data Hold After TSCLK1 tHDTI tSCLKIW TSCLK/RSCLK Width 1 2 Min 8.0 –2.0 6.0 0.0 4.5 15.0 Max Unit ns ns ns ns ns ns 3.0 –1.0 3.0 –2.0 4.5 ns ns ns ns ns Referenced to sample edge. Referenced to drive edge. Table 24. Serial Ports—Enable and Three-State Parameter Switching Characteristics tDTENE Data Enable Delay from External TSCLK1 tDDTTE Data Disable Delay from External TSCLK1 tDTENI Data Enable Delay from Internal TSCLK Data Disable Delay from Internal TSCLK1 tDDTTI 1 Min 0 Max Unit ns ns ns ns 10.0 –2.0 3.0 Referenced to drive edge. Rev. A | Page 31 of 60 | May 2006 ADSP-BF561 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DATA RECEIVE—EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE tSCLKIW RSCLK RSCLK tSCLKEW tDFSE tHOFSE RFS tDFSE tSFSI tHFSI RFS tHOFSE tSFSE tHFSE tSDRI DR tHDRI DR tSDRE tHDRE NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DATA TRANSMIT—EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE tSCLKIW TSCLK TSCLK tSCLKEW tDFSI tHOFSI TFS tDFSE tSFSI tHFSI TFS tHOFSE tSFSE tHFSE tDDTI tHDTI DT DT tDDTE tHDTE NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE. DRIVE EDGE TSCLK (EXT) TFS ("LATE", EXT.) TSCLK / RSCLK DRIVE EDGE tDTENE DT DRIVE EDGE TSCLK (INT) TFS ("LATE", INT.) TSCLK / RSCLK DRIVE EDGE tDDTTE tDTENI DT tDDTTI Figure 17. Serial Ports Rev. A | Page 32 of 60 | May 2006 ADSP-BF561 Table 25. External Late Frame Sync Parameter Switching Characteristics tDDTLFSE Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 01, 2 tDTENLFS Data Enable from Late FS or MCE = 1, MFD = 01, 2 1 2 Min Max 10.0 Unit ns ns 0 MCE = 1, TFS enable and TFS valid follow tDTENLFS and tDDTLFSE. If external RFS/TFS setup to RSCLK/TSCLK > tSCLKE/2, then tDDTE/I and tDTENE/I apply; otherwise tDDTLFSE and tDTENLFS apply. EXTERNAL RFS WITH MCE = 1, MFD = 0 DRIVE RSCLK SAMPLE DRIVE tSFSE/I tHOFSE/I RFS tDTENLFS tDDTE/I tHDTE/I 1ST BIT 2ND BIT DT tDDTLFSE LATE EXTERNAL TFS DRIVE TSCLK SAMPLE DRIVE tSFSE/I tHOFSE/I TFS tDTENLFS DT tDDTE/I tHDTE/I 1ST BIT 2ND BIT tDDTLFSE Figure 18. External Late Frame Sync (Frame Sync Setup < tSCLK/2) Rev. A | Page 33 of 60 | May 2006 ADSP-BF561 EXTERNAL RFS WITH MCE = 1, MFD = 0 DRIVE SAMPLE DRIVE RSCLK tSFSE/I tHOFSE/I RFS tDDTE/I tDTENLSCK tHDTE/I DT 1ST BIT 2ND BIT tDDTLSCK LATE EXTERNAL TFS DRIVE SAMPLE DRIVE TSCLK tSFSE/I tHOFSE/I TFS tDDTE/I tDTENLSCK tHDTE/I 2ND BIT DT 1ST BIT tDDTLSCK Figure 19. External Late Frame Sync (Frame Sync Setup > tSCLK/2) Rev. A | Page 34 of 60 | May 2006 ADSP-BF561 Serial Peripheral Interface (SPI) Port— Master Timing Table 26 and Figure 20 describe SPI port master operations. Table 26. Serial Peripheral Interface (SPI) Port—Master Timing Parameter Timing Requirements Data Input Valid to SCK Edge (Data Input Setup) tSSPIDM tHSPIDM SCK Sampling Edge to Data Input Invalid Switching Characteristics tSDSCIM SPISELx Low to First SCK Edge tSPICHM Serial Clock High Period tSPICLM Serial Clock Low Period Serial Clock Period tSPICLK tHDSM Last SCK Edge to SPISELx High tSPITDM Sequential Transfer Delay tDDSPIDM SCK Edge to Data Out Valid (Data Out Delay) tHDSPIDM SCK Edge to Data Out Invalid (Data Out Hold) Min 7.5 –1.5 2tSCLK–1.5 2tSCLK–0.5 2tSCLK–1.5 4tSCLK–1.5 2tSCLK–1.5 2tSCLK–1.5 0 –1.0 Max Unit ns ns ns ns ns ns ns ns ns ns 6 +4.0 SPISELx (OUTPUT) tSDSCIM SCK (CPOL = 0) (OUTPUT) tSPICHM tSPICLM tSPICLK tHDSM tSPITDM tSPICLM SCK (CPOL = 1) (OUTPUT) tSPICHM tDDSPIDM MOSI (OUTPUT) CPHA=1 MISO (INPUT) MSB tHDSPIDM LSB tSSPIDM MSB VALID tHSPIDM tSSPIDM LSB VALID tHSPIDM tDDSPIDM MOSI (OUTPUT) CPHA=0 MISO (INPUT) MSB tHDSPIDM LSB tSSPIDM MSB VALID tHSPIDM LSB VALID Figure 20. Serial Peripheral Interface (SPI) Port—Master Timing Rev. A | Page 35 of 60 | May 2006 ADSP-BF561 Serial Peripheral Interface (SPI) Port— Slave Timing Table 27 and Figure 21 describe SPI port slave operations. Table 27. Serial Peripheral Interface (SPI) Port—Slave Timing Parameter Timing Requirements Serial Clock High Period tSPICHS tSPICLS Serial Clock Low Period tSPICLK Serial Clock Period tHDS Last SCK Edge to SPISS Not Asserted tSPITDS Sequential Transfer Delay tSDSCI SPISS Assertion to First SCK Edge Data Input Valid to SCK Edge (Data Input Setup) tSSPID tHSPID SCK Sampling Edge to Data Input Invalid Switching Characteristics tDSOE SPISS Assertion to Data Out Active tDSDHI SPISS Deassertion to Data High Impedance tDDSPID SCK Edge to Data Out Valid (Data Out Delay) SCK Edge to Data Out Invalid (Data Out Hold) tHDSPID Min 2tSCLK–1.5 2tSCLK–1.5 4tSCLK–1.5 2tSCLK–1.5 2tSCLK–1.5 2tSCLK–1.5 1.6 1.6 0 0 0 0 8 8 10 10 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns SPISS (INPUT) tSPICHS SCK (CPOL = 0) (INPUT) tSPICLS tSPICLK tHDS tSPITDS tSDSCI SCK (CPOL = 1) (INPUT) tSPICLS tSPICHS tDSOE tDDSPID tHDSPID tDDSPID tDSDHI LSB MISO (OUTPUT) CPHA=1 MOSI (INPUT) MSB tSSPID MSB VALID tHSPID tSSPID tHSPID LSB VALID tDSOE MISO (OUTPUT) CPHA=0 MOSI (INPUT) tDDSPID MSB LSB tDSDHI tHSPID tSSPID MSB VALID LSB VALID Figure 21. Serial Peripheral Interface (SPI) Port—Slave Timing Rev. A | Page 36 of 60 | May 2006 ADSP-BF561 Universal Asynchronous Receiver Transmitter (UART) Port—Receive and Transmit Timing Figure 22 describes UART port receive and transmit operations. The maximum baud rate is SCLK/16. As shown in Figure 22, there is some latency between the generation internal UART interrupts and the external data operations. These latencies are negligible at the data transmission rates for the UART. CLKOUT (SAMPLE CLOCK) RXD DATA8–5 STOP RECEIVE INTERNAL UART RECEIVE INTERRUPT UART RECEIVE BIT SET BY DATA STOP; CLEARED BY FIFO READ START TXD AS DATA WRITEN TO BUFFER INTERNAL UART TRANSMIT INTERRUPT UART TRANSMIT BIT SET BY PROGRAM; CLEARED BY WRITE TO TRANSMIT DATA8–5 STOP2–1 TRANSMIT Figure 22. UART Port—Receive and Transmit Timing Rev. A | Page 37 of 60 | May 2006 ADSP-BF561 Programmable Flags Cycle Timing Table 28 and Figure 23 describe programmable flag operations. Table 28. Programmable Flags Cycle Timing Parameter Timing Requirement tWFI Flag Input Pulse Width Switching Characteristic tDFO Flag Output Delay from CLKOUT Low Min tSCLK + 1 6 Max Unit ns ns CLKOUT tDFO PF (OUTPUT) FLAG OUTPUT tWFI PF (INPUT) FLAG INPUT Figure 23. Programmable Flags Cycle Timing Rev. A | Page 38 of 60 | May 2006 ADSP-BF561 Timer Cycle Timing Table 29 and Figure 24 describe timer expired operations. The input signal is asynchronous in width capture mode and external clock mode and has an absolute maximum input frequency of fSCLK/2 MHz. Table 29. Timer Cycle Timing Parameter Timing Characteristics Timer Pulse Width Input Low1 (Measured in SCLK Cycles) tWL tWH Timer Pulse Width Input High1 (Measured in SCLK Cycles) Switching Characteristic tHTO Timer Pulse Width Output2 (Measured in SCLK Cycles) 1 2 Min 1 1 1 Max Unit SCLK SCLK (232–1) SCLK The minimum pulse-widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPICLK input pins in PWM output mode. The minimum time for tHTO is one cycle, and the maximum time for tHTO equals (232–1) cycles. CLKOUT tHTO TMRx (PWM OUTPUT MODE) TMRx (WIDTH CAPTURE AND EXTERNAL CLOCK MODES) tWL tWH Figure 24. Timer PWM_OUT Cycle Timing Rev. A | Page 39 of 60 | May 2006 ADSP-BF561 JTAG Test and Emulation Port Timing Table 30 and Figure 25 describe JTAG port operations. Table 30. JTAG Port Timing Parameter Timing Parameters tTCK TCK Period tSTAP TDI, TMS Setup Before TCK High tHTAP TDI, TMS Hold After TCK High tSSYS System Inputs Setup Before TCK High1 tHSYS System Inputs Hold After TCK High1 tTRSTW TRST Pulse-Width2 (Measured in TCK Cycles) Switching Characteristics tDTDO TDO Delay from TCK Low tDSYS System Outputs Delay After TCK Low3 1 Min 20 4 4 4 5 4 Max Unit ns ns ns ns ns TCK 0 10 12 ns ns System Inputs= DATA31–0, ARDY, TMR2–0, PF47–0, PPIx_CLK, RSCLK0–1, RFS0–1, DR0PRI, DR0SEC, TSCLK0–1, TFS0–1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RX, RESET, NMI0 and NMI1, BMODE1–0, BR, PPIxD7–0. 2 50 MHz maximum 3 System Outputs = DATA31–0, ADDR25–2, ABE3–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS3–0, PF47–0, RSCLK0–1, RFS0–1, TSCLK0–1, TFS0–1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, PPIxD7–0. tTCK TCK tSTAP TMS TDI tHTAP tDTDO TDO tSSYS SYSTEM INPUTS tHSYS tDSYS SYSTEM OUTPUTS Figure 25. JTAG Port Timing Rev. A | Page 40 of 60 | May 2006 ADSP-BF561 OUTPUT DRIVE CURRENTS Figure 26 through Figure 33 show typical current voltage characteristics for the output drivers of the ADSP-BF561 processor. The curves represent the current drive capability of the output drivers as a function of output voltage. Refer to Table 8 on Page 17 to identify the driver type for a pin. 150 VDDEXT = 2.75V @ –40°C VDDEXT = 2.50V @ 25°C VDDEXT = 2.25V @ 95°C 150 VDDEXT = 2.75V @ –40°C VDDEXT = 2.50V @ 25°C VDDEXT = 2.25V @ 95°C 100 SOURCE CURRENT (mA) 50 0 VOH –50 100 SOURCE CURRENT (mA) –100 50 –150 0 VOH VOL 0 0.5 1.0 1.5 2.0 2.5 3.0 SOURCE VOLTAGE (V) –50 VOL –100 150 –150 0 Figure 28. Drive Current B (Low VDDEXT) 0.5 1.0 1.5 2.0 2.5 3.0 SOURCE CURRENT (mA) 100 VDDEXT = 3.65V @ –40°C VDDEXT = 3.30V @ 25°C VDDEXT = 2.95V @ 95°C SOURCE VOLTAGE (V) Figure 26. Drive Current A (Low VDDEXT) 150 VDDEXT = 3.65V @ –40°C VDDEXT = 3.30V @ 25°C VDDEXT = 2.95V @ 95°C 50 0 VOH –50 100 SOURCE CURRENT (mA) –100 50 –150 0 VOH –50 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) 2.5 3.0 3. VOL Figure 29. Drive Current B (High VDDEXT) –100 VOL 60 VDDEXT = 2.75V @ –40°C VDDEXT = 2.50V @ 25°C VDDEXT = 2.25V @ 95°C –150 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 40 SOURCE VOLTAGE (V) 20 SOURCE CURRENT (mA) Figure 27. Drive Current A (High VDDEXT) 0 VOH –20 –40 VOL –60 0 0.5 1.0 1.5 2.0 2.5 3.0 SOURCE VOLTAGE (V) Figure 30. Drive Current C (Low VDDEXT) Rev. A | Page 41 of 60 | May 2006 ADSP-BF561 100 80 60 SOURCE CURRENT (mA) 40 20 0 VOH –20 –40 –60 –80 –100 0 VOL VDDEXT = 3.65V @ –40°C VDDEXT = 3.30V @ 25°C V = 2.95V @ 95°C DDEXT POWER DISSIPATION Total power dissipation has two components: one due to internal circuitry (PINT) and one due to the switching of external output drivers (PEXT). Table 31 through Table 33 show the power dissipation for internal circuitry (VDDINT). See the ADSP-BF561 Blackfin Processor Hardware Reference Manual for definitions of the various operating modes and for instructions on how to minimize system power. Many operating conditions can affect power dissipation. System designers should refer to EE-293: Estimating Power for ADSPBF561 Blackfin Processors on the Analog Devices website (www.analog.com)—use site search on “EE-293.” This document provides detailed information for optimizing your design for lowest power. Table 31. Internal Power Dissipation (Hibernate mode) IDDHIBERNATE VDDEXT = 2.75V @ –40°C VDDEXT = 2.50V @ 25°C VDDEXT = 2.25V @ 95°C 1 2 0.5 1.0 1.5 2.0 2.5 3.0 3.5 SOURCE VOLTAGE (V) Figure 31. Drive Current C (High VDDEXT) 2 100 80 60 SOURCE CURRENT (mA) 40 20 0 –20 –40 –60 –80 –100 0 0.5 1.0 1.5 2.0 2.5 3.0 VOL VOH IDD (nominal1) 50 Unit µA Nominal assumes an operating temperature of 25°C. Measured at VDDEXT = 3.65 V with voltage regulator off (VDDINT = 0 V). Table 32. Internal Power Dissipation (Deep Sleep mode) VDDINT1 0.8 0.9 1.0 1.1 1.25 1.35 1 2 IDD (nominal2) 32 40 50 62 84 95 Unit mA mA mA mA mA mA SOURCE VOLTAGE (V) Assumes VDDINT is regulated externally. Nominal assumes an operating temperature of 25°C. Figure 32. Drive Current D (Low VDDEXT) 150 Table 33. Internal Power Dissipation (Full On1 mode) VDDINT2 @ fCCLK 0.8 @ 50 MHz 0.8 @ 250 MHz 0.9 @ 300 MHz 1.0 @ 350 MHz 1.1 @ 444 MHz 1.25 @ 500 MHz 1.35 @ 600 MHz 1 2 100 SOURCE CURRENT (mA) VDDEXT = 3.65V @ –40°C VDDEXT = 3.30V @ 25°C V = 2.95V @ 95°C DDEXT 50 0 VOH –50 VOL –100 IDD (nominal3) 66 144 194 249 346 469 588 Unit mA mA mA mA mA mA mA Processor executing 75% dual MAC, 25% ADD with moderate data bus activity. Assumes VDDINT is regulated externally. 3 Nominal assumes an operating temperature of 25°C. –150 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) 2.5 3.0 3.5 Figure 33. Drive Current D (High VDDEXT) Rev. A | Page 42 of 60 | May 2006 ADSP-BF561 TEST CONDITIONS All timing parameters appearing in this data sheet were measured under the conditions described in this section. Figure 34 shows the measurement point for ac measurements (except output enable/disable). The measurement point VMEAS is 1.5 V for VDDEXT (nominal) = 2.5 V/3.3 V. INPUT OR OUTPUT Example System Hold Time Calculation To determine the data output hold time in a particular system, first calculate tDECAY using the equation given above. Choose ∆V to be the difference between the ADSP-BF561 processor’s output voltage and the input threshold for the device requiring the hold time. CL is the total bus capacitance (per data line), and IL is the total leakage or three-state current (per data line). The hold time will be tDECAY plus the various output disable times as specified in the Timing Specifications on Page 22 (for example tDSDAT for an SDRAM write cycle as shown in SDRAM Interface Timing on Page 26). VMEAS VMEAS Figure 34. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) REFERENCE SIGNAL Output Enable Time Measurement Output pins are considered to be enabled when they have made a transition from a high impedance state to the point when they start driving. The output enable time tENA is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown on the right side of Figure 35 on Page 43. The time tENA_MEASURED is the interval, from when the reference signal switches, to when the output voltage reaches VTRIP(high) or VTRIP(low). VTRIP(high) is 2.0 V and VTRIP(low) is 1.0 V for VDDEXT (nominal) = 2.5 V/3.3 V. Time tTRIP is the interval from when the output starts driving to when the output reaches the VTRIP(high) or VTRIP(low) trip voltage. Time tENA is calculated as shown in the equation: t ENA = t ENA_MEASURED – t TRIP If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. tDIS_MEASURED tDIS VOH (MEASURED) VOL (MEASURED) tENA_MEASURED tENA VOH (MEASURED) V VOH(MEASURED) VTRIP(HIGH) VTRIP(LOW) VOL(MEASURED) VOL (MEASURED) + V tDECAY tTRIP OUTPUT STOPS DRIVING OUTPUT STARTS DRIVING HIGH IMPEDANCE STATE Figure 35. Output Enable/Disable TO OUTPUT PIN 30pF 50 VLOAD Output Disable Time Measurement Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. The output disable time tDIS is the difference between tDIS_MEASURED and tDECAY as shown on the left side of Figure 35. t DIS = t DIS_MEASURED – t DECAY The time for the voltage on the bus to decay by ∆V is dependent on the capacitive load CL and the load current IL. This decay time can be approximated by the equation: t DECAY = ( C L ∆V ) ⁄ I L The time tDECAY is calculated with test loads CL and IL, and with ∆V equal to 0.5 V for VDDEXT (nominal) = 2.5 V/3.3 V. The time tDIS_MEASURED is the interval from when the reference signal switches, to when the output voltage decays ∆V from the measured output high or output low voltage. Figure 36. Equivalent Device Loading for AC Measurements (Includes All Fixtures) Capacitive Loading Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 36). VLOAD is 1.5 V for VDDEXT (nominal) = 2.5 V/3.3 V. Figure 37 on Page 44 through Figure 44 on Page 45 show how output rise time varies with capacitance. The delay and hold specifications given should be derated by a factor derived from these figures. The graphs in these figures may not be linear outside the ranges shown. Rev. A | Page 43 of 60 | May 2006 ADSP-BF561 ABE_B[0] (133 MHz DRIVER), VDDEXT (MIN) = 2.25V, TEMPERATURE = 85°C 14 RISE AND FALL TIME ns (10% to 90%) RISE AND FALL TIME ns (10% to 90%) 10 9 8 RISE TIME 7 6 FALL TIME 5 4 3 2 1 0 0 50 100 150 LOAD CAPACITANCE (pF) 200 250 0 50 100 150 LOAD CAPACITANCE (pF) 200 250 CLKOUT (CLKOUT DRIVER), VDDEXT (MAX) = 3.65V, TEMPERATURE = 85°C 12 RISE TIME 10 8 FALL TIME 6 4 2 0 Figure 37. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance for Driver A at VDDEXT (min) ABE0 (133 MHz DRIVER), VDDEXT (MAX) = 3.65V, TEMPERATURE = 85°C 12 RISE AND FALL TIME ns (10% to 90%) Figure 40. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance for Driver B at VDDEXT (max) TMR0 (33 MHz DRIVER), VDDEXT (MIN) = 2.25V, TEMPERATURE = 85°C 30 RISE AND FALL TIME ns (10% to 90%) 10 RISE TIME 8 FALL TIME 6 25 RISE TIME 20 15 FALL TIME 10 4 2 5 0 0 50 100 150 LOAD CAPACITANCE (pF) 200 250 0 0 50 100 150 LOAD CAPACITANCE (pF) 200 250 Figure 38. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance for Driver A at VDDEXT (max) CLKOUT (CLKOUT DRIVER), VDDEXT (MIN) = 2.25V, TEMPERATURE = 85°C 12 RISE AND FALL TIME ns (10% to 90%) Figure 41. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance for Driver C at VDDEXT (min) TMR0 (33 MHz DRIVER), VDDEXT (MAX) = 3.65V, TEMPERATURE = 85°C 20 RISE AND FALL TIME ns (10% to 90%) 18 16 RISE TIME 14 12 FALL TIME 10 8 6 4 2 10 RISE TIME 8 FALL TIME 6 4 2 0 0 0 50 100 150 LOAD CAPACITANCE (pF) 200 250 0 50 100 150 LOAD CAPACITANCE (pF) 200 250 Figure 39. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance for Driver B at VDDEXT (min) Figure 42. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance for Driver C at VDDEXT (max) Rev. A | Page 44 of 60 | May 2006 ADSP-BF561 SCK (66 MHz DRIVER), VDDEXT (MIN) = 2.25V, TEMPERATURE = 85°C 18 RISE AND FALL TIME ns (10% to 90%) 16 14 RISE TIME 12 10 FALL TIME 8 6 4 2 0 ENVIRONMENTAL CONDITIONS To determine the junction temperature on the application printed circuit board use: T J = T CASE + ( Ψ JT × P D ) where: TJ = junction temperature ( C). TCASE = case temperature ( C) measured by customer at top center of package. ΨJT = from Table 34 and Table 35. PD = power dissipation (see Power Dissipation on Page 42 for the method to calculate PD). 0 50 100 150 LOAD CAPACITANCE (pF) 200 250 Values of θJA are provided for package comparison and printed circuit board design considerations. θJA can be used for a first order approximation of TJ by the equation: T J = T A + ( θ JA × P D ) where: TA = ambient temperature ( C). In Table 34 and Table 35, airflow measurements comply with JEDEC standards JESD51–2 and JESD51–6, and the junctionto-board measurement complies with JESD51–8. The junctionto-case measurement complies with MIL-STD-883 (Method 1012.1). All measurements use a 2S2P JEDEC test board. Figure 43. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance for Driver D at VDDEXT (min) SCK (66 MHz DRIVER), VDDEXT (MAX) = 3.65V, TEMPERATURE = 85°C 14 RISE AND FALL TIME ns (10% to 90%) 12 10 RISE TIME 8 FALL TIME 6 4 2 0 0 50 100 150 LOAD CAPACITANCE (pF) 200 250 Thermal resistance θJA in Table 34 and Table 35 is the figure of merit relating to performance of the package and board in a convective environment. θJMA represents the thermal resistance under two conditions of airflow. θJB represents the heat extracted from the periphery of the board. ΨJT represents the correlation between TJ and TCASE. Values of θJB are provided for package comparison and printed circuit board design considerations. Table 34. Thermal Characteristics for BC-256 Package Parameter θJA θJMA θJMA θJB θJC ΨJT Condition 0 Linear m/s Airflow 1 Linear m/s Airflow 2 Linear m/s Airflow Not Applicable Not Applicable 0 Linear m/s Airflow Typical 25.6 22.4 21.6 18.9 4.85 0.15 Unit C/W C/W C/W C/W C/W C/W Figure 44. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance for Driver D at VDDEXT (max) Table 35. Thermal Characteristics for B-297 Package Parameter θJA θJMA θJMA θJB θJC ΨJT Condition 0 Linear m/s Airflow 1 Linear m/s Airflow 2 Linear m/s Airflow Not Applicable Not Applicable 0 Linear m/s Airflow Typical 20.6 17.8 17.4 16.3 7.15 0.37 Unit C/W C/W C/W C/W C/W C/W Rev. A | Page 45 of 60 | May 2006 ADSP-BF561 256-BALL MBGA PINOUT Table 36 lists the 256-Ball MBGA pinout by ball number. Table 37 on Page 48 lists the 256-Ball MBGA pinout alphabetically by signal. Table 36. 256-Ball MBGA Pin Assignment (Numerically by Ball Number) Ball No. Signal A01 VDDEXT A02 ADDR24 A03 ADDR20 A04 VDDEXT A05 ADDR14 A06 ADDR10 A07 AMS3 A08 AWE A09 VDDEXT A10 SMS3 A11 SCLK0/CLKOUT A12 SCLK1 A13 BG A14 ABE2/SDQM2 A15 ABE3/SDQM3 A16 VDDEXT B01 PPI1CLK B02 ADDR22 B03 ADDR18 B04 ADDR16 B05 ADDR12 B06 VDDEXT B07 AMS1 B08 ARE B09 SMS1 B10 SCKE B11 VDDEXT B12 BR B13 ABE1/SDQM1 B14 ADDR06 B15 ADDR04 B16 DATA0 C01 PPI0SYNC2/TMR9 C02 PPI0CLK C03 ADDR25 C04 ADDR19 C05 GND C06 ADDR11 C07 AOE C08 AMS0 Ball No. Signal C09 SMS2 C10 SRAS C11 GND C12 BGH C13 GND C14 ADDR07 C15 DATA1 C16 DATA3 D01 PPI0D13/PF45 D02 PPI0D15/PF47 D03 PPI0SYNC3 D04 ADDR23 D05 GND D06 GND D07 ADDR09 D08 GND D09 ARDY D10 SCAS D11 SA10 D12 VDDEXT D13 ADDR02 D14 GND D15 DATA5 D16 DATA6 E01 GND E02 PPI0D11/PF43 E03 PPI0D12/PF44 E04 PPI0SYNC1/TMR8 E05 ADDR15 E06 ADDR13 E07 AMS2 E08 VDDINT E09 SMS0 E10 SWE E11 ABE0/SDQM0 E12 DATA2 E13 GND E14 DATA4 E15 DATA7 E16 VDDEXT Ball No. Signal F01 CLKIN F02 VDDEXT F03 RESET F04 PPI0D10/PF42 F05 ADDR21 F06 ADDR17 F07 VDDINT F08 GND F09 VDDINT F10 GND F11 ADDR08 F12 DATA10 F13 DATA8 F14 DATA12 F15 DATA9 F16 DATA11 G01 XTAL G02 GND G03 VDDEXT G04 BYPASS G05 PPI0D14/PF46 G06 GND G07 GND G08 GND G09 VDDINT G10 ADDR05 G11 ADDR03 G12 DATA15 G13 DATA14 G14 GND G15 DATA13 G16 VDDEXT H01 GND H02 GND H03 PPI0D9/PF41 H04 PPI0D7 H05 PPI0D5 H06 VDDINT H07 VDDINT H08 GND Ball No. Signal Ball No. Signal H09 GND L01 PPI0D0 H10 GND L02 PPI1SYNC2/TMR11 H11 VDDINT L03 GND H12 DATA16 L04 PPI1SYNC3 H13 DATA18 L05 VDDEXT H14 DATA20 L06 PPI1D11/PF35 H15 DATA17 L07 GND H16 DATA19 L08 VDDINT J01 VROUT0 L09 GND J02 VROUT1 L10 VDDEXT J03 PPI0D2 L11 GND J04 PPI0D3 L12 DR0PRI J05 PPI0D1 L13 TFS0/PF16 J06 VDDEXT L14 GND J07 GND L15 DATA27 J08 VDDINT L16 DATA29 J09 VDDINT M01 PPI1D15/PF39 J10 VDDINT M02 PPI1D13/PF37 J11 GND M03 PPI1D9/PF33 J12 DATA30 M04 GND J13 DATA22 M05 NC J14 GND M06 PF3/SPISEL3/TMR3 J15 DATA21 M07 PF7/SPISEL7/TMR7 J16 DATA23 M08 VDDINT K01 PPI0D6 M09 GND K02 PPI0D4 M10 BMODE0 K03 PPI0D8/PF40 M11 SCK K04 PPI1SYNC1/TMR10 M12 DR1PRI K05 PPI1D14/PF38 M13 NC K06 VDDEXT M14 VDDEXT K07 GND M15 DATA31 K08 VDDINT M16 DT0PRI/PF18 K09 GND N01 PPI1D12/PF36 K10 GND N02 PPI1D10/PF34 K11 VDDINT N03 PPI1D3 K12 DATA28 N04 PPI1D1 K13 DATA26 N05 PF1/SPISEL1/TMR1 K14 DATA24 N06 PF9 K15 DATA25 N07 GND K16 VDDEXT N08 PF13 Rev. A | Page 46 of 60 | May 2006 ADSP-BF561 Table 36. 256-Ball MBGA Pin Assignment (Numerically by Ball Number) (Continued) Ball No. Signal N09 TDO N10 BMODE1 N11 MOSI N12 GND N13 RFS1/PF24 N14 GND N15 DT0SEC/PF17 N16 TSCLK0/PF29 P01 PPI1D8/PF32 P02 GND P03 PPI1D5 P04 PF0/SPISS/TMR0 Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal P05 GND R01 PPI1D7 R13 TX/PF26 T09 TCK P06 PF5/SPISEL5/TMR5 R02 PPI1D6 R14 TSCLK1/PF31 T10 TMS P07 PF11 R03 PPI1D2 R15 DT1PRI/PF23 T11 SLEEP P08 PF15/EXTCLK R04 PPI1D0 R16 RFS0/PF19 T12 VDDEXT P09 GND R05 PF4/SPISEL4/TMR4 T01 VDDEXT T13 RX/PF27 P10 TRST R06 PF8 T02 PPI1D4 T14 DR1SEC/PF25 P11 NMI0 R07 PF10 T03 VDDEXT T15 DT1SEC/PF22 P12 GND R08 PF14 T04 PF2/SPISEL2/TMR2 T16 VDDEXT P13 RSCLK1/PF30 R09 NMI1 T05 PF6/SPISEL6/TMR6 P14 TFS1/PF21 R10 TDI T06 VDDEXT P15 RSCLK0/PF28 R11 EMU T07 PF12 P16 DR0SEC/PF20 R12 MISO T08 VDDEXT Rev. A | Page 47 of 60 | May 2006 ADSP-BF561 Table 37. 256-Ball MBGA Pin Assignment (Alphabetically by Signal) Signal ABE0/SDQM0 ABE1/SDQM1 ABE2/SDQM2 ABE3/SDQM3 ADDR02 ADDR03 ADDR04 ADDR05 ADDR06 ADDR07 ADDR08 ADDR09 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 ADDR24 ADDR25 AMS0 AMS1 AMS2 AMS3 AOE ARDY ARE AWE BG BGH BMODE0 BMODE1 Ball No. E11 B13 A14 A15 D13 G11 B15 G10 B14 C14 F11 D07 A06 C06 B05 E06 A05 E05 B04 F06 B03 C04 A03 F05 B02 D04 A02 C03 C08 B07 E07 A07 C07 D09 B08 A08 A13 C12 M10 N10 Signal BR BYPASS CLKIN DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 DR0PRI DR0SEC/PF20 DR1PRI DR1SEC/PF25 DT0PRI/PF18 Ball No. B12 G04 F01 B16 C15 E12 C16 E14 D15 D16 E15 F13 F15 F12 F16 F14 G15 G13 G12 H12 H15 H13 H16 H14 J15 J13 J16 K14 K15 K13 L15 K12 L16 J12 M15 L12 P16 M12 T14 M16 Signal DT0SEC/PF17 DT1PRI/PF23 DT1SEC/PF22 EMU GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball No. N15 R15 T15 R11 C05 C11 C13 D05 D06 D08 D14 E01 E13 F08 F10 G02 G06 G07 G08 G14 H01 H02 H08 H09 H10 J07 J11 J14 K07 K09 K10 L03 L07 L09 L11 L14 M04 M09 N07 N12 Signal GND GND GND GND GND MISO MOSI NC NC NMI0 NMI1 PF0/SPISS/TMR0 PF1/SPISEL1/TMR1 PF2/SPISEL2/TMR2 PF3/SPISEL3/TMR3 PF4/SPISEL4/TMR4 PF5/SPISEL5/TMR5 PF6/SPISEL6/TMR6 PF7/SPISEL7/TMR7 PF8 PF9 PF10 PF11 PF12 PF13 PF14 PF15/EXTCLK PPI0CLK PPI0D0 PPI0D1 PPI0D2 PPI0D3 PPI0D4 PPI0D5 PPI0D6 PPI0D7 PPI0D8/PF40 PPI0D9/PF41 PPI0D10/PF42 PPI0D11/PF43 Ball No. N14 P02 P05 P09 P12 R12 N11 M05 M13 P11 R09 P04 N05 T04 M06 R05 P06 T05 M07 R06 N06 R07 P07 T07 N08 R08 P08 C02 L01 J05 J03 J04 K02 H05 K01 H04 K03 H03 F04 E02 Rev. A | Page 48 of 60 | May 2006 ADSP-BF561 Table 37. 256-Ball MBGA Pin Assignment (Alphabetically by Signal) (Continued) Signal PPI0D12/PF44 PPI0D13/PF45 PPI0D14/PF46 PPI0D15/PF47 PPI0SYNC1/TMR8 PPI0SYNC2/TMR9 PPI0SYNC3 PPI1CLK PPI1D0 PPI1D1 PPI1D2 PPI1D3 PPI1D4 PPI1D5 PPI1D6 PPI1D7 PPI1D8/PF32 PPI1D9/PF33 PPI1D10/PF34 PPI1D11/PF35 PPI1D12/PF36 PPI1D13/PF37 PPI1D14/PF38 PPI1D15/PF39 Ball No. E03 D01 G05 D02 E04 C01 D03 B01 R04 N04 R03 N03 T02 P03 R02 R01 P01 M03 N02 L06 N01 M02 K05 M01 Signal PPI1SYNC1/TMR10 PPI1SYNC2/TMR11 PPI1SYNC3 RESET RFS0/PF19 RFS1/PF24 RSCLK0/PF28 RSCLK1/PF30 RX/PF27 SA10 SCAS SCK SCKE SCLK0/CLKOUT SCLK1 SLEEP SMS0 SMS1 SMS2 SMS3 SRAS SWE TCK TDI Ball No. K04 L02 L04 F03 R16 N13 P15 P13 T13 D11 D10 M11 B10 A11 A12 T11 E09 B09 C09 A10 C10 E10 T09 R10 Signal TDO TFS0/PF16 TFS1/PF21 TMS TRST TSCLK0/PF29 TSCLK1/PF31 TX/PF26 VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT Ball No. N09 L13 P14 T10 P10 N16 R14 R13 A01 A04 A09 A16 B06 B11 D12 E16 F02 G03 G16 J06 K06 K16 L05 L10 Signal VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VROUT0 VROUT1 XTAL Ball No. M14 T01 T03 T06 T08 T12 T16 E08 F07 F09 G09 H06 H07 H11 J08 J09 J10 K08 K11 L08 M08 J01 J02 G01 Rev. A | Page 49 of 60 | May 2006 ADSP-BF561 Figure 45 lists the top view of the 256-Ball MBGA ball configuration. Figure 46 lists the bottom view of the 256-Ball MBGA ball configuration. A1 BALL PAD CORNER A B C D E F G H J K L M N P R T KEY: VDDINT VDDEXT GND I/O NC VROUT 1 2 3 4 5 6 7 8 TOP VIEW 9 10 11 12 13 14 15 16 Figure 45. 256-Ball MBGA Ball Configuration (Top View) A1 BALL PAD CORNER A B C D E F G H J K L M N P R T KEY: VDDINT VDDEXT GND I/O NC VROUT 16 15 14 13 12 11 10 9 8 7 BOTTOM VIEW 6 5 4 3 2 1 Figure 46. 256-Ball MBGA Ball Configuration (Bottom View) Rev. A | Page 50 of 60 | May 2006 ADSP-BF561 297-BALL PBGA PINOUT Table 38 lists the 297-Ball PBGA pinout numerically by ball number. Table 39 on Page 53 lists the 297-Ball PBGA pinout alphabetically by signal. Table 38. 297-Ball PBGA Pin Assignment (Numerically by Ball Number) Ball No. A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 Signal GND ADDR25 ADDR23 ADDR21 ADDR19 ADDR17 ADDR15 ADDR13 ADDR11 ADDR09 AMS3 AMS1 AWE ARE SMS0 SMS2 SRAS SCAS SCLK0/CLKOUT SCLK1 BGH ABE0/SDQM0 ABE2/SDQM2 ADDR08 ADDR06 GND PPI1CLK GND ADDR24 ADDR22 ADDR20 ADDR18 ADDR16 ADDR14 ADDR12 ADDR10 AMS2 AMS0 AOE ARDY Ball No. B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C01 C02 C03 C04 C05 C22 C23 C24 C25 C26 D01 D02 D03 D04 D23 D24 D25 D26 E01 E02 E03 E24 E25 E26 F01 F02 F25 F26 Signal SMS1 SMS3 SCKE SWE SA10 BR BG ABE1/SDQM1 ABE3/SDQM3 ADDR07 GND ADDR05 PPI0SYNC3 PPI0CLK GND GND GND GND GND GND ADDR04 ADDR03 PPI0SYNC1/TMR8 PPI0SYNC2/TMR9 GND GND GND GND ADDR02 DATA1 PPI0D15/PF47 PPI0D14/PF46 GND GND DATA0 DATA3 PPI0D13/PF45 PPI0D12/PF44 DATA2 DATA5 Ball No. G01 G02 G25 G26 H01 H02 H25 H26 J01 J02 J10 J11 J12 J13 J14 J15 J16 J17 J18 J25 J26 K01 K02 K10 K11 K12 K13 K14 K15 K16 K17 K18 K25 K26 L01 L02 L10 L11 L12 L13 Signal PPI0D11/PF43 PPI0D10/PF42 DATA4 DATA7 BYPASS RESET DATA6 DATA9 CLKIN GND VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT DATA8 DATA11 XTAL NC VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT DATA10 DATA13 NC NC VDDEXT GND GND GND Ball No. L14 L15 L16 L17 L18 L25 L26 M01 M02 M10 M11 M12 M13 M14 M15 M16 M17 M18 M25 M26 N01 N02 N10 N11 N12 N13 N14 N15 N16 N17 N18 N25 N26 P01 P02 P10 P11 P12 P13 P14 Signal GND GND GND GND VDDINT DATA12 DATA15 VROUT0 GND VDDEXT GND GND GND GND GND GND GND VDDINT DATA14 DATA17 VROUT1 PPI0D9/PF41 VDDEXT GND GND GND GND GND GND GND VDDINT DATA16 DATA19 PPI0D7 PPI0D8/PF40 VDDEXT GND GND GND GND Rev. A | Page 51 of 60 | May 2006 ADSP-BF561 Table 38. 297-Ball PBGA Pin Assignment (Numerically by Ball Number) (Continued) Ball No. P15 P16 P17 P18 P25 P26 R01 R02 R10 R11 R12 R13 R14 R15 R16 R17 R18 R25 R26 T01 T02 T10 T11 T12 T13 T14 T15 T16 T17 T18 T25 T26 U01 U02 U10 Signal GND GND GND VDDINT DATA18 DATA21 PPI0D5 PPI0D6 VDDEXT GND GND GND GND GND GND GND VDDINT DATA20 DATA23 PPI0D3 PPI0D4 VDDEXT GND GND GND GND GND GND GND VDDINT DATA22 DATA25 PPI0D1 PPI0D2 VDDEXT Ball No. U11 U12 U13 U14 U15 U16 U17 U18 U25 U26 V01 V02 V25 V26 W01 W02 W25 W26 Y01 Y02 Y25 Y26 AA01 AA02 AA25 AA26 AB01 AB02 AB03 AB24 AB25 AB26 AC01 AC02 AC03 Signal VDDEXT VDDEXT VDDEXT GND VDDINT VDDINT VDDINT VDDINT DATA24 DATA27 PPI1SYNC3 PPI0D0 DATA26 DATA29 PPI1SYNC1/TMR10 PPI1SYNC2/TMR11 DATA28 DATA31 PPI1D15/PF39 PPI1D14/PF38 DATA30 DT0PRI/PF18 PPI1D13/PF37 PPI1D12/PF36 DT0SEC/PF17 TSCLK0/PF29 PPI1D11/PF35 PPI1D10/PF34 GND GND TFS0/PF16 DR0PRI PPI1D9/PF33 PPI1D8/PF32 GND Ball No. AC04 AC23 AC24 AC25 AC26 AD01 AD02 AD03 AD04 AD05 AD22 AD23 AD24 AD25 AD26 AE01 AE02 AE03 AE04 AE05 AE06 AE07 AE08 AE09 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 Signal GND GND GND DR0SEC/PF20 RFS0/PF19 PPI1D7 PPI1D6 GND GND GND GND GND GND NC RSCLK0/PF28 PPI1D5 GND PPI1D3 PPI1D1 PF0/SPISS/TMR0 PF2/SPISEL2/TMR2 PF4/SPISEL4/TMR4 PF6/SPISEL6/TMR6 PF8 PF10 PF12 PF14 NC TDO TRST EMU BMODE1 BMODE0 MISO MOSI Ball No. AE21 AE22 AE23 AE24 AE25 AE26 AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Signal RX/PF27 RFS1/PF24 DR1SEC/PF25 TFS1/PF21 GND NC GND PPI1D4 PPI1D2 PPI1D0 PF1/SPISEL1/TMR1 PF3/SPISEL3/TMR3 PF5/SPISEL5/TMR5 PF7/SPISEL7/TMR7 PF9 PF11 PF13 PF15/EXT CLK NMI1 TCK TDI TMS SLEEP NMI0 SCK TX/PF26 RSCLK1/PF30 DR1PRI TSCLK1/PF31 DT1SEC/PF22 DT1PRI/PF23 GND Rev. A | Page 52 of 60 | May 2006 ADSP-BF561 Table 39. 297-Ball PBGA Pin Assignment (Alphabetically by Signal) Signal ABE0/SDQM0 ABE1/SDQM1 ABE2/SDQM2 ABE3/SDQM3 ADDR02 ADDR03 ADDR04 ADDR05 ADDR06 ADDR07 ADDR08 ADDR09 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 ADDR24 ADDR25 AMS0 AMS1 AMS2 AMS3 AOE ARDY ARE AWE BG BGH BMODE0 BMODE1 Ball No. A22 B22 A23 B23 D25 C26 C25 B26 A25 B24 A24 A10 B10 A09 B09 A08 B08 A07 B07 A06 B06 A05 B05 A04 B04 A03 B03 A02 B12 A12 B11 A11 B13 B14 A14 A13 B21 A21 AE18 AE17 Signal BR BYPASS CLKIN DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 DR0PRI DR0SEC/PF20 DR1PRI DR1SEC/PF25 DT0PRI/PF18 Ball No. B20 H01 J01 E25 D26 F25 E26 G25 F26 H25 G26 J25 H26 K25 J26 L25 K26 M25 L26 N25 M26 P25 N26 R25 P26 T25 R26 U25 T26 V25 U26 W25 V26 Y25 W26 AB26 AC25 AF22 AE23 Y26 Signal DT0SEC/PF17 DT1PRI/PF23 DT1SEC/PF22 EMU GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball No. AA25 AF25 AF24 AE16 A01 A26 B02 B25 C03 C04 C05 C22 C23 C24 D03 D04 D23 D24 E03 E24 J02 L11 L12 L13 L14 L15 L16 L17 M02 M11 M12 M13 M14 M15 M16 M17 N11 N12 N13 N14 Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball No. N15 N16 N17 P11 P12 P13 P14 P15 P16 P17 R11 R12 R13 R14 R15 R16 R17 T11 T12 T13 T14 T15 T16 T17 U14 AB03 AB24 AC03 AC04 AC23 AC24 AD03 AD04 AD05 AD22 AD23 AD24 AE02 AE25 AF01 Rev. A | Page 53 of 60 | May 2006 ADSP-BF561 Table 39. 297-Ball PBGA Pin Assignment (Alphabetically by Signal) (Continued) Signal GND MISO MOSI NC NC NC NC NC NC NMI0 NMI1 PF0/SPISS/TMR0 PF1/SPISEL1/TMR1 PF2/SPISEL2/TMR2 PF3/SPISEL3/TMR3 PF4/SPISEL4/TMR4 PF5/SPISEL5/TMR5 PF6/SPISEL6/TMR6 PF7/SPISEL7/TMR7 PF8 PF9 PF10 PF11 PF12 PF13 PF14 PF15/EXT CLK PPI0CLK PPI0D0 PPI0D1 PPI0D2 PPI0D3 PPI0D4 PPI0D5 PPI0D6 Ball No. AF26 AE19 AE20 K02 L01 L02 AD25 AE13 AE26 AF18 AF13 AE05 AF05 AE06 AF06 AE07 AF07 AE08 AF08 AE09 AF09 AE10 AF10 AE11 AF11 AE12 AF12 C02 V02 U01 U02 T01 T02 R01 R02 Signal PPI0D7 PPI0D8/PF40 PPI0D9/PF41 PPI0D10/PF42 PPI0D11/PF43 PPI0D12/PF44 PPI0D13/PF45 PPI0D14/PF46 PPI0D15/PF47 PPI0SYNC1/TMR8 PPI0SYNC2/TMR9 PPI0SYNC3 PPI1CLK PPI1D0 PPI1D1 PPI1D2 PPI1D3 PPI1D4 PPI1D5 PPI1D6 PPI1D7 PPI1D8/PF32 PPI1D9/PF33 PPI1D10/PF34 PPI1D11/PF35 PPI1D12/PF36 PPI1D13/PF37 PPI1D14/PF38 PPI1D15/PF39 PPI1SYNC1/TMR10 PPI1SYNC2/TMR11 PPI1SYNC3 RESET RFS0/PF19 RFS1/PF24 Ball No. P01 P02 N02 G02 G01 F02 F01 E02 E01 D01 D02 C01 B01 AF04 AE04 AF03 AE03 AF02 AE01 AD02 AD01 AC02 AC01 AB02 AB01 AA02 AA01 Y02 Y01 W01 W02 V01 H02 AC26 AE22 Signal RSCLK0/PF28 RSCLK1/PF30 RX/PF27 SA10 SCAS SCK SCKE SCLK0/CLKOUT SCLK1 SLEEP SMS0 SMS1 SMS2 SMS3 SRAS SWE TCK TDI TDO TFS0/PF16 TFS1/PF21 TMS TRST TSCLK0/PF29 TSCLK1/PF31 TX/PF26 VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT Ball No. AD26 AF21 AE21 B19 A18 AF19 B17 A19 A20 AF17 A15 B15 A16 B16 A17 B18 AF14 AF15 AE14 AB25 AE24 AF16 AE15 AA26 AF23 AF20 J10 J11 J12 J13 J14 J15 K10 K11 K12 Signal VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VROUT0 VROUT1 XTAL Ball No. K13 K14 K15 L10 M10 N10 P10 R10 T10 U10 U11 U12 U13 J16 J17 J18 K16 K17 K18 L18 M18 N18 P18 R18 T18 U15 U16 U17 U18 M01 N01 K01 Rev. A | Page 54 of 60 | May 2006 ADSP-BF561 Figure 47 lists the top view of the 297-Ball PBGA ball configuration. Figure 48 lists the bottom view of the 297-Ball PBGA ball configuration. A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 KEY: VDDINT VDDEXT GND I/O NC VROUT TOP VIEW Figure 47. 297-Ball PBGA Ball Configuration (Top View) A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 KEY: VDDINT VDDEXT GND I/O NC VROUT BOTTOM VIEW Figure 48. 297-Ball PBGA Ball Configuration (Bottom View) Rev. A | Page 55 of 60 | May 2006 ADSP-BF561 OUTLINE DIMENSIONS Dimensions in the outline dimension figures are shown in millimeters. 12.00 BSC SQ 0.65 BSC BALL PITCH A1 BALL PAD CORNER A B C D E F G H J K L M N P R T 9.75 BSC SQ CL A1 BALL PAD CORNER CL TOP VIEW 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BOTTOM VIEW 1.70 1.51 1.36 SIDE VIEW 0.25 MIN DETAIL A NOTES 1. DIMENSIONS ARE IN MILLIMETERS. 2. COMPLIES WITH JEDEC REGISTERED OUTLINE MO-225, WITH NO EXACT PACKAGE SIZE AND EXCEPTION TO PACKAGE HEIGHT. 3. MINIMUM BALL HEIGHT 0.25 0.10 MAX COPLANARITY 0.45 BALL DIAMETER 0.40 0.35 SEATING PLANE DETAIL A Figure 49. 256-Ball Mini-Ball Grid Array (BC-256) Rev. A | Page 56 of 60 | May 2006 ADSP-BF561 27.00 BSC SQ 1.00 BSC BALL PITCH A1 BALL PAD CORNER A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 25.00 BSC SQ 8.00 CL A1 BALL PAD CORNER 8.00 CL TOP VIEW 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BOTTOM VIEW 2.43 2.23 2.03 SIDE VIEW 0.40 MIN DETAIL A NOTES 1. DIMENSIONS ARE IN MILLIMETERS. 2. COMPLIES WITH JEDEC REGISTERED OUTLINE MS-034, VARIATION AAL-1. 3. MINIMUM BALL HEIGHT 0.40 0.20 MAX COPLANARITY SEATING PLANE DETAIL A 0.70 BALL DIAMETER 0.60 0.50 Figure 50. 297-Ball PBGA Grid Array (B-297) SURFACE MOUNT DESIGN Table 40 is provided as an aid to PCB design. For industrystandard design recommendations, refer to IPC-7351, Generic Requirements for Surface Mount Design and Land Pattern Standard. Table 40. BGA Data for Use with Surface Mount Design Package 256-Ball Mini-Ball Grid Array (BC-256) 297-Ball PBGA Grid Array (B-297) Ball Attach Type Solder Mask Defined Solder Mask Defined Solder Mask Opening 0.30 mm diameter 0.43 mm diameter Ball Pad Size 0.43 mm diameter 0.58 mm diameter Rev. A | Page 57 of 60 | May 2006 ADSP-BF561 ORDERING GUIDE Temperature Model Range1 Package Description 2 ADSP-BF561SKBCZ600 0°C to +70°C 256-Ball Chip Scale Package Ball Grid Array (Mini-BGA) ADSP-BF561SKBCZ5002 0°C to +70°C 256-Ball Chip Scale Package Ball Grid Array (Mini-BGA) ADSP-BF561SKB500 0°C to +70°C 297-Ball Plastic Ball Grid Array (PBGA) ADSP-BF561SKB600 0°C to +70°C 297-Ball Plastic Ball Grid Array (PBGA) ADSP-BF561SKBZ5002 0°C to +70°C 297-Ball Plastic Ball Grid Array (PBGA) ADSP-BF561SKBZ6002 0°C to +70°C 297-Ball Plastic Ball Grid Array (PBGA) ADSP-BF561SBB600 –40°C to +85°C 297-Ball Plastic Ball Grid Array (PBGA) ADSP-BF561SBB500 –40°C to +85°C 297-Ball Plastic Ball Grid Array (PBGA) ADSP-BF561SBBZ6002 –40°C to +85°C 297-Ball Plastic Ball Grid Array (PBGA) ADSP-BF561SBBZ5002 –40°C to +85°C 297-Ball Plastic Ball Grid Array (PBGA) ADSP-BF561WBBZ-5A2, 3 –40°C to +85°C 297-Ball Plastic Ball Grid Array (PBGA) 1 2 Package Instruction Operating Voltage Option Rate (Max) (Nom) BC-256 600 MHz 1.25 V Internal, 2.5 V or 3.3 V I/O BC-256 B-297 B-297 B-297 B-297 B-297 B-297 B-297 B-297 B-297 500 MHz 500 MHz 600 MHz 500 MHz 600 MHz 600 MHz 500 MHz 600 MHz 500 MHz 500 MHz 1.25 V Internal, 2.5 V or 3.3 V I/O 1.25 V Internal, 2.5 V or 3.3 V I/O 1.35 V Internal, 2.5 V or 3.3 V I/O 1.25 V Internal, 2.5 V or 3.3 V I/O 1.35 V Internal, 2.5 V or 3.3 V I/O 1.35 V Internal, 2.5 V or 3.3 V I/O 1.25 V Internal, 2.5 V or 3.3 V I/O 1.35 V Internal, 2.5 V or 3.3 V I/O 1.25 V Internal, 2.5 V or 3.3 V I/O 1.2 V Internal, 2.5 V or 3.3 V I/O Referenced temperature is ambient temperature. Z = Pb-free part. 3 Automotive grade part. Rev. A | Page 58 of 60 | May 2006 ADSP-BF561 Rev. A | Page 59 of 60 | May 2006 ADSP-BF561 © 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04696-0-5/06(A) Rev. A | Page 60 of 60 | May 2006