ADSP-BF707KBCZ-3

Blackfin+ Core Embedded Processor ADSP-BF700/701/702/703/704/705/706/707 FEATURES MEMORY Blackfin+ core with up to 400 MHz performance Dual 16-bit or single 32-bit MAC support per cycle 16-bit complex MAC and many other instruction set enhancements Instruction set compatible with previous Blackfin products Low-cost packaging 88-Lead LFCSP_VQ (QFN) package (12 mm × 12 mm),  RoHS compliant 184-Ball CSP_BGA package (12 mm × 12 mm × 0.8 mm pitch), RoHS compliant Low system power with < 100 mW core domain power at 400 MHz (< 0.25 mW/MHz) at 25°C TJUNCTION AEC-Q100 qualified for automotive applications 136 kB L1 SRAM with multi-parity-bit protection  (64 kB instruction, 64 kB data, 8 kB scratchpad) Large on-chip L2 SRAM with ECC protection 256 kB, 512 kB, 1 MB variants On-chip L2 ROM (512 kB) L3 interface (CSP_BGA only) optimized for lowest system power, providing 16-bit interface to DDR2 or LPDDR DRAM devices (up to 200 MHz) Security and one-time-programmable memory Crypto hardware accelerators Fast secure boot for IP protection memDMA encryption/decryption for fast run-time security PERIPHERALS FEATURES See Figure 1, Processor Block Diagram and Table 1, Processor Comparison SYSTEM CONTROL BLOCKS PERIPHERALS 1× TWI EMULATOR TEST & CONTROL PLL & POWER MANAGEMENT FAULT MANAGEMENT EVENT CONTROL WATCHDOG 8× TIMER 1× COUNTER 2× CAN L2 MEMORY B 512K BYTE ROM 136K BYTE PARITY BIT PROTECTED L1 SRAM INSTRUCTION/DATA UP TO 1M BYTE SRAM 2× UART ECC-PROTECTED (& DMA MEMORY PROTECTION) SPI HOST PORT 2x QUAD SPI 1x DUAL SPI GPIO 2× SPORT 1× MSI (SD/SDIO) SYSTEM FABRIC EXTERNAL BUS INTERFACES MEMORY PROTECTION HARDWARE FUNCTIONS OTP MEMORY ANALOG SUB SYSTEM STATIC MEMORY CONTROLLER SYSTEM PROTECTION 3× MDMA STREAMS CRYPTO ENGINE (SECURITY) 2× CRC HADC DYNAMIC MEMORY CONTROLLER LPDDR DDR2 1× PPI 1× RTC 1× USB 2.0 HS OTG 16 Figure 1. Processor Block Diagram Blackfin, Blackfin+, and the Blackfin logo are registered trademarks of Analog Devices, Inc. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 ©2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADSP-BF700/701/702/703/704/705/706/707 TABLE OF CONTENTS Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Peripherals Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Blackfin+ Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Processor Infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Security Features Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Processor Safety Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Additional Processor Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power and Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 System Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal  Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 GPIO Multiplexing for 12 mm × 12 mm 88-Lead  LFCSP (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 ADSP-BF70x Designer Quick Reference . . . . . . . . . . . . . . . . . . . . . . 37 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 HADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 ADSP-BF70x 184-Ball CSP_BGA Ball Assignments  (Numerical by Ball Number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN)  Lead Assignments (Numerical by Lead Number) . . . . . . 108 Related Signal Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 ADSP-BF70x Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . 17 Surface-Mount Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 184-Ball CSP_BGA Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . 21 Automotive Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 GPIO Multiplexing for 184-Ball CSP_BGA . . . . . . . . . . . . . . . . . . 28 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 REVISION HISTORY 2/2019—Rev. C to Rev. D Deleted Package Information (Figure 7 and Table 27) in Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Changes to  TWI0VSEL Settings and VDD_EXT/VBUSTWI . . . . . . . . . . . 50 Changes to Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Changes to Output Enable Time Measurement . . . . . . . . . . . . 102 Changes to Output Disable Time Measurement . . . . . . . . . . . 102 Changes to Output Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Changes to Automotive Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Rev. D | Page 2 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 GENERAL DESCRIPTION The ADSP-BF70x processor is a member of the Blackfin®  family of products. The Blackfin processor combines a dualMAC 16-bit state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. New enhancements to the Blackfin+ core add 32-bit MAC and 16-bit complex MAC support, cache enhancements, branch prediction and other instruction set improvements—all while maintaining instruction set compatibility to previous Blackfin products. The processor offers performance up to 400 MHz, as well as low static power consumption. Produced with a low-power and lowvoltage design methodology, they provide world-class power management and performance. By integrating a rich set of industry-leading system peripherals and memory (shown in Table 1), the Blackfin processor is the platform of choice for next-generation applications that require RISC-like programmability, multimedia support, and leadingedge signal processing in one integrated package. These applications span a wide array of markets, from automotive systems to embedded industrial, instrumentation, video/image analysis, biometric and power/motor control applications. Table 1. Processor Comparison Processor Feature Maximum Speed Grade (MHz)1 Maximum SYSCLK (MHz) Package Options 1 ADSPBF701 ADSPBF702 ADSPBF703 200 100 88-Lead LFCSP 43 Memory (bytes) GPIOs L1 Instruction SRAM L1 Instruction SRAM/Cache L1 Data SRAM L1 Data SRAM/Cache L1 Scratchpad (L1 Data C) L2 SRAM L2 ROM DDR2/LPDDR (16-bit) 2 IC Up/Down/Rotary Counter GP Timer Watchdog Timer GP Counter SPORTs Quad SPI Dual SPI SPI Host Port USB 2.0 HS OTG Parallel Peripheral Interface CAN UART Real-Time Clock Static Memory Controller (SMC) Security Crypto Engine SD/SDIO (MSI) 4-Channel 12-Bit ADC ADSPBF700 ADSPBF704 ADSPBF705 ADSPBF706 ADSPBF707 88-Lead LFCSP 43 184-Ball CSP_BGA 47 400 200 184-Ball CSP_BGA 47 128K No Yes 4-bit No 8-bit Yes 88-Lead LFCSP 43 184-Ball 88-Lead 184-Ball CSP_BGA LFCSP CSP_BGA 47 43 47 48K 16K 32K 32K 8K 256K 512K 512K No Yes No Yes 1 1 8 1 1 2 2 1 1 1 1 2 2 1 Yes Yes 4-bit 8-bit 4-bit 8-bit No Yes No Yes Other speed grades available. Rev. D | Page 3 of 114 | February 2019 1024K No Yes 4-bit No 8-bit Yes ADSP-BF700/701/702/703/704/705/706/707 BLACKFIN+ PROCESSOR CORE As shown in Figure 1, the processor integrates a Blackfin+ processor core. The core, shown in Figure 2, contains two 16-bit multipliers, one 32-bit multiplier, two 40-bit accumulators (which may be used together as a 72-bit accumulator), two  40-bit ALUs, one 72-bit ALU, four video ALUs, and a 40-bit shifter. The computation units process 8-, 16-, or 32-bit data from the register file. The ALUs perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. In addition, many special instructions are included to accelerate various signal processing tasks. These include bit operations such as field extract and population count, divide primitives, saturation and rounding, and sign/exponent detection. The set of video instructions include byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided are the compare/select and vector search instructions. The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields. For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute register). If a second ALU is used, quad 16-bit operations are possible. The core can perform two 16-bit by 16-bit multiply-accumulates or one 32-bit multiply-accumulate in each cycle. Signed and unsigned formats, rounding, saturation, and complex multiplies are supported. The 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. ADDRESS ARITHMETIC UNIT I3 L3 B3 M3 I2 L2 B2 M2 I1 L1 B1 M1 I0 L0 B0 M0 SP FP P5 DAG1 P4 P3 DAG0 P2 DA1 32 DA0 32 P1 TO MEMORY P0 32 PREG 32 RAB SD 32 LD1 32 LD0 32 ASTAT 32 32 R7.H R6.H R7.L R6.L R5.H R5.L R4.H R4.L R3.H R3.L R2.H R2.L R1.H R1.L R0.H R0.L SEQUENCER 16 8 ALIGN 16 32 8 8 8 DECODE BARREL SHIFTER 40 40 A0 A1 32 32 DATA ARITHMETIC UNIT Figure 2. Blackfin+ Processor Core Rev. D | Page 4 of 114 LOOP BUFFER 40 72 | February 2019 40 CONTROL UNIT ADSP-BF700/701/702/703/704/705/706/707 The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For program flow control, the sequencer supports PC relative and indirect conditional jumps (with dynamic branch prediction), and subroutine calls. Hardware supports zero-overhead looping. The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies. The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported register file consisting of four sets of 32-bit index, modify, length, and base registers (for circular buffering), and eight additional 32-bit pointer registers (for C-style indexed stack manipulation). The Blackfin processor supports a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. At the L1 level, the instruction memory holds instructions only. The data memory holds data, and a dedicated scratchpad data memory stores stack and local variable information. In addition, multiple L1 memory blocks are provided, offering a configurable mix of SRAM and cache. The memory management unit (MMU) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access. The architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources. INSTRUCTION SET DESCRIPTION The Blackfin processor instruction set has been optimized so that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. The Blackfin processor supports a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle. The Blackfin processor family assembly language instruction set employs an algebraic syntax designed for ease of coding and readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to a very small final memory size. The instruction set also provides fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single instruction. Coupled with many features more often seen on microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture supports both user (algorithm/application code) and supervisor (O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core processor resources. Rev. D | Page 5 of 114 The assembly language, which takes advantage of the processor’s unique architecture, offers the following advantages: • Seamlessly integrated DSP/MCU features are optimized for both 8-bit and 16-bit operations. • A multi-issue load/store modified-Harvard architecture, which supports two 16-bit MAC or four 8-bit ALU + two load/store + two pointer updates per cycle. • All registers, I/O, and memory are mapped into a unified 4G byte memory space, providing a simplified programming model. • Control of all asynchronous and synchronous events to the processor is handled by two subsystems: the core event controller (CEC) and the system event controller (SEC). • Microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data-types; and separate user and supervisor stack pointers. • Code density enhancements, which include intermixing of 16-bit and 32-bit instructions (no mode switching, no code segregation). Frequently used instructions are encoded in 16 bits. PROCESSOR INFRASTRUCTURE The following sections provide information on the primary infrastructure components of the ADSP-BF70x processor. DMA Controllers The processor uses direct memory access (DMA) to transfer data within memory spaces or between a memory space and a peripheral. The processor can specify data transfer operations and return to normal processing while the fully integrated DMA controller carries out the data transfers independent of processor activity. DMA transfers can occur between memory and a peripheral or between one memory and another memory. Each memory-tomemory DMA stream uses two channels, where one channel is the source channel, and the second is the destination channel. All DMAs can transport data to and from all on-chip and offchip memories. Programs can use two types of DMA transfers, descriptor-based or register-based. Register-based DMA allows the processor to directly program DMA control registers to initiate a DMA transfer. On completion, the control registers may be automatically updated with their original setup values for continuous transfer. Descriptor-based DMA transfers require a set of parameters stored within memory to initiate a DMA sequence. Descriptor-based DMA transfers allow multiple DMA sequences to be chained together and a DMA channel can be programmed to automatically set up and start another DMA transfer after the current sequence completes. The DMA controller supports the following DMA operations. • A single linear buffer that stops on completion. • A linear buffer with negative, positive, or zero stride length. • A circular, auto-refreshing buffer that interrupts when each buffer becomes full. | February 2019 ADSP-BF700/701/702/703/704/705/706/707 • A similar buffer that interrupts on fractional buffers (for example, 1/2, 1/4). • 1D DMA—uses a set of identical ping-pong buffers defined by a linked ring of two-word descriptor sets, each containing a link pointer and an address. • 1D DMA—uses a linked list of 4 word descriptor sets containing a link pointer, an address, a length, and a configuration. • 2D DMA—uses an array of one-word descriptor sets, specifying only the base DMA address. • 2D DMA—uses a linked list of multi-word descriptor sets, specifying everything. Trigger Routing Unit (TRU) The TRU provides system-level sequence control without core intervention. The TRU maps trigger masters (generators of triggers) to trigger slaves (receivers of triggers). Slave endpoints can be configured to respond to triggers in various ways. Common applications enabled by the TRU include: • Automatically triggering the start of a DMA sequence after a sequence from another DMA channel completes • Software triggering • Synchronization of concurrent activities General-Purpose I/O (GPIO) Each general-purpose port pin can be individually controlled by manipulation of the port control, status, and interrupt registers: Event Handling The processor provides event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher-priority event takes precedence over servicing of a lower-priority event. The processor provides support for five different types of events: • Emulation—An emulation event causes the processor to enter emulation mode, allowing command and control of the processor through the JTAG interface. • Reset—This event resets the processor. • Nonmaskable interrupt (NMI)—The NMI event can be generated either by the software watchdog timer, by the NMI input signal to the processor, or by software. The NMI event is frequently used as a power-down indicator to initiate an orderly shutdown of the system. • Exceptions—Events that occur synchronously to program flow (in other words, the exception is taken before the instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause exceptions. • Interrupts —Events that occur asynchronously to program flow. They are caused by input signals, timers, and other peripherals, as well as by an explicit software instruction. System Event Controller (SEC) The SEC manages the enabling, prioritization, and routing of events from each system interrupt or fault source. Additionally, it provides notification and identification of the highest priority active system interrupt request to the core and routes system fault sources to its integrated fault management unit. The SEC triggers core general-purpose interrupt IVG11. It is recommended that IVG11 be set to allow self-nesting. The four lower priority interrupts (IVG15-12) may be used for software interrupts. • GPIO direction control register—Specifies the direction of each individual GPIO pin as input or output. • GPIO control and status registers—A write one to modify mechanism allows any combination of individual GPIO pins to be modified in a single instruction, without affecting the level of any other GPIO pins. • GPIO interrupt mask registers—Allow each individual GPIO pin to function as an interrupt to the processor. GPIO pins defined as inputs can be configured to generate hardware interrupts, while output pins can be triggered by software interrupts. • GPIO interrupt sensitivity registers—Specify whether individual pins are level- or edge-sensitive and specify—if edge-sensitive—whether just the rising edge or both the rising and falling edges of the signal are significant. Pin Interrupts Every port pin on the processor can request interrupts in either an edge-sensitive or a level-sensitive manner with programmable polarity. Interrupt functionality is decoupled from GPIO operation. Three system-level interrupt channels (PINT0–3) are reserved for this purpose. Each of these interrupt channels can manage up to 32 interrupt pins. The assignment from pin to interrupt is not performed on a pin-by-pin basis. Rather, groups of eight pins (half ports) can be flexibly assigned to interrupt channels. Every pin interrupt channel features a special set of 32-bit memory-mapped registers that enable half-port assignment and interrupt management. This includes masking, identification, and clearing of requests. These registers also enable access to the respective pin states and use of the interrupt latches, regardless of whether the interrupt is masked or not. Most control registers feature multiple MMR address entries to write-one-to-set or write-one-to-clear them individually. Pin Multiplexing The processor supports a flexible multiplexing scheme that multiplexes the GPIO pins with various peripherals. A maximum of 4 peripherals plus GPIO functionality is shared by each GPIO pin. All GPIO pins have a bypass path feature—that is, when the Rev. D | Page 6 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 output enable and the input enable of a GPIO pin are both active, the data signal before the pad driver is looped back to the receive path for the same GPIO pin. PROCESSOR MEMORY MAP 0x FFFF FFFF - MEMORY ARCHITECTURE Reserved 0x 9000 0000 - Reserved 0x 7400 0000 - Static Memory Block 1 (8 KB) Reserved 0x 7000 2000 - The L1 memory domain also features a 8K byte data SRAM block which is ideal for storing local variables and the software stack. All L1 memory is protected by a multi-parity-bit concept, regardless of whether the memory is operating in SRAM or cache mode. Outside of the L1 domain, L2 and L3 memories are arranged using a Von Neumann topology. The L2 memory domain is a unified instruction and data memory and can hold any mixture of code and data required by the system design. The L2 memory domain is accessible by the Blackfin+ core through a dedicated 64-bit interface. It operates at SYSCLK frequency. The processor features up to 1M byte of L2 SRAM, which is ECC-protected and organized in eight banks. Individual banks can be made private to any system master. There is also a 512K byte single-bank ROM in the L2 domain. It contains boot code, security code, and general-purpose ROM space. Reserved 0x 4800 0000 SPI2 Memory (128 MB) 0x 4000 0000 Reserved 0x 3800 0500 0x 3800 0000 - Reserved 0x 2030 1000 0x 2030 0000 0x 2000 0000 0x 1FC0 0000 - Rev. D | Page 7 of 114 Core MMR Registers (4 MB) Reserved 0x 11B0 0000 0x 11A1 0000 0x 11A0 C000 0x 11A0 0000 0x 1190 8000 0x 1190 4000 0x 1190 0000 - L1 Data Block C (8 KB) Reserved L1 Instruction SRAM/Cache (16 KB) L1 Instruction SRAM (48 KB) Reserved L1 Data Block B SRAM/Cache (16 KB) L1 Data Block B SRAM (16 KB) Reserved 0x 1180 8000 0x 1180 4000 0x 1180 0000 - L1 Data Block A SRAM/Cache (16 KB) L1 Data Block A SRAM (16 KB) Reserved 0x 0810 0000 L2 SRAM (1024 KB) 0x 0800 0000 Reserved 0x 0408 0000 - 0x 0400 0000 - The processor features 1 kB of one-time-programmable (OTP) memory, which is memory-map accessible. This memory stores a unique chip identification and is used to support secure-boot and secure operation. STM Memory (4 KB) System MMR Registers (3 MB) 0x 11B0 2000 - 0x 0401 0000 - OTP Memory OTP Memory (1 KB) INTERNAL MEMORY The core has its own private L1 memory. The modified Harvard architecture supports two concurrent 32-bit data accesses along with an instruction fetch at full processor speed which provides high-bandwidth processor performance. In the core, a 64K byte block of data memory partners with an 64K byte memory block for instruction storage. Each data block is multibanked for efficient data exchange through DMA and can be configured as SRAM. Alternatively, 16K bytes of each block can be configured in L1 cache mode. The four-way set-associative instruction cache and the 2 two-way set-associative data caches greatly accelerate memory access performance, especially when accessing external memories. 0x 7000 0000 - L1 Instruction The L1 memory system is the highest-performance memory available to the Blackfin+ processor core. Static Memory Block 0 (8 KB) L1 Data Block B Internal (Core-Accessible) Memory Static Memory 0x 7400 2000 - EXTERNAL MEMORY DDR2 or LPDDR Memory (256 MB) 0x 8000 0000 - L1 Data Block A The processor views memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low-latency core-accessible memory as cache or SRAM, and larger, lower-cost and performance interface-accessible memory systems. See Figure 3. L2 ROM (448 KB) Boot ROM (64 KB) Reserved 0x 0000 0000 - Figure 3. ADSP-BF706/ADSP-BF707 Internal/External Memory Map | February 2019 ADSP-BF700/701/702/703/704/705/706/707 Static Memory Controller (SMC) The SMC can be programmed to control up to two blocks of external memories or memory-mapped devices, with very flexible timing parameters. Each block occupies a 8K byte segment regardless of the size of the device used. The following hardware-accelerated cryptographic ciphers are supported: • AES in ECB, CBC, ICM, and CTR modes with 128-, 192-, and 256-bit keys • DES in ECB and CBC mode with 56-bit key • 3DES in ECB and CBC mode with 3x 56-bit key Dynamic Memory Controller (DMC) The DMC includes a controller that supports JESD79-2E compatible double-data-rate (DDR2) SDRAM and JESD209A lowpower DDR (LPDDR) SDRAM devices. The DMC PHY features on-die termination on all data and data strobe pins that can be used during reads. The following hardware-accelerated hash functions are supported: • SHA-1 • SHA-2 with 224-bit and 256-bit digest • HMAC transforms for SHA-1 and SHA-2 I/O Memory Space The processor does not define a separate I/O space. All resources are mapped through the flat 32-bit address space. Onchip I/O devices have their control registers mapped into memory-mapped registers (MMRs) at addresses in a region of the 4G byte address space. These are separated into two smaller blocks, one which contains the control MMRs for all core functions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. The MMRs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals. Booting Public key accelerator is available to offload computation-intensive public key cryptography operations. Both a hardware-based nondeterministic random number generator and pseudo-random number generator are available. The TRNG also provides HW post-processing to meet NIST requirements of FIPS 140-2, while the PRNG is ANSI X9.31 compliant. Secure boot is also available with 224-bit elliptic curve digital signatures ensuring integrity and authenticity of the boot stream. Optionally, confidentiality is also ensured through AES128 encryption. The processor has several mechanisms for automatically loading internal and external memory after a reset. The boot mode is defined by the SYS_BMODE input pins dedicated for this purpose. There are two categories of boot modes. In master boot mode, the processor actively loads data from serial memories. In slave boot modes, the processor receives data from external host devices. The boot modes are shown in Table 2. These modes are implemented by the SYS_BMODE bits of the reset configuration register and are sampled during power-on resets and softwareinitiated resets. Table 2. Boot Modes SYS_BMODE Setting 00 01 10 11 CAUTION This product includes security features that can be used to protect embedded nonvolatile memory contents and prevent execution of unauthorized code. When security is enabled on this device (either by the ordering party or the subsequent receiving parties), the ability of Analog Devices to conduct failure analysis on returned devices is limited. Contact Analog Devices for details on the failure analysis limitations for this device. Secure debug is also employed to allow only trusted users to access the system with debug tools. SECURITY FEATURES DISCLAIMER Boot Mode No Boot/Idle SPI2 Master SPI2 Slave UART0 Slave SECURITY FEATURES The ADSP-BF70x processor supports standards-based hardware-accelerated encryption, decryption, authentication, and true random number generation. Rev. D | Page 8 of 114 To our knowledge, the Security Features, when used in accordance with the data sheet and hardware reference manual specifications, provide a secure method of implementing code and data safeguards. However, Analog Devices does not guarantee that this technology provides absolute security. ACCORDINGLY, ANALOG DEVICES HEREBY DISCLAIMS ANY AND ALL EXPRESS AND IMPLIED WARRANTIES THAT THE SECURITY FEATURES CANNOT BE BREACHED, COMPROMISED, OR OTHERWISE CIRCUMVENTED AND IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY LOSS, DAMAGE, DESTRUCTION, OR RELEASE OF DATA, INFORMATION, PHYSICAL PROPERTY, OR INTELLECTUAL PROPERTY. | February 2019 ADSP-BF700/701/702/703/704/705/706/707 PROCESSOR SAFETY FEATURES The ADSP-BF70x processor has been designed for functional safety applications. While the level of safety is mainly dominated by the system concept, the following primitives are provided by the devices to build a robust safety concept. Multi-Parity-Bit-Protected L1 Memories In the processor’s L1 memory space, whether SRAM or cache, each word is protected by multiple parity bits to detect the single event upsets that occur in all RAMs. This applies both to L1 instruction and data memory spaces. ECC-Protected L2 Memories Error correcting codes (ECC) are used to correct single event upsets. The L2 memory is protected with a single error correctdouble error detect (SEC-DED) code. By default ECC is enabled, but it can be disabled on a per-bank basis. Single-bit errors are transparently corrected. Dual-bit errors can issue a system event or fault if enabled. ECC protection is fully transparent to the user, even if L2 memory is read or written by 8-bit or 16-bit entities. CRC-Protected Memories Synonymously, the system memory protection unit (SMPU) provides memory protection against read and/or write transactions to defined regions of memory. There are two SMPU units in the ADSP-BF70x processors. One is for the L2 memory and the other is for the external DDR memory. The SMPU is also part of the security infrastructure. It allows the user to not only protect against arbitrary read and/or write transactions, but it also allows regions of memory to be defined as secure and prevent non-secure masters from accessing those memory regions. Watchpoint Protection The primary purpose of watchpoints and hardware breakpoints is to serve emulator needs. When enabled, they signal an emulator event whenever user-defined system resources are accessed or the core executes from user-defined addresses. Watchpoint events can be configured such that they signal the events to the fault management unit of the SEC. Watchdog The on-chip software watchdog timer can supervise the Blackfin+ core. Bandwidth Monitor While parity bit and ECC protection mainly protect against random soft errors in L1 and L2 memory cells, the CRC engines can be used to protect against systematic errors (pointer errors) and static content (instruction code) of L1, L2, and even L3 memories (DDR2, LPDDR). The processor features two CRC engines which are embedded in the memory-to-memory DMA controllers. CRC checksums can be calculated or compared on the fly during memory transfers, or one or multiple memory regions can be continuously scrubbed by a single DMA work unit as per DMA descriptor chain instructions. The CRC engine also protects data loaded during the boot process. Memory Protection The Blackfin+ core features a memory protection concept, which grants data and/or instruction accesses to enabled memory regions only. A supervisor mode vs. user mode programming model supports dynamically varying access rights. Increased flexibility in memory page size options supports a simple method of static memory partitioning. System Protection Memory-to-memory DMA channels are equipped with a bandwidth monitor mechanism. They can signal a system event or fault when transactions tend to starve because system buses are fully loaded with higher-priority traffic. Signal Watchdogs The eight general-purpose timers feature modes to monitor offchip signals. The watchdog period mode monitors whether external signals toggle with a period within an expected range. The watchdog width mode monitors whether the pulse widths of external signals are within an expected range. Both modes help to detect undesired toggling (or lack thereof) of  system-level signals. Up/Down Count Mismatch Detection The GP counter can monitor external signal pairs, such as request/grant strobes. If the edge count mismatch exceeds the expected range, the GP counter can flag this to the processor or to the fault management unit of the SEC. Fault Management The system protection unit (SPU) guards against accidental or unwanted access to the MMR space of a peripheral by providing a write-protection mechanism. The user is able to choose and configure the peripherals that are protected as well as configure which ones of the four system MMR masters (core, memory DMA, the SPI host port, and Coresight debug) the peripherals are guarded against. The SPU is also part of the security infrastructure. Along with providing write-protection functionality, the SPU is employed to define which resources in the system are secure or non-secure and to block access to secure resources from non-secure masters. Rev. D | Page 9 of 114 The fault management unit is part of the system event controller (SEC). Any system event, whether a dual-bit uncorrectable ECC error, or any peripheral status interrupt, can be defined as being a fault. Additionally, the system events can be defined as an interrupt to the core. If defined as such, the SEC forwards the event to the fault management unit, which may automatically reset the entire device for reboot, or simply toggle the  SYS_FAULT output pin to signal off-chip hardware. Optionally, the fault management unit can delay the action taken through a keyed sequence, to provide a final chance for the Blackfin+ core to resolve the issue and to prevent the fault action from being taken. | February 2019 ADSP-BF700/701/702/703/704/705/706/707 ADDITIONAL PROCESSOR PERIPHERALS The processor contains a rich set of peripherals connected to the core through several high-bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see the block diagram on Page 1). The processor contains high-speed serial and parallel ports, an interrupt controller for flexible management of interrupts from the on-chip peripherals or external sources, and power management control functions to tailor the performance and power characteristics of the processor and system to many application scenarios. The following sections describe additional peripherals that were not previously described. Timers The processor includes several timers which are described in the following sections. General-Purpose Timers There is one GP timer unit, and it provides eight general-purpose programmable timers. Each timer has an external pin that can be configured either as a pulse width modulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchronized to an external clock input on the TIMER_TMRx pins, an external TIMER_CLK input pin, or to the internal SCLK0. These timer units can be used in conjunction with the UARTs and the CAN controller to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels. The GP timers can generate interrupts to the processor core, providing periodic events for synchronization to either the system clock or to external signals. Timer events can also trigger other peripherals through the TRU (for instance, to signal a fault). Each timer may also be started and/or stopped by any TRU master without core intervention. Core Timer The processor core also has its own dedicated timer. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generating periodic operating system interrupts. Watchdog Timer The core includes a 32-bit timer, which may be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known state, through generation of a hardware reset, nonmaskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts down to zero from the programmed value. This protects the system from remaining in an unknown state where software that would normally reset the timer has stopped running due to an external noise condition or software error. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in its timer control register that is set only upon a watchdog-generated reset. Serial Ports (SPORTs) Two synchronous serial ports (comprised of four half-SPORTs) provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as Analog Devices’ audio codecs, ADCs, and DACs. Each half-SPORT is made up of two data lines, a clock, and frame sync. The data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel. Serial port data can be automatically transferred to and from on-chip memory/external memory through dedicated DMA channels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. In this configuration, one SPORT provides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared. Serial ports operate in six modes: • Standard DSP serial mode • Multichannel (TDM) mode • I2S mode • Packed I2S mode • Left-justified mode • Right-justified mode General-Purpose Counters A 32-bit counter is provided that can operate in general-purpose up/down count modes and can sense 2-bit quadrature or binary codes as typically emitted by industrial drives or manual thumbwheels. Count direction is either controlled by a levelsensitive input pin or by two edge detectors. A third counter input can provide flexible zero marker support and can alternatively be used to input the push-button signal of thumbwheel devices. All three pins have a programmable debouncing circuit. Internal signals forwarded to a GP timer enable this timer to measure the intervals between count events. Boundary registers enable auto-zero operation or simple system warning by interrupts when programmed count values are exceeded. Parallel Peripheral Interface (PPI) The processor provides a parallel peripheral interface (PPI) that supports data widths up to 18 bits. The PPI supports direct connection to TFT LCD panels, parallel analog-to-digital and digital-to-analog converters, video encoders and decoders, image sensor modules, and other general-purpose peripherals. Rev. D | Page 10 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 The following features are supported in the PPI module: • Programmable data length: 8 bits, 10 bits, 12 bits, 14 bits, 16 bits, and 18 bits per clock. memory-mapped resources of the processor through a SPI SRAM/FLASH style protocol. The following features are included: • Various framed, non-framed, and general-purpose operating modes. Frame syncs can be generated internally or can be supplied by an external device. • Direct read/write of memory and memory-mapped registers • ITU-656 status word error detection and correction for ITU-656 receive modes and ITU-656 preamble and status word decode. • Support for SPI controllers that implement hardwarebased SPI memory protocol • Optional packing and unpacking of data to/from 32 bits from/to 8 bits, 16 bits and 24 bits. If packing/unpacking is enabled, endianness can be configured to change the order of packing/unpacking of bytes/words. • Support for pre-fetch for faster reads • Error capture and reporting for protocol errors, bus errors, and over/underflow UART Ports Serial Peripheral Interface (SPI) Ports The processor provides two full-duplex universal asynchronous receiver/transmitter (UART) ports, which are fully compatible with PC-standard UARTs. Each UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. A UART port includes support for five to eight data bits, and none, even, or odd parity. Optionally, an additional address bit can be transferred to interrupt only addressed nodes in multi-drop bus (MDB) systems. A frame is terminated by a configurable number of stop bits. The processors have three industry-standard SPI-compatible ports that allow it to communicate with multiple SPI-compatible devices. The UART ports support automatic hardware flow control through the clear to send (CTS) input and request to send (RTS) output with programmable assertion FIFO levels. The baseline SPI peripheral is a synchronous, four-wire interface consisting of two data pins, one device select pin, and a gated clock pin. The two data pins allow full-duplex operation to other SPI-compatible devices. An additional two (optional) data pins are provided to support quad SPI operation. Enhanced modes of operation such as flow control, fast mode, and dual I/O mode (DIOM) are also supported. In addition, a direct memory access (DMA) mode allows for transferring several words with minimal CPU interaction. To help support the local interconnect network (LIN) protocols, a special command causes the transmitter to queue a break command of programmable bit length into the transmit buffer. Similarly, the number of stop bits can be extended by a programmable inter-frame space. With a range of configurable options, the SPI ports provide a glueless hardware interface with other SPI-compatible devices in master mode, slave mode, and multimaster environments. The SPI peripheral includes programmable baud rates, clock phase, and clock polarity. The peripheral can operate in a multimaster environment by interfacing with several other devices, acting as either a master device or a slave device. In a multimaster environment, the SPI peripheral uses open-drain outputs to avoid data bus contention. The flow control features enable slow slave devices to interface with fast master devices by providing an SPI Ready pin which flexibly controls the transfers. 2-Wire Controller Interface (TWI) The SPI port’s baud rate and clock phase/polarities are programmable, and it has integrated DMA channels for both transmit and receive data streams. Additionally, the TWI module is fully compatible with serial camera control bus (SCCB) functionality for easier control of various CMOS camera sensor devices. • RGB888 can be converted to RGB666 or RGB565 for transmit modes. • Various de-interleaving/interleaving modes for receiving/transmitting 4:2:2 YCrCb data. • Configurable LCD data enable (DEN) output available on Frame Sync 3. The capabilities of the UARTs are further extended with support for the Infrared Data Association (IrDA®) serial infrared physical layer link specification (SIR) protocol. The processor includes a 2-wire interface (TWI) module for providing a simple exchange method of control data between multiple devices. The TWI module is compatible with the widely used I2C bus standard. The TWI module offers the capabilities of simultaneous master and slave operation and support for both 7-bit addressing and multimedia data arbitration. The TWI interface utilizes two pins for transferring clock (TWI_SCL) and data (TWI_SDA) and supports the protocol at speeds up to 400k bits/sec. The TWI interface pins are compatible with 5 V logic levels. SPI Host Port (SPIHP) The processor includes one SPI host port which may be used in conjunction with any available SPI port to enhance its SPI slave mode capabilities. The SPIHP allows a SPI host device access to Rev. D | Page 11 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 Mobile Storage Interface (MSI) The mobile storage interface (MSI) controller acts as the host interface for multimedia cards (MMC), secure digital memory cards (SD), and secure digital input/output cards (SDIO). The following list describes the main features of the MSI controller: The USB clock is provided through a dedicated external crystal or crystal oscillator. The USB OTG dual-role device controller includes a phase locked loop with programmable multipliers to generate the necessary internal clocking frequency for USB. • Support for a single MMC, SD memory, and SDIO card Housekeeping ADC (HADC) • Support for 1-bit and 4-bit SD modes The HADC provides a general-purpose, multichannel successive approximation analog-to-digital converter. It supports the following features: • Support for 1-bit, 4-bit, and 8-bit MMC modes • Support for eMMC 4.5 embedded NAND flash devices • Support for power management and clock control • An eleven-signal external interface with clock, command, optional interrupt, and up to eight data lines • Card interface clock generation from SCLK0 or SCLK1 • SDIO interrupt and read wait features • 12-bit ADC core with built-in sample and hold • 4 single-ended input channels • Throughput rates up to 1 MSPS • Single external reference with analog inputs between 0 V and 3.3 V • Selectable ADC clock frequency including the ability to program a prescaler Controller Area Network (CAN) A CAN controller implements the CAN 2.0B (active) protocol. This protocol is an asynchronous communications protocol used in both industrial and automotive control systems. The CAN protocol is well suited for control applications due to its capability to communicate reliably over a network. This is because the protocol incorporates CRC checking, message error tracking, and fault node confinement. The CAN controller offers the following features: • 32 mailboxes (8 receive only, 8 transmit only, 16 configurable for receive or transmit) • Dedicated acceptance masks for each mailbox • Additional data filtering on first two bytes • Support for both the standard (11-bit) and extended (29-bit) identifier (ID) message formats • Support for remote frames • Active or passive network support • Adaptable conversion type: allows single or continuous conversion with option of autoscan • Auto sequencing capability with up to 4 autoconversions in a single session. Each conversion can be programmed to select any input channel. • Four data registers (individually addressable) to store conversion values System Crossbars (SCB) The system crossbars (SCB) are the fundamental building blocks of a switch-fabric style for (on-chip) system bus interconnection. The SCBs connect system bus masters to system bus slaves, providing concurrent data transfer between multiple bus masters and multiple bus slaves. A hierarchical model— built from multiple SCBs—provides a power and area efficient system interconnect, which satisfies the performance and flexibility requirements of a specific system. The SCBs provide the following features: • CAN wake-up from hibernation mode (lowest static power consumption mode) • Interrupts, including: TX complete, RX complete, error and global An additional crystal is not required to supply the CAN clock, as the CAN clock is derived from a system clock through a programmable divider. USB 2.0 On-the-Go Dual-Role Device Controller The USB 2.0 on-the-go (OTG) dual-role device controller provides a low-cost connectivity solution for the growing adoption of this bus standard in industrial applications, as well as consumer mobile devices such as cell phones, digital still cameras, and MP3 players. The USB 2.0 controller allows these devices to transfer data using a point-to-point USB connection without the need for a PC host. The module can operate in a traditional USB peripheral-only mode as well as the host mode presented in the OTG supplement to the USB 2.0 specification. • Highly efficient, pipelined bus transfer protocol for sustained throughput • Full-duplex bus operation for flexibility and reduced latency • Concurrent bus transfer support to allow multiple bus masters to access bus slaves simultaneously • Protection model (privileged/secure) support for selective bus interconnect protection POWER AND CLOCK MANAGEMENT The processor provides three operating modes, each with a different performance/power profile. Control of clocking to each of the processor peripherals also reduces power consumption. See Table 5 for a summary of the power settings for each mode. Rev. D | Page 12 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 System Crystal Oscillator and USB Crystal Oscillator Real-Time Clock The processor can be clocked by an external crystal (see Figure 4), a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. If an external clock is used, it should be a TTL compatible signal and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is connected to the SYS_CLKIN pin of the processor. When an external clock is used, the SYS_XTAL pin must be left unconnected. Alternatively, because the processor includes an on-chip oscillator circuit, an external crystal may be used. The real-time clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.768 kHz crystal external to the processor. Connect RTC pins RTC_CLKIN and RTC_XTAL with external components as shown in Figure 5. For fundamental frequency operation, use the circuit shown in Figure 4. A parallel-resonant, fundamental frequency, microprocessor grade crystal is connected across the SYS_CLKIN and SYS_XTAL pins. The on-chip resistance between SYS_CLKIN and the SYS_XTAL pin is in the 500 kΩ range. Further parallel resistors are typically not recommended. The RTC peripheral has dedicated power supply pins so that it can remain powered up and clocked even when the rest of the processor is in a low power state. The RTC provides several programmable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm time. RTC_CLKIN 0ȍ The two capacitors and the series resistor shown in Figure 4 fine-tune phase and amplitude of the sine frequency. The capacitor and resistor values shown in Figure 4 are typical values only. The capacitor values are dependent upon the load capacitance recommendations of the crystal manufacturer and the PCB physical layout. The resistor value depends on the drive level specified by the crystal manufacturer. The user should verify the customized values based on careful investigations on multiple devices over the required temperature range. BLACKFIN ȍ SYS_XTAL ȍ * 18 pF* X1 NOTE: CRYSTAL LOAD CAPACITORS ARE NOT NECESSARY IN MOST CASES. Figure 5. External Components for RTC The 32.768 kHz input clock frequency is divided down to a 1 Hz signal by a prescaler. The counter function of the timer consists of four counters: a 60-second counter, a 60-minute counter, a 24-hour counter, and a 32,768-day counter. When the alarm interrupt is enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. There are two alarms. The first alarm is for a time of day. The second alarm is for a specific day and time of that day. TO PLL CIRCUITRY SYS_CLKIN RTC_XTAL R1 FOR OVERTONE OPERATION ONLY: 18 pF* The stopwatch function counts down from a programmed value, with one-second resolution. When the stopwatch interrupt is enabled and the counter underflows, an interrupt is generated. Clock Generation NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING ON THE CRYSTAL AND LAYOUT. ANALYZE CAREFULLY. FOR FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE OF 18pF SHOULD BE TREATED AS A MAXIMUM. Figure 4. External Crystal Connection A third-overtone crystal can be used for frequencies above  25 MHz. The circuit is then modified to ensure crystal operation only at the third overtone by adding a tuned inductor circuit as shown in Figure 4. A design procedure for third-overtone operation is discussed in detail in application note (EE-168) Using Third Overtone Crystals with the ADSP-218x DSP (www.analog.com/ee-168). The clock generation unit (CGU) generates all on-chip clocks and synchronization signals. Multiplication factors are programmed to define the PLLCLK frequency. Programmable values divide the PLLCLK frequency to generate the core clock (CCLK), the system clocks (SYSCLK, SCLK0, and SCLK1), the LPDDR or DDR2 clock (DCLK), and the output clock (OCLK). Writing to the CGU control registers does not affect the behavior of the PLL immediately. Registers are first programmed with a new value, and the PLL logic executes the changes so that it transitions smoothly from the current conditions to the new ones. The same recommendations may be used for the USB crystal oscillator. Rev. D | Page 13 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 SYS_CLKIN oscillations start when power is applied to the VDD_EXT pins. The rising edge of SYS_HWRST can be applied after all voltage supplies are within specifications, and SYS_CLKIN oscillations are stable. Clock Out/External Clock The SYS_CLKOUT output pin has programmable options to output divided-down versions of the on-chip clocks. By default, the SYS_CLKOUT pin drives a buffered version of the SYS_ CLKIN input. Clock generation faults (for example, PLL unlock) may trigger a reset by hardware. The clocks shown in Table 3 can be output on the SYS_CLKOUT pin. Table 3. Clock Dividers Divider (if Available on  Clock Source SYS_CLKOUT) CCLK (Core Clock) By 16 SYSCLK (System Clock) By 8 SCLK0 (System Clock, All Periph- By 1 erals not Covered by SCLK1) SCLK1 (System Clock for Crypto By 8 Engines and MDMA) DCLK (LPDDR/DDR2 Clock) By 8 OCLK (Output Clock) Programmable CLKBUF None, direct from SYS_CLKIN Power Management As shown in Table 4, the processor supports multiple power domains, which maximizes flexibility while maintaining compliance with industry standards and conventions. There are no sequencing requirements for the various power domains, but all domains must be powered according to the appropriate Specifications table for processor operating conditions; even if the feature/peripheral is not used. Table 4. Power Domains Power Domain All Internal Logic DDR2/LPDDR USB OTP Memory HADC RTC All Other I/O (Includes SYS, JTAG, and Ports Pins) VDD Range VDD_INT VDD_DMC VDD_USB VDD_OTP VDD_HADC VDD_RTC VDD_EXT The dynamic power management feature of the processor allows the processor’s core clock frequency (fCCLK) to be dynamically controlled. The power dissipated by a processor is largely a function of its clock frequency and the square of the operating voltage. For example, reducing the clock frequency by 25% results in a 25% reduction in dynamic power dissipation. Full-On Operating Mode—Maximum Performance In the full-on mode, the PLL is enabled and is not bypassed, providing capability for maximum operational frequency. This is the power-up default execution state in which maximum performance can be achieved. The processor core and all enabled peripherals run at full speed. Deep Sleep Operating Mode—Maximum Dynamic Power Savings The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core and to all synchronous peripherals. Asynchronous peripherals may still be running but cannot access internal resources or external memory. Table 5. Power Settings fSYSCLK, fDCLK, PLL fSCLK0, fSCLK1 Mode/State PLL Bypassed fCCLK Full On Enabled No Enabled Enabled Deep Sleep Disabled — Disabled Disabled Hibernate Disabled — Disabled Disabled Core Power On On Off Hibernate State—Maximum Static Power Savings The hibernate state maximizes static power savings by disabling the voltage and clocks to the processor core and to all of the peripherals. This setting signals the external voltage regulator supplying the VDD_INT pins to shut off using the SYS_ EXTWAKE signal, which provides the lowest static power dissipation. Any critical information stored internally (for example, memory contents, register contents, and other information) must be written to a nonvolatile storage device (or self-refreshed DRAM) prior to removing power if the processor state is to be preserved. Because the VDD_EXT pins can still be supplied in this mode, all of the external pins three-state, unless otherwise specified. This allows other devices that may be connected to the processor to still have power applied without drawing unwanted current. Reset Control Unit Reset is the initial state of the whole processor or the core and is the result of a hardware- or software-triggered event. In this state, all control registers are set to their default values and functional units are idle. Exiting a full system reset starts with the core being ready to boot. The reset control unit (RCU) controls how all the functional units enter and exit reset. Differences in functional requirements and clocking constraints define how reset signals are generated. Programs must guarantee that none of the reset functions puts the system into an undefined state or causes resources to stall. This is particularly important when the core is reset (programs must ensure that there is no pending system activity involving the core when it is being reset). See Table 5 for a summary of the power settings for each mode. Rev. D | Page 14 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 From a system perspective, reset is defined by both the reset target and the reset source described as follows in the following list. Target defined: • Hardware Reset—All functional units are set to their default states without exception. History is lost. • System Reset—All functional units except the RCU are set to their default states. • Core-only Reset—Affects the core only. The system software should guarantee that the core, while in reset state, is not accessed by any bus master. Source defined: • Hardware Reset—The SYS_HWRST input signal is asserted active (pulled down). • System Reset—May be triggered by software (writing to the RCU_CTL register) or by another functional unit such as the dynamic power management (DPM) unit (hibernate) or any of the system event controller (SEC), trigger routing unit (TRU), or emulator inputs. • Core-only Reset—Triggered by software. • Trigger request (peripheral). Voltage Regulation The processor requires an external voltage regulator to power the VDD_INT pins. To reduce standby power consumption, the external voltage regulator can be signaled through  SYS_EXTWAKE to remove power from the processor core. This signal is high-true for power-up and may be connected directly to the low-true shut-down input of many common regulators. While in the hibernate state, all external supply pins (VDD_ EXT, VDD_USB, and VDD_DMC) can still be powered, eliminating the need for external buffers. The external voltage regulator can be activated from this power down state by asserting the SYS_HWRST pin, which then initiates a boot sequence. SYS_EXTWAKE indicates a wake-up to the external voltage regulator. SYSTEM DEBUG The processor includes various features that allow for easy system debug. These are described in the following sections. System Watchpoint Unit The system watchpoint unit (SWU) is a single module which connects to a single system bus and provides for transaction monitoring. One SWU is attached to the bus going to each system slave. The SWU provides ports for all system bus address channel signals. Each SWU contains four match groups of registers with associated hardware. These four SWU match groups operate independently, but share common event (interrupt, trigger, and others) outputs. Rev. D | Page 15 of 114 Debug Access Port The debug access port (DAP) provides IEEE-1149.1 JTAG interface support through its JTAG debug and serial wire debug port (SWJ-DP). SWJ-DP is a combined JTAG-DP and SW-DP that enables either serial wire debug (SWD) or a JTAG emulator to be connected to a target. SWD signals share the same pins as JTAG. The DAP provides an optional instrumentation trace for both the core and system. It provides a trace stream that conforms to MIPI System Trace Protocol version 2 (STPv2). DEVELOPMENT TOOLS Analog Devices supports its processors with a complete line of software and hardware development tools, including integrated development environments (CrossCore® Embedded Studio), evaluation products, emulators, and a wide variety of software add-ins. Integrated Development Environments (IDEs) CrossCore Embedded Studio is based on the EclipseTM framework. Supporting most Analog Devices processor families, it is the IDE of choice for future processors, including multicore devices. CrossCore Embedded Studio seamlessly integrates available software add-ins to support real time operating systems, file systems, TCP/IP stacks, USB stacks, algorithmic software modules, and evaluation hardware board support packages. For more information, visit www.analog.com/cces. EZ-KIT Lite Evaluation Board For processor evaluation, Analog Devices provides a wide range of EZ-KIT Lite® evaluation boards. Including the processor and key peripherals, the evaluation board also supports on-chip emulation capabilities and other evaluation and development features. Also available are various EZ-Extenders®, which are daughter cards delivering additional specialized functionality, including audio and video processing. For more information, visit www.analog.com and search on “ezkit” or “ezextender”. EZ-KIT Lite Evaluation Kits For a cost-effective way to learn more about developing with Analog Devices processors, Analog Devices offer a range of EZKIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT Lite evaluation board, directions for downloading an evaluation version of the available IDE, a USB cable, and a power supply. The USB controller on the EZ-KIT Lite board connects to the USB port of the user’s PC, enabling the chosen IDE evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also supports in-circuit programming of the on-board Flash device to store user-specific boot code, enabling standalone operation. With the full version of CrossCore Embedded Studio installed (sold separately), engineers can develop software for supported EZ-KITs or any custom system utilizing supported Analog Devices processors. | February 2019 ADSP-BF700/701/702/703/704/705/706/707 ADSP-BF706 EZ-KIT Mini Designing an Emulator-Compatible DSP Board (Target) TM The ADSP-BF706 EZ-KIT Mini product (ADZS-BF706EZMini) contains the ADSP-BF706 processor and is shipped with all of the necessary hardware. Users can start their evaluation immediately. The EZ-KIT Mini product includes the standalone evaluation board and USB cable. The EZ-KIT Mini ships with an on-board debug agent. The evaluation board is designed to be used in conjunction with the CrossCore Embedded Studio (CCES) development tools to test capabilities of the ADSP-BF706 Blackfin processor. Blackfin Low Power Imaging Platform (BLIP) The Blackfin low power imaging platform (BLIP) integrates the ADSP-BF707 Blackfin processor and Analog Devices software code libraries. The code libraries are optimized to detect the presence and behavior of humans or vehicles in indoor and outdoor environments. The BLIP hardware platform is delivered preloaded with the occupancy software module. Software Add-Ins for CrossCore Embedded Studio Analog Devices offers software add-ins which seamlessly integrate with CrossCore Embedded Studio to extend its capabilities and reduce development time. Add-ins include board support packages for evaluation hardware, various middleware packages, and algorithmic modules. Documentation, help, configuration dialogs, and coding examples present in these add-ins are viewable through the CrossCore Embedded Studio IDE once the add-in is installed. For embedded system test and debug, Analog Devices provides a family of emulators. On each DAP-enabled processor, Analog Devices supplies an IEEE 1149.1 JTAG test access port (TAP), serial wire debug port (SWJ-DP), and trace capabilities.  In-circuit emulation is facilitated by use of the JTAG or SWD interface. The emulator accesses the processor’s internal features through the processor’s TAP, allowing the developer to load code, set breakpoints, and view variables, memory, and registers. The emulators require the target board to include a header(s) that supports connection of the processor’s DAP to the emulator for trace and debug. Analog Devices emulators actively drive JTG_TRST high. Third-party emulators may expect a pull-up on JTG_TRST and therefore will not drive JTG_TRST high. When using this type of third-party emulator JTG_TRST must still be driven low during power-up reset, but should subsequently be driven high externally before any emulation or boundary-scan operations. See Power-Up Reset Timing for more information on POR specifications. For more details on target board design issues including mechanical layout, single processor connections, signal buffering, signal termination, and emulator pod logic, contact the factory for more information. ADDITIONAL INFORMATION The following publications that describe the ADSP-BF70x processors can be accessed electronically on our website: Board Support Packages for Evaluation Hardware • ADSP-BF70x Blackfin+ Processor Hardware Reference Software support for the EZ-KIT Lite evaluation boards and EZExtender daughter cards is provided by software add-ins called board support packages (BSPs). The BSPs contain the required drivers, pertinent release notes, and select example code for the given evaluation hardware. A download link for a specific BSP is located on the web page for the associated EZ-KIT or EZExtender product. The link is found in the Product Download area of the product web page. • ADSP-BF70x Blackfin+ Processor Programming Reference Middleware Packages Analog Devices separately offers middleware add-ins such as real time operating systems, file systems, USB stacks, and TCP/IP stacks. For more information, see the following web pages: • www.analog.com/ucos3 • www.analog.com/ucfs • www.analog.com/ucusbd • ADSP-BF70x Blackfin+ Processor Anomaly List RELATED SIGNAL CHAINS A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the www.analog.com website. The application signal chains page in the Circuits from the Lab® site (http:\\www.analog.com\circuits) provides: • www.analog.com/lwip Algorithmic Modules To speed development, Analog Devices offers add-ins that perform popular audio and video processing algorithms. These are available for use with CrossCore Embedded Studio. For more information, visit www.analog.com and search on “Blackfin software modules” or “SHARC software modules”. • Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications • Drill down links for components in each chain to selection guides and application information • Reference designs applying best practice design techniques Rev. D | Page 16 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 ADSP-BF70x DETAILED SIGNAL DESCRIPTIONS Table 6 provides a detailed description of each pin. Table 6. ADSP-BF70x Detailed Signal Descriptions Port Name CAN_RX CAN_TX CNT_DG Direction Input Output Input CNT_UD Input CNT_ZM Input DMC_Ann DMC_BAn Output Output DMC_CAS Output DMC_CK DMC_CK DMC_CKE DMC_CSn DMC_DQnn DMC_LDM Output Output Output Output I/O Output DMC_LDQS I/O DMC_LDQS DMC_ODT I/O Output DMC_RAS Output DMC_UDM Output DMC_UDQS I/O DMC_UDQS I/O DMC_VREF DMC_WE Input Output PPI_CLK PPI_Dnn PPI_FS1 PPI_FS2 PPI_FS3 HADC_VINn I/O I/O I/O I/O I/O Input Description Receive. Typically an external CAN transceiver’s RX output. Transmit. Typically an external CAN transceiver’s TX input. Count Down and Gate. Depending on the mode of operation this input acts either as a count down signal or a gate signal Count Down - This input causes the GP counter to decrement Gate - Stops the GP counter from incrementing or decrementing. Count Up and Direction. Depending on the mode of operation this input acts either as a count up signal or a direction signal Count Up - This input causes the GP counter to increment Direction - Selects whether the GP counter is incrementing or decrementing. Count Zero Marker. Input that connects to the zero marker output of a rotary device or detects the pressing of a pushbutton. Address n. Address bus. Bank Address Input n. Defines which internal bank an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied to on the dynamic memory. Also defines which mode registers (MR, EMR, EMR2, and/or EMR3) are loaded during the LOAD MODE REGISTER command. Column Address Strobe. Defines the operation for external dynamic memory to perform in conjunction with other DMC command signals. Connect to the CAS input of dynamic memory. Clock. Outputs DCLK to external dynamic memory. Clock (Complement). Complement of DMC_CK. Clock enable. Active high clock enables. Connects to the dynamic memory’s CKE input. Chip Select n. Commands are recognized by the memory only when this signal is asserted. Data n. Bidirectional Data bus. Data Mask for Lower Byte. Mask for DMC_DQ07:DMC_DQ00 write data when driven high. Sampled on both edges of the data strobe by the dynamic memory. Data Strobe for Lower Byte. DMC_DQ07:DMC_DQ00 data strobe. Output with Write Data. Input with Read Data. May be single-ended or differential depending on register settings. Data Strobe for Lower Byte (complement). Complement of LDQS. Not used in single-ended mode. On-die termination. Enables dynamic memory termination resistances when driven high (assuming the memory is properly configured). ODT is enabled/disabled regardless of read or write commands. Row Address Strobe. Defines the operation for external dynamic memory to perform in conjunction with other DMC command signals. Connect to the RAS input of dynamic memory. Data Mask for Upper Byte. Mask for DMC_DQ15:DMC_DQ08 write data when driven high. Sampled on both edges of the data strobe by the dynamic memory. Data Strobe for Upper Byte. DMC_DQ15:DMC_DQ08 data strobe. Output with Write Data. Input with Read Data. May be single-ended or differential depending on register settings. Data Strobe for Upper Byte (complement). Complement of DMC_UDQS. Not used in single-ended mode. Voltage Reference. Connect to half of the VDD_DMC voltage. Applies to the DMC0_VREF pin. Write Enable. Defines the operation for external dynamic memory to perform in conjunction with other DMC command signals. Connect to the WE input of dynamic memory. Clock. Input in external clock mode, output in internal clock mode. Data n. Bidirectional data bus. Frame Sync 1 (HSYNC). Behavior depends on EPPI mode. See the EPPI HRM chapter for more details. Frame Sync 2 (VSYNC). Behavior depends on EPPI mode. See the EPPI HRM chapter for more details. Frame Sync 3 (FIELD). Behavior depends on EPPI mode. See the EPPI HRM chapter for more details. Analog Input at channel n. Analog voltage inputs for digital conversion. Rev. D | Page 17 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 Table 6. ADSP-BF70x Detailed Signal Descriptions (Continued) Port Name HADC_VREFN Direction Input HADC_VREFP Input MSI_CD MSI_CLK MSI_CMD MSI_Dn MSI_INT Input Output I/O I/O Input Px_nn I/O RTC_CLKIN RTC_XTAL Input Output SMC_ABEn Output SMC_AMSn SMC_AOE SMC_ARDY Output Output Input SMC_ARE SMC_AWE SMC_Ann SMC_Dnn SPI_CLK SPI_D2 SPI_D3 SPI_MISO Output Output Output I/O I/O I/O I/O I/O SPI_MOSI I/O SPI_RDY SPI_SELn SPI_SS I/O Output Input SPT_ACLK I/O SPT_AD0 I/O SPT_AD1 I/O SPT_AFS I/O SPT_ATDV Output Description Ground Reference for ADC. Connect to an external voltage reference that meets data sheet specifications. External Reference for ADC. Connect to an external voltage reference that meets data sheet specifications. Card Detect. Connects to a pull-up resistor and to the card detect output of an SD socket. Clock. The clock signal applied to the connected device from the MSI. Command. Used to send commands to and receive responses from the connected device. Data n. Bidirectional data bus. eSDIO Interrupt Input. Used only for eSDIO. Connects to an eSDIO card’s interrupt output. An interrupt may be sampled even when the MSI clock to the card is switched off. Position n. General purpose input/output. See the GP Ports chapter of the HRM for programming information. Crystal input/external oscillator connection. Connect to an external clock source or crystal. Crystal output. Drives an external crystal. Must be left unconnected if an external clock is driving RTC_CLKIN. Byte Enable n. Indicate whether the lower or upper byte of a memory is being accessed. When an asynchronous write is made to the upper byte of a 16-bit memory, SMC_ABE1=0 and SMC_ABE0=1. When an asynchronous write is made to the lower byte of a 16-bit memory, SMC_ABE1=1 and  SMC_ABE0=0. Memory Select n. Typically connects to the chip select of a memory device. Output Enable. Asserts at the beginning of the setup period of a read access. Asynchronous Ready. Flow control signal used by memory devices to indicate to the SMC when further transactions may proceed. Read Enable. Asserts at the beginning of a read access. Write Enable. Asserts for the duration of a write access period. Address n. Address bus. Data n. Bidirectional data bus. Clock. Input in slave mode, output in master mode. Data 2. Used to transfer serial data in Quad mode. Open-drain when ODM mode is enabled. Data 3. Used to transfer serial data in Quad mode. Open-drain when ODM mode is enabled. Master In, Slave Out. Used to transfer serial data. Operates in the same direction as SPI_MOSI in Dual and Quad modes. Open-drain when ODM mode is enabled. Master Out, Slave In. Used to transfer serial data. Operates in the same direction as SPI_MISO in Dual and Quad modes. Open-drain when ODM mode is enabled. Ready. Optional flow signal. Output in slave mode, input in master mode. Slave Select Output n. Used in Master mode to enable the desired slave. Slave Select Input. Slave mode - Acts as the slave select input. Master mode- Optionally serves as an error detection input for the SPI when there are multiple masters. Channel A Clock. Data and Frame Sync are driven/sampled with respect to this clock. This signal can be either internally or externally generated. Channel A Data 0. Primary bidirectional data I/O. This signal can be configured as an output to transmit serial data, or as an input to receive serial data. Channel A Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to transmit serial data, or as an input to receive serial data. Channel A Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either generated internally or externally. Channel A Transmit Data Valid. This signal is optional and only active when SPORT is configured in multichannel transmit mode. It is asserted during enabled slots. Rev. D | Page 18 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 Table 6. ADSP-BF70x Detailed Signal Descriptions (Continued) Port Name SPT_BCLK Direction I/O SPT_BD0 I/O SPT_BD1 I/O SPT_BFS I/O SPT_BTDV Output SYS_BMODEn SYS_CLKIN SYS_CLKOUT Input Input Output SYS_EXTWAKE Output SYS_FAULT I/O SYS_HWRST SYS_NMI SYS_RESOUT SYS_WAKEn SYS_XTAL Input Input Output Input Output JTG_SWCLK JTG_SWDIO JTG_SWO JTG_TCK JTG_TDI JTG_TDO JTG_TMS JTG_TRST TM_ACIn TM_ACLKn TM_CLK TM_TMRn TRACE_CLK TRACE_Dnn TWI_SCL TWI_SDA UART_CTS UART_RTS UART_RX Input I/O Output Input Input Output Input Input Input Input Input I/O Output Output I/O I/O Input Output Input UART_TX Output USB_CLKIN Input Description Channel B Clock. Data and Frame Sync are driven/sampled with respect to this clock. This signal can be either internally or externally generated. Channel B Data 0. Primary bidirectional data I/O. This signal can be configured as an output to transmit serial data, or as an input to receive serial data. Channel B Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to transmit serial data, or as an input to receive serial data. Channel B Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either generated internally or externally. Channel B Transmit Data Valid. This signal is optional and only active when SPORT is configured in multi-channel transmit mode. It is asserted during enabled slots. Boot Mode Control n. Selects the boot mode of the processor. Clock/Crystal Input. Connect to an external clock source or crystal. Processor Clock Output. Outputs internal clocks. Clocks may be divided down. See the CGU chapter of the HRM for more details. External Wake Control. Drives low during hibernate and high all other times. Typically connected to the enable input of the voltage regulator controlling the VDD_INT supply. Active-Low Fault Output. Indicates internal faults or senses external faults depending on the operating mode. Processor Hardware Reset Control. Resets the device when asserted. Non-maskable Interrupt. See the processor hardware and programming references for more details. Reset Output. Indicates that the device is in the reset or hibernate state. Power Saving Mode Wakeup n. Wake-up source input for deep sleep and/or hibernate mode. Crystal Output. Drives an external crystal. Must be left unconnected if an external clock is driving CLKIN. Serial Wire Clock. Clocks data into and out of the target during debug. Serial Wire DIO. Sends and receives serial data to and from the target during debug. Serial Wire Out. Provides trace data to the emulator. JTAG Clock. JTAG test access port clock. JTAG Serial Data In. JTAG test access port data input. JTAG Serial Data Out. JTAG test access port data output. JTAG Mode Select. JTAG test access port mode select. JTAG Reset. JTAG test access port reset. Alternate Capture Input n. Provides an additional input for WIDCAP, WATCHDOG, and PININT modes. Alternate Clock n. Provides an additional time base for use by an individual timer. Clock. Provides an additional global time base for use by all the GP timers. Timer n. The main input/output signal for each timer. Trace Clock. Clock output. Trace Data n. Unidirectional data bus. Serial Clock. Clock output when master, clock input when slave. Serial Data. Receives or transmits data. Clear to Send. Flow control signal. Request to Send. Flow control signal. Receive. Receive input. Typically connects to a transceiver that meets the electrical requirements of the device being communicated with. Transmit. Transmit output. Typically connects to a transceiver that meets the electrical requirements of the device being communicated with. Clock/Crystal Input. This clock input is multiplied by a PLL to form the USB clock. See data sheet specifications for frequency/tolerance information. Rev. D | Page 19 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 Table 6. ADSP-BF70x Detailed Signal Descriptions (Continued) Port Name USB_DM USB_DP USB_ID Direction I/O I/O Input USB_VBC Output USB_VBUS USB_XTAL I/O Output Description Data –. Bidirectional differential data line. Data +. Bidirectional differential data line. OTG ID. Senses whether the controller is a host or device. This signal is pulled low when an A-type plug is sensed (signifying that the USB controller is the A device), but the input is high when a B-type plug is sensed (signifying that the USB controller is the B device). VBUS Control. Controls an external voltage source to supply VBUS when in host mode. May be configured as open-drain. Polarity is configurable as well. Bus Voltage. Connects to bus voltage in host and device modes. Crystal. Drives an external crystal. Must be left unconnected if an external clock is driving USB_CLKIN. Rev. D | Page 20 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 184-BALL CSP_BGA SIGNAL DESCRIPTIONS The processor’s pin definitions are shown in Table 7. The columns in this table provide the following information: • Signal Name: The Signal Name column in the table includes the signal name for every pin and (where applicable) the GPIO multiplexed pin function for every pin. • Description: The Description column in the table provides a verbose (descriptive) name for the signal. • General-Purpose Port: The Port column in the table shows whether or not the signal is multiplexed with other signals on a general-purpose I/O port pin. • Pin Name: The Pin Name column in the table identifies the name of the package pin (at power on reset) on which the signal is located (if a single function pin) or is multiplexed (if a general-purpose I/O pin). Table 7. ADSP-BF70x 184-Ball CSP_BGA Signal Descriptions Signal Name CAN0_RX CAN0_TX CAN1_RX CAN1_TX CNT0_DG CNT0_UD CNT0_ZM DMC0_A00 DMC0_A01 DMC0_A02 DMC0_A03 DMC0_A04 DMC0_A05 DMC0_A06 DMC0_A07 DMC0_A08 DMC0_A09 DMC0_A10 DMC0_A11 DMC0_A12 DMC0_A13 DMC0_BA0 DMC0_BA1 DMC0_BA2 DMC0_CAS DMC0_CK DMC0_CKE DMC0_CK DMC0_CS0 DMC0_DQ00 DMC0_DQ01 DMC0_DQ02 DMC0_DQ03 DMC0_DQ04 DMC0_DQ05 DMC0_DQ06 Description CAN0 Receive CAN0 Transmit CAN1 Receive CAN1 Transmit CNT0 Count Down and Gate CNT0 Count Up and Direction CNT0 Count Zero Marker DMC0 Address 0 DMC0 Address 1 DMC0 Address 2 DMC0 Address 3 DMC0 Address 4 DMC0 Address 5 DMC0 Address 6 DMC0 Address 7 DMC0 Address 8 DMC0 Address 9 DMC0 Address 10 DMC0 Address 11 DMC0 Address 12 DMC0 Address 13 DMC0 Bank Address Input 0 DMC0 Bank Address Input 1 DMC0 Bank Address Input 2 DMC0 Column Address Strobe DMC0 Clock DMC0 Clock enable DMC0 Clock (complement) DMC0 Chip Select 0 DMC0 Data 0 DMC0 Data 1 DMC0 Data 2 DMC0 Data 3 DMC0 Data 4 DMC0 Data 5 DMC0 Data 6 Rev. D Port C C A A A A A Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed | Page 21 of 114 | February 2019 Pin Name PC_02 PC_03 PA_12 PA_13 PA_07 PA_15 PA_13 DMC0_A00 DMC0_A01 DMC0_A02 DMC0_A03 DMC0_A04 DMC0_A05 DMC0_A06 DMC0_A07 DMC0_A08 DMC0_A09 DMC0_A10 DMC0_A11 DMC0_A12 DMC0_A13 DMC0_BA0 DMC0_BA1 DMC0_BA2 DMC0_CAS DMC0_CK DMC0_CKE DMC0_CK DMC0_CS0 DMC0_DQ00 DMC0_DQ01 DMC0_DQ02 DMC0_DQ03 DMC0_DQ04 DMC0_DQ05 DMC0_DQ06 ADSP-BF700/701/702/703/704/705/706/707 Table 7. ADSP-BF70x 184-Ball CSP_BGA Signal Descriptions (Continued) Signal Name DMC0_DQ07 DMC0_DQ08 DMC0_DQ09 DMC0_DQ10 DMC0_DQ11 DMC0_DQ12 DMC0_DQ13 DMC0_DQ14 DMC0_DQ15 DMC0_LDM DMC0_LDQS DMC0_LDQS DMC0_ODT DMC0_RAS DMC0_UDM DMC0_UDQS DMC0_UDQS DMC0_VREF DMC0_WE GND GND_HADC HADC0_VIN0 HADC0_VIN1 HADC0_VIN2 HADC0_VIN3 HADC0_VREFN HADC0_VREFP JTG_SWCLK JTG_SWDIO JTG_SWO JTG_TCK JTG_TDI JTG_TDO JTG_TMS JTG_TRST MSI0_CD MSI0_CLK MSI0_CMD MSI0_D0 MSI0_D1 MSI0_D2 MSI0_D3 MSI0_D4 MSI0_D5 MSI0_D6 MSI0_D7 Description DMC0 Data 7 DMC0 Data 8 DMC0 Data 9 DMC0 Data 10 DMC0 Data 11 DMC0 Data 12 DMC0 Data 13 DMC0 Data 14 DMC0 Data 15 DMC0 Data Mask for Lower Byte DMC0 Data Strobe for Lower Byte DMC0 Data Strobe for Lower Byte (complement) DMC0 On-die termination DMC0 Row Address Strobe DMC0 Data Mask for Upper Byte DMC0 Data Strobe for Upper Byte DMC0 Data Strobe for Upper Byte (complement) DMC0 Voltage Reference DMC0 Write Enable Ground Ground HADC HADC0 Analog Input at channel 0 HADC0 Analog Input at channel 1 HADC0 Analog Input at channel 2 HADC0 Analog Input at channel 3 HADC0 Ground Reference for ADC HADC0 External Reference for ADC TAPC0 Serial Wire Clock TAPC0 Serial Wire DIO TAPC0 Serial Wire Out TAPC0 JTAG Clock TAPC0 JTAG Serial Data In TAPC0 JTAG Serial Data Out TAPC0 JTAG Mode Select TAPC0 JTAG Reset MSI0 Card Detect MSI0 Clock MSI0 Command MSI0 Data 0 MSI0 Data 1 MSI0 Data 2 MSI0 Data 3 MSI0 Data 4 MSI0 Data 5 MSI0 Data 6 MSI0 Data 7 Rev. D | Page 22 of 114 | February 2019 Port Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed A C C C C C C C C C C Pin Name DMC0_DQ07 DMC0_DQ08 DMC0_DQ09 DMC0_DQ10 DMC0_DQ11 DMC0_DQ12 DMC0_DQ13 DMC0_DQ14 DMC0_DQ15 DMC0_LDM DMC0_LDQS DMC0_LDQS DMC0_ODT DMC0_RAS DMC0_UDM DMC0_UDQS DMC0_UDQS DMC0_VREF DMC0_WE GND GND_HADC HADC0_VIN0 HADC0_VIN1 HADC0_VIN2 HADC0_VIN3 HADC0_VREFN HADC0_VREFP JTG_TCK_SWCLK JTG_TMS_SWDIO JTG_TDO_SWO JTG_TCK_SWCLK JTG_TDI JTG_TDO_SWO JTG_TMS_SWDIO JTG_TRST PA_08 PC_09 PC_05 PC_08 PC_04 PC_07 PC_06 PC_10 PC_11 PC_12 PC_13 ADSP-BF700/701/702/703/704/705/706/707 Table 7. ADSP-BF70x 184-Ball CSP_BGA Signal Descriptions (Continued) Signal Name MSI0_INT PA_00-PA_15 PB_00-PB_15 PC_00-PC_14 PPI0_CLK PPI0_D00 PPI0_D01 PPI0_D02 PPI0_D03 PPI0_D04 PPI0_D05 PPI0_D06 PPI0_D07 PPI0_D08 PPI0_D09 PPI0_D10 PPI0_D11 PPI0_D12 PPI0_D13 PPI0_D14 PPI0_D15 PPI0_D16 PPI0_D17 PPI0_FS1 PPI0_FS2 PPI0_FS3 RTC0_CLKIN RTC0_XTAL SMC0_A01 SMC0_A02 SMC0_A03 SMC0_A04 SMC0_A05 SMC0_A06 SMC0_A07 SMC0_A08 SMC0_A09 SMC0_A10 SMC0_A11 SMC0_A12 SMC0_ABE0 SMC0_ABE1 SMC0_AMS0 SMC0_AMS1 SMC0_AOE SMC0_ARDY Description MSI0 eSDIO Interrupt Input Position 00 through Position 15 Position 00 through Position 15 Position 00 through Position 14 EPPI0 Clock EPPI0 Data 0 EPPI0 Data 1 EPPI0 Data 2 EPPI0 Data 3 EPPI0 Data 4 EPPI0 Data 5 EPPI0 Data 6 EPPI0 Data 7 EPPI0 Data 8 EPPI0 Data 9 EPPI0 Data 10 EPPI0 Data 11 EPPI0 Data 12 EPPI0 Data 13 EPPI0 Data 14 EPPI0 Data 15 EPPI0 Data 16 EPPI0 Data 17 EPPI0 Frame Sync 1 (HSYNC) EPPI0 Frame Sync 2 (VSYNC) EPPI0 Frame Sync 3 (FIELD) RTC0 Crystal input/external oscillator connection RTC0 Crystal output SMC0 Address 1 SMC0 Address 2 SMC0 Address 3 SMC0 Address 4 SMC0 Address 5 SMC0 Address 6 SMC0 Address 7 SMC0 Address 8 SMC0 Address 9 SMC0 Address 10 SMC0 Address 11 SMC0 Address 12 SMC0 Byte Enable 0 SMC0 Byte Enable 1 SMC0 Memory Select 0 SMC0 Memory Select 1 SMC0 Output Enable SMC0 Asynchronous Ready Rev. D | Page 23 of 114 Port C A B C A B B B B B B B B A A A A C C C C B B A A A Not Muxed Not Muxed A A A A A A A A C C C C A A A A A A | February 2019 Pin Name PC_14 PA_00-PA_15 PB_00-PB_15 PC_00-PC_14 PA_14 PB_07 PB_06 PB_05 PB_04 PB_03 PB_02 PB_01 PB_00 PA_11 PA_10 PA_09 PA_08 PC_03 PC_02 PC_01 PC_00 PB_08 PB_09 PA_12 PA_13 PA_15 RTC0_CLKIN RTC0_XTAL PA_08 PA_09 PA_10 PA_11 PA_07 PA_06 PA_05 PA_04 PC_01 PC_02 PC_03 PC_04 PA_00 PA_01 PA_15 PA_02 PA_12 PA_03 ADSP-BF700/701/702/703/704/705/706/707 Table 7. ADSP-BF70x 184-Ball CSP_BGA Signal Descriptions (Continued) Signal Name SMC0_ARE SMC0_AWE SMC0_D00 SMC0_D01 SMC0_D02 SMC0_D03 SMC0_D04 SMC0_D05 SMC0_D06 SMC0_D07 SMC0_D08 SMC0_D09 SMC0_D10 SMC0_D11 SMC0_D12 SMC0_D13 SMC0_D14 SMC0_D15 SPI0_CLK SPI0_CLK SPI0_D2 SPI0_D2 SPI0_D3 SPI0_D3 SPI0_MISO SPI0_MISO SPI0_MOSI SPI0_MOSI SPI0_RDY SPI0_SEL1 SPI0_SEL2 SPI0_SEL3 SPI0_SEL4 SPI0_SEL5 SPI0_SEL6 SPI0_SS SPI1_CLK SPI1_MISO SPI1_MOSI SPI1_RDY SPI1_SEL1 SPI1_SEL2 SPI1_SEL3 SPI1_SEL4 SPI1_SS SPI2_CLK Description SMC0 Read Enable SMC0 Write Enable SMC0 Data 0 SMC0 Data 1 SMC0 Data 2 SMC0 Data 3 SMC0 Data 4 SMC0 Data 5 SMC0 Data 6 SMC0 Data 7 SMC0 Data 8 SMC0 Data 9 SMC0 Data 10 SMC0 Data 11 SMC0 Data 12 SMC0 Data 13 SMC0 Data 14 SMC0 Data 15 SPI0 Clock SPI0 Clock SPI0 Data 2 SPI0 Data 2 SPI0 Data 3 SPI0 Data 3 SPI0 Master In, Slave Out SPI0 Master In, Slave Out SPI0 Master Out, Slave In SPI0 Master Out, Slave In SPI0 Ready SPI0 Slave Select Output 1 SPI0 Slave Select Output 2 SPI0 Slave Select Output 3 SPI0 Slave Select Output 4 SPI0 Slave Select Output 5 SPI0 Slave Select Output 6 SPI0 Slave Select Input SPI1 Clock SPI1 Master In, Slave Out SPI1 Master Out, Slave In SPI1 Ready SPI1 Slave Select Output 1 SPI1 Slave Select Output 2 SPI1 Slave Select Output 3 SPI1 Slave Select Output 4 SPI1 Slave Select Input SPI2 Clock Rev. D | Page 24 of 114 | February 2019 Port A A B B B B B B B B B B B B B B B B B C B C B C B C B C A A A C B B B A A A A A A A C A A B Pin Name PA_13 PA_14 PB_07 PB_06 PB_05 PB_04 PB_03 PB_02 PB_01 PB_00 PB_08 PB_09 PB_10 PB_11 PB_12 PB_13 PB_14 PB_15 PB_00 PC_04 PB_03 PC_08 PB_07 PC_09 PB_01 PC_06 PB_02 PC_07 PA_06 PA_05 PA_06 PC_11 PB_04 PB_05 PB_06 PA_05 PA_00 PA_01 PA_02 PA_03 PA_04 PA_03 PC_10 PA_14 PA_04 PB_10 ADSP-BF700/701/702/703/704/705/706/707 Table 7. ADSP-BF70x 184-Ball CSP_BGA Signal Descriptions (Continued) Signal Name SPI2_D2 SPI2_D3 SPI2_MISO SPI2_MOSI SPI2_RDY SPI2_SEL1 SPI2_SEL2 SPI2_SEL3 SPI2_SS SPT0_ACLK SPT0_ACLK SPT0_AD0 SPT0_AD0 SPT0_AD1 SPT0_AFS SPT0_AFS SPT0_ATDV SPT0_BCLK SPT0_BCLK SPT0_BD0 SPT0_BD0 SPT0_BD1 SPT0_BD1 SPT0_BFS SPT0_BFS SPT0_BTDV SPT1_ACLK SPT1_AD0 SPT1_AD1 SPT1_AFS SPT1_ATDV SPT1_BCLK SPT1_BCLK SPT1_BD0 SPT1_BD0 SPT1_BD1 SPT1_BD1 SPT1_BFS SPT1_BFS SPT1_BTDV SPT1_BTDV SYS_BMODE0 SYS_BMODE1 SYS_CLKIN SYS_CLKOUT SYS_EXTWAKE Description SPI2 Data 2 SPI2 Data 3 SPI2 Master In, Slave Out SPI2 Master Out, Slave In SPI2 Ready SPI2 Slave Select Output 1 SPI2 Slave Select Output 2 SPI2 Slave Select Output 3 SPI2 Slave Select Input SPORT0 Channel A Clock SPORT0 Channel A Clock SPORT0 Channel A Data 0 SPORT0 Channel A Data 0 SPORT0 Channel A Data 1 SPORT0 Channel A Frame Sync SPORT0 Channel A Frame Sync SPORT0 Channel A Transmit Data Valid SPORT0 Channel B Clock SPORT0 Channel B Clock SPORT0 Channel B Data 0 SPORT0 Channel B Data 0 SPORT0 Channel B Data 1 SPORT0 Channel B Data 1 SPORT0 Channel B Frame Sync SPORT0 Channel B Frame Sync SPORT0 Channel B Transmit Data Valid SPORT1 Channel A Clock SPORT1 Channel A Data 0 SPORT1 Channel A Data 1 SPORT1 Channel A Frame Sync SPORT1 Channel A Transmit Data Valid SPORT1 Channel B Clock SPORT1 Channel B Clock SPORT1 Channel B Data 0 SPORT1 Channel B Data 0 SPORT1 Channel B Data 1 SPORT1 Channel B Data 1 SPORT1 Channel B Frame Sync SPORT1 Channel B Frame Sync SPORT1 Channel B Transmit Data Valid SPORT1 Channel B Transmit Data Valid Boot Mode Control 0 Boot Mode Control 1 Clock/Crystal Input Processor Clock Output External Wake Control Rev. D | Page 25 of 114 Port B B B B A B B B B A C A C C A C A B C B C B C B C A A A A A A B C B C B C B C A C Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed | February 2019 Pin Name PB_13 PB_14 PB_11 PB_12 PA_04 PB_15 PB_08 PB_09 PB_15 PA_13 PC_09 PA_14 PC_08 PC_00 PA_12 PC_05 PA_15 PB_04 PC_04 PB_05 PC_06 PB_07 PC_01 PB_06 PC_07 PA_15 PA_08 PA_10 PA_11 PA_09 PA_07 PB_00 PC_10 PB_02 PC_12 PB_03 PC_13 PB_01 PC_11 PA_07 PC_14 SYS_BMODE0 SYS_BMODE1 SYS_CLKIN SYS_CLKOUT SYS_EXTWAKE ADSP-BF700/701/702/703/704/705/706/707 Table 7. ADSP-BF70x 184-Ball CSP_BGA Signal Descriptions (Continued) Signal Name SYS_FAULT SYS_HWRST SYS_NMI SYS_RESOUT SYS_WAKE0 SYS_WAKE1 SYS_WAKE2 SYS_WAKE3 SYS_WAKE4 SYS_XTAL TM0_ACI0 TM0_ACI1 TM0_ACI2 TM0_ACI3 TM0_ACI4 TM0_ACI5 TM0_ACI6 TM0_ACLK0 TM0_ACLK1 TM0_ACLK2 TM0_ACLK3 TM0_ACLK4 TM0_ACLK5 TM0_ACLK6 TM0_CLK TM0_TMR0 TM0_TMR1 TM0_TMR2 TM0_TMR3 TM0_TMR4 TM0_TMR5 TM0_TMR6 TM0_TMR7 TRACE0_CLK TRACE0_D00 TRACE0_D01 TRACE0_D02 TRACE0_D03 TRACE0_D04 TRACE0_D05 TRACE0_D06 TRACE0_D07 TWI0_SCL TWI0_SDA UART0_CTS UART0_RTS Description Active-Low Fault Output Processor Hardware Reset Control Nonmaskable Interrupt Reset Output Power Saving Mode Wake-up 0 Power Saving Mode Wake-up 1 Power Saving Mode Wake-up 2 Power Saving Mode Wake-up 3 Power Saving Mode Wake-up 4 Crystal Output TIMER0 Alternate Capture Input 0 TIMER0 Alternate Capture Input 1 TIMER0 Alternate Capture Input 2 TIMER0 Alternate Capture Input 3 TIMER0 Alternate Capture Input 4 TIMER0 Alternate Capture Input 5 TIMER0 Alternate Capture Input 6 TIMER0 Alternate Clock 0 TIMER0 Alternate Clock 1 TIMER0 Alternate Clock 2 TIMER0 Alternate Clock 3 TIMER0 Alternate Clock 4 TIMER0 Alternate Clock 5 TIMER0 Alternate Clock 6 TIMER0 Clock TIMER0 Timer 0 TIMER0 Timer 1 TIMER0 Timer 2 TIMER0 Timer 3 TIMER0 Timer 4 TIMER0 Timer 5 TIMER0 Timer 6 TIMER0 Timer 7 TPIU0 Trace Clock TPIU0 Trace Data 0 TPIU0 Trace Data 1 TPIU0 Trace Data 2 TPIU0 Trace Data 3 TPIU0 Trace Data 4 TPIU0 Trace Data 5 TPIU0 Trace Data 6 TPIU0 Trace Data 7 TWI0 Serial Clock TWI0 Serial Data UART0 Clear to Send UART0 Request to Send Rev. D | Page 26 of 114 | February 2019 Port Not Muxed Not Muxed Not Muxed Not Muxed B B B C A Not Muxed C B C B C C A C C C B B A B B A A A C A A A A B B B B B B A A A Not Muxed Not Muxed C C Pin Name SYS_FAULT SYS_HWRST SYS_NMI SYS_RESOUT PB_07 PB_08 PB_12 PC_02 PA_12 SYS_XTAL PC_03 PB_01 PC_07 PB_09 PC_01 PC_02 PA_12 PC_04 PC_10 PC_09 PB_00 PB_10 PA_14 PB_04 PB_06 PA_05 PA_06 PA_07 PC_05 PA_09 PA_10 PA_11 PA_04 PB_10 PB_15 PB_14 PB_13 PB_12 PB_11 PA_02 PA_01 PA_00 TWI0_SCL TWI0_SDA PC_03 PC_02 ADSP-BF700/701/702/703/704/705/706/707 Table 7. ADSP-BF70x 184-Ball CSP_BGA Signal Descriptions (Continued) Signal Name UART0_RX UART0_TX UART1_CTS UART1_RTS UART1_RX UART1_TX USB0_CLKIN USB0_DM USB0_DP USB0_ID USB0_VBC USB0_VBUS USB0_XTAL VDD_DMC VDD_EXT VDD_HADC VDD_INT VDD_OTP VDD_RTC VDD_USB Description UART0 Receive UART0 Transmit UART1 Clear to Send UART1 Request to Send UART1 Receive UART1 Transmit USB0 Clock/Crystal Input USB0 Data – USB0 Data + USB0 OTG ID USB0 VBUS Control USB0 Bus Voltage USB0 Crystal VDD for DMC External VDD VDD for HADC Internal VDD VDD for OTP VDD for RTC VDD for USB Port B B B B C C Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Rev. D | Page 27 of 114 | February 2019 Pin Name PB_09 PB_08 PB_14 PB_13 PC_01 PC_00 USB0_CLKIN USB0_DM USB0_DP USB0_ID USB0_VBC USB0_VBUS USB0_XTAL VDD_DMC VDD_EXT VDD_HADC VDD_INT VDD_OTP VDD_RTC VDD_USB ADSP-BF700/701/702/703/704/705/706/707 GPIO MULTIPLEXING FOR 184-BALL CSP_BGA Table 8 through Table 10 identify the pin functions that are multiplexed on the general-purpose I/O pins of the 184-ball CSP_BGA package. Table 8. Signal Multiplexing for Port A Signal Name PA_00 PA_01 PA_02 PA_03 PA_04 PA_05 PA_06 PA_07 PA_08 PA_09 PA_10 PA_11 PA_12 PA_13 PA_14 PA_15 Multiplexed Function 0 SPI1_CLK SPI1_MISO SPI1_MOSI SPI1_SEL2 SPI1_SEL1 TM0_TMR0 TM0_TMR1 TM0_TMR2 PPI0_D11 PPI0_D10 PPI0_D09 PPI0_D08 PPI0_FS1 PPI0_FS2 PPI0_CLK PPI0_FS3 Multiplexed Function 1 SPI1_RDY TM0_TMR7 SPI0_SEL1 SPI0_SEL2 SPT1_BTDV MSI0_CD TM0_TMR4 TM0_TMR5 TM0_TMR6 CAN1_RX CAN1_TX SPI1_SEL4 SPT0_ATDV Multiplexed Function 2 TRACE0_D07 TRACE0_D06 TRACE0_D05 SPI0_RDY SPT1_ATDV SPT1_ACLK SPT1_AFS SPT1_AD0 SPT1_AD1 SPT0_AFS SPT0_ACLK SPT0_AD0 SPT0_BTDV Multiplexed Function 3 SMC0_ABE0 SMC0_ABE1 SMC0_AMS1 SMC0_ARDY SMC0_A08 SMC0_A07 SMC0_A06 SMC0_A05 SMC0_A01 SMC0_A02 SMC0_A03 SMC0_A04 SMC0_AOE SMC0_ARE SMC0_AWE SMC0_AMS0 Multiplexed Function 2 SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_D2 SPI0_SEL4 SPI0_SEL5 SPI0_SEL6 SPI0_D3 SPI2_SEL2 SPI2_SEL3 TRACE0_CLK TRACE0_D04 TRACE0_D03 TRACE0_D02 TRACE0_D01 TRACE0_D00 Multiplexed Function 3 SMC0_D07 SMC0_D06 SMC0_D05 SMC0_D04 SMC0_D03 SMC0_D02 SMC0_D01 SMC0_D00 SMC0_D08 SMC0_D09 SMC0_D10 SMC0_D11 SMC0_D12 SMC0_D13 SMC0_D14 SMC0_D15 SPI2_RDY Multiplexed Function Input Tap SPI1_SS SPI0_SS CNT0_DG TM0_ACI6/SYS_WAKE4 CNT0_ZM TM0_ACLK5 CNT0_UD Table 9. Signal Multiplexing for Port B Signal Name PB_00 PB_01 PB_02 PB_03 PB_04 PB_05 PB_06 PB_07 PB_08 PB_09 PB_10 PB_11 PB_12 PB_13 PB_14 PB_15 Multiplexed Function 0 PPI0_D07 PPI0_D06 PPI0_D05 PPI0_D04 PPI0_D03 PPI0_D02 PPI0_D01 PPI0_D00 UART0_TX UART0_RX SPI2_CLK SPI2_MISO SPI2_MOSI SPI2_D2 SPI2_D3 SPI2_SEL1 Multiplexed Function 1 SPT1_BCLK SPT1_BFS SPT1_BD0 SPT1_BD1 SPT0_BCLK SPT0_BD0 SPT0_BFS SPT0_BD1 PPI0_D16 PPI0_D17 UART1_RTS UART1_CTS Rev. D | Page 28 of 114 | February 2019 Multiplexed Function Input Tap TM0_ACLK3 TM0_ACI1 TM0_ACLK6 TM0_CLK SYS_WAKE0 SYS_WAKE1 TM0_ACI3 TM0_ACLK4 SYS_WAKE2 SPI2_SS ADSP-BF700/701/702/703/704/705/706/707 Table 10. Signal Multiplexing for Port C Signal Name PC_00 PC_01 PC_02 PC_03 PC_04 PC_05 PC_06 PC_07 PC_08 PC_09 PC_10 PC_11 PC_12 PC_13 PC_14 Multiplexed Function 0 UART1_TX UART1_RX UART0_RTS UART0_CTS SPT0_BCLK SPT0_AFS SPT0_BD0 SPT0_BFS SPT0_AD0 SPT0_ACLK SPT1_BCLK SPT1_BFS SPT1_BD0 SPT1_BD1 SPT1_BTDV Multiplexed Function 1 SPT0_AD1 SPT0_BD1 CAN0_RX CAN0_TX SPI0_CLK TM0_TMR3 SPI0_MISO SPI0_MOSI SPI0_D2 SPI0_D3 MSI0_D4 MSI0_D5 MSI0_D6 MSI0_D7 MSI0_INT Rev. D Multiplexed Function 2 PPI0_D15 PPI0_D14 PPI0_D13 PPI0_D12 MSI0_D1 MSI0_CMD MSI0_D3 MSI0_D2 MSI0_D0 MSI0_CLK SPI1_SEL3 SPI0_SEL3 | Page 29 of 114 | February 2019 Multiplexed Function 3 Multiplexed Function Input Tap SMC0_A09 SMC0_A10 SMC0_A11 SMC0_A12 TM0_ACI4 TM0_ACI5/SYS_WAKE3 TM0_ACI0 TM0_ACLK0 TM0_ACI2 TM0_ACLK2 TM0_ACLK1 ADSP-BF700/701/702/703/704/705/706/707 12 mm × 12 mm 88-LEAD LFCSP (QFN) SIGNAL DESCRIPTIONS The processor’s pin definitions are shown in Table 11. The columns in this table provide the following information: • Signal Name: The Signal Name column in the table includes the signal name for every pin and (where applicable) the GPIO multiplexed pin function for every pin. • Description: The Description column in the table provides a verbose (descriptive) name for the signal. • General-Purpose Port: The Port column in the table shows whether or not the signal is multiplexed with other signals on a general-purpose I/O port pin. • Pin Name: The Pin Name column in the table identifies the name of the package pin (at power on reset) on which the signal is located (if a single function pin) or is multiplexed (if a general-purpose I/O pin). Table 11. ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions Signal Name CAN0_RX CAN0_TX CAN1_RX CAN1_TX CNT0_DG CNT0_UD CNT0_ZM GND JTG_SWCLK JTG_SWDIO JTG_SWO JTG_TCK JTG_TDI JTG_TDO JTG_TMS JTG_TRST MSI0_CD MSI0_CLK MSI0_CMD MSI0_D0 MSI0_D1 MSI0_D2 MSI0_D3 MSI0_D4 PA_00-PA_15 PB_00-PB_15 PC_00-PC_10 PPI0_CLK PPI0_D00 PPI0_D01 PPI0_D02 PPI0_D03 PPI0_D04 PPI0_D05 PPI0_D06 PPI0_D07 Description CAN0 Receive CAN0 Transmit CAN1 Receive CAN1 Transmit CNT0 Count Down and Gate CNT0 Count Up and Direction CNT0 Count Zero Marker Ground TAPC0 Serial Wire Clock TAPC0 Serial Wire DIO TAPC0 Serial Wire Out TAPC0 JTAG Clock TAPC0 JTAG Serial Data In TAPC0 JTAG Serial Data Out TAPC0 JTAG Mode Select TAPC0 JTAG Reset MSI0 Card Detect MSI0 Clock MSI0 Command MSI0 Data 0 MSI0 Data 1 MSI0 Data 2 MSI0 Data 3 MSI0 Data 4 Position 00 through Position 15 Position 00 through Position 15 Position 00 through Position 10 EPPI0 Clock EPPI0 Data 0 EPPI0 Data 1 EPPI0 Data 2 EPPI0 Data 3 EPPI0 Data 4 EPPI0 Data 5 EPPI0 Data 6 EPPI0 Data 7 Rev. D | Page 30 of 114 | February 2019 Port C C A A A A A Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed A C C C C C C C A B C A B B B B B B B B Pin Name PC_02 PC_03 PA_12 PA_13 PA_07 PA_15 PA_13 GND JTG_TCK_SWCLK JTG_TMS_SWDIO JTG_TDO_SWO JTG_TCK_SWCLK JTG_TDI JTG_TDO_SWO JTG_TMS_SWDIO JTG_TRST PA_08 PC_09 PC_05 PC_08 PC_04 PC_07 PC_06 PC_10 PA_00-PA_15 PB_00-PB_15 PC_00-PC_10 PA_14 PB_07 PB_06 PB_05 PB_04 PB_03 PB_02 PB_01 PB_00 ADSP-BF700/701/702/703/704/705/706/707 Table 11. ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions (Continued) Signal Name PPI0_D08 PPI0_D09 PPI0_D10 PPI0_D11 PPI0_D12 PPI0_D13 PPI0_D14 PPI0_D15 PPI0_D16 PPI0_D17 PPI0_FS1 PPI0_FS2 PPI0_FS3 RTC0_CLKIN RTC0_XTAL SMC0_A01 SMC0_A02 SMC0_A03 SMC0_A04 SMC0_A05 SMC0_A06 SMC0_A07 SMC0_A08 SMC0_A09 SMC0_A10 SMC0_A11 SMC0_A12 SMC0_ABE0 SMC0_ABE1 SMC0_AMS0 SMC0_AMS1 SMC0_AOE SMC0_ARDY SMC0_ARE SMC0_AWE SMC0_D00 SMC0_D01 SMC0_D02 SMC0_D03 SMC0_D04 SMC0_D05 SMC0_D06 SMC0_D07 SMC0_D08 SMC0_D09 SMC0_D10 Description EPPI0 Data 8 EPPI0 Data 9 EPPI0 Data 10 EPPI0 Data 11 EPPI0 Data 12 EPPI0 Data 13 EPPI0 Data 14 EPPI0 Data 15 EPPI0 Data 16 EPPI0 Data 17 EPPI0 Frame Sync 1 (HSYNC) EPPI0 Frame Sync 2 (VSYNC) EPPI0 Frame Sync 3 (FIELD) RTC0 Crystal input/external oscillator connection RTC0 Crystal output SMC0 Address 1 SMC0 Address 2 SMC0 Address 3 SMC0 Address 4 SMC0 Address 5 SMC0 Address 6 SMC0 Address 7 SMC0 Address 8 SMC0 Address 9 SMC0 Address 10 SMC0 Address 11 SMC0 Address 12 SMC0 Byte Enable 0 SMC0 Byte Enable 1 SMC0 Memory Select 0 SMC0 Memory Select 1 SMC0 Output Enable SMC0 Asynchronous Ready SMC0 Read Enable SMC0 Write Enable SMC0 Data 0 SMC0 Data 1 SMC0 Data 2 SMC0 Data 3 SMC0 Data 4 SMC0 Data 5 SMC0 Data 6 SMC0 Data 7 SMC0 Data 8 SMC0 Data 9 SMC0 Data 10 Rev. D | Page 31 of 114 Port A A A A C C C C B B A A A Not Muxed Not Muxed A A A A A A A A C C C C A A A A A A A A B B B B B B B B B B B | February 2019 Pin Name PA_11 PA_10 PA_09 PA_08 PC_03 PC_02 PC_01 PC_00 PB_08 PB_09 PA_12 PA_13 PA_15 RTC0_CLKIN RTC0_XTAL PA_08 PA_09 PA_10 PA_11 PA_07 PA_06 PA_05 PA_04 PC_01 PC_02 PC_03 PC_04 PA_00 PA_01 PA_15 PA_02 PA_12 PA_03 PA_13 PA_14 PB_07 PB_06 PB_05 PB_04 PB_03 PB_02 PB_01 PB_00 PB_08 PB_09 PB_10 ADSP-BF700/701/702/703/704/705/706/707 Table 11. ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions (Continued) Signal Name SMC0_D11 SMC0_D12 SMC0_D13 SMC0_D14 SMC0_D15 SPI0_CLK SPI0_CLK SPI0_D2 SPI0_D2 SPI0_D3 SPI0_D3 SPI0_MISO SPI0_MISO SPI0_MOSI SPI0_MOSI SPI0_RDY SPI0_SEL1 SPI0_SEL2 SPI0_SEL4 SPI0_SEL5 SPI0_SEL6 SPI0_SS SPI1_CLK SPI1_MISO SPI1_MOSI SPI1_RDY SPI1_SEL1 SPI1_SEL2 SPI1_SEL3 SPI1_SEL4 SPI1_SS SPI2_CLK SPI2_D2 SPI2_D3 SPI2_MISO SPI2_MOSI SPI2_RDY SPI2_SEL1 SPI2_SEL2 SPI2_SEL3 SPI2_SS SPT0_ACLK SPT0_ACLK SPT0_AD0 SPT0_AD0 SPT0_AD1 Description SMC0 Data 11 SMC0 Data 12 SMC0 Data 13 SMC0 Data 14 SMC0 Data 15 SPI0 Clock SPI0 Clock SPI0 Data 2 SPI0 Data 2 SPI0 Data 3 SPI0 Data 3 SPI0 Master In, Slave Out SPI0 Master In, Slave Out SPI0 Master Out, Slave In SPI0 Master Out, Slave In SPI0 Ready SPI0 Slave Select Output 1 SPI0 Slave Select Output 2 SPI0 Slave Select Output 4 SPI0 Slave Select Output 5 SPI0 Slave Select Output 6 SPI0 Slave Select Input SPI1 Clock SPI1 Master In, Slave Out SPI1 Master Out, Slave In SPI1 Ready SPI1 Slave Select Output 1 SPI1 Slave Select Output 2 SPI1 Slave Select Output 3 SPI1 Slave Select Output 4 SPI1 Slave Select Input SPI2 Clock SPI2 Data 2 SPI2 Data 3 SPI2 Master In, Slave Out SPI2 Master Out, Slave In SPI2 Ready SPI2 Slave Select Output 1 SPI2 Slave Select Output 2 SPI2 Slave Select Output 3 SPI2 Slave Select Input SPORT0 Channel A Clock SPORT0 Channel A Clock SPORT0 Channel A Data 0 SPORT0 Channel A Data 0 SPORT0 Channel A Data 1 Rev. D | Page 32 of 114 | February 2019 Port B B B B B B C B C B C B C B C A A A B B B A A A A A A A C A A B B B B B A B B B B A C A C C Pin Name PB_11 PB_12 PB_13 PB_14 PB_15 PB_00 PC_04 PB_03 PC_08 PB_07 PC_09 PB_01 PC_06 PB_02 PC_07 PA_06 PA_05 PA_06 PB_04 PB_05 PB_06 PA_05 PA_00 PA_01 PA_02 PA_03 PA_04 PA_03 PC_10 PA_14 PA_04 PB_10 PB_13 PB_14 PB_11 PB_12 PA_04 PB_15 PB_08 PB_09 PB_15 PA_13 PC_09 PA_14 PC_08 PC_00 ADSP-BF700/701/702/703/704/705/706/707 Table 11. ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions (Continued) Signal Name SPT0_AFS SPT0_AFS SPT0_ATDV SPT0_BCLK SPT0_BCLK SPT0_BD0 SPT0_BD0 SPT0_BD1 SPT0_BD1 SPT0_BFS SPT0_BFS SPT0_BTDV SPT1_ACLK SPT1_AD0 SPT1_AD1 SPT1_AFS SPT1_ATDV SPT1_BCLK SPT1_BCLK SPT1_BD0 SPT1_BD1 SPT1_BFS SPT1_BTDV SYS_BMODE0 SYS_BMODE1 SYS_CLKIN SYS_CLKOUT SYS_EXTWAKE SYS_FAULT SYS_HWRST SYS_NMI SYS_RESOUT SYS_WAKE0 SYS_WAKE1 SYS_WAKE2 SYS_WAKE3 SYS_WAKE4 SYS_XTAL TM0_ACI0 TM0_ACI1 TM0_ACI2 TM0_ACI3 TM0_ACI4 TM0_ACI5 TM0_ACI6 TM0_ACLK0 Description SPORT0 Channel A Frame Sync SPORT0 Channel A Frame Sync SPORT0 Channel A Transmit Data Valid SPORT0 Channel B Clock SPORT0 Channel B Clock SPORT0 Channel B Data 0 SPORT0 Channel B Data 0 SPORT0 Channel B Data 1 SPORT0 Channel B Data 1 SPORT0 Channel B Frame Sync SPORT0 Channel B Frame Sync SPORT0 Channel B Transmit Data Valid SPORT1 Channel A Clock SPORT1 Channel A Data 0 SPORT1 Channel A Data 1 SPORT1 Channel A Frame Sync SPORT1 Channel A Transmit Data Valid SPORT1 Channel B Clock SPORT1 Channel B Clock SPORT1 Channel B Data 0 SPORT1 Channel B Data 1 SPORT1 Channel B Frame Sync SPORT1 Channel B Transmit Data Valid Boot Mode Control 0 Boot Mode Control 1 Clock/Crystal Input Processor Clock Output External Wake Control Active-Low Fault Output Processor Hardware Reset Control Non-maskable Interrupt Reset Output Power Saving Mode Wake-up 0 Power Saving Mode Wake-up 1 Power Saving Mode Wake-up 2 Power Saving Mode Wake-up 3 Power Saving Mode Wake-up 4 Crystal Output TIMER0 Alternate Capture Input 0 TIMER0 Alternate Capture Input 1 TIMER0 Alternate Capture Input 2 TIMER0 Alternate Capture Input 3 TIMER0 Alternate Capture Input 4 TIMER0 Alternate Capture Input 5 TIMER0 Alternate Capture Input 6 TIMER0 Alternate Clock 0 Rev. D | Page 33 of 114 Port A C A B C B C B C B C A A A A A A B C B B B A Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed B B B C A Not Muxed C B C B C C A C | February 2019 Pin Name PA_12 PC_05 PA_15 PB_04 PC_04 PB_05 PC_06 PB_07 PC_01 PB_06 PC_07 PA_15 PA_08 PA_10 PA_11 PA_09 PA_07 PB_00 PC_10 PB_02 PB_03 PB_01 PA_07 SYS_BMODE0 SYS_BMODE1 SYS_CLKIN SYS_CLKOUT SYS_EXTWAKE SYS_FAULT SYS_HWRST SYS_NMI SYS_RESOUT PB_07 PB_08 PB_12 PC_02 PA_12 SYS_XTAL PC_03 PB_01 PC_07 PB_09 PC_01 PC_02 PA_12 PC_04 ADSP-BF700/701/702/703/704/705/706/707 Table 11. ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions (Continued) Signal Name TM0_ACLK1 TM0_ACLK2 TM0_ACLK3 TM0_ACLK4 TM0_ACLK5 TM0_ACLK6 TM0_CLK TM0_TMR0 TM0_TMR1 TM0_TMR2 TM0_TMR3 TM0_TMR4 TM0_TMR5 TM0_TMR6 TM0_TMR7 TRACE0_CLK TRACE0_D00 TRACE0_D01 TRACE0_D02 TRACE0_D03 TRACE0_D04 TRACE0_D05 TRACE0_D06 TRACE0_D07 TWI0_SCL TWI0_SDA UART0_CTS UART0_RTS UART0_RX UART0_TX UART1_CTS UART1_RTS UART1_RX UART1_TX USB0_CLKIN USB0_DM USB0_DP USB0_ID USB0_VBC USB0_VBUS USB0_XTAL VDD_EXT VDD_INT VDD_OTP VDD_RTC VDD_USB Description TIMER0 Alternate Clock 1 TIMER0 Alternate Clock 2 TIMER0 Alternate Clock 3 TIMER0 Alternate Clock 4 TIMER0 Alternate Clock 5 TIMER0 Alternate Clock 6 TIMER0 Clock TIMER0 Timer 0 TIMER0 Timer 1 TIMER0 Timer 2 TIMER0 Timer 3 TIMER0 Timer 4 TIMER0 Timer 5 TIMER0 Timer 6 TIMER0 Timer 7 TPIU0 Trace Clock TPIU0 Trace Data 0 TPIU0 Trace Data 1 TPIU0 Trace Data 2 TPIU0 Trace Data 3 TPIU0 Trace Data 4 TPIU0 Trace Data 5 TPIU0 Trace Data 6 TPIU0 Trace Data 7 TWI0 Serial Clock TWI0 Serial Data UART0 Clear to Send UART0 Request to Send UART0 Receive UART0 Transmit UART1 Clear to Send UART1 Request to Send UART1 Receive UART1 Transmit USB0 Clock/Crystal Input USB0 Data – USB0 Data + USB0 OTG ID USB0 VBUS Control USB0 Bus Voltage USB0 Crystal External VDD Internal VDD VDD for OTP VDD for RTC VDD for USB Port C C B B A B B A A A C A A A A B B B B B B A A A Not Muxed Not Muxed C C B B B B C C Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Rev. D | Page 34 of 114 | February 2019 Pin Name PC_10 PC_09 PB_00 PB_10 PA_14 PB_04 PB_06 PA_05 PA_06 PA_07 PC_05 PA_09 PA_10 PA_11 PA_04 PB_10 PB_15 PB_14 PB_13 PB_12 PB_11 PA_02 PA_01 PA_00 TWI0_SCL TWI0_SDA PC_03 PC_02 PB_09 PB_08 PB_14 PB_13 PC_01 PC_00 USB0_CLKIN USB0_DM USB0_DP USB0_ID USB0_VBC USB0_VBUS USB0_XTAL VDD_EXT VDD_INT VDD_OTP VDD_RTC VDD_USB ADSP-BF700/701/702/703/704/705/706/707 GPIO MULTIPLEXING FOR 12 mm × 12 mm 88-LEAD LFCSP (QFN) Table 12 through Table 14 identify the pin functions that are multiplexed on the general-purpose I/O pins of the  12 mm  12 mm 88-Lead LFCSP (QFN) package. Table 12. Signal Multiplexing for Port A Signal Name PA_00 PA_01 PA_02 PA_03 PA_04 PA_05 PA_06 PA_07 PA_08 PA_09 PA_10 PA_11 PA_12 PA_13 PA_14 PA_15 Multiplexed Function 0 SPI1_CLK SPI1_MISO SPI1_MOSI SPI1_SEL2 SPI1_SEL1 TM0_TMR0 TM0_TMR1 TM0_TMR2 PPI0_D11 PPI0_D10 PPI0_D09 PPI0_D08 PPI0_FS1 PPI0_FS2 PPI0_CLK PPI0_FS3 Multiplexed Function 1 SPI1_RDY TM0_TMR7 SPI0_SEL1 SPI0_SEL2 SPT1_BTDV MSI0_CD TM0_TMR4 TM0_TMR5 TM0_TMR6 CAN1_RX CAN1_TX SPI1_SEL4 SPT0_ATDV Multiplexed Function 2 TRACE0_D07 TRACE0_D06 TRACE0_D05 SPI0_RDY SPT1_ATDV SPT1_ACLK SPT1_AFS SPT1_AD0 SPT1_AD1 SPT0_AFS SPT0_ACLK SPT0_AD0 SPT0_BTDV Multiplexed Function 3 SMC0_ABE0 SMC0_ABE1 SMC0_AMS1 SMC0_ARDY SMC0_A08 SMC0_A07 SMC0_A06 SMC0_A05 SMC0_A01 SMC0_A02 SMC0_A03 SMC0_A04 SMC0_AOE SMC0_ARE SMC0_AWE SMC0_AMS0 Multiplexed Function 2 SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_D2 SPI0_SEL4 SPI0_SEL5 SPI0_SEL6 SPI0_D3 SPI2_SEL2 SPI2_SEL3 TRACE0_CLK TRACE0_D04 TRACE0_D03 TRACE0_D02 TRACE0_D01 TRACE0_D00 Multiplexed Function 3 SMC0_D07 SMC0_D06 SMC0_D05 SMC0_D04 SMC0_D03 SMC0_D02 SMC0_D01 SMC0_D00 SMC0_D08 SMC0_D09 SMC0_D10 SMC0_D11 SMC0_D12 SMC0_D13 SMC0_D14 SMC0_D15 SPI2_RDY Multiplexed Function Input Tap SPI1_SS SPI0_SS CNT0_DG TM0_ACI6/SYS_WAKE4 CNT0_ZM TM0_ACLK5 CNT0_UD Table 13. Signal Multiplexing for Port B Signal Name PB_00 PB_01 PB_02 PB_03 PB_04 PB_05 PB_06 PB_07 PB_08 PB_09 PB_10 PB_11 PB_12 PB_13 PB_14 PB_15 Multiplexed Function 0 PPI0_D07 PPI0_D06 PPI0_D05 PPI0_D04 PPI0_D03 PPI0_D02 PPI0_D01 PPI0_D00 UART0_TX UART0_RX SPI2_CLK SPI2_MISO SPI2_MOSI SPI2_D2 SPI2_D3 SPI2_SEL1 Multiplexed Function 1 SPT1_BCLK SPT1_BFS SPT1_BD0 SPT1_BD1 SPT0_BCLK SPT0_BD0 SPT0_BFS SPT0_BD1 PPI0_D16 PPI0_D17 UART1_RTS UART1_CTS Rev. D | Page 35 of 114 | February 2019 Multiplexed Function Input Tap TM0_ACLK3 TM0_ACI1 TM0_ACLK6 TM0_CLK SYS_WAKE0 SYS_WAKE1 TM0_ACI3 TM0_ACLK4 SYS_WAKE2 SPI2_SS ADSP-BF700/701/702/703/704/705/706/707 Table 14. Signal Multiplexing for Port C Signal Name PC_00 PC_01 PC_02 PC_03 PC_04 PC_05 PC_06 PC_07 PC_08 PC_09 PC_10 Multiplexed Function 0 UART1_TX UART1_RX UART0_RTS UART0_CTS SPT0_BCLK SPT0_AFS SPT0_BD0 SPT0_BFS SPT0_AD0 SPT0_ACLK SPT1_BCLK Multiplexed Function 1 SPT0_AD1 SPT0_BD1 CAN0_RX CAN0_TX SPI0_CLK TM0_TMR3 SPI0_MISO SPI0_MOSI SPI0_D2 SPI0_D3 MSI0_D4 Multiplexed Function 2 PPI0_D15 PPI0_D14 PPI0_D13 PPI0_D12 MSI0_D1 MSI0_CMD MSI0_D3 MSI0_D2 MSI0_D0 MSI0_CLK SPI1_SEL3 Rev. D | Page 36 of 114 | February 2019 Multiplexed Function 3 Multiplexed Function Input Tap SMC0_A09 SMC0_A10 SMC0_A11 SMC0_A12 TM0_ACI4 TM0_ACI5/SYS_WAKE3 TM0_ACI0 TM0_ACLK0 TM0_ACI2 TM0_ACLK2 TM0_ACLK1 ADSP-BF700/701/702/703/704/705/706/707 ADSP-BF70x DESIGNER QUICK REFERENCE Table 15 provides a quick reference summary of pin related information for circuit board design. The columns in this table provide the following information: • Power Domain: The Power Domain column in the table specifies the power supply domain in which the signal resides. • Signal Name: The Signal Name column in the table includes the signal name for every pin and (where applicable) the GPIO multiplexed pin function for every pin. • Description and Notes: The Description and Notes column in the table identifies any special requirements or characteristics for the signal. If no special requirements are listed the signal may be left unconnected if it is not used. Also, for multiplexed general-purpose I/O pins, this column identifies the functions available on the pin. • Pin Type: The Type column in the table identifies the I/O type or supply type of the pin. The abbreviations used in this column are na (none), I/O (input/output), a (analog), s (supply), and g (ground). If an external pull-up or pull-down resistor is required for any signal, 100 kΩ is the maximum value that can be used unless otherwise noted. • Driver Type: The Driver Type column in the table identifies the driver type used by the pin. The driver types are defined in the output drive currents section of this data sheet. Note that for Port A, Port B, and Port C (PA_00 to PC_14), when SYS_HWRST is low, these pads are three-state. After  SYS_HWRST is released, but before code execution begins, these pins are internally pulled up. Subsequently, the state depends on the input enable and output enable which are controlled by software. • Internal Termination: The Int Term column in the table specifies the termination present when the processor is not in the reset or hibernate state. The abbreviations used in this column are wk (weak keeper, weakly retains previous value driven on the pin), pu (pull-up), or pd (pull-down). Software control of internal pull-ups works according to the following settings in the PADS_PCFG0 register. When  PADS_PCFG0 = 0: For PA_15:PA_00, PB_15:PB_00, and  PC_14:PC_00, the internal pull-up is enabled when both the input enable and output enable of a particular pin are  deasserted. When PADS_PCFG0 = 1: For PA_15:PA_00,  PB_15:PB_00, and PC_14:PC_00, the internal pull-up is enabled as long as the output enable of a particular pin is  deasserted. • Reset Termination: The Reset Term column in the table specifies the termination present when the processor is in the reset state. The abbreviations used in this column are wk (weak keeper, weakly retains previous value driven on the pin), pu (pull-up), or pd (pull-down). • Reset Drive: The Reset Drive column in the table specifies the active drive on the signal when the processor is in the reset state. There are some exceptions to this scheme: • Hibernate Termination: The Hiber Term column in the table specifies the termination present when the processor is in the hibernate state. The abbreviations used in this column are wk (weak keeper, weakly retains previous value driven on the pin), pu (pull-up), or pd (pull-down). • Internal pull-ups are always disabled if MSI mode is selected for that signal. • The following signals enabled the internal pull-down when the output enable is de-asserted: SMC0_AMS[1:0],  SMC0_ARE, SMC0_AWE, SMC0_AOE, SMC0_ARDY, SPI0_SEL[6:1], SPI1_SEL[4:1], and SPI2_SEL[3:1]. • Hibernate Drive: The Hiber Drive column in the table specifies the active drive on the signal when the processor is in the hibernate state. Table 15. ADSP-BF70x Designer Quick Reference Driver Type Int  Term Reset Term Reset Drive Hiber Term Hiber Drive Power Domain B none none none none none VDD_DMC I/O B none none none none none VDD_DMC DMC0_A02 I/O B none none none none none VDD_DMC DMC0_A03 I/O B none none none none none VDD_DMC DMC0_A04 I/O B none none none none none VDD_DMC DMC0_A05 I/O B none none none none none VDD_DMC Signal Name DMC0_A00 Type I/O DMC0_A01 Rev. D | Page 37 of 114 | February 2019 Description and Notes Desc: DMC0 Address 0 Notes: No notes. Desc: DMC0 Address 1 Notes: No notes. Desc: DMC0 Address 2 Notes: No notes. Desc: DMC0 Address 3 Notes: No notes. Desc: DMC0 Address 4 Notes: No notes. Desc: DMC0 Address 5 Notes: No notes. ADSP-BF700/701/702/703/704/705/706/707 Table 15. ADSP-BF70x Designer Quick Reference (Continued) Driver Type Int  Term Reset Term Reset Drive Hiber Term Hiber Drive Power Domain B none none none none none VDD_DMC I/O B none none none none none VDD_DMC DMC0_A08 I/O B none none none none none VDD_DMC DMC0_A09 I/O B none none none none none VDD_DMC DMC0_A10 I/O B none none none none none VDD_DMC DMC0_A11 I/O B none none none none none VDD_DMC DMC0_A12 I/O B none none none none none VDD_DMC DMC0_A13 I/O B none none none none none VDD_DMC DMC0_BA0 I/O B none none none none none VDD_DMC DMC0_BA1 I/O B none none none none none VDD_DMC DMC0_BA2 I/O B none none none none none VDD_DMC DMC0_CAS I/O B none none none none none VDD_DMC DMC0_CK I/O C none none L none L VDD_DMC DMC0_CK I/O C none none L none L VDD_DMC DMC0_CKE I/O B none none L none L VDD_DMC DMC0_CS0 I/O B none none none none none VDD_DMC DMC0_DQ00 I/O B none none none none none VDD_DMC DMC0_DQ01 I/O B none none none none none VDD_DMC DMC0_DQ02 I/O B none none none none none VDD_DMC DMC0_DQ03 I/O B none none none none none VDD_DMC DMC0_DQ04 I/O B none none none none none VDD_DMC DMC0_DQ05 I/O B none none none none none VDD_DMC DMC0_DQ06 I/O B none none none none none VDD_DMC DMC0_DQ07 I/O B none none none none none VDD_DMC Signal Name DMC0_A06 Type I/O DMC0_A07 Rev. D | Page 38 of 114 | February 2019 Description and Notes Desc: DMC0 Address 6 Notes: No notes. Desc: DMC0 Address 7 Notes: No notes. Desc: DMC0 Address 8 Notes: No notes. Desc: DMC0 Address 9 Notes: No notes. Desc: DMC0 Address 10 Notes: No notes. Desc: DMC0 Address 11 Notes: No notes. Desc: DMC0 Address 12 Notes: No notes. Desc: DMC0 Address 13 Notes: No notes. Desc: DMC0 Bank Address Input 0 Notes: No notes. Desc: DMC0 Bank Address Input 1 Notes: No notes. Desc: DMC0 Bank Address Input 2 Notes: For LPDDR, leave unconnected. Desc: DMC0 Column Address Strobe Notes: No notes. Desc: DMC0 Clock Notes: No notes. Desc: DMC0 Clock (complement) Notes: No notes. Desc: DMC0 Clock enable Notes: No notes. Desc: DMC0 Chip Select 0 Notes: No notes. Desc: DMC0 Data 0 Notes: No notes. Desc: DMC0 Data 1 Notes: No notes. Desc: DMC0 Data 2 Notes: No notes. Desc: DMC0 Data 3 Notes: No notes. Desc: DMC0 Data 4 Notes: No notes. Desc: DMC0 Data 5 Notes: No notes. Desc: DMC0 Data 6 Notes: No notes. Desc: DMC0 Data 7 Notes: No notes. ADSP-BF700/701/702/703/704/705/706/707 Table 15. ADSP-BF70x Designer Quick Reference (Continued) Driver Type Int  Term Reset Term Reset Drive Hiber Term Hiber Drive Power Domain B none none none none none VDD_DMC I/O B none none none none none VDD_DMC DMC0_DQ10 I/O B none none none none none VDD_DMC DMC0_DQ11 I/O B none none none none none VDD_DMC DMC0_DQ12 I/O B none none none none none VDD_DMC DMC0_DQ13 I/O B none none none none none VDD_DMC DMC0_DQ14 I/O B none none none none none VDD_DMC DMC0_DQ15 I/O B none none none none none VDD_DMC DMC0_LDM I/O B none none none none none VDD_DMC DMC0_LDQS I/O C none none none none none VDD_DMC DMC0_LDQS I/O C none none none none none VDD_DMC DMC0_ODT I/O B none none none none none VDD_DMC DMC0_RAS I/O B none none none none none VDD_DMC DMC0_UDM I/O B none none none none none VDD_DMC DMC0_UDQS I/O C none none none none none VDD_DMC DMC0_UDQS I/O C none none none none none VDD_DMC DMC0_VREF a na none none none none none VDD_DMC DMC0_WE I/O B none none none none none VDD_DMC GND g na none none none none none na Signal Name DMC0_DQ08 Type I/O DMC0_DQ09 Rev. D | Page 39 of 114 | February 2019 Description and Notes Desc: DMC0 Data 8 Notes: No notes. Desc: DMC0 Data 9 Notes: No notes. Desc: DMC0 Data 10 Notes: No notes. Desc: DMC0 Data 11 Notes: No notes. Desc: DMC0 Data 12 Notes: No notes. Desc: DMC0 Data 13 Notes: No notes. Desc: DMC0 Data 14 Notes: No notes. Desc: DMC0 Data 15 Notes: No notes. Desc: DMC0 Data Mask for Lower Byte Notes: No notes. Desc: DMC0 Data Strobe for Lower Byte Notes: For LPDDR, a pull-down is required. Desc: DMC0 Data Strobe for Lower Byte (complement) Notes: For single ended DDR2, connect to DMC0_VREF. For LPDDR, leave unconnected. Desc: DMC0 On-die termination Notes: For LPDDR, leave unconnected. Desc: DMC0 Row Address Strobe Notes: No notes. Desc: DMC0 Data Mask for Upper Byte Notes: No notes. Desc: DMC0 Data Strobe for Upper Byte Notes: For LPDDR, a pull-down is required. Desc: DMC0 Data Strobe for Upper Byte (complement) Notes: For single ended DDR2, connect to DMC0_VREF. For LPDDR, leave unconnected. Desc: DMC0 Voltage Reference Notes: For LPDDR, leave unconnected. If the DMC is not used, connect to ground. Desc: DMC0 Write Enable Notes: No notes. Desc: Ground Notes: No notes. ADSP-BF700/701/702/703/704/705/706/707 Table 15. ADSP-BF70x Designer Quick Reference (Continued) Driver Type Int  Term Reset Term Reset Drive Hiber Term Hiber Drive Power Domain na none none none none none na a na none none none none none VDD_HADC HADC0_VIN1 a na none none none none none VDD_HADC HADC0_VIN2 a na none none none none none VDD_HADC HADC0_VIN3 a na none none none none none VDD_HADC HADC0_VREFN a na none none none none none VDD_HADC HADC0_VREFP a na none none none none none VDD_HADC JTG_TCK_ SWCLK I/O na pd none none none none VDD_EXT JTG_TDI I/O na pu none none none none VDD_EXT JTG_TDO_SWO I/O A none none none none none VDD_EXT JTG_TMS_ SWDIO I/O A pu none none none none VDD_EXT JTG_TRST I/O na pd none none none none VDD_EXT PA_00 I/O A none none none none none VDD_EXT PA_01 I/O A none none none none none VDD_EXT Signal Name GND_HADC Type g HADC0_VIN0 Rev. D | Page 40 of 114 | February 2019 Description and Notes Desc: Ground HADC Notes: If HADC is not used, connect to ground. Desc: HADC0 Analog Input at channel 0 Notes: If HADC is not used, connect to ground. Desc: HADC0 Analog Input at channel 1 Notes: If HADC is not used, connect to ground. Desc: HADC0 Analog Input at channel 2 Notes: If HADC is not used, connect to ground. Desc: HADC0 Analog Input at channel 3 Notes: If HADC is not used, connect to ground. Desc: HADC0 Ground Reference for ADC Notes: If HADC is not used, connect to ground. Desc: HADC0 External Reference for ADC Notes: If HADC is not used, connect to ground. Desc: JTAG Clock | Serial Wire Clock Notes: Functional during reset. Desc: JTAG Serial Data In Notes: Functional during reset. Desc: JTAG Serial Data Out | Serial Wire Out Notes: Functional during reset, threestate when JTG_TRST is asserted. Desc: JTAG Mode Select | Serial Wire DIO Notes: Functional during reset. Desc: JTAG Reset Notes: Functional during reset, a 10k external pull-down may be used to shorten the tVDDEXT_RST timing requirement. Desc: SPI1 Clock | TRACE0 Trace Data 7 | SMC0 Byte Enable 0 Notes: SPI clock requires a pull-down when controlling most SPI flash devices. Desc: SPI1 Master In, Slave Out | TRACE0 Trace Data 6 | SMC0 Byte Enable 1 Notes: Pull-up required for SPI_MISO if SPI master boot is used. ADSP-BF700/701/702/703/704/705/706/707 Table 15. ADSP-BF70x Designer Quick Reference (Continued) Driver Type Int  Term Reset Term Reset Drive Hiber Term Hiber Drive Power Domain A none none none none none VDD_EXT I/O A none none none none none VDD_EXT PA_04 I/O A none none none none none VDD_EXT PA_05 I/O A none none none none none VDD_EXT PA_06 I/O A none none none none none VDD_EXT PA_07 I/O A none none none none none VDD_EXT PA_08 I/O A none none none none none VDD_EXT PA_09 I/O A none none none none none VDD_EXT PA_10 I/O A none none none none none VDD_EXT PA_11 I/O A none none none none none VDD_EXT Signal Name PA_02 Type I/O PA_03 Rev. D | Page 41 of 114 | February 2019 Description and Notes Desc: SPI1 Master Out, Slave In | TRACE0 Trace Data 5 | SMC0 Memory Select 1 Notes: May require a pull-up if used as an SMC memory select. Check the data sheet requirements of the IC it connects to. Desc: SPI1 Slave Select Output 2 | SPI1 Ready | SMC0 Asynchronous Ready Notes: May require a pull-up or pulldown if used as an SMC asynchronous ready. Check the data sheet requirements of the IC it connects to and the programmed polarity. Desc: SPI1 Slave Select Output 1 | TM0 Timer 7 | SPI2 Ready | SMC0 Address 8 | SPI1 Slave Select Input Notes: SPI slave select outputs require a pull-up when used. Desc: TM0 Timer 0 | SPI0 Slave Select Output 1 | SMC0 Address 7 | SPI0 Slave Select Input Notes: SPI slave select outputs require a pull-up when used. Desc: TM0 Timer 1 | SPI0 Slave Select Output 2 | SPI0 Ready | SMC0 Address 6 Notes: SPI slave select outputs require a pull-up when used. Desc: TM0 Timer 2 | SPT1 Channel B Transmit Data Valid | SPT1 Channel A Transmit Data Valid | SMC0 Address 5 | CNT0 Count Down and Gate Notes: No notes. Desc: PPI0 Data 11 | MSI0 Card Detect | SPT1 Channel A Clock | SMC0 Address 1 Notes: An external pull-up may be required for MSI modes, see the MSI chapter in the hardware reference for details. Desc: PPI0 Data 10 | TM0 Timer 4 | SPT1 Channel A Frame Sync | SMC0 Address 2 Notes: No notes. Desc: PPI0 Data 9 | TM0 Timer 5 | SPT1 Channel A Data 0 | SMC0 Address 3 Notes: No notes. Desc: PPI0 Data 8 | TM0 Timer 6 | SPT1 Channel A Data 1 | SMC0 Address 4 Notes: No notes. ADSP-BF700/701/702/703/704/705/706/707 Table 15. ADSP-BF70x Designer Quick Reference (Continued) Driver Type Int  Term Reset Term Reset Drive Hiber Term Hiber Drive Power Domain A none none none none none VDD_EXT I/O A none none none none none VDD_EXT PA_14 I/O A none none none none none VDD_EXT PA_15 I/O A none none none none none VDD_EXT PB_00 I/O A none none none none none VDD_EXT PB_01 I/O A none none none none none VDD_EXT PB_02 I/O A none none none none none VDD_EXT PB_03 I/O A none none none none none VDD_EXT Signal Name PA_12 Type I/O PA_13 Rev. D | Page 42 of 114 | February 2019 Description and Notes Desc: PPI0 Frame Sync 1 (HSYNC) | CAN1 Receive | SPORT0 Channel A Frame Sync |SMC0 Output Enable |SYS Power Saving Mode Wakeup 4 | TM0 Alternate Capture Input 6 Notes: If hibernate mode is used one of the following must be true during hibernate. Either this pin must be actively driven by another IC, or it must have a pull-up or pull-down. Desc: PPI0 Frame Sync 2 (VSYNC) | CAN1 Transmit | SPORT0 Channel A Clock | SMC0 Read Enable | CNT0 Count Zero Marker Notes: No notes. Desc: PPI0 Clock | SPI1 Slave Select Output 4 | SPORT0 Channel A Data 0 | SMC0 Write Enable | TM0 Alternate Clock 5 Notes: SPI slave select outputs require a pull-up when used. Desc: PPI0 Frame Sync 3 (FIELD) | SPT0 Channel A Transmit Data Valid | SPT0 Channel B Transmit Data Valid | SMC0 Memory Select 0 | CNT0 Count Up and Direction Notes: May require a pull-up if used as an SMC memory select. Check the data sheet requirements of the IC it connects to. Desc: PPI0 Data 7 | SPT1 Channel B Clock | SPI0 Clock | SMC0 Data 7 | TM0 Alternate Clock 3 Notes: SPI clock requires a pull-down when controlling most SPI flash devices. Desc: PPI0 Data 6 | SPT1 Channel B Frame Sync | SPI0 Master In, Slave Out | SMC0 Data 6 | TM0 Alternate Capture Input 1 Notes: Pull-up required for SPI_MISO if SPI master boot is used. Desc: PPI0 Data 5 | SPT1 Channel B Data 0 | SPI0 Master Out, Slave In | SMC0 Data 5 Notes: No notes. Desc: PPI0 Data 4 | SPT1 Channel B Data 1 | SPI0 Data 2 | SMC0 Data 4 Notes: No notes. ADSP-BF700/701/702/703/704/705/706/707 Table 15. ADSP-BF70x Designer Quick Reference (Continued) Driver Type Int  Term Reset Term Reset Drive Hiber Term Hiber Drive Power Domain A none none none none none VDD_EXT I/O A none none none none none VDD_EXT PB_06 I/O A none none none none none VDD_EXT PB_07 I/O A none none none none none VDD_EXT PB_08 I/O A none none none none none VDD_EXT PB_09 I/O A none none none none none VDD_EXT PB_10 I/O A none none none none none VDD_EXT PB_11 I/O A none none none none none VDD_EXT Signal Name PB_04 Type I/O PB_05 Rev. D | Page 43 of 114 | February 2019 Description and Notes Desc: PPI0 Data 3 | SPT0 Channel B Clock | SPI0 Slave Select Output 4 | SMC0 Data 3 | TM0 Alternate Clock 6 Notes: SPI slave select outputs require a pull-up when used. Desc: PPI0 Data 2 | SPT0 Channel B Data 0 | SPI0 Slave Select Output 5 | SMC0 Data 2 Notes: SPI slave select outputs require a pull-up when used. Desc: PPI0 Data 1 | SPT0 Channel B Frame Sync | SPI0 Slave Select Output 6 | SMC0 Data 1 | TM0 Clock Notes: SPI slave select outputs require a pull-up when used. Desc: PPI0 Data 0 | SPT0 Channel B Data 1 | SPI0 Data 3 | SMC0 Data 0 | SYS Power Saving Mode Wakeup 0 Notes: If hibernate mode is used, one of the following must be true during hibernate. Either this pin must be actively driven by another IC, or it must have a pull-up or pull-down. Desc: UART0 Transmit | PPI0 Data 16 | SPI2 Slave Select Output 2 | SMC0 Data 8 | SYS Power Saving Mode Wakeup 1 Notes: SPI slave select outputs require a pull-up when used. If hibernate mode is used, one of the following must be true during hibernate. Either this pin must be actively driven by another IC, or it must have a pull-up or pull-down. Desc: UART0 Receive | PPI0 Data 17 | SPI2 Slave Select Output 3 | SMC0 Data 9 | TM0 Alternate Capture Input 3 Notes: SPI slave select outputs require a pull-up when used. Desc: SPI2 Clock | TRACE0 Trace Clock | SMC0 Data 10 | TM0 Alternate Clock 4 Notes: SPI clock requires a pull-down when controlling most SPI flash devices. Desc: SPI2 Master In, Slave Out | TRACE0 Trace Data 4 | SMC0 Data 11 Notes: Pull-up required for SPI_MISO if SPI master boot is used. ADSP-BF700/701/702/703/704/705/706/707 Table 15. ADSP-BF70x Designer Quick Reference (Continued) Driver Type Int  Term Reset Term Reset Drive Hiber Term Hiber Drive Power Domain A none none none none none VDD_EXT I/O A none none none none none VDD_EXT PB_14 I/O A none none none none none VDD_EXT PB_15 I/O A none none none none none VDD_EXT PC_00 I/O A none none none none none VDD_EXT PC_01 I/O A none none none none none VDD_EXT PC_02 I/O A none none none none none VDD_EXT PC_03 I/O A none none none none none VDD_EXT PC_04 I/O A none none none none none VDD_EXT Signal Name PB_12 Type I/O PB_13 Rev. D | Page 44 of 114 | February 2019 Description and Notes Desc: SPI2 Master Out, Slave In | TRACE0 Trace Data 3 | SMC0 Data 12 | SYS Power Saving Mode Wakeup 2 Notes: If hibernate mode is used, one of the following must be true during hibernate. Either this pin must be actively driven by another IC, or it must have a pull-up or pull-down. Desc: SPI2 Data 2 | UART1 Request to Send | TRACE0 Trace Data 2 | SMC0 Data 13 Notes: No notes. Desc: SPI2 Data 3 | UART1 Clear to Send | TRACE0 Trace Data 1 | SMC0 Data 14 Notes: No notes. Desc: SPI2 Slave Select Output 1 | TRACE0 Trace Data 0 | SMC0 Data 15 | SPI2 Slave Select Input Notes: SPI slave select outputs require a pull-up when used. Desc: UART1 Transmit | SPT0 Channel A Data 1 | PPI0 Data 15 Notes: No notes. Desc: UART1 Receive | SPT0 Channel B Data 1 | PPI0 Data 14 | SMC0 Address 9 | TM0 Alternate Capture Input 4 Notes: No notes. Desc: UART0 Request to Send | CAN0 Receive | PPI0 Data 13 | SMC0 Address 10 | SYS Power Saving Mode Wakeup 3 | TM0 Alternate Capture Input 5 Notes: If hibernate mode is used, one of the following must be true during hibernate. Either this pin must be actively driven by another IC, or it must have a pull-up or pull-down. Desc: UART0 Clear to Send | CAN0 Transmit | PPI0 Data 12 | SMC0 Address 11 | TM0 Alternate Capture Input 0 Notes: No notes. Desc: SPT0 Channel B Clock | SPI0 Clock | MSI0 Data 1 | SMC0 Address 12 | TM0 Alternate Clock 0 Notes: An external pull-up may be required for MSI modes, see the MSI chapter in the hardware reference for details. ADSP-BF700/701/702/703/704/705/706/707 Table 15. ADSP-BF70x Designer Quick Reference (Continued) Driver Type Int  Term Reset Term Reset Drive Hiber Term Hiber Drive Power Domain A none none none none none VDD_EXT I/O A none none none none none VDD_EXT PC_07 I/O A none none none none none VDD_EXT PC_08 I/O A none none none none none VDD_EXT PC_09 I/O A none none none none none VDD_EXT PC_10 I/O A none none none none none VDD_EXT PC_11 I/O A none none none none none VDD_EXT PC_12 I/O A none none none none none VDD_EXT Signal Name PC_05 Type I/O PC_06 Rev. D | Page 45 of 114 | February 2019 Description and Notes Desc: SPT0 Channel A Frame Sync | TM0 Timer 3 | MSI0 Command Notes: An external pull-up may be required for MSI modes, see the MSI chapter in the hardware reference for details. Desc: SPT0 Channel B Data 0 | SPI0 Master In, Slave Out | MSI0 Data 3 Notes: An external pull-up may be required for MSI modes, see the MSI chapter in the hardware reference for details. Desc: SPT0 Channel B Frame Sync | SPI0 Master Out, Slave In | MSI0 Data 2 | TM0 Alternate Capture Input 2 Notes: An external pull-up may be required for MSI modes, see the MSI chapter in the hardware reference for details. Desc: SPT0 Channel A Data 0 | SPI0 Data 2 | MSI0 Data 0 Notes: An external pull-up may be required for MSI modes, see the MSI chapter in the hardware reference for details. Desc: SPT0 Channel A Clock | SPI0 Data 3 | MSI0 Clock | TM0 Alternate Clock 2 Notes: No notes. Desc: SPT1 Channel B Clock | MSI0 Data 4 | SPI1 Slave Select Output 3 | TM0 Alternate Clock 1 Notes: An external pull-up may be required for MSI modes, see the MSI chapter in the hardware reference for details. SPI slave select outputs require a pull-up when used. Desc: SPT1 Channel B Frame Sync | MSI0 Data 5 | SPI0 Slave Select Output 3 Notes: An external pull-up may be required for MSI modes, see the MSI chapter in the hardware reference for details. SPI slave select outputs require a pull-up when used. Desc: SPT1 Channel B Data 0 | MSI0 Data 6 Notes: An external pull-up may be required for MSI modes, see the MSI chapter in the hardware reference for details. ADSP-BF700/701/702/703/704/705/706/707 Table 15. ADSP-BF70x Designer Quick Reference (Continued) Driver Type Int  Term Reset Term Reset Drive Hiber Term Hiber Drive Power Domain A none none none none none VDD_EXT I/O A none none none none none VDD_EXT RTC0_CLKIN a na none none none none none VDD_RTC RTC0_XTAL a na none none none none none VDD_RTC SYS_BMODE0 I/O na none none none none none VDD_EXT SYS_BMODE1 I/O na none none none none none VDD_EXT SYS_CLKIN a na none none none none none VDD_EXT SYS_CLKOUT I/O A none none L none none VDD_EXT SYS_EXTWAKE I/O A none none H none L VDD_EXT SYS_FAULT I/O A none none none none none VDD_EXT SYS_HWRST I/O na none none none none none VDD_EXT SYS_NMI I/O na none none none none none VDD_EXT SYS_RESOUT I/O A none none L none none VDD_EXT SYS_XTAL a na none none none none none VDD_EXT Signal Name PC_13 Type I/O PC_14 Rev. D | Page 46 of 114 | February 2019 Description and Notes Desc: SPT1 Channel B Data 1 | MSI0 Data 7 Notes: An external pull-up may be required for MSI modes, see the MSI chapter in the hardware reference for details. Desc: SPT1 Channel B Transmit Data Valid | MSI0 eSDIO Interrupt Input Notes: No notes. Desc: RTC0 Crystal input / external oscillator connection Notes: If RTC is not used, connect to ground. Desc: RTC0 Crystal output Notes: No notes. Desc: SYS Boot Mode Control 0 Notes: A pull-down is required for setting to 0 and a pull-up is required for setting to 1. Desc: SYS Boot Mode Control 1 Notes: A pull-down is required for setting to 0 and a pull-up is required for setting to 1. Desc: SYS Clock/Crystal Input Notes: No notes. Desc: SYS Processor Clock Output Notes: During reset, SYS_CLKOUT drives out SYS_CLKIN Frequency. Desc: SYS External Wake Control Notes: Drives low during hibernate and high all other times including reset. Desc: SYS Complementary Fault Output Notes: Open drain, requires an external pull-up resistor. Desc: SYS Processor Hardware Reset Control Notes: Active during reset, must be externally driven. Desc: SYS Non-maskable Interrupt Notes: Requires an external pull-up resistor. Desc: SYS Reset Output Notes: Active during reset. Desc: SYS Crystal Output Notes: Leave unconnected if an oscillator is used to provide SYS_CLKIN. Active during reset. State during hibernate is controlled by DPM_HIB_ DIS. ADSP-BF700/701/702/703/704/705/706/707 Table 15. ADSP-BF70x Designer Quick Reference (Continued) Driver Type Int  Term Reset Term Reset Drive Hiber Term Hiber Drive Power Domain D none none none none none VDD_EXT I/O D none none none none none VDD_EXT USB0_CLKIN a na none none none none none VDD_USB USB0_DM I/O F none none none none none VDD_USB USB0_DP I/O F none none none none none VDD_USB USB0_ID I/O na none none none none none VDD_USB USB0_VBC I/O E none none none none none VDD_USB USB0_VBUS I/O G none none none none none VDD_USB USB0_XTAL a na none none none none none VDD_USB VDD_DMC s na none none none none none na VDD_EXT s na none none none none none na VDD_HADC s na none none none none none na VDD_INT s na none none none none none na Signal Name TWI0_SCL Type I/O TWI0_SDA Rev. D | Page 47 of 114 | February 2019 Description and Notes Desc: TWI0 Serial Clock Notes: Open drain, requires external pull up. Consult version 2.1 of the I2C specification for the proper resistor value. If TWI is not used, connect to ground. Desc: TWI0 Serial Data Notes: Open drain, requires external pull up. Consult version 2.1 of the I2C specification for the proper resistor value. If TWI is not used, connect to ground. Desc: USB0 Clock/Crystal Input Notes: If USB is not used, connect to ground. Active during reset Desc: USB0 Data – Notes: Pull low if not using USB. For complete documentation of hibernate behavior when USB is used, see the USB chapter in the HRM. Desc: USB0 Data + Notes: Pull low if not using USB. For complete documentation of hibernate behavior when USB is used, see the USB chapter in the HRM. Desc: USB0 OTG ID Notes: If USB is not used connect to ground. When USB is being used, the internal pull-up that is present during hibernate is programmable. See the USB chapter in the HRM. Active during reset. Desc: USB0 VBUS Control Notes: If USB is not, used pull low. Desc: USB0 Bus Voltage Notes: If USB is not used, connect to ground. Desc: USB0 Crystal Notes: No notes. Desc: VDD for DMC Notes: If the DMC is not used, connect to VDD_INT. Desc: External VDD Notes: Must be powered. Desc: VDD for HADC Notes: If HADC is not used, connect to ground. Desc: Internal VDD Notes: Must be powered. ADSP-BF700/701/702/703/704/705/706/707 Table 15. ADSP-BF70x Designer Quick Reference (Continued) Driver Type Int  Term Reset Term Reset Drive Hiber Term Hiber Drive Power Domain na none none none none none na s na none none none none none na s na none none none none none na Signal Name VDD_OTP Type s VDD_RTC VDD_USB Rev. D | Page 48 of 114 | February 2019 Description and Notes Desc: VDD for OTP Notes: Must be powered. Desc: VDD for RTC Notes: If RTC is not used, connect to ground. Desc: VDD for USB Notes: If USB is not used, connect to VDD_EXT. ADSP-BF700/701/702/703/704/705/706/707 SPECIFICATIONS For information about product specifications, contact your Analog Devices, Inc. representative. OPERATING CONDITIONS Parameter Internal Supply Voltage VDD_INT Conditions Min Nominal Max Unit CCLK ≤ 400 MHz 1.045 1.100 1.155 V VDD_EXT1 External Supply Voltage 1.7 1.8 1.9 V 1 External Supply Voltage 3.13 3.30 3.47 V VDD_EXT VDD_DMC DDR2/LPDDR Supply Voltage 1.7 1.8 1.9 V VDD_USB2 USB Supply Voltage 3.13 3.30 3.47 V VDD_RTC Real-Time Clock Supply Voltage 2.00 3.30 3.47 V VDD_HADC HADC Supply Voltage 3.13 3.30 3.47 V VDD_OTP1 OTP Supply Voltage 2.25 3.30 3.47 V For Reads For Writes 3.13 3.30 3.47 V VDDR_VREF DDR2 Reference Voltage Applies to the DMC0_VREF pin. 0.49 × VDD_DMC 0.50 × VDD_DMC 0.51 × VDD_DMC V VHADC_REF3 HADC Reference Voltage 2.5 3.30 VDD_HADC V VHADC0_VINx HADC Input Voltage 0 VHADC_REF + 0.2 V VIH 4 VIH 4 High Level Input Voltage VDD_EXT = 3.47 V 2.0 V 0.7 × VDD_EXT V High Level Input Voltage VDD_EXT = 1.9 V 5, 6 High Level Input Voltage VDD_EXT = maximum 0.7 × VBUSTWI VIH_DDR27 High Level Input Voltage VDD_DMC = 1.9 V VDDR_VREF + 0.25 V VIHTWI VIH_LPDDR 8 VBUSTWI V High Level Input Voltage VDD_DMC = 1.9 V 0.8 × VDD_DMC V 9 Differential Input Voltage VIX = 1.075 V 0.50 V VID_DDR29 Differential Input Voltage VIX = 0.725 V 0.55 V VIL 4 Low Level Input Voltage VDD_EXT = 3.13 V 0.8 V VIL 4 VID_DDR2 Low Level Input Voltage VDD_EXT = 1.7 V 0.3 × VDD_EXT V VILTWI5, 6 Low Level Input Voltage VDD_EXT = minimum 0.3 × VBUSTWI V 7 Low Level Input Voltage VDD_DMC = 1.7 V VDDR_VREF – 0.25 V VIL_DDR2 VIL_LPDDR8 Low Level Input Voltage VDD_DMC = 1.7 V 0.2 × VDD_DMC V TJ Junction Temperature TAMBIENT = 0°C to +70°C 0 105 °C TJ Junction Temperature TAMBIENT = –40°C to +85°C –40 +105 °C TAMBIENT = –40°C to +105°C –40 +12510 °C AUTOMOTIVE USE ONLY TJ Junction Temperature (Automotive Grade) 1 Must remain powered (even if the associated function is not used). If not used, connect to 1.8 V or 3.3 V. 3 VHADC_VREF must always be less than VDD_HADC. 4 Parameter value applies to all input and bidirectional signals except RTC signals, TWI signals, DMC0 signals, and USB0 signals. 5 Parameter applies to TWI signals. 6 TWI signals are pulled up to VBUSTWI. See Table 16. 7 Parameter applies to DMC0 signals in DDR2 mode. 8 Parameter applies to DMC0 signals in LPDDR mode. 9 Parameter applies to signals DMC0_LDQS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS when used in DDR2 differential input mode. 10 Automotive application use profile only. Not supported for nonautomotive use. Contact Analog Devices for more information. 2 Rev. D | Page 49 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 Table 16. TWI0VSEL1 Settings and VDD_EXT/VBUSTWI TWI0VSEL VDD_EXT Nominal VBUSTWI Min VBUSTWI Nominal VBUSTWI Max Unit 3.30 3.13 3.30 3.47 V TWI001 1.80 1.70 1.80 1.90 V TWI011 1.80 3.13 3.30 3.47 V TWI100 3.30 4.75 5.00 5.25 V TWI000 1 2 2 TWI0VSEL is the TWI voltage select field in the PADS_PCFG0 register. See the hardware reference manual. Designs must comply with the VDD_EXT and VBUSTWI voltages specified for the default TWI0VSEL setting for correct JTAG boundary scan operation during reset. Clock Related Operating Conditions Table 17 and Table 18 describe the core clock, system clock, and peripheral clock timing requirements. The data presented in the tables applies to all speed grades (found in the Ordering Guide) except where expressly noted. Figure 6 provides a graphical representation of the various clocks and their available divider values. Table 17. Core and System Clock Operating Conditions 1 Parameter Ratio Restriction PLLCLK Restriction Max Unit fCCLK Core Clock Frequency fCCLK ≥ fSYSCLK PLLCLK = 800 400 MHz fCCLK Core Clock Frequency fCCLK ≥ fSYSCLK 600 ≤ PLLCLK < 800 390 MHz fCCLK Core Clock Frequency fCCLK ≥ fSYSCLK 380 ≤ PLLCLK < 600 380 MHz fCCLK Core Clock Frequency fCCLK ≥ fSYSCLK 230.2 ≤ PLLCLK < 380 PLLCLK MHz fSYSCLK SYSCLK Frequency1 PLLCLK = 800 60 200 MHz fSYSCLK SYSCLK Frequency1 600 ≤ PLLCLK < 800 60 195 MHz fSYSCLK SYSCLK Frequency 1 380 ≤ PLLCLK < 600 60 190 MHz fSYSCLK SYSCLK Frequency1 230.2 ≤ PLLCLK < 380 60 PLLCLK ÷ 2 MHz fSCLK0 SCLK0 Frequency1 fSYSCLK ≥ fSCLK0 30 100 MHz fSCLK1 SCLK1 Frequency fSYSCLK ≥ fSCLK1 200 MHz fDCLK DDR2 Clock Frequency fSYSCLK ≥ fDCLK 125 200 MHz fDCLK LPDDR Clock Frequency fSYSCLK ≥ fDCLK 10 200 MHz The minimum frequency for SYSCLK and SCLK0 applies only when the USB is used. Rev. D | Page 50 of 114 | February 2019 Min ADSP-BF700/701/702/703/704/705/706/707 Table 18. Peripheral Clock Operating Conditions Parameter fOCLK Restriction Min Typ Output Clock Frequency 1, 2 Max Unit 50 MHz fSYS_CLKOUTJ SYS_CLKOUT Period Jitter fPCLKPROG Programmed PPI Clock When Transmitting Data and Frame Sync ±2 50 MHz fPCLKPROG Programmed PPI Clock When Receiving Data or Frame Sync 50 MHz fPCLKEXT ≤ fSCLK0 50 MHz fPCLKEXT ≤ fSCLK0 50 MHz 50 MHz 3, 4 fPCLKEXT External PPI Clock When Receiving Data and Frame Sync fPCLKEXT External PPI Clock Transmitting Data or Frame Sync3, 4 fSPTCLKPROG Programmed SPT Clock When Transmitting Data and Frame Sync fSPTCLKPROG Programmed SPT Clock When Receiving Data or Frame Sync fSPTCLKEXT External SPT Clock When Receiving Data and Frame Sync3, 4 3, 4 % 50 MHz fSPTCLKEXT ≤ fSCLK0 50 MHz fSPTCLKEXT ≤ fSCLK0 50 MHz fSPTCLKEXT External SPT Clock Transmitting Data or Frame Sync fSPICLKPROG Programmed SPI Clock When Transmitting Data 50 MHz fSPICLKPROG Programmed SPI Clock When Receiving Data 50 MHz fSPICLKEXT ≤ fSCLK0 50 MHz fSPICLKEXT ≤ fSCLK0 50 MHz 50 MHz fSPICLKEXT External SPI Clock When Receiving Data 3, 4 fSPICLKEXT External SPI Clock When Transmitting Data fMSICLKPROG Programmed MSI Clock 3, 4 1 SYS_CLKOUT jitter is dependent on the application system design including pin switching activity, board layout, and the jitter characteristics of the SYS_CLKIN source. Due to the dependency on these factors the measured jitter may be higher or lower than this typical specification for each end application. 2 The value in the Typ field is the percentage of the SYS_CLKOUT period. 3 The maximum achievable frequency for any peripheral in external clock mode is dependent on being able to meet the setup and hold times in the ac timing specifications section for that peripheral. Pay particular attention to setup and hold times for VDD_EXT = 1.8 V which may preclude the maximum frequency listed here. 4 The peripheral external clock frequency must also be less than or equal to the fSCLK that clocks the peripheral. CSEL (1-32) CCLK S0SEL (1-8) SYSSEL (1-32) SYS_CLKIN PLL SCLK0 (ALL OTHER PERIPHERALS) SYSCLK PLLCLK S1SEL (1-8) DSEL (1-32) DCLK OSEL (1-128) OCLK SCLK1 (MDMA1, MDMA2, CRYPTOGRAPHIC ACCELERATORS) Figure 6. Clock Relationships and Divider Values Table 19. Phase-Locked Loop Operating Conditions Parameter fPLLCLK CGU_CTL.MSEL1 1 Min 230.2 8 PLL Clock Frequency PLL Multiplier The CGU_CTL.MSEL setting must also be chosen to ensure that the fPLLCLK specification is not violated. Rev. D | Page 51 of 114 | February 2019 Max 800 41 Unit MHz ADSP-BF700/701/702/703/704/705/706/707 ELECTRICAL CHARACTERISTICS Parameter VOH1 VOH1 VOH_DDR22 VOH_DDR22 VOH_DDR22 VOH_DDR22 VOH_LPDDR2 VOL3 VOL3 VOL_DDR22 VOL_DDR22 VOL_DDR22 VOL_DDR22 VOL_LPDDR2 IIH4 IIH_DMC0_VREF5 IIH_PD6 RPD6 IIL7 IIL_DMC0_VREF5 IIL_PU8 RPU8 IIH_USB09 IIL_USB09 IOZH10 IOZH11 IOZL12 IOZH_PD13 High Level Output Voltage High Level Output Voltage High Level Output Voltage, DDR2, Programmed Impedance = 34 Ω High Level Output Voltage, DDR2, Programmed Impedance = 40 Ω High Level Output Voltage, DDR2, Programmed Impedance = 50 Ω High Level Output Voltage, DDR2, Programmed Impedance = 60 Ω High Level Output Voltage, LPDDR Low Level Output Voltage Low Level Output Voltage Low Level Output Voltage, DDR2, Programmed Impedance = 34 Ω Low Level Output Voltage, DDR2, Programmed Impedance = 40 Ω Low Level Output Voltage, DDR2, Programmed Impedance = 50 Ω Low Level Output Voltage, DDR2, Programmed Impedance = 60 Ω Low Level Output Voltage, LPDDR High Level Input Current Conditions VDD_EXT = 1.7 V, IOH = –1.0 mA VDD_EXT = 3.13 V, IOH = –2.0 mA VDD_DMC = 1.70 V, IOH = –7.1 mA Min Typ 0.8 × VDD_EXT 0.9 × VDD_EXT VDD_DMC – 0.320 VDD_DMC = 1.70 V, IOH = –5.8 mA VDD_DMC – 0.320 V VDD_DMC = 1.70 V, IOH = –4.1 mA VDD_DMC – 0.320 V VDD_DMC = 1.70 V, IOH = –3.4 mA VDD_DMC – 0.320 V VDD_DMC = 1.70 V, IOH = –2.0 mA VDD_EXT = 1.7 V, IOL = 1.0 mA VDD_EXT = 3.13 V, IOL = 2.0 mA VDD_DMC = 1.70 V, IOL = 7.1 mA VDD_DMC – 0.320 0.400 0.400 0.320 V V V V VDD_DMC = 1.70 V, IOL = 5.8 mA 0.320 V VDD_DMC = 1.70 V, IOL = 4.1 mA 0.320 V VDD_DMC = 1.70 V, IOL = 3.4 mA 0.320 V 0.320 10 V μA 1 μA 100 μA 130 kΩ 10 μA 1 μA 100 μA 129 kΩ 10 μA 10 μA 10 μA 10 μA 10 μA 100 μA VDD_DMC = 1.70 V, IOL = 2.0 mA VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,  VDD_USB = 3.47 V, VIN = 3.47 V High Level Input Current VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,  VDD_USB = 3.47 V, VIN = 3.47 V High Level Input Current with Pull- VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,  down Resistor VDD_USB = 3.47 V, VIN = 3.47 V Internal Pull-down Resistance VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,  VDD_USB = 3.47 V, VIN = 3.47 V Low Level Input Current VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,  VDD_USB = 3.47 V, VIN = 0 V Low Level Input Current VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,  VDD_USB = 3.47 V, VIN = 0 V Low Level Input Current with Pull-up VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,  Resistor VDD_USB = 3.47 V, VIN = 0 V Internal Pull-up Resistance VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,  VDD_USB = 3.47 V, VIN = 0 V High Level Input Current VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,  VDD_USB = 3.47 V, VIN = 3.47 V Low Level Input Current VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,  VDD_USB = 3.47 V, VIN = 0 V Three-State Leakage Current VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,  VDD_USB = 3.47 V, VIN = 3.47 V Three-State Leakage Current VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,  VDD_USB = 3.47 V, VIN = 1.9 V Three-State Leakage Current VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,  VDD_USB = 3.47 V, VIN = 0 V Three-State Leakage Current VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,  VDD_USB = 3.47 V, VIN = 3.47 V Rev. D | Page 52 of 114 | February 2019 57 53 Max Unit V V V ADSP-BF700/701/702/703/704/705/706/707 Parameter IOZH_TWI14 Conditions VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,  VDD_USB = 3.47 V, VIN = 5.5 V Three-State Leakage Current ADSP-BF701/703/705/707 Input Capacitance Input Capacitance CIN (GPIO)15 14 Input Capacitance CIN_TWI Input Capacitance CIN_DDR 16 ADSP-BF700/702/704/706 Input Capacitance Input Capacitance CIN (GPIO)15 Input Capacitance CIN_TWI14 IDD_DEEPSLEEP17, 18 VDD_INT Current in Deep Sleep Mode IDD_IDLE18 VDD_INT Current in Idle IDD_TYP18 VDD_INT Current IDD_TYP18 VDD_INT Current IDD_TYP18 VDD_INT Current IDD_TYP18 VDD_INT Current Typ Max 10 Unit μA TAMBIENT = 25°C TAMBIENT = 25°C TAMBIENT = 25°C 5.2 6.9 6.1 6.0 7.4 6.9 pF pF pF TAMBIENT = 25°C TAMBIENT = 25°C Clocks disabled TJ = 25°C fPLLCLK = 300 MHz fCCLK = 100 MHz ASF = 0.05 (idle) fSYSCLK = fSCLK0 = 25 MHz USBCLK = DCLK = OUTCLK =  SCLK1 = DISABLED Peripherals disabled TJ = 25°C fPLLCLK = 800 MHz fCCLK = 400 MHz ASF = 1.0 (full-on typical) fSYSCLK = fSCLK0 = 25 MHz USBCLK = DCLK = OUTCLK =  SCLK1 = DISABLED Peripherals disabled TJ = 25°C fPLLCLK = 300 MHz fCCLK = 300 MHz ASF = 1.0 (full-on typical) fSYSCLK = fSCLK0 = 25 MHz USBCLK = DCLK = OUTCLK =  SCLK1 = DISABLED Peripherals disabled TJ = 25°C fPLLCLK = 400 MHz fCCLK = 200 MHz ASF = 1.0 (full-on typical) fSYSCLK = fSCLK0 = 25 MHz USBCLK = DCLK = OUTCLK =  SCLK1 = DISABLED Peripherals disabled TJ = 25°C fPLLCLK = 300 MHz fCCLK = 100 MHz ASF = 1.0 (full-on typical) fSYSCLK = fSCLK0 = 25 MHz USBCLK = DCLK = OUTCLK =  SCLK1 = DISABLED Peripherals disabled TJ = 25°C 5.0 6.8 1.4 5.3 7.4 pF pF mA Rev. D | Page 53 of 114 | February 2019 Min 13 mA 90 mA 66 mA 49 mA 30 mA ADSP-BF700/701/702/703/704/705/706/707 Parameter IDD_HIBERNATE17, 19 Hibernate State Current IDD_HIBERNATE17, 19 Hibernate State Current Without USB IDD_INT18 VDD_INT Current IDD_RTC IDD_RTC Current Conditions Min VDD_INT = 0 V, VDD_DMC = 1.8 V, VDD_EXT = VDD_HADC = VDD_OTP =  VDD_RTC = VDD_USB = 3.3 V, TJ = 25°C, fCLKIN = 0 VDD_INT = 0 V, VDD_DMC = 1.8 V, VDD_EXT = VDD_HADC = VDD_OTP =  VDD_RTC = VDD_USB = 3.3 V, TJ = 25°C, fCLKIN = 0, USB protection disabled  (USB_PHY_CTLDIS = 1) VDD_INT within operating conditions table specifications VDD_RTC = 3.3 V, TJ = 125°C 1 Typ 33 15 Max Unit A A See IDDINT_TOT mA equation on on Page 55 10 A Applies to all output and bidirectional signals except DMC0 signals, TWI signals, and USB0 signals. 2 Applies to DMC0_Axx, DMC0_CAS, DMC0_CKE, DMC0_CK, DMC0_CK, DMC0_CS, DMC0_DQxx, DMC0_LDM, DMC0_LDQS, DMC0_LDQS,  DMC0_ODT, DMC0_RAS, DMC0_UDM, DMC0_UDQS, DMC0_UDQS, and DMC0_WE signals. 3 Applies to all output and bidirectional signals except DMC0 signals and USB0 signals. 4 Applies to SMC0_ARDY, SYS_BMODEx, SYS_CLKIN, SYS_HWRST, JTG_TDI, and JTG_TMS_SWDIO signals. 5 Applies to DMC0_VREF signal. 6 Applies to JTG_TCK_SWCLK and JTG_TRST signals. 7 Applies to SMC0_ARDY, SYS_BMODEx, SYS_CLKIN, SYS_HWRST, JTG_TCK, and JTG_TRST signals. 8 Applies to JTG_TDI, JTG_TMS_SWDIO, PA_xx, PB_xx, and PC_xx signals when internal GPIO pull-ups are enabled. For information on when internal pull-ups are enabled for GPIOs. See ADSP-BF70x Designer Quick Reference. 9 Applies to USB0_CLKIN signal. 10 Applies to PA_xx, PB_xx, PC_xx, SMC0_AMS0, SMC0_ARE, SMC0_AWE, SMC0_A0E, SMC0_Axx, SMC0_Dxx, SYS_FAULT, JTG_TDO_SWO, USB0_DM, USB0_DP, USB0_ID, and USB0_VBC signals. 11 Applies to DMC0_Axx, DMC0_BAxx, DMC0_CAS, DMC0_CS0, DMC0_DQxx, DMC0_LDQS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS, DMC0_LDM, DMC0_ UDM, DMC0_ODT, DMC0_RAS, and DMC0_WE signals. 12 Applies to PA_xx, PB_xx, PC_xx, SMC0_A0E, SMC0_Axx, SMC0_Dxx, SYS_FAULT, JTG_TDO_SWO, USB0_DM, USB0_DP, USB0_ID, USB0_VBC, USB0_VBUS,  DMC0_Axx, DMC0_BAx, DMC0_CAS, DMC0_CS0, DMC0_DQxx, DMC0_LDQS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS, DMC0_LDM,  DMC0_UDM, DMC0_ODT, DMC0_RAS, DMC0_WE, and TWI signals. 13 Applies to USB0_VBUS signals. 14 Applies to all TWI signals. 15 Applies to all signals, except DMC0 and TWI signals. 16 Applies to all DMC0 signals. 17 See the ADSP-BF70x Blackfin+ Processor Hardware Reference for definition of deep sleep and hibernate operating modes. 18 Additional information can be found at Total Internal Power Dissipation. 19 Applies to VDD_EXT, VDD_DMC, and VDD_USB supply signals only. Clock inputs are tied high or low. Rev. D | Page 54 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 Total Internal Power Dissipation Clock Current Total power dissipation has two components: The dynamic clock currents provide the total power dissipated by all transistors switching in the clock paths. The power dissipated by each clock domain is dependent on voltage (VDD_INT), operating frequency and a unique scaling factor. 1. Static, including leakage current (deep sleep) 2. Dynamic, due to transistor switching characteristics for each clock domain Many operating conditions can also affect power dissipation, including temperature, voltage, operating frequency, and processor activity. The following equation describes the internal current consumption. IDDINT_TOT = IDDINT_DEEPSLEEP + IDDINT_CCLK_DYN + IDDINT_PLLCLK_DYN + IDDINT_SYSCLK_DYN +  IDDINT_SCLK0_DYN + IDDINT_SCLK1_DYN +  IDDINT_DCLK_DYN + IDDINT_DMA_DR_DYN +  IDDINT_USBCLK_DYN IDDINT_PLLCLK_DYN (mA) = 0.012 × fPLLCLK (MHz) × VDD_INT (V) IDDINT_SYSCLK_DYN (mA) = 0.120 × fSYSCLK (MHz) × VDD_INT (V) IDDINT_SCLK0_DYN (mA) = 0.110 × fSCLK0 (MHz) × VDD_INT (V) IDDINT_SCLK1_DYN (mA) = 0.068 × fSCLK1 (MHz) × VDD_INT (V) IDDINT_DCLK_DYN (mA) = 0.055 × fDCLK (MHz) × VDD_INT (V) The dynamic component of the USB clock is a unique case. The USB clock contributes a near constant current value when used. IDDINT_DEEPSLEEP is the only item present that is part of the static power dissipation component. IDDINT_DEEPSLEEP is specified as a function of voltage (VDD_INT) and temperature (see Table 21). There are eight different items that contribute to the dynamic power dissipation. These components fall into three broad categories: application-dependent currents, clock currents, and data transmission currents. Table 20. IDDINT_USBCLK_DYN Current Is USB Enabled? IDDINT_USBCLK_DYN (mA) Yes – High-Speed Mode 13.94 Yes – Full-Speed Mode 10.83 Yes – Suspend Mode 5.2 No 0.34 Application-Dependent Current Data Transmission Current The application-dependent currents include the dynamic current in the core clock domain. The data transmission current represents the power dissipated when transmitting data. This current is expressed in terms of data rate. The calculation is performed by adding the data rate (MB/s) of each DMA-driven access to peripherals, L1, L2, and external memory. This number is then multiplied by a weighted data-rate coefficient and VDD_INT: Core clock (CCLK) use is subject to an activity scaling factor (ASF) that represents application code running on the processor cores and L1/L2 memories (Table 22). The ASF is combined with the CCLK frequency and VDD_INT dependent data in Table 23 to calculate this portion. IDDINT_CCLK_DYN (mA) = Table 23 × ASF IDDINT_DMADR_DYN (mA) = Weighted DRC × Total Data Rate (MB/s) × VDD_INT (V) A weighted data-rate coefficient is used because different coefficients exist depending on the source and destination of the transfer. For details on using this equation and calculating the weighted DRC, see the related Engineer Zone material. For a quick maximum calculation, the weighted DRC can be assumed to be 0.0497, which is the coefficient for L1 to L1 transfers. Rev. D | Page 55 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 Table 21. Static Current—IDD_DEEPSLEEP (mA) TJ (°C) Voltage (VDD_INT) 1.100 1.110 0.8 0.8 –40 1.045 0.6 1.050 0.6 1.060 0.7 1.070 0.7 1.080 0.7 1.090 0.8 1.120 0.9 1.130 0.9 1.140 0.9 1.150 1.0 1.155 1.0 –20 1.1 1.1 1.2 1.2 1.2 1.3 1.4 0 2.0 2.0 2.1 2.2 2.3 2.4 2.5 1.4 1.5 1.5 1.6 1.7 1.7 2.5 2.6 2.7 2.8 3.0 3.0 25 4.3 4.3 4.5 4.7 4.8 5.0 5.2 5.3 5.5 5.7 5.9 6.1 6.2 40 6.7 6.8 7.0 7.3 7.5 7.8 8.0 8.3 8.6 8.8 9.1 9.4 9.6 55 10.3 10.5 10.8 11.2 70 15.7 15.9 16.4 16.8 11.5 11.9 12.3 12.6 13.0 13.4 13.9 14.3 14.5 17.4 17.9 18.4 18.9 19.5 20.1 20.7 21.3 21.6 85 23.3 23.6 24.3 25.0 25.7 26.4 27.2 27.9 28.7 29.5 30.4 31.2 31.7 100 34.2 34.6 35.5 36.5 37.5 38.5 39.5 40.6 41.7 42.8 43.9 45.1 45.7 105 38.7 39.2 40.2 41.3 42.4 43.5 44.6 45.8 47.0 48.2 49.5 50.8 51.5 115 125 48.9 49.5 50.7 52.0 53.4 54.7 56.0 57.5 59.0 60.5 62.0 63.6 64.4 61.5 62.1 63.6 65.1 66.7 68.3 69.9 71.7 73.4 75.2 77.0 79.0 79.9 1.120 72.6 1.130 73.4 1.140 74.2 1.150 74.9 1.155 75.4 Table 22. Activity Scaling Factors (ASF) IDDINT Power Vector IDD-IDLE1 IDD-IDLE2 IDD-NOP1 IDD-NOP2 IDD-APP3 IDD-APP1 IDD-APP2 IDD-TYP1 IDD-TYP3 IDD-TYP2 IDD-HIGH1 IDD-HIGH3 IDD-HIGH2 ASF 0.05 0.05 0.56 0.59 0.78 0.79 0.83 1.00 1.01 1.03 1.39 1.39 1.54 Table 23. CCLK Dynamic Current per core (mA, with ASF = 1) 400 1.045 66.7 1.050 67.2 1.060 67.9 1.070 68.7 1.080 69.4 Voltage (VDD_INT) 1.090 1.100 1.110 70.2 71.1 71.8 350 58.6 59.0 59.6 60.3 61.0 61.7 62.4 63.0 63.7 64.4 65.1 65.8 66.1 300 50.2 50.5 51.1 51.7 52.3 52.9 53.5 54.1 54.7 55.3 55.9 56.4 56.8 250 42.1 42.3 42.8 43.3 43.8 44.3 44.7 45.3 45.8 46.3 46.8 47.4 47.6 200 33.7 33.9 34.3 34.7 35.1 35.5 35.9 36.3 36.7 37.1 37.5 37.9 38.0 150 25.4 25.5 25.8 26.1 26.4 26.7 27.0 27.3 27.6 27.9 28.2 28.5 28.8 100 17.0 17.1 17.3 17.5 17.7 17.9 18.1 18.3 18.5 18.6 18.8 19.0 19.1 fCCLK (MHz) Rev. D | Page 56 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 HADC ABSOLUTE MAXIMUM RATINGS HADC Electrical Characteristics Stresses at or above those listed in Table 27 may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 24. HADC Electrical Characteristics Parameter Conditions IDD_HADC_IDLE Current Consumption on VDD_HADC. HADC is powered on, but not converting. IDD_HADC_ACTIVE Current Consumption on VDD_HADC during a conversion. Typ 2.0 Unit mA 2.5 mA IDD_HADC_ 10 POWERDOWN Current Consumption on VDD_HADC. Analog circuitry of the HADC is powered down Table 27. Absolute Maximum Ratings Parameter Internal Supply Voltage (VDD_INT) External (I/O) Supply Voltage (VDD_EXT) DDR2/LPDDR Controller Supply Voltage (VDD_DMC) USB PHY Supply Voltage (VDD_USB) Real-Time Clock Supply Voltage  (VDD_RTC) One-Time Programmable Memory Supply Voltage (VDD_OTP) HADC Supply Voltage (VDD_HADC) HADC Reference Voltage (VHADC_REF) DDR2 Reference Voltage (VDDR_VREF) Input Voltage1, 2, 3 Input Voltage1, 2, 4 TWI Input Voltage2, 5 USB0_Dx Input Voltage2, 6 USB0_VBUS Input Voltage2, 6 DDR2/LPDDR Input Voltage2 Output Voltage Swing Analog Input Voltage7 IOH/IOL Current per Signal1 Storage Temperature Range Junction Temperature While Biased μA HADC DC Accuracy Table 25. HADC DC Accuracy1 Parameter Resolution No Missing Codes (NMC) Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Offset Error Offset Error Matching Gain Error Gain Error Matching 1 2 Unit2 Bits Bits LSB LSB LSB LSB LSB LSB Typ 12 10 ±2 ±2 ±8 ±10 ±4 ±4 See the Operating Conditions section for the HADC0_VINx specification. LSB = HADC0_VREFP ÷ 4096 HADC Timing Specifications Table 26. HADC Timing Specifications Parameter Conversion Time Throughput Range TWAKEUP Typ 20 × TSAMPLE Max 1 100 Unit μs MSPS μs Rating –0.33 V to +1.26 V –0.33 V to +3.60 V –0.33 V to +1.90 V –0.33 V to +3.60 V –0.33 V to +3.60 V –0.33 V to +3.60 V –0.33 V to +3.60 V –0.33 V to +3.60 V –0.33 V to +1.90 V –0.33 V to +3.63 V –0.33 V to +2.10 V –0.33 V to +5.50 V –0.33 V to +5.25 V –0.33 V to +6.00 V –0.33 V to +2.10 V –0.33 V to VDD_EXT + 0.5 V –0.2 V to VDD_HADC + 0.2 V 4 mA (maximum) –65°C to +150°C +125°C 1 Applies to 100% transient duty cycle. Applies only when the related power supply (VDD_DMC, VDD_EXT, or VDD_USB) is within specification. When the power supply is below specification, the range is the voltage being applied to that power domain ± 0.2 V. 3 Applies when nominal VDD_EXT is 3.3 V. 4 Applies when nominal VDD_EXT is 1.8 V. 5 Applies to TWI_SCL and TWI_SDA. 6 If the USB is not used, connect these pins according to Table 15. 7 Applies only when VDD_HADC is within specifications and ≤ 3.4 V. When VDD_HADC is within specifications and > 3.4 V, the maximum rating is 3.6 V. When VDD_ HADC is below specifications, the range is VDD_HADC ± 0.2 V. 2 ESD SENSITIVITY ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Rev. D | Page 57 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 TIMING SPECIFICATIONS Specifications are subject to change without notice. Clock and Reset Timing Table 28 and Figure 7 describe clock and reset operations related to the clock generation unit (CGU). Per the CCLK, SYSCLK, SCLK0, SCLK1, DCLK, and OCLK timing specifications in Table 17 and Table 18, combinations of SYS_CLKIN and clock multipliers must not select clock rates in excess of the processor’s maximum instruction rate. Table 28. Clock and Reset Timing VDD_EXT 1.8 V Nominal Parameter VDD_EXT 3.3 V Nominal Min Max Min Max Unit Timing Requirement fCKIN SYS_CLKIN Crystal Frequency (CGU_CTL.DF = 0)1, 2, 3 19.2 35 19.2 50 MHz fCKIN SYS_CLKIN Crystal Frequency (CGU_CTL.DF = 1)1, 2, 3 N/A N/A 38.4 50 MHz fCKIN SYS_CLKIN External Source Frequency (CGU_CTL.DF = 0)1, 2, 3 19.2 60 19.2 60 MHz fCKIN SYS_CLKIN External Source Frequency (CGU_CTL.DF = 1)1, 2, 3 38.4 60 38.4 60 MHz 1 tCKINL SYS_CLKIN Low Pulse tCKINH SYS_CLKIN High Pulse1 tWRST SYS_HWRST Asserted Pulse Width Low 4 8.33 8.33 ns 8.33 8.33 ns 11 × tCKIN 11 × tCKIN ns 1 Applies to PLL bypass mode and PLL nonbypass mode. The tCKIN period (see Figure 7) equals 1/fCKIN. 3 Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fPLLCLK setting discussed in Table 19. 4 Applies after power-up sequence is complete. See Table 29 and Figure 8 for power-up reset timing. 2 tCKIN SYS_CLKIN tCKINL tCKINH tWRST SYS_HWRST Figure 7. Clock and Reset Timing Rev. D | Page 58 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 Power-Up Reset Timing A power-up reset is required to place the processor in a known state after power-up. A power-up reset is initiated by asserting  SYS_HWRST and JTG_TRST. During power-up reset, all pins are high impedance except for those noted in the ADSP-BF70x Designer Quick Reference. Both JTG_TRST and SYS_HWRST need to be asserted upon power-up, but only SYS_HWRST needs to be released for the device to boot properly. JTG_TRST may be asserted indefinitely for normal operation. JTG_TRST only needs to be released when using an emulator to connect to the DAP for debug or boundary scan. There is an internal pull-down on JTG_TRST to ensure internal emulation logic will always be properly initialized during power-up reset. Table 29 and Figure 8 show the relationship between power supply startup and processor reset timing, related to the clock generation unit (CGU) and reset control unit (RCU). In Figure 8, VDD_SUPPLIES are VDD_INT, VDD_EXT, VDD_DMC, VDD_USB, VDD_RTC, VDD_OTP, and VDD_HADC. There is no power supply sequencing requirement for the ADSP-BF70x processor. However, if saving power during power-on is important, bringing up VDD_INT last is recommended. This avoids a small current drain in the VDD_INT domain during the transition period of I/O voltages from 0 V to within the voltage specification. Table 29. Power-Up Reset Timing Parameter Min Max Unit Timing Requirement tRST_IN_PWR SYS_HWRST and JTG_TRST Deasserted After VDD_INT, VDD_DMC, VDD_USB,  VDD_RTC, VDD_OTP, VDD_HADC, and SYS_CLKIN are Stable and Within Specification 11 × tCKIN ns tVDDEXT_RST SYS_HWRST Deasserted After VDD_EXT is Stable and Within Specifications  (No External Pull-Down on JTG_TRST) 10 μs tVDDEXT_RST SYS_HWRST Deasserted After VDD_EXT is Stable and Within Specifications (10k External Pull-Down on JTG_TRST) 1 μs SYS_HWRST AND JTG_TRST tRST_IN_PWR CLKIN VDD_SUPPLIES (EXCEPT V ) DD_EXT VDD_EXT tVDDEXT_RST Figure 8. Power-Up Reset Timing Rev. D | Page 59 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 Asynchronous Read Table 30 and Figure 9 show asynchronous memory read timing, related to the static memory controller (SMC). Table 30. Asynchronous Memory Read (BxMODE = b#00) Parameter Timing Requirements tSDATARE DATA in Setup Before SMC0_ARE High tHDATARE DATA in Hold After SMC0_ARE High tDARDYARE SMC0_ARDY Valid After SMC0_ARE Low1, 2 Switching Characteristics tAMSARE SMC0_Ax/SMC0_AMSx Assertion Before  SMC0_ARE Low3 tDADVARE SMC0_ARE Low Delay From ADV High SMC0_AOE Assertion tAOEARE Before SMC0_ARE Low tHARE Output4 Hold After SMC0_ARE High5 tWARE SMC0_ARE Active Low Width6 SMC0_ARE High Delay tDAREARDY After SMC0_ARDY Assertion1 VDD_EXT 1.8 V Nominal Max Min Min VDD_EXT 3.3 V Nominal Max Unit 11.8 10.8 ns 0 0 ns (RAT – 2.5) ×  tSCLK0 – 17.5 (RAT – 2.5) ×  tSCLK0 – 17.5 ns (PREST + RST + PREAT) × tSCLK0 – 2 (PREST + RST + PREAT) × tSCLK0 – 2 ns PREAT × tSCLK0 – 2 PREAT × tSCLK0 – 2 ns (RST + PREAT) × tSCLK0 – 2 RHT × tSCLK0 – 2 (RST + PREAT) × tSCLK0 – 2 RHT × tSCLK0 – 2 ns RAT × tSCLK0 – 2 RAT × tSCLK0 – 2 ns 3.5 × tSCLK0 + 17.5 1 SMC0_BxCTL.ARDYEN bit = 1. RAT value set using the SMC_BxTIM.RAT bits. 3 PREST, RST, and PREAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.RST bits, and the SMC_BxETIM.PREAT bits. 4 Output signals are SMC0_Ax, SMC0_AMSx, SMC0_AOE, and SMC0_ABEx. 5 RHT value set using the SMC_BxTIM.RHT bits. 6 SMC0_BxCTL.ARDYEN bit = 0. 2 Rev. D | Page 60 of 114 | February 2019 ns 3.5 × tSCLK0 + 17.5 ns ADSP-BF700/701/702/703/704/705/706/707 tWARE SMC0_ARE SMC0_AMSx tHARE tADDRARE SMC0_Ax tAOEARE SMC0_AOE tDARDYARE tDAREARDY SMC0_ARDY tSDATARE SMC0_Dx (DATA) Figure 9. Asynchronous Read Rev. D | Page 61 of 114 | February 2019 tHDATARE ADSP-BF700/701/702/703/704/705/706/707 SMC Read Cycle Timing With Reference to SYS_CLKOUT The following SMC specifications with respect to SYS_CLKOUT are given to accommodate the connection of the SMC to  programmable logic devices. These specifications assume that SYS_CLKOUT is outputting a buffered version of SCLK0 by  setting CGU_CLKOUTSEL.CLKOUTSEL = 0x3. However, SCLK0 must not run faster than the maximum fOCLK specification.  For this example, RST = 0x2, RAT = 0x4, and RHT = 0x1. Table 31. SMC Read Cycle Timing With Reference to SYS_CLKOUT (BxMODE = b#00) VDD_EXT 3.3 V Nominal VDD_EXT 1.8 V Nominal Parameter Min Max Min Max Unit Timing Requirements tSDAT SMC0_Dx Setup Before SYS_CLKOUT 5.3 4.3 ns tHDAT SMC0_Dx Hold After SYS_CLKOUT 1.5 1.5 ns tSARDY SMC0_ARDY Setup Before SYS_CLKOUT 16.6 14.4 ns tHARDY SMC0_ARDY Hold After SYS_CLKOUT 0.7 0.7 ns Switching Characteristics tDO Output Delay After SYS_CLKOUT1 tHO 1 1 Output Hold After SYS_CLKOUT 7 7 –2.5 –2.5 ns Output signals are SMC0_Ax, SMC0_AMSx, SMC0_AOE, and SMC0_ABEx. SETUP 2 CYCLES PROGRAMMED READ ACCESS 4 CYCLES ACCESS EXTENDED 3 CYCLES HOLD 1 CYCLE SYS_CLKOUT tDO tHO SMC0_AMSx SMC0_ABEx SMC0_Ax SMC0_AOE tDO tHO SMC0_ARE tSARDY tHARDY SMC0_ARDY tSARDY tHARDY DATA 15–0 Figure 10. Asynchronous Memory Read Cycle Timing Rev. D | Page 62 of 114 | February 2019 tSDAT tHDAT ns ADSP-BF700/701/702/703/704/705/706/707 Asynchronous Flash Read Table 32 and Figure 11 show asynchronous flash memory read timing, related to the static memory controller (SMC). Table 32. Asynchronous Flash Read Parameter Switching Characteristics tAMSADV SMC0_Ax (Address)/SMC0_AMSx Assertion Before SMC0_NORDV Low1 tWADV SMC0_NORDV Active Low Width2 tDADVARE SMC0_ARE Low Delay From SMC0_NORDV High3 tHARE Output4 Hold After SMC0_ARE High5 tWARE6 SMC0_ARE Active Low Width7 Min VDD_EXT 1.8 V/3.3 V Nominal Max PREST × tSCLK0 – 2 ns RST × tSCLK0 – 2 PREAT × tSCLK0 – 2 RHT × tSCLK0 – 2 RAT × tSCLK0 – 2 ns ns ns ns 1 PREST value set using the SMC_BxETIM.PREST bits. RST value set using the SMC_BxTIM.RST bits. 3 PREAT value set using the SMC_BxETIM.PREAT bits. 4 Output signals are SMC0_Ax, SMC0_AMS, SMC0_AOE. 5 RHT value set using the SMC_BxTIM.RHT bits. 6 SMC0_BxCTL.ARDYEN bit = 0. 7 RAT value set using the SMC_BxTIM.RAT bits. 2 SMC0_Ax SMC0_AMSx (NOR_CE) tAMSADV tWADV SMC0_NORDV tDADVARE tWARE tHARE SMC0_ARE (NOR_OE) SMC0_Dx (DATA) READ LATCHED DATA Figure 11. Asynchronous Flash Read Rev. D | Page 63 of 114 Unit | February 2019 ADSP-BF700/701/702/703/704/705/706/707 Asynchronous Page Mode Read Table 33 and Figure 12 show asynchronous memory page mode read timing, related to the static memory controller (SMC). Table 33. Asynchronous Page Mode Read VDD_EXT 1.8 V /3.3 V Nominal Parameter Switching Characteristics tAV SMC0_Ax (Address) Valid for First Address Min Width1 tAV1 SMC0_Ax (Address) Valid for Subsequent SMC0_Ax (Address) Min Width tWADV SMC0_NORDV Active Low Width2 tHARE Output3 Hold After SMC0_ARE High4 tWARE5 SMC0_ARE Active Low Width6 Min Max Unit (PREST + RST + PREAT + RAT) × tSCLK0 – 2 PGWS × tSCLK0 – 2 ns ns RST × tSCLK0 – 2 RHT × tSCLK0 – 2 (RAT + (Nw – 1) × PGWS) × tSCLK0 – 2 ns ns ns 1 PREST, RST, PREAT and RAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.RST bits, SMC_BxETIM.PREAT bits, and the SMC_BxTIM.RAT bits. RST value set using the SMC_BxTIM.RST bits. 3 Output signals are SMC0_Ax, SMC0_AMSx, SMC0_AOE. 4 RHT value set using the SMC_BxTIM.RHT bits. 5 SMC_BxCTL.ARDYEN bit = 0. 6 RAT value set using the SMC_BxTIM.RAT bits. 2 READ LATCHED DATA SMC0_Ax (ADDRESS) READ LATCHED DATA READ LATCHED DATA READ LATCHED DATA tAV tAV1 tAV1 tAV1 A0 A0 + 1 A0 + 2 A0 + 3 SMC0_AMSx (NOR_CE) SMC0_AOE NOR_ADV tWADV SMC0_ARE (NOR_OE) tWARE SMC0_Dx (DATA) tHARE D0 D1 Figure 12. Asynchronous Page Mode Read Rev. D | Page 64 of 114 | February 2019 D2 D3 ADSP-BF700/701/702/703/704/705/706/707 Asynchronous Write Table 34 and Figure 13 show asynchronous memory write timing, related to the static memory controller (SMC). Table 34. Asynchronous Memory Write (BxMODE = b#00) Parameter Timing Requirement tDARDYAWE1 SMC0_ARDY Valid After  SMC0_AWE Low2 Switching Characteristics tENDAT DATA Enable After SMC0_AMSx Assertion tDDAT DATA Disable After SMC0_AMSx Deassertion SMC0_Ax/SMC0_AMSx Assertion tAMSAWE Before SMC0_AWE Low3 tHAWE Output4 Hold After SMC0_AWE High5 tWAWE6 SMC0_AWE Active Low Width6 1 tDAWEARDY SMC0_AWE High Delay After  SMC0_ARDY Assertion Min VDD_EXT 1.8 V Nominal Max Min VDD_EXT 3.3 V Nominal Max (WAT – 2.5) × tSCLK0 – 17.5 (WAT – 2.5) × tSCLK0 – 17.5 –3 –2 4 (PREST + WST + PREAT) × tSCLK0 – 4 WHT × tSCLK0 WAT × tSCLK0 – 2 3.5 × tSCLK0 + 17.5 SMC_BxCTL.ARDYEN bit = 1. WAT value set using the SMC_BxTIM.WAT bits. 3 PREST, WST, PREAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.WST bits, SMC_BxETIM.PREAT bits, and the SMC_BxTIM.RAT bits. 4 Output signals are DATA, SMC0_Ax, SMC0_AMSx, SMC0_ABEx. 5 WHT value set using the SMC_BxTIM.WHT bits. 6 SMC_BxCTL.ARDYEN bit = 0. 2 SMC0_AWE SMC0_ABEx SMC0_Ax tWAWE tHAWE SMC0_ARDY tDARDYAWE tDAWEARDY SMC0_AMSx SMC0_Dx (DATA) tDDAT tENDAT Figure 13. Asynchronous Write Rev. D | Page 65 of 114 | February 2019 ns ns 3.5 × tSCLK0 + 17.5 1 tAMSAWE ns ns 4.5 (PREST + WST + PREAT) × tSCLK0 – 2 WHT × tSCLK0 WAT × tSCLK0 – 2 Unit ns ns ns ADSP-BF700/701/702/703/704/705/706/707 SMC Write Cycle Timing With Reference to SYS_CLKOUT The following SMC specifications with respect to SYS_CLKOUT are given to accommodate the connection of the SMC to  programmable logic devices. These specifications assume that SYS_CLKOUT is outputting a buffered version of SCLK0 by  setting CGU_CLKOUTSEL.CLKOUTSEL = 0x3. However, SCLK0 must not run faster than the maximum fOCLK specification.  For this example WST = 0x2, WAT = 0x2, and WHT = 0x1. Table 35. SMC Write Cycle Timing With Reference to SYS_CLKOUT (BxMODE = b#00) VDD_EXT 1.8 V/3.3 V Nominal Parameter Min Max Unit Timing Requirements tSARDY SMC0_ARDY Setup Before SYS_CLKOUT 14.4 ns tHARDY SMC0_ARDY Hold After SYS_CLKOUT 0.7 ns Switching Characteristics tDDAT SMC0_Dx Disable After SYS_CLKOUT tENDAT SMC0_Dx Enable After SYS_CLKOUT tDO Output Delay After SYS_CLKOUT1 tHO Output Hold After SYS_CLKOUT 1 1 –2.5 PROGRAMMED WRITE ACCESS ACCESS EXTEND HOLD 2 CYCLES 1 CYCLE 1 CYCLE SYS_CLKOUT tDO tHO SMC0_AMSx SMC0_ABEx SMC0_Ax tHO tDO SMC0_AWE tSARDY tHARDY SMC0_ARDY tENDAT tSARDY ns 7 ns –2.5 Output pins/balls include SMC0_AMSx, SMC0_ABEx, SMC0_Ax, SMC0_Dx, SMC0_AOE, and SMC0_AWE. SETUP 2 CYCLES 7 tHARDY tDDAT SMC0_Dx Figure 14. SMC Write Cycle Timing With Reference to SYS_CLKOUT Timing Rev. D | Page 66 of 114 | February 2019 ns ns ADSP-BF700/701/702/703/704/705/706/707 Asynchronous Flash Write Table 36 and Figure 15 show asynchronous flash memory write timing, related to the static memory controller (SMC). Table 36. Asynchronous Flash Write Parameter Switching Characteristics tAMSADV SMC0_Ax/SMC0_AMSx Assertion Before ADV Low1 tDADVAWE SMC0_AWE Low Delay From ADV High2 tWADV NR_ADV Active Low Width3 tHAWE Output4 Hold After SMC0_AWE High5 6 tWAWE SMC0_AWE Active Low Width7 Min VDD_EXT 1.8 V/3.3 V Nominal Max PREST × tSCLK0 – 2 PREAT × tSCLK0 – 4 WST × tSCLK0 – 2 WHT × tSCLK0 WAT × tSCLK0 – 2 Unit ns ns ns ns ns 1 PREST value set using the SMC_BxETIM.PREST bits. PREAT value set using the SMC_BxETIM.PREAT bits. 3 WST value set using the SMC_BxTIM.WST bits. 4 Output signals are DATA, SMC0_Ax, SMC0_AMSx, SMC0_ABEx. 5 WHT value set using the SMC_BxTIM.WHT bits. 6 SMC_BxCTL.ARDYEN bit = 0. 7 WAT value set using the SMC_BxTIM.WAT bits. 2 NOR_A x-1 (SMC0_Ax) NR_CE (SMC0_AMSx) tAMSADV tWADV NR_ADV (SMC0_AOE) tDADVAWE tWAWE tHAWE NR_WE (SMC0_AWE) NR_DQ 15-0 (SMC0_Dx) Figure 15. Asynchronous Flash Write All Accesses Table 37 describes timing that applies to all memory accesses, related to the static memory controller (SMC). Table 37. All Accesses Parameter Switching Characteristic tTURN SMC0_AMSx Inactive Width VDD_EXT 1.8 V Nominal Max Min (IT + TT) × tSCLK0 – 2 Rev. D | Page 67 of 114 Min VDD_EXT 3.3 V Nominal Max (IT + TT) × tSCLK0 – 2 | February 2019 Unit ns ADSP-BF700/701/702/703/704/705/706/707 DDR2 SDRAM Clock and Control Cycle Timing Table 38 and Figure 16 show DDR2 SDRAM clock and control cycle timing, related to the dynamic memory controller (DMC). Table 38. DDR2 SDRAM Read Cycle Timing, VDD_DMC Nominal 1.8 V Parameter Switching Characteristics tCK Clock Cycle Time (CL = 2 Not Supported) tCH High Clock Pulse Width tCL Low Clock Pulse Width tIS Control/Address Setup Relative to DMC0_CK Rise tIH Control/Address Hold Relative to DMC0_CK Rise tCK 200 MHz Max Min 5 0.45 0.45 350 475 0.55 0.55 tCH tCL DMC0_CK DMC0_CK tIS tIH ADDRESS CONTROL NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE. ADDRESS = DMC0_A00-13, AND DMC0_BA0-2. Figure 16. DDR2 SDRAM Clock and Control Cycle Timing Rev. D | Page 68 of 114 | February 2019 Unit ns tCK tCK ps ps ADSP-BF700/701/702/703/704/705/706/707 DDR2 SDRAM Read Cycle Timing Table 39 and Figure 17 show DDR2 SDRAM read cycle timing, related to the dynamic memory controller (DMC). Table 39. DDR2 SDRAM Read Cycle Timing, VDD_DMC Nominal 1.8 V Parameter Timing Requirements tDQSQ tQH tRPRE tRPST 1 Min DMC0_DQS-DMC0_DQ Skew for DMC0_DQS and Associated DMC0_ DQ Signals DMC0_DQ, DMC0_DQS Output Hold Time From DMC0_DQS Read Preamble Read Postamble To ensure proper operation of the DDR2, all the DDR2 guidelines have to be strictly followed. DMC0_CKx DMC0_CKx DMC0_Ax DMC0 CONTROL tRPRE DMC0_DQSn DMC0_DQSn tDQSQ tDQSQ tRPST tQH tQH DMC0_DQx Figure 17. DDR2 SDRAM Controller Input AC Timing Rev. D | Page 69 of 114 | February 2019 200 MHz1 Max 0.35 1.8 0.9 0.4 Unit ns ns tCK tCK ADSP-BF700/701/702/703/704/705/706/707 DDR2 SDRAM Write Cycle Timing Table 40 and Figure 18 show DDR2 SDRAM write cycle timing, related to the dynamic memory controller (DMC). Table 40. DDR2 SDRAM Write Cycle Timing, VDD_DMC Nominal 1.8 V Parameter Switching Characteristics tDQSS2 DMC0_DQS Latching Rising Transitions to Associated Clock Edges tDS Last Data Valid to DMC0_DQS Delay tDH DMC0_DQS to First Data Invalid Delay tDSS DMC0_DQS Falling Edge to Clock Setup Time tDSH DMC0_DQS Falling Edge Hold Time From DMC0_CK tDQSH DMC0_DQS Output High Pulse Width tDQSL DMC0_DQS Output Low Pulse Width tWPRE Write Preamble tWPST Write Postamble tIPW Address and Control Output Pulse Width tDIPW DMC0_DQ and DMC0_DM Output Pulse Width 1 2 Min 200 MHz1 Max –0.25 0.15 0.275 0.2 0.2 0.35 0.35 0.35 0.4 0.6 0.35 +0.25 To ensure proper operation of the DDR2, all the DDR2 guidelines have to be strictly followed. Write command to first DMC0_DQS delay = WL × tCK + tDQSS. DMC0_CK DMC0_CK tIPW DMC0_Ax DMC0 CONTROL tDSH tDSS tDQSS DMC0_LDQS DMC0_UDQS tWPRE tDQSL tDS tDH tDQSH tDIPW DMC0_LDM DMC0_UDM DMC0_DQx Figure 18. DDR2 SDRAM Controller Output AC Timing Rev. D | Page 70 of 114 | February 2019 tWPST Unit tCK ns ns tCK tCK tCK tCK tCK tCK tCK tCK ADSP-BF700/701/702/703/704/705/706/707 Mobile DDR SDRAM Clock and Control Cycle Timing Table 41 and Figure 19 show mobile DDR SDRAM clock and control cycle timing, related to the dynamic memory controller (DMC). Table 41. Mobile DDR SDRAM Clock and Control Cycle Timing, VDD_DMC Nominal 1.8 V Parameter Switching Characteristics tCK Clock Cycle Time (CL = 2 Not Supported) tCH Minimum Clock Pulse Width tCL Maximum Clock Pulse Width tIS Control/Address Setup Relative to DMC0_CK Rise tIH Control/Address Hold Relative to DMC0_CK Rise tCK 200 MHz Max Min 5 0.45 0.45 1.5 1.5 0.55 0.55 tCH tCL DMC0_CK DMC0_CK tIS tIH ADDRESS CONTROL NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE. ADDRESS = DMC0_A00-13, AND DMC0_BA0-2. Figure 19. Mobile DDR SDRAM Clock and Control Cycle Timing Rev. D | Page 71 of 114 | February 2019 Unit ns tCK tCK ns ns ADSP-BF700/701/702/703/704/705/706/707 Mobile DDR SDRAM Read Cycle Timing Table 42 and Figure 20 show mobile DDR SDRAM read cycle timing, related to the dynamic memory controller (DMC). Table 42. Mobile DDR SDRAM Read Cycle Timing, VDD_DMC Nominal 1.8 V Parameter Timing Requirements tQH DMC0_DQ, DMC0_DQS Output Hold Time From DMC0_DQS tDQSQ DMC0_DQS-DMC0_DQ Skew for DMC0_DQS and Associated DMC0_DQ Signals Read Preamble tRPRE tRPST Read Postamble Min 1.5 0.9 0.4 DMC0_CK tRPRE tRPST DMC0_DQS tQH DMC0_DQS (DATA) Dn Dn+1 Dn+2 tDQSQ Figure 20. Mobile DDR SDRAM Controller Input AC Timing Rev. D | Page 72 of 114 | February 2019 200 MHz Max Dn+3 Unit 0.7 ns ns 1.1 0.6 tCK tCK ADSP-BF700/701/702/703/704/705/706/707 Mobile DDR SDRAM Write Cycle Timing Table 43 and Figure 21 show mobile DDR SDRAM write cycle timing, related to the dynamic memory controller (DMC). Table 43. Mobile DDR SDRAM Write Cycle Timing, VDD_DMC Nominal 1.8 V Parameter Switching Characteristics tDQSS1 DMC0_DQS Latching Rising Transitions to Associated Clock Edges tDS Last Data Valid to DMC0_DQS Delay (Slew > 1 V/ns) tDH DMC0_DQS to First Data Invalid Delay (Slew > 1 V/ns) tDSS DMC0_DQS Falling Edge to Clock Setup Time tDSH DMC0_DQS Falling Edge Hold Time From DMC0_CK tDQSH DMC0_DQS Input High Pulse Width tDQSL DMC0_DQS Input Low Pulse Width tWPRE Write Preamble tWPST Write Postamble tIPW Address and Control Output Pulse Width tDIPW DMC0_DQ and DMC0_DM Output Pulse Width 1 Min 200 MHz Max 0.75 0.48 0.48 0.2 0.2 0.4 0.4 0.25 0.4 2.3 1.8 1.25 Write command to first DMC0_DQS delay = WL × tCK + tDQSS. DMC0_CK tDSS tDSH tDQSS DMC0_DQS0-1 tWPRE tDS tDQSL tDH tDQSH tWPST tDIPW DMC0_DQ0-15/ DMC0_DQM0-1 Dn Dn+1 Dn+2 Dn+3 tDIPW CONTROL Write CMD NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE. ADDRESS = DMC0_A00-13, AND DMC0_BA0-1. tIPW Figure 21. Mobile DDR SDRAM Controller Output AC Timing Rev. D | Page 73 of 114 | February 2019 Unit tCK ns ns tCK tCK tCK tCK tCK tCK ns ns ADSP-BF700/701/702/703/704/705/706/707 General-Purpose I/O Port Timing (GPIO) Table 44 and Figure 22 describe I/O timing, related to the general-purpose ports (PORT). Table 44. General-Purpose I/O Port Timing Parameter Timing Requirement tWFI General-Purpose Port Pin Input Pulse Width Min VDD_EXT 1.8 V/3.3 V Nominal Max 2 × tSCLK0 – 1.5 Unit ns tWFI GPIO INPUT Figure 22. General-Purpose I/O Port Timing Timer Cycle Timing Table 45 and Figure 23 describe timer expired operations, related to the general-purpose timer (TIMER). The input signal is asynchronous in width capture mode and external clock mode and has an ideal maximum input frequency of (fSCLK0/4) MHz. The Period Value (VALUE) is the timer period assigned in the TMx_TMRn_PER register and can range from 2 to 232 – 1. Table 45. Timer Cycle Timing VDD_EXT 1.8 V Nominal Min Parameter Max VDD_EXT 3.3 V Nominal Min Max Unit Timing Requirements tWL tWH Timer Pulse Width Input Low1 Timer Pulse Width Input High 1 2 × tSCLK0 – 1.5 2 × tSCLK0 – 1.5 ns 2 × tSCLK0 – 1.5 2 × tSCLK0 – 1.5 ns tSCLK0 × VALUE – 1 tSCLK0 × VALUE – 1 ns Switching Characteristic tHTO 1 Timer Pulse Width Output This specification indicates the minimum instantaneous width that can be tolerated due to duty cycle variation or jitter for TMx signals in width capture and external clock modes. The ideal maximum frequency for TMx signals is listed in Timer Cycle Timing on this page. TMR OUTPUT tHTO TMR INPUT tWH, tWL Figure 23. Timer Cycle Timing Rev. D | Page 74 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 Up/Down Counter/Rotary Encoder Timing Table 46 and Figure 24 describe timing, related to the general-purpose counter (CNT). Table 46. Up/Down Counter/Rotary Encoder Timing VDD_EXT 1.8 V Nominal Parameter Min Max VDD_EXT 3.3 V Nominal Min Max Unit Timing Requirement tWCOUNT Up/Down Counter/Rotary Encoder Input Pulse Width 2 × tSCLK0 CNT_UD CNT_DG CNT_ZM tWCOUNT Figure 24. Up/Down Counter/Rotary Encoder Timing Rev. D | Page 75 of 114 | February 2019 2 × tSCLK0 ns ADSP-BF700/701/702/703/704/705/706/707 Debug Interface (JTAG Emulation Port) Timing Table 47 and Figure 25 provide I/O timing, related to the debug interface (JTAG emulator port). Table 47. JTAG Port Timing VDD_EXT 1.8 V Nominal Min Parameter Max VDD_EXT 3.3 V Nominal Min Max Unit Timing Requirements tTCK JTG_TCK Period 20 tSTAP JTG_TDI, JTG_TMS Setup Before JTG_TCK High 5 4 ns tHTAP JTG_TDI, JTG_TMS Hold After JTG_TCK High 4 4 ns tSSYS System Inputs Setup Before JTG_TCK High1 4 4 ns 1 20 ns tHSYS System Inputs Hold After JTG_TCK High 4 4 ns tTRSTW JTG_TRST Pulse Width (Measured in JTG_TCK Cycles)2 4 4 tTCK Switching Characteristics JTG_TDO Delay From JTG_TCK Low tDTDO 16.5 tDSYS System Outputs Delay After JTG_TCK Low tDTMS TMS Delay After TCK High in SWD Mode 3 14.5 18 3.5 16.5 3.5 ns 16.5 ns 14.5 ns System inputs = DMC0_DQxx, DMC0_LDQS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS, PA_xx, PB_xx, PC_xx, SYS_BMODEx, SYS_HWRST, SYS_FAULT,  SYS_NMI, TWI0_SCL, TWI0_SDA, and SYS_EXTWAKE. 2 50 MHz maximum. 3 System outputs = DMC0_Axx, DMC0_BAx, DMC0_CAS, DMC0_CK, DMC0_CK, DMC0_CKE, DMC0_CS0, DMC0_DQxx, DMC0_LDM, DMC0_LDQS, DMC0_LDQS, DMC0_ODT, DMC0_RAS, DMC0_UDM, DMC0_UDQS, DMC0_UDQS, DMC0_WE, PA_xx, PB_xx, PC_xx, SYS_CLKOUT, SYS_FAULT, SYS_RESOUT, and SYS_NMI. 1 tTCK JTG_TCK tSTAP tHTAP JTG_TMS JTG_TDI tDTDO JTG_TDO tSSYS tHSYS SYSTEM INPUTS tDSYS SYSTEM OUTPUTS Figure 25. JTAG Port Timing Rev. D | Page 76 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 Serial Ports To determine whether serial port (SPORT) communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) serial clock  (SPT_CLK) width. In Figure 26 either the rising edge or the falling edge of SPT_CLK (external or internal) can be used as the active sampling edge. When externally generated the SPORT clock is called fSPTCLKEXT: 1 t SPTCLKEXT = -----------------------------f SPTCLKEXT When internally generated, the programmed SPORT clock (fSPTCLKPROG) frequency in MHz is set by the following equation where CLKDIV is a field in the SPORT_DIV register that can be set from 0 to 65,535: f SCLK0 f SPTCLKPROG = --------------------------- CLKDIV + 1  1 t SPTCLKPROG = ---------------------------------f SPTCLKPROG Table 48. Serial Ports—External Clock VDD_EXT 1.8 V Nominal Parameter Timing Requirements Frame Sync Setup Before SPT_CLK  tSFSE (Externally Generated Frame Sync in Either Transmit or Receive Mode)1 tHFSE Frame Sync Hold After SPT_CLK  (Externally Generated Frame Sync in Either Transmit or Receive Mode)1 tSDRE Receive Data Setup Before Receive SPT_CLK1 tHDRE Receive Data Hold After SPT_CLK1 tSCLKW SPT_CLK Width2 tSPTCLKE SPT_CLK Period2 Switching Characteristics tDFSE Frame Sync Delay After SPT_CLK  (Internally Generated Frame Sync in Either Transmit or Receive Mode)3 tHOFSE Frame Sync Hold After SPT_CLK  (Internally Generated Frame Sync in Either Transmit or Receive Mode)3 tDDTE Transmit Data Delay After Transmit SPT_CLK3 Transmit Data Hold After Transmit SPT_CLK3 tHDTE Min VDD_EXT 3.3 V Nominal Max Min Max Unit 1.5 1 ns 3 3 ns 1.5 3 (0.5 × tSPTCLKEXT) – 1 tSPTCLKEXT – 1 1 3 (0.5 × tSPTCLKEXT) – 1 tSPTCLKEXT – 1 ns ns ns ns 18 2.5 15 2.5 18 2.5 1 ns 15 2.5 ns ns ns Referenced to sample edge. This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPT_CLK. For the external SPT_CLK ideal maximum frequency, see the fSPTCLKEXT specification in Table 18 in Clock Related Operating Conditions. 3 Referenced to drive edge. 2 Rev. D | Page 77 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 Table 49. Serial Ports—Internal Clock Parameter Timing Requirements tSFSI Frame Sync Setup Before SPT_CLK (Externally Generated Frame Sync in Either Transmit or Receive Mode)1 tHFSI Frame Sync Hold After SPT_CLK (Externally Generated Frame Sync in Either Transmit or Receive Mode)1 tSDRI Receive Data Setup Before SPT_CLK1 Receive Data Hold After SPT_CLK1 tHDRI Switching Characteristics tDFSI Frame Sync Delay After SPT_CLK (Internally Generated Frame Sync in Transmit or Receive Mode)2 tHOFSI Frame Sync Hold After SPT_CLK (Internally Generated Frame Sync in Transmit or Receive Mode)2 tDDTI Transmit Data Delay After SPT_CLK2 tHDTI Transmit Data Hold After SPT_CLK2 tSCLKIW SPT_CLK Width3 tSPTCLKI SPT_CLK Period3 Min VDD_EXT 1.8 V Nominal Max VDD_EXT 3.3 V Nominal Min Max Unit 17 14.5 ns –0.5 –0.5 ns 6.5 1.5 5 1 ns ns 2 –4.5 2 –3.5 2 –5 0.5 × tSPTCLKPROG – 1.5 tSPTCLKPROG – 1.5 1 Referenced to the sample edge. Referenced to drive edge. 3 See Table 18 in Clock Related Operating Conditions for details on the minimum period that may be programmed for tSPTCLKPROG. 2 Rev. D | Page 78 of 114 | February 2019 ns 2 –3.5 0.5 × tSPTCLKPROG – 1.5 tSPTCLKPROG – 1.5 ns ns ns ns ns ADSP-BF700/701/702/703/704/705/706/707 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE tSCLKIW DATA RECEIVE—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE SAMPLE EDGE tSCLKW SPT_A/BCLK (SPORT CLOCK) SPT_A/BCLK (SPORT CLOCK) tDFSI tDFSE tSFSI tHOFSI tHFSI tSFSE tHFSE tSDRE tHDRE tHOFSE SPT_A/BFS (FRAME SYNC) SPT_A/BFS (FRAME SYNC) tSDRI tHDRI SPT_A/BDx (DATA CHANNEL A/B) SPT_A/BDx (DATA CHANNEL A/B) DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE tSCLKIW DATA TRANSMIT—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE tSCLKW SAMPLE EDGE SPT_A/BCLK (SPORT CLOCK) SPT_A/BCLK (SPORT CLOCK) tDFSI tDFSE tHOFSI tSFSI tHFSI tSFSE tHOFSE SPT_A/BFS (FRAME SYNC) SPT_A/BFS (FRAME SYNC) tHDTI tDDTI tHDTE SPT_A/BDx (DATA CHANNEL A/B) SPT_A/BDx (DATA CHANNEL A/B) Figure 26. Serial Ports Rev. D | Page 79 of 114 | February 2019 tDDTE tHFSE ADSP-BF700/701/702/703/704/705/706/707 Table 50. Serial Ports—Enable and Three-State Parameter Switching Characteristics tDDTEN Data Enable from External Transmit SPT_CLK1 Data Disable from External Transmit SPT_CLK1 tDDTTE tDDTIN Data Enable from Internal Transmit SPT_CLK1 tDDTTI Data Disable from Internal Transmit SPT_CLK1 1 Min VDD_EXT 1.8 V Nominal Max 1 VDD_EXT 3.3 V Nominal Min 1 14 –1.12 14 –1 2.8 2.8 Referenced to drive edge. DRIVE EDGE DRIVE EDGE SPT_CLK (SPORT CLOCK EXTERNAL) tDDTEN tDDTTE SPT_A/BDx (DATA CHANNEL A/B) DRIVE EDGE SPT_CLK (SPORT CLOCK INTERNAL) Max DRIVE EDGE tDDTIN tDDTTI SPT_A/BDx (DATA CHANNEL A/B) Figure 27. Serial Ports—Enable and Three-State Rev. D | Page 80 of 114 | February 2019 Unit ns ns ns ns ADSP-BF700/701/702/703/704/705/706/707 The SPT_TDV output signal becomes active in SPORT multichannel mode. During transmit slots (enabled with active channel selection registers) the SPT_TDV is asserted for communication with external devices. Table 51. Serial Ports—Transmit Data Valid (TDV) VDD_EXT 1.8 V Nominal Min Max Parameter Switching Characteristics Data-Valid Enable Delay from Drive Edge of External Clock1 2.5 tDRDVEN tDFDVEN Data-Valid Disable Delay from Drive Edge of External Clock1 tDRDVIN Data-Valid Enable Delay from Drive Edge of Internal Clock1 –4.5 tDFDVIN Data-Valid Disable Delay from Drive Edge of Internal Clock1 1 17.5 2 SPT_CLK (SPORT CLOCK EXTERNAL) tDFDVEN SPT_A/BTDV DRIVE EDGE DRIVE EDGE SPT_CLK (SPORT CLOCK INTERNAL) tDRDVIN tDFDVIN SPT_A/BTDV Figure 28. Serial Ports—Transmit Data Valid Internal and External Clock Rev. D | Page 81 of 114 Max 14.5 –3.5 DRIVE EDGE tDRDVEN Min 2.5 Referenced to drive edge. DRIVE EDGE VDD_EXT 3.3 V Nominal | February 2019 2 Unit ns ns ns ns ADSP-BF700/701/702/703/704/705/706/707 Table 52. Serial Ports—External Late Frame Sync VDD_EXT 1.8 V Nominal Min Max Parameter Switching Characteristics tDDTLFSE Data Delay from Late External Transmit Frame Sync or External Receive Frame Sync with MCE = 1, MFD = 01 tDDTENFS Data Enable for MCE = 1, MFD = 01 0.5 1 VDD_EXT 3.3 V Nominal Min 19 0.5 The tDDTLFSE and tDDTENFS parameters apply to left-justified as well as standard serial mode, and MCE = 1, MFD = 0. DRIVE SAMPLE DRIVE SPT_A/BCLK (SPORT CLOCK) tSFSE/I tHFSE/I SPT_A/BFS (FRAME SYNC) tDDTE/I tDDTENFS SPT_A/BDx (DATA CHANNEL A/B) tHDTE/I 1ST BIT tDDTLFSE Figure 29. External Late Frame Sync Rev. D | Page 82 of 114 | February 2019 2ND BIT Max Unit 15.5 ns ns ADSP-BF700/701/702/703/704/705/706/707 Serial Peripheral Interface (SPI) Port—Master Timing Table 53 and Figure 30 describe serial peripheral interface (SPI) port master operations. When internally generated, the programmed SPI clock (fSPICLKPROG) frequency in MHz is set by the following equation where BAUD is a field in the SPI_CLK register that can be set from 0 to 65,535: f SCLK0 f SPICLKPROG = ----------------------- BAUD + 1  1 t SPICLKPROG = --------------------------------f SPICLKPROG Note that: • In dual mode data transmit, the SPI_MISO signal is also an output. • In quad mode data transmit, the SPI_MISO, SPI_D2, and SPI_D3 signals are also outputs. • In dual mode data receive, the SPI_MOSI signal is also an input. • In quad mode data receive, the SPI_MOSI, SPI_D2, and SPI_D3 signals are also inputs. • To add additional frame delays, see the documentation for the SPI_DLY register in the hardware reference manual. Table 53. Serial Peripheral Interface (SPI) Port—Master Timing VDD_EXT 1.8 V Nominal Parameter Min Max VDD_EXT 3.3 V Nominal Min Max Unit Timing Requirements tSSPIDM Data Input Valid to SPI_CLK Edge (Data Input 6.5 Setup) 5.5 ns tHSPIDM SPI_CLK Sampling Edge to Data Input Invalid 1 1 ns Switching Characteristics tSDSCIM SPI_SEL low to First SPI_CLK Edge 0.5 × tSCLK0 – 2.5 0.5 × tSCLK0 – 1.5 ns tSPICHM SPI_CLK High Period1 0.5 × tSPICLKPROG – 1.5 0.5 × tSPICLKPROG – 1.5 ns 0.5 × tSPICLKPROG – 1.5 0.5 × tSPICLKPROG – 1.5 ns tSPICLM SPI_CLK Low Period 1 1 tSPICLK SPI_CLK Period tSPICLKPROG – 1.5 tSPICLKPROG – 1.5 ns tHDSM Last SPI_CLK Edge to SPI_SEL High (0.5 × tSCLK0 ) – 2.5 (0.5 × tSCLK0 ) – 1.5 ns tSPITDM Sequential Transfer Delay2 (STOP × tSPICLK) – 1.5 tDDSPIDM SPI_CLK Edge to Data Out Valid (Data Out Delay) tHDSPIDM SPI_CLK Edge to Data Out Invalid (Data Out –4.5 Hold) 1 2 (STOP × tSPICLK) – 1.5 2.5 –3.5 See Table 18 in Clock Related Operating Conditions for details on the minimum period that may be programmed for tSPICLKPROG. STOP value set using the SPI_DLY.STOP bits. Rev. D | Page 83 of 114 | February 2019 ns 2 ns ns ADSP-BF700/701/702/703/704/705/706/707 SPI_SEL (OUTPUT) tSDSCIM tSPICLM tSPICHM tSPICLK tHDSM SPI_CLK (OUTPUT) tHDSPIDM tDDSPIDM DATA OUTPUTS (SPI_MOSI) tSSPIDM CPHA = 1 tHSPIDM DATA INPUTS (SPI_MISO) tHDSPIDM tDDSPIDM DATA OUTPUTS (SPI_MOSI) CPHA = 0 tSSPIDM tHSPIDM DATA INPUTS (SPI_MISO) Figure 30. Serial Peripheral Interface (SPI) Port—Master Timing Rev. D | Page 84 of 114 | February 2019 tSPITDM ADSP-BF700/701/702/703/704/705/706/707 Serial Peripheral Interface (SPI) Port—Slave Timing Table 54 and Figure 31 describe serial peripheral interface (SPI) port slave operations. Note that: • In dual mode data transmit, the SPI_MOSI signal is also an output. • In quad mode data transmit, the SPI_MOSI, SPI_D2, and SPI_D3 signals are also outputs. • In dual mode data receive, the SPI_MISO signal is also an input. • In quad mode data receive, the SPI_MISO, SPI_D2, and SPI_D3 signals are also inputs. • In SPI slave mode, the SPI clock is supplied externally and is called fSPICLKEXT: 1 t SPICLKEXT = ----------------------------f SPICLKEXT Table 54. Serial Peripheral Interface (SPI) Port—Slave Timing VDD_EXT 1.8 V Nominal Parameter Min Max VDD_EXT 3.3 V Nominal Min Max Unit Timing Requirements tSPICHS SPI_CLK High Period1 (0.5 × tSPICLKEXT) – 1.5 (0.5 × tSPICLKEXT) – 1.5 ns tSPICLS SPI_CLK Low Period1 (0.5 × tSPICLKEXT) – 1.5 (0.5 × tSPICLKEXT) – 1.5 ns 1 tSPICLK SPI_CLK Period tSPICLKEXT – 1.5 tSPICLKEXT – 1.5 ns tHDS Last SPI_CLK Edge to SPI_SS Not Asserted (NonSPIHP) 5 5 ns tHDS Last SPI_CLK Edge to SPI_SS Not Asserted  (Using SPIHP) 1.5 × tSCLK0 1.5 × tSCLK0 ns tSPITDS Sequential Transfer Delay (NonSPIHP) 0.5 × tSPICLK – 1.5 0.5 × tSPICLK – 1.5 ns tSPITDS Sequential Transfer Delay (Using SPIHP) 3 × tSCLK0 3 × tSCLK0 ns tSDSCI SPI_SS Assertion to First SPI_CLK Edge 11.5 11.5 ns tSSPID Data Input Valid to SPI_CLK Edge (Data Input Setup) 1.5 1 ns tHSPID SPI_CLK Sampling Edge to Data Input Invalid 3.3 3 ns Switching Characteristics tDSOE SPI_SS Assertion to Data Out Active 0 tDSDHI SPI_SS Deassertion to Data High Impedance 0 tDDSPID SPI_CLK Edge to Data Out Valid (Data Out Delay) tHDSPID SPI_CLK Edge to Data Out Invalid (Data Out Hold) 2.5 1 17.5 0 13 0 17.5 2.5 14.5 ns 11.5 ns 14.5 ns ns This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPI_CLK. For the external SPI_CLK ideal maximum frequency see the fSPICLKTEXT specification in Table 18 of Clock Related Operating Conditions. Rev. D | Page 85 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 SPI_SS (INPUT) tSDSCI tSPICLS tSPICHS tHDS tSPICLK SPI_CLK (INPUT) tDSOE tDDSPID tDDSPID tHDSPID tDSDHI DATA OUTPUTS (SPI_MISO) CPHA = 1 tSSPID tHSPID DATA INPUTS (SPI_MOSI) tDSOE tHDSPID tDDSPID tDSDHI DATA OUTPUTS (SPI_MISO) CPHA = 0 tSSPID DATA INPUTS (SPI_MOSI) Figure 31. Serial Peripheral Interface (SPI) Port—Slave Timing Rev. D | Page 86 of 114 | February 2019 tHSPID tSPITDS ADSP-BF700/701/702/703/704/705/706/707 Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing Table 55. SPI Port—SPI_RDY Slave Timing VDD_EXT 1.8 V/3.3 V Nominal Max Parameter Min Switching Characteristics tDSPISCKRDYSR SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Receive 2.5 × tSCLK0 + tHDSPID tDSPISCKRDYST SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Transmit 3.5 × tSCLK0 + tHDSPID tDSPISCKRDYSR SPI_CLK (CPOL = 0) CPHA = 0 SPI_CLK (CPOL = 1) SPI_CLK (CPOL = 0) CPHA = 1 SPI_CLK (CPOL = 1) SPI_RDY (O) Figure 32. SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Receive (FCCH = 0) tDSPISCKRDYST SPI_CLK (CPOL = 1) CPHA = 0 SPI_CLK (CPOL = 0) SPI_CLK (CPOL = 1) CPHA = 1 SPI_CLK (CPOL = 0) SPI_RDY (O) Figure 33. SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Transmit (FCCH = 1) Rev. D | Page 87 of 114 | February 2019 Unit 3.5 × tSCLK0 + tDDSPID ns 4.5 × tSCLK0 + tDDSPID ns ADSP-BF700/701/702/703/704/705/706/707 Serial Peripheral Interface (SPI) Port—Open Drain Mode (ODM) Timing In Figure 34 and Figure 35, the outputs can be SPI_MOSI SPI_MISO, SPI_D2, and/or SPI_D3 depending on the mode of operation. Table 56. SPI Port ODM Master Mode Timing VDD_EXT 1.8 V Nominal Parameter Min Max VDD_EXT 3.3 V Nominal Min Max Unit Switching Characteristics tHDSPIODMM SPI_CLK Edge to High Impedance from Data Out Valid tDDSPIODMM SPI_CLK Edge to Data Out Valid from High Impedance –4.5 tHDSPIODMM SPI_CLK (CPOL = 0) SPI_CLK (CPOL = 1) OUTPUT (CPHA = 1) OUTPUT (CPHA = 0) tDDSPIODMM tDDSPIODMM Figure 34. ODM Master Rev. D | Page 88 of 114 | February 2019 –3.5 2.5 tHDSPIODMM ns 2 ns ADSP-BF700/701/702/703/704/705/706/707 Table 57. SPI Port—ODM Slave Mode VDD_EXT 1.8 V Nominal Parameter Min Max VDD_EXT 3.3 V Nominal Min Max Unit 14.5 ns Switching Characteristics tHDSPIODMS SPI_CLK Edge to High Impedance from Data Out Valid tDDSPIODMS SPI_CLK Edge to Data Out Valid from High Impedance 2.5 tHDSPIODMS tHDSPIODMS SPI_CLK (CPOL = 0) SPI_CLK (CPOL = 1) OUTPUT (CPHA = 1) OUTPUT (CPHA = 0) tDDSPIODMS tDDSPIODMS Figure 35. ODM Slave Rev. D | Page 89 of 114 2.5 17.5 | February 2019 ns ADSP-BF700/701/702/703/704/705/706/707 Serial Peripheral Interface (SPI) Port—SPI_RDY Timing SPI_RDY is used to provide flow control. The CPOL and CPHA bits are set in SPI_CTL, while LEADX, LAGX, and STOP are in  SPI_DLY. Table 58. SPI Port—SPI_RDY Timing Parameter Timing Requirements tSRDYSCKM0 Minimum Setup Time for SPI_RDY De-assertion in Master Mode Before Last SPI_CLK Edge of Valid Data Transfer to Block Subsequent Transfer with CPHA = 0 tSRDYSCKM1 Minimum Setup Time for SPI_RDY De-assertion in Master Mode Before Last SPI_CLK Edge of Valid Data Transfer to Block Subsequent Transfer with CPHA = 1 Switching Characteristic tSRDYSCKM Time Between Assertion of SPI_RDY by Slave and First Edge of SPI_CLK for New SPI Transfer with CPHA = 0 and BAUD = 0 (STOP, LEADX, LAGX = 0) Time Between Assertion of SPI_RDY by Slave and First Edge of SPI_CLK for New SPI Transfer with CPHA = 0 and BAUD ≥ 1 (STOP, LEADX, LAGX = 0) Time Between Assertion of SPI_RDY by Slave and First Edge of SPI_CLK for New SPI Transfer with CPHA = 1 (STOP, LEADX, LAGX = 0) 1 Min VDD_EXT 1.8 V/3.3 V Nominal Max Unit (2.5 + 1.5 × BAUD1) × tSCLK0 + 14.5 ns (2.5 + BAUD1) × tSCLK0 + 14.5 ns 3 × tSCLK0 4 × tSCLK0 + 17.5 (4 + 1.5 × BAUD1) × tSCLK0 (5 + 1.5 × BAUD1) × tSCLK0 + 17.5 ns (3 + 0.5 × BAUD1) × tSCLK0 (4 + 0.5 × BAUD1) × tSCLK0 + 17.5 ns BAUD value set using the SPI_CLK.BAUD bits. tSRDYSCKM0 SPI_RDY SPI_CLK (CPOL = 0) SPI_CLK (CPOL = 1) Figure 36. SPI_RDY Setup Before SPI_CLK with CPHA = 0 Rev. D | Page 90 of 114 | February 2019 ns ADSP-BF700/701/702/703/704/705/706/707 tSRDYSCKM1 SPI_RDY SPI_CLK (CPOL = 0) SPI_CLK (CPOL = 1) Figure 37. SPI_RDY Setup Before SPI_CLK with CPHA = 1 tSRDYSCKM SPI_RDY SPI_CLK (CPOL = 0) SPI_CLK (CPOL = 1) Figure 38. SPI_CLK Switching Diagram after SPI_RDY Assertion, CPHA = x Rev. D | Page 91 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 Enhanced Parallel Peripheral Interface Timing The following tables and figures describe enhanced parallel peripheral interface timing operations. The POLC bits in the EPPI_CTL register may be used to set the sampling/driving edges of the EPPI clock. When internally generated, the programmed PPI clock (fPCLKPROG) frequency in MHz is set by the following equation where VALUE is a field in the EPPI_CLKDIV register that can be set from 0 to 65,535: f SCLK0 f PCLKPROG = -------------------------  VALUE + 1  1 t PCLKPROG = -----------------------f PCLKPROG When externally generated the EPPI_CLK is called fPCLKEXT: 1 t PCLKEXT = -------------------f PCLKEXT Table 59. Enhanced Parallel Peripheral Interface—Internal Clock Parameter Timing Requirements tSFSPI External FS Setup Before EPPI_CLK External FS Hold After EPPI_CLK tHFSPI tSDRPI Receive Data Setup Before EPPI_CLK tHDRPI Receive Data Hold After EPPI_CLK tSFS3GI External FS3 Input Setup Before EPPI_CLK Fall Edge in Clock Gating Mode tHFS3GI External FS3 Input Hold Before EPPI_CLK Fall Edge in Clock Gating Mode Switching Characteristics tPCLKW EPPI_CLK Width1 tPCLK EPPI_CLK Period1 tDFSPI Internal FS Delay After EPPI_CLK tHOFSPI Internal FS Hold After EPPI_CLK Transmit Data Delay After EPPI_CLK tDDTPI tHDTPI Transmit Data Hold After EPPI_CLK 1 Min VDD_EXT 1.8 V Nominal Max VDD_EXT 3.3 V Nominal Min Max Unit 6.5 1.5 6.4 1 16.5 5 1 5 1 14 ns ns ns ns ns 1.5 0 ns 0.5 × tPCLKPROG – 2 tPCLKPROG – 2 0.5 × tPCLKPROG – 2 tPCLKPROG – 2 ns ns ns ns ns ns 2 –4 2 –3 2 –4 2 –3 See Table 18 in Clock Related Operating Conditions for details on the minimum period that may be programmed for tPCLKPROG. Rev. D | Page 92 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 FRAME SYNC DRIVEN DATA SAMPLED POLC[1:0] = 10 EPPI_CLK POLC[1:0] = 01 tHOFSPI tDFSPI tPCLKW tPCLK EPPI_FS1/2 tSDRPI tHDRPI EPPI_Dx Figure 39. PPI Internal Clock GP Receive Mode with Internal Frame Sync Timing FRAME SYNC DRIVEN DATA DRIVEN DATA DRIVEN tPCLK POLC[1:0] = 11 EPPI_CLK POLC[1:0] = 00 tHOFSPI tDFSPI tPCLKW EPPI_FS1/2 tHDTPI tDDTPI EPPI_Dx Figure 40. PPI Internal Clock GP Transmit Mode with Internal Frame Sync Timing DATA SAMPLED / FRAME SYNC SAMPLED DATA SAMPLED / FRAME SYNC SAMPLED POLC[1:0] = 11 EPPI_CLK POLC[1:0] = 00 tSFSPI tPCLKW tHFSPI tPCLK EPPI_FS1/2 tSDRPI tHDRPI EPPI_Dx Figure 41. PPI Internal Clock GP Receive Mode with External Frame Sync Timing Rev. D | Page 93 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 DATA DRIVEN / FRAME SYNC SAMPLED POLC[1:0] = 11 EPPI_CLK POLC[1:0] = 00 tSFSPI tHFSPI tPCLKW tPCLK EPPI_FS1/2 tDDTPI tHDTPI EPPI_Dx Figure 42. PPI Internal Clock GP Transmit Mode with External Frame Sync Timing EPPI_CLK tHFS3GI tSFS3GI EPPI_FS3 Figure 43. Clock Gating Mode with Internal Clock and External Frame Sync Timing Rev. D | Page 94 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 Table 60. Enhanced Parallel Peripheral Interface—External Clock Parameter Timing Requirements tPCLKW EPPI_CLK Width1 EPPI_CLK Period1 tPCLK tSFSPE External FS Setup Before EPPI_CLK tHFSPE External FS Hold After EPPI_CLK tSDRPE Receive Data Setup Before EPPI_CLK tHDRPE Receive Data Hold After EPPI_CLK Switching Characteristics Internal FS Delay After EPPI_CLK tDFSPE tHOFSPE Internal FS Hold After EPPI_CLK tDDTPE Transmit Data Delay After EPPI_CLK tHDTPE Transmit Data Hold After EPPI_CLK 1 Min VDD_EXT 1.8 V Nominal Max VDD_EXT 3.3 V Nominal Min (0.5 × tPCLKEXT) – 1 tPCLKEXT – 1 1.5 3.3 1 3 Max (0.5 × tPCLKEXT) – 1 tPCLKEXT – 1 1 3 1 3 17.5 ns ns ns ns ns ns 14.5 2.5 2.5 17.5 14.5 2.5 2.5 Unit ns ns ns ns This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external EPPI_CLK. For the external EPPI_CLK ideal maximum frequency, see the fPCLKEXT specification in Table 18 in Clock Related Operating Conditions. FRAME SYNC DRIVEN DATA SAMPLED POLC[1:0] = 10 EPPI_CLK POLC[1:0] = 01 tHOFSPE tDFSPE tPCLKW tPCLK EPPI_FS1/2 tSDRPE tHDRPE EPPI_Dx Figure 44. PPI External Clock GP Receive Mode with Internal Frame Sync Timing FRAME SYNC DRIVEN DATA DRIVEN DATA DRIVEN tPCLK POLC[1:0] = 11 EPPI_CLK POLC[1:0] = 00 tHOFSPE tDFSPE tPCLKW EPPI_FS1/2 tDDTPE tHDTPE EPPI_Dx Figure 45. PPI External Clock GP Transmit Mode with Internal Frame Sync Timing Rev. D | Page 95 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 DATA SAMPLED/ FRAME SYNC SAMPLED DATA SAMPLED/ FRAME SYNC SAMPLED POLC[1:0] = 11 EPPI_CLK POLC[1:0] = 00 tSFSPE tPCLKW tHFSPE tPCLK EPPI_FS1/2 tSDRPE tHDRPE EPPI_Dx Figure 46. PPI External Clock GP Receive Mode with External Frame Sync Timing DATA DRIVEN/ FRAME SYNC SAMPLED POLC[1:0] = 11 EPPI_CLK POLC[1:0] = 00 tSFSPE tHFSPE tPCLKW tPCLK EPPI_FS1/2 tDDTPE tHDTPE EPPI_Dx Figure 47. PPI External Clock GP Transmit Mode with External Frame Sync Timing Rev. D | Page 96 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 Universal Asynchronous Receiver-Transmitter  (UART) Ports—Receive and Transmit Timing The universal asynchronous receiver-transmitter (UART) ports receive and transmit operations are described in the ADSP-BF70x Blackfin+ Processor Hardware Reference. Controller Area Network (CAN) Interface The controller area network (CAN) interface timing is described in the ADSP-BF70x Blackfin+ Processor Hardware Reference. Universal Serial Bus (USB) Table 61 describes the universal serial bus (USB) clock timing. Refer to the USB 2.0 Specification for timing and dc specifications for USB pins (including output characteristics for driver types E, F, and G listed in the ADSP-BF70x Designer Quick Reference). Table 61. USB Clock Timing VDD_EXT 3.3 V Nominal Parameter Min Max Unit Timing Requirements fUSBS USB_CLKIN Frequency 24 24 MHz fsUSB USB_CLKIN Clock Frequency Stability –50 +50 ppm Rev. D | Page 97 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 Mobile Storage Interface (MSI) Controller Timing Table 63 and Figure 48 show I/O timing, related to the mobile storage interface (MSI). The MSI timing depends on the period of the input clock that has been routed to the MSI peripheral (tMSICLKIN) by setting the  MSI0_UHS_EXT register. See Table 62 for this information. Table 62. tMSICLKIN Settings EXT_CLK_MUX_CTRL[31:30] 00 01 10 tMSICLKIN tSCLK0 × 2 tSCLK0 tSCLK1 × 3 1 t MSICLKIN = ---------------------f MSICLKIN (fMSICLKPROG) frequency in MHz is set by the following equation where DIV0 is a field in the MSI_CLKDIV register that can be set from 0 to 255. When DIV0 is set between 1 and 255, the following equation is used to determine fMSICLKPROG: f MSICLKIN f MSICLKPROG = ------------------------DIV0  2 When DIV0 = 0, f MSICLKPROG = f MSICLKIN Also note the following: 1 t MSICLKPROG = ----------------------------f MSICLKPROG Table 63. MSI Controller Timing Parameter Timing Requirements Input Setup Time tISU Input Hold Time tIH Switching Characteristics tMSICLK Clock Period Data Transfer Mode1 Clock Low Time tWL Clock High Time tWH Clock Rise Time tTLH tTHL Clock Fall Time tODLY Output Delay Time During Data Transfer Mode Output Hold Time tOH 1 Min VDD_EXT 1.8 V Nominal Max VDD_EXT 3.3 V Nominal Min 5.5 2 4.7 0.5 tMSICLKPROG – 1.5 7 7 tMSICLKPROG – 1.5 7 7 Max Unit ns ns ns ns ns 3 3 ns 3 3 ns (0.5 × tMSICLKIN) + 3.2 (0.5 × tMSICLKIN) + 3 ns (0.5 × tMSICLKIN) – 4 (0.5 × tMSICLKIN) – 3 ns See Table 18 in Clock Related Operating Conditions for details on the minimum period that may be programmed for tMSICLKPROG. Rev. D | Page 98 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 VOH (MIN) tMSICLK MSI_CLK tTHL tISU tTLH tWL tIH tWH INPUT tODLY tOH OUTPUT NOTES: 1 INPUT INCLUDES MSI_Dx AND MSI_CMD SIGNALS. 2 OUTPUT INCLUDES MSI_Dx AND MSI_CMD SIGNALS. Figure 48. MSI Controller Timing Rev. D | Page 99 of 114 | February 2019 VOL (MAX) ADSP-BF700/701/702/703/704/705/706/707 OUTPUT DRIVE CURRENTS 0 25 20 VOH 10 5 VOL –5 VOL –6 VDD_EXT = 1.7V @ 125°C –8 –10 VDD_EXT = 1.8V @ 25°C –12 –16 VDD_EXT = 1.9V @ –40°C 0 0.5 1.0 1.5 SOURCE VOLTAGE (V) –10 VDD_EXT = 1.9V @ –40°C VDD_EXT = 1.8V @ 25°C VDD_EXT = 1.7V @ 125°C 2.5 0 0.2 0.4 5 0 0.6 0.8 1.0 1.2 1.4 SOURCE VOLTAGE (V) 1.6 1.8 2.0 Figure 49. Driver Type A Current (1.8 V VDD_EXT) 60 40 VOH –5 SOURCE CURRENT (mA) –25 –30 2.0 Figure 51. Driver Type D Current (1.8 V VDD_EXT) –15 –20 SOURCE CURRENT (mA) –4 –14 0 VDD_EXT = 3.47V @ –40°C VDD_EXT = 3.30V @ 25°C VDD_EXT = 3.13V @ 125°C –10 VOL –15 –20 VDD_EXT = 3.13V @ 125°C –25 –30 VDD_EXT = 3.30V @ 25°C –35 –40 20 VDD_EXT = 3.47V @ –40°C –45 0 –50 VOL 0 0.5 1.0 1.5 2.0 2.5 SOURCE VOLTAGE (V) –20 3.0 3.5 4.0 Figure 52. Driver Type D Current (3.3 V VDD_EXT) VDD_EXT = 3.47V @ –40°C VDD_EXT = 3.30V @ 25°C VDD_EXT = 3.13V @ 125°C –40 –60 0 0.5 1.0 1.5 2.0 2.5 SOURCE VOLTAGE (V) 5 3.0 3.5 0 4.0 Figure 50. Driver Type A Current (3.3 V VDD_EXT) SOURCE CURRENT (mA) SOURCE CURRENT (mA) 15 VDD_EXT = 1.9V @ –40°C VDD_EXT = 1.8V @ 25°C VDD_EXT = 1.7V @ 125°C –2 SOURCE CURRENT (mA) Figure 49 through Figure 60 show typical current-voltage characteristics for the output drivers of the ADSP-BF70x Blackfin processors. The curves represent the current drive capability of the output drivers as a function of output voltage. –5 VOL VDD_DMC = 1.7V @ 125°C VDD_DMC = 1.8V @ 25°C VDD_DMC = 1.9V @ –40°C –10 –15 –20 –25 –30 –35 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 SOURCE VOLTAGE (V) Figure 53. Driver Type B and Driver Type C (DDR Drive Strength 34 Ω) Rev. D | Page 100 of 114 | February 2019 5 35 0 30 VOL –5 SOURCE CURRENT (mA) SOURCE CURRENT (mA) ADSP-BF700/701/702/703/704/705/706/707 VDD_DMC = 1.7V @ 125°C VDD_DMC = 1.8V @ 25°C VDD_DMC = 1.9V @ –40°C –10 –15 –20 –25 –30 VDD_DMC = 1.7V @ 125°C VDD_DMC = 1.8V @ 25°C VDD_DMC = 1.9V @ –40°C 25 20 VOH 15 10 5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 2.0 0 0.2 0.4 0.6 SOURCE VOLTAGE (V) Figure 54. Driver Type B and Driver Type C (DDR Drive Strength 40 Ω) 30 0 VDD_DMC = 1.7V @ 125°C VDD_DMC = 1.8V @ 25°C VDD_DMC = 1.9V @ –40°C –5 –10 –15 –20 1.4 1.6 1.8 2.0 20 15 VOH 10 5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 2.0 0 0.2 0.4 0.6 SOURCE VOLTAGE (V) 0.8 1.0 25 20 SOURCE CURRENT (mA) VOL VDD_DMC = 1.7V @ 125°C VDD_DMC = 1.8 V @ 25°C VDD_DMC = 1.9 V @ –4 0°C –6 1.6 1.8 2.0 VDD_DMC = 1.7V @ 125°C VDD_DMC = 1.8V @ 25°C VDD_DMC = 1.9V @ –40°C 0 –4 1.4 Figure 58. Driver Type B and Driver Type C (DDR Drive Strength 40 Ω) 2 –2 1.2 SOURCE VOLTAGE (V) Figure 55. Driver Type B and Driver Type C (DDR Drive Strength 50 Ω) SOURCE CURRENT (mA) 1.2 VDD_DMC = 1.7V @ 125°C VDD_DMC = 1.8V @ 25°C VDD_DMC = 1.9V @ –40°C 25 VOL SOURCE CURRENT (mA) SOURCE CURRENT (mA) 1.0 Figure 57. Driver Type B and Driver Type C (DDR Drive Strength 34 Ω) 5 –25 0.8 SOURCE VOLTAGE (V) –8 –10 –12 –14 15 VOH 10 5 –16 –18 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 0 0.2 SOURCE VOLTAGE (V) 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 SOURCE VOLTAGE (V) Figure 56. Driver Type B and Driver Type C (DDR Drive Strength 60 Ω) Figure 59. Driver Type B and Driver Type C (DDR Drive Strength 50 Ω) Rev. D | Page 101 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 20 VDD_DMC = 1.7V @ 125°C VDD_DMC = 1.8V @ 25°C VDD_DMC = 1.9V @ –40°C 18 SOURCE CURRENT (mA) 16 REFERENCE SIGNAL 14 tDIS tENA 12 10 VOH 8 6 4 2 0 OUTPUT STOPS DRIVING 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 OUTPUT STARTS DRIVING HIGH IMPEDANCE STATE 2.0 SOURCE VOLTAGE (V) Figure 62. Output Enable/Disable Figure 60. Driver Type B and Device Driver C (DDR Drive Strength 60 Ω) TEST CONDITIONS All timing parameters appearing in this data sheet were measured under the conditions described in this section. Figure 61 shows the measurement point for ac measurements (except output enable/disable). The measurement point, VMEAS, is VDD_EXT/2 for VDD_EXT (nominal) = 1.8 V/3.3 V. Capacitive Loading Output delays and holds are based on standard capacitive loads of an average of 6 pF on all pins (see Figure 63). VLOAD is equal to VDD_EXT/2. TESTER PIN ELECTRONICS 50: VLOAD T1 45: INPUT OR OUTPUT DUT OUTPUT 70: VMEAS VMEAS ZO = 50:(impedance) TD = 4.04 r 1.18 ns 50: 4pF Figure 61. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) 0.5pF 2pF 400: Output Enable Time Measurement Output pins are considered enabled when they make a transition from a high impedance state to the point when they start driving. The output enable time, tENA, is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving, as shown on the right side of Figure 62. If multiple pins are enabled, the measurement value is that of the first pin to start driving. NOTES: THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS. ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES. Figure 63. Equivalent Device Loading for AC Measurements (Includes All Fixtures) Output Disable Time Measurement Output pins are considered disabled when they stop driving, enter a high impedance state, and start to decay from the output high or low voltage. The output disable time, tDIS, is the interval from when a reference signal reaches a high or low voltage level to the point when the output stops driving, as shown on the left side of Figure 62. Rev. D | Page 102 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 40 RISE AND FALL TIMES (ns) 35 tRISE = 1.8V @ 25°C 30 25 1.4 tFALL = 1.8V @ 25°C 20 1.0 tRISE = 1.8V @ 25°C 0.8 0.6 0.4 0.2 0 15 0 2 0 4 6 8 10 12 LOAD CAPACITANCE (pF) 10 Figure 66. Driver Type B & C Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance (VDD_DMC = 1.8 V) 5 0 50 100 150 200 250 0.9 LOAD CAPACITANCE (pF) 35 30 tRISE = 3.3V @ 25°C 25 tFALL = 3.3V @ 25°C 20 0.8 RISE AND FALL TIMES (ns) Figure 64. Driver Type A Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance (VDD_EXT = 1.8 V) RISE AND FALL TIMES (ns) tFALL = 1.8V @ 25°C 1.2 RISE AND FALL TIMES (ns) Figure 64 through Figure 67 show how output rise time varies with capacitance. The delay and hold specifications given must be derated by a factor derived from these figures. The graphs in these figures may not be linear outside the ranges shown. 0.7 tRISE = 1.8V @ 25°C 0.6 tFALL = 1.8V @ 25°C 0.5 0.4 0.3 0.2 0.1 15 0 10 2 4 6 8 10 12 LOAD CAPACITANCE (pF) Figure 67. Driver Type B and Driver Type C Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance (VDD_DMC = 1.8 V) for LPDDR 5 0 0 0 50 100 150 200 250 LOAD CAPACITANCE (pF) Figure 65. Driver Type A Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance (VDD_EXT = 3.3 V) Rev. D | Page 103 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 ENVIRONMENTAL CONDITIONS To determine the junction temperature on the application printed circuit board, use the following equation:   T J = T CASE +   JT  P D  where: TJ = junction temperature (°C). TCASE = case temperature (°C) measured by customer at top center of package. JT = from Table 64 and Table 65. PD = power dissipation (see Total Internal Power Dissipation section for the method to calculate PD). Values of JA are provided for package comparison and printed circuit board design considerations. JA can be used for a firstorder approximation of TJ by the following equation:   T J = T A +   JA  P D  where: TA = ambient temperature (°C). Values of JC are provided for package comparison and printed circuit board design considerations when an external heat sink is required. In Table 64 and Table 65, airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6. The junction-tocase measurement complies with MIL-STD-883 (Method 1012.1). All measurements use a 2S2P JEDEC test board. Table 64. Thermal Characteristics for CSP_BGA Parameter JA JMA JMA JC JT JT JT Condition 0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow 0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow Typical 28.7 26.2 25.2 10.1 0.24 0.40 0.51 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W Table 65. Thermal Characteristics for LFCSP (QFN) Parameter JA JMA JMA JC JT JT JT Condition 0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow 0 linear m/s air flow 1 linear m/s air flow 2 linear m/s air flow Typical 22.9 17.9 16.4 2.26 0.14 0.27 0.30 Rev. D Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W | Page 104 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 ADSP-BF70x 184-BALL CSP_BGA BALL ASSIGNMENTS  (NUMERICAL BY BALL NUMBER) Figure 68 shows an overview of signal placement on the  184-ball CSP_BGA. Table 66 lists the 184-ball CSP_BGA package by ball number for the ADSP-BF70x. Table 67 lists the 184-ball CSP_BGA package by signal. TOP VIEW A1 BALL CORNER 1 2 3 4 5 6 7 8 GND 9 10 11 12 13 14 H GND_HADC I/O SIGNALS A B C D E F G H J K L M N P VDD_EXT D D D D VDD_INT D D D D D D D D H O H R D VDD_DMC H VDD_HADC O VDD_OTP R VDD_RTC U VDD_USB U BOTTOM VIEW 14 13 12 11 10 9 8 7 6 5 D D D D D D D D D D D D O H H R U 4 3 2 A1 BALL CORNER 1 A B C D E F G H J K L M N P Figure 68. 184-Ball CSP_BGA Configuration Rev. D | Page 105 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 Table 66. 184-Ball CSP_BGA Ball Assignment (Numerical by Ball Number) Ball No. A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 D01 D02 D03 D06 D07 Signal Name GND DMC0_A09 DMC0_BA0 DMC0_BA1 DMC0_BA2 DMC0_CAS DMC0_RAS DMC0_A13 PA_03 DMC0_CK DMC0_CK DMC0_LDQS DMC0_LDQS GND DMC0_A07 DMC0_A08 DMC0_A11 DMC0_A10 DMC0_A12 DMC0_WE DMC0_CS0 DMC0_ODT DMC0_CKE DMC0_DQ00 DMC0_DQ02 DMC0_DQ01 DMC0_DQ04 DMC0_DQ03 JTG_TDO_SWO JTG_TMS_SWDIO JTG_TCK_SWCLK PA_01 SYS_EXTWAKE PA_02 SYS_NMI GND PA_04 PA_05 PA_06 PA_07 SYS_HWRST SYS_BMODE1 DMC0_A00 DMC0_A04 JTG_TRST VDD_DMC VDD_DMC Ball No. D08 D09 D12 D13 D14 E01 E02 E03 E05 E06 E07 E08 E09 E10 E12 E13 E14 F01 F02 F03 F04 F05 F06 F07 F08 F09 F10 F11 F12 F13 F14 G01 G02 G03 G04 G05 G06 G07 G08 G09 G10 G11 G12 G13 G14 H01 H02 Signal Name VDD_DMC VDD_DMC PA_08 DMC0_DQ06 DMC0_DQ05 DMC0_A06 DMC0_A05 JTG_TDI VDD_INT VDD_DMC VDD_DMC VDD_DMC VDD_DMC DMC0_VREF SYS_BMODE0 DMC0_DQ08 DMC0_DQ07 DMC0_A01 DMC0_A02 PC_09 VDD_INT VDD_INT GND GND GND GND VDD_DMC VDD_DMC SYS_FAULT DMC0_DQ10 DMC0_DQ09 DMC0_A03 PA_00 PC_08 VDD_INT GND GND GND GND GND GND VDD_DMC PA_09 DMC0_DQ11 DMC0_DQ12 PC_07 PC_10 Rev. D Ball No. H03 H04 H05 H06 H07 H08 H09 H10 H11 H12 H13 H14 J01 J02 J03 J04 J05 J06 J07 J08 J09 J10 J11 J12 J13 J14 K01 K02 K03 K05 K06 K07 K08 K09 K10 K12 K13 K14 L01 L02 L03 L06 L07 L08 L09 L12 L13 Signal Name SYS_CLKOUT VDD_INT GND GND GND GND GND GND VDD_DMC PA_10 PA_11 DMC0_UDQS PC_05 PC_06 SYS_RESOUT VDD_INT VDD_RTC GND GND GND GND GND_HADC VDD_OTP PA_13 DMC0_DQ13 DMC0_UDQS PC_04 PC_01 PC_02 VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_HADC PA_12 DMC0_DQ15 DMC0_DQ14 PC_03 TWI0_SDA TWI0_SCL VDD_USB VDD_EXT VDD_EXT VDD_EXT PB_02 DMC0_UDM | Page 106 of 114 | February 2019 Ball No. L14 M01 M02 M03 M04 M05 M06 M07 M08 M09 M10 M11 M12 M13 M14 N01 N02 N03 N04 N05 N06 N07 N08 N09 N10 N11 N12 N13 N14 P01 P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 Signal Name GND PC_00 RTC0_CLKIN PB_15 PB_12 PC_12 USB0_VBUS USB0_VBC PB_09 PB_05 PB_04 PB_01 PB_03 DMC0_LDM SYS_CLKIN RTC0_XTAL PB_14 PB_11 PC_14 PC_11 USB0_ID USB0_DP PB_08 PB_06 PB_00 HADC0_VIN2 HADC0_VIN1 PA_15 SYS_XTAL GND PB_13 PB_10 PC_13 USB0_XTAL USB0_CLKIN USB0_DM PB_07 HADC0_VREFN HADC0_VREFP HADC0_VIN3 HADC0_VIN0 PA_14 GND ADSP-BF700/701/702/703/704/705/706/707 Table 67. ADSP-BF70x 184-Ball CSP_BGA Ball Assignments (Alphabetical by Signal Name) Signal Name DMC0_A00 DMC0_A01 DMC0_A02 DMC0_A03 DMC0_A04 DMC0_A05 DMC0_A06 DMC0_A07 DMC0_A08 DMC0_A09 DMC0_A10 DMC0_A11 DMC0_A12 DMC0_A13 DMC0_BA0 DMC0_BA1 DMC0_BA2 DMC0_CAS DMC0_CK DMC0_CKE DMC0_CK DMC0_CS0 DMC0_DQ00 DMC0_DQ01 DMC0_DQ02 DMC0_DQ03 DMC0_DQ04 DMC0_DQ05 DMC0_DQ06 DMC0_DQ07 DMC0_DQ08 DMC0_DQ09 DMC0_DQ10 DMC0_DQ11 DMC0_DQ12 DMC0_DQ13 DMC0_DQ14 DMC0_DQ15 DMC0_LDM DMC0_LDQS DMC0_LDQS DMC0_ODT DMC0_RAS DMC0_UDM DMC0_UDQS DMC0_UDQS DMC0_VREF Ball No. D01 F01 F02 G01 D02 E02 E01 B01 B02 A02 B04 B03 B05 A08 A03 A04 A05 A06 A10 B09 A11 B07 B10 B12 B11 B14 B13 D14 D13 E14 E13 F14 F13 G13 G14 J13 K14 K13 M13 A12 A13 B08 A07 L13 J14 H14 E10 Signal Name DMC0_WE GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND_HADC HADC0_VIN0 HADC0_VIN1 HADC0_VIN2 HADC0_VIN3 HADC0_VREFN HADC0_VREFP JTG_TCK_SWCLK JTG_TDI JTG_TDO_SWO JTG_TMS_SWDIO JTG_TRST PA_00 PA_01 PA_02 PA_03 PA_04 PA_05 PA_06 PA_07 Ball No. B06 C08 A01 A14 F06 F07 F08 F09 G05 G06 G07 G08 G09 G10 H05 H06 H07 H08 H09 H10 J06 J07 J08 J09 L14 P01 P14 J10 P12 N12 N11 P11 P09 P10 C03 E03 C01 C02 D03 G02 C04 C06 A09 C09 C10 C11 C12 Signal Name PA_08 PA_09 PA_10 PA_11 PA_12 PA_13 PA_14 PA_15 PB_00 PB_01 PB_02 PB_03 PB_04 PB_05 PB_06 PB_07 PB_08 PB_09 PB_10 PB_11 PB_12 PB_13 PB_14 PB_15 PC_00 PC_01 PC_02 PC_03 PC_04 PC_05 PC_06 PC_07 PC_08 PC_09 PC_10 PC_11 PC_12 PC_13 PC_14 RTC0_CLKIN RTC0_XTAL SYS_BMODE0 SYS_BMODE1 SYS_CLKIN SYS_CLKOUT SYS_EXTWAKE SYS_FAULT Rev. D | Page 107 of 114 | February 2019 Ball No. D12 G12 H12 H13 K12 J12 P13 N13 N10 M11 L12 M12 M10 M09 N09 P08 N08 M08 P03 N03 M04 P02 N02 M03 M01 K02 K03 L01 K01 J01 J02 H01 G03 F03 H02 N05 M05 P04 N04 M02 N01 E12 C14 M14 H03 C05 F12 Signal Name SYS_HWRST SYS_NMI SYS_RESOUT SYS_XTAL TWI0_SCL TWI0_SDA USB0_CLKIN USB0_DM USB0_DP USB0_ID USB0_VBC USB0_VBUS USB0_XTAL VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_HADC VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_OTP VDD_RTC VDD_USB Ball No. C13 C07 J03 N14 L03 L02 P06 P07 N07 N06 M07 M06 P05 D06 D07 D08 D09 E06 E07 E08 E09 F10 F11 G11 H11 K05 K06 K07 K08 K09 L07 L08 L09 K10 E05 F04 F05 G04 H04 J04 J11 J05 L06 ADSP-BF700/701/702/703/704/705/706/707 ADSP-BF70x 12 mm × 12 mm 88-LEAD LFCSP (QFN) LEAD ASSIGNMENTS  (NUMERICAL BY LEAD NUMBER) Figure 69 shows an overview of signal placement on the12 mm × 12 mm 88-lead LFCSP (QFN). PIN 88 PIN 67 PIN 1 PIN 66 PIN 1 INDICATOR ADSP-BF70x 88-LEAD LFCSP (QFN) TOP VIEW PIN 22 PIN 45 PIN 23 PIN 44 PIN 88 PIN 67 PIN 66 PIN 1 PIN 1 INDICATOR GND PAD (PIN 89) BOTTOM VIEW PIN 45 PIN 44 PIN 22 PIN 23 Figure 69. 12 mm × 12 mm 88-Lead LFCSP (QFN) Configuration Rev. D | Page 108 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 Table 68 lists the 12 mm × 12 mm 88-Lead LFCSP (QFN) package by lead number for the ADSP-BF70x. Table 69 lists the  12 mm ×12 mm 88-Lead LFCSP (QFN) package by signal. Table 68. 12 mm × 12 mm 88-Lead LFCSP (QFN) Lead Assignment (Numerical by Lead Number) Lead No. Signal Name Lead No. Signal Name Lead No. Signal Name 1 PC_10 24 PB_14 47 PB_02 2 PC_09 25 PB_13 48 PB_01 3 PC_08 26 VDD_EXT 49 VDD_OTP 4 VDD_EXT 27 PB_12 50 VDD_EXT 5 PC_07 28 PB_11 51 VDD_INT 6 PC_06 29 PB_10 52 PB_00 7 PC_05 30 VDD_INT 53 PA_15 8 PC_04 31 USB0_XTAL 54 PA_14 9 PC_03 32 USB0_CLKIN 55 VDD_EXT 10 PC_02 33 USB0_ID 56 SYS_XTAL 11 VDD_EXT 34 USB0_VBUS 57 SYS_CLKIN 12 SYS_CLKOUT 35 USB0_DP 58 PA_13 13 PC_01 36 VDD_USB 59 PA_12 14 VDD_INT 37 USB0_DM 60 PA_11 15 SYS_RESOUT 38 USB0_VBC 61 VDD_INT 16 PC_00 39 PB_09 62 VDD_EXT 17 VDD_EXT 40 PB_08 63 PA_10 18 TWI0_SDA 41 VDD_EXT 64 PA_09 19 TWI0_SCL 42 PB_07 65 SYS_FAULT 20 RTC0_XTAL 43 PB_06 66 SYS_BMODE0 21 RTC0_CLKIN 44 PB_05 67 SYS_BMODE1 22 VDD_RTC 45 PB_04 68 SYS_HWRST 23 PB_15 46 PB_03 69 PA_08 *Pin no. 89 is the GND supply (see Figure 69) for the processor; this pad must connect to GND. Rev. D | Page 109 of 114 | February 2019 Lead No. 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89* Signal Name PA_07 PA_06 VDD_EXT PA_05 PA_04 PA_03 GND SYS_NMI PA_02 SYS_EXTWAKE PA_01 VDD_INT VDD_EXT JTG_TDO_SWO JTG_TMS_SWDIO JTG_TCK_SWCLK JTG_TDI JTG_TRST PA_00 GND ADSP-BF700/701/702/703/704/705/706/707 Table 69. ADSP-BF70x 12 mm × 12 mm 88 -Lead LFCSP (QFN) Lead Assignments (Alphabetical by Signal Name) Signal Name GND GND JTG_TCK_SWCLK JTG_TDI JTG_TDO_SWO JTG_TMS_SWDIO JTG_TRST PA_00 PA_01 PA_02 PA_03 PA_04 PA_05 PA_06 PA_07 PA_08 PA_09 PA_10 PA_11 PA_12 PA_13 PA_14 PA_15 Lead No. 76 89 85 86 83 84 87 88 80 78 75 74 73 71 70 69 64 63 60 59 58 54 53 Signal Name PB_00 PB_01 PB_02 PB_03 PB_04 PB_05 PB_06 PB_07 PB_08 PB_09 PB_10 PB_11 PB_12 PB_13 PB_14 PB_15 PC_00 PC_01 PC_02 PC_03 PC_04 PC_05 PC_06 Lead No. 52 48 47 46 45 44 43 42 40 39 29 28 27 25 24 23 16 13 10 9 8 7 6 Rev. D Signal Name PC_07 PC_08 PC_09 PC_10 RTC0_CLKIN RTC0_XTAL SYS_BMODE0 SYS_BMODE1 SYS_CLKIN SYS_CLKOUT SYS_EXTWAKE SYS_FAULT SYS_HWRST SYS_NMI SYS_RESOUT SYS_XTAL TWI0_SCL TWI0_SDA USB0_CLKIN USB0_DM USB0_DP USB0_ID USB0_VBC | Page 110 of 114 | February 2019 Lead No. 5 3 2 1 21 20 66 67 57 12 79 65 68 77 15 56 19 18 32 37 35 33 38 Signal Name USB0_VBUS USB0_XTAL VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_OTP VDD_RTC VDD_USB Lead No. 34 31 4 11 17 26 41 50 55 62 72 82 14 30 51 61 81 49 22 36 ADSP-BF700/701/702/703/704/705/706/707 OUTLINE DIMENSIONS Dimensions for the 12 mm × 12 mm CSP_BGA package in Figure 70 are shown in millimeters. A1 BALL CORNER 12.10 12.00 SQ 11.90 14 13 12 11 10 9 8 7 6 5 4 3 2 A B C D E F G H J K L M N P 10.40 REF SQ 0.80 BSC TOP VIEW 1.70 1.54 1.39 0.80 REF BOTTOM VIEW DETAIL A DETAIL A SEATING PLANE A1 BALL CORNER 1 1.29 1.19 1.09 0.39 0.35 0.30 0.50 COPLANARITY 0.45 0.12 0.40 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-275-GGAA-1 Figure 70. 184-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-184-1) Dimensions shown in millimeters Rev. D | Page 111 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 Dimensions for the 12 mm × 12 mm LFCSP_VQ package in Figure 71 are shown in millimeters. 12.10 12.00 SQ 11.90 0.28 0.23 0.18 0.60 MAX 0.60 MAX 88 67 66 1 PIN 1 INDICATOR PIN 1 INDICATOR 11.85 11.75 SQ 11.65 0.50 BSC 0.50 0.40 0.30 45 22 0.90 0.85 0.80 SEATING PLANE 23 44 BOTTOM VIEW TOP VIEW 12° MAX 6.00 5.90 SQ 5.80 EXPOSED PAD 0.70 0.65 0.60 0.190~0.245 REF 10.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.045 0.025 0.005 COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220 Figure 71. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ] (CP-88-8) Dimensions shown in millimeters SURFACE-MOUNT DESIGN Table 70 is provided as an aid to PCB design. For industry-standard design recommendations, refer to IPC-7351, Generic Requirements for Surface-Mount Design and Land Pattern Standard. Table 70. CSP_BGA Data for Use with Surface-Mount Design Package  Ball Attach Type Solder Mask Defined Package BC-184-1 Rev. D | Page 112 of 114 | February 2019 Package  Solder Mask Opening 0.4 mm Diameter Package  Ball Pad Size 0.5 mm Diameter ADSP-BF700/701/702/703/704/705/706/707 AUTOMOTIVE PRODUCTS The following models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the nonautomotive models; therefore designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown in Table 71 are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Table 71. Automotive Products Model 1, 2, 3 ADBF700WCCPZ2xx ADBF701WCBCZ2xx ADBF702WCCPZ3xx ADBF702WCCPZ4xx ADBF703WCBCZ3xx ADBF703WCBCZ4xx ADBF704WCCPZ3xx ADBF704WCCPZ4xx ADBF705WCBCZ3xx ADBF705WCBCZ4xx ADBF706WCCPZ3xx ADBF706WCCPZ4xx ADBF707WCBCZ3xx ADBF707WCBCZ4xx Processor Instruction  Rate (Max) 200 MHz 200 MHz 300 MHz 400 MHz 300 MHz 400 MHz 300 MHz 400 MHz 300 MHz 400 MHz 300 MHz 400 MHz 300 MHz 400 MHz L2 SRAM 128K bytes 128K bytes 256K bytes 256K bytes 256K bytes 256K bytes 512K bytes 512K bytes 512K bytes 512K bytes 1024K bytes 1024K bytes 1024K bytes 1024K bytes Temperature Grade4 –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C 1 Package Description 88-Lead LFCSP_VQ 184-Ball CSP_BGA 88-Lead LFCSP_VQ 88-Lead LFCSP_VQ 184-Ball CSP_BGA 184-Ball CSP_BGA 88-Lead LFCSP_VQ 88-Lead LFCSP_VQ 184-Ball CSP_BGA 184-Ball CSP_BGA 88-Lead LFCSP_VQ 88-Lead LFCSP_VQ 184-Ball CSP_BGA 184-Ball CSP_BGA Package Option CP-88-8 BC-184-1 CP-88-8 CP-88-8 BC-184-1 BC-184-1 CP-88-8 CP-88-8 BC-184-1 BC-184-1 CP-88-8 CP-88-8 BC-184-1 BC-184-1 Select Automotive grade products, supporting –40°C to +105°C TAMBIENT condition, will be available when they appear in the Automotive Products table. Z = RoHS Compliant Part. 3 xx denotes the current die revision. 4 Referenced temperature is ambient temperature. The ambient temperature is not a specification. See Operating Conditions for the junction temperature (TJ) specification which is the only temperature specification. 2 Rev. D | Page 113 of 114 | February 2019 ADSP-BF700/701/702/703/704/705/706/707 ORDERING GUIDE Model1 ADSP-BF700KCPZ-1 ADSP-BF700KCPZ-2 ADSP-BF700BCPZ-2 ADSP-BF701KBCZ-1 ADSP-BF701KBCZ-2 ADSP-BF701BBCZ-2 ADSP-BF702KCPZ-3 ADSP-BF702BCPZ-3 ADSP-BF702KCPZ-4 ADSP-BF702BCPZ-4 ADSP-BF703KBCZ-3 ADSP-BF703BBCZ-3 ADSP-BF703KBCZ-4 ADSP-BF703BBCZ-4 ADSP-BF704KCPZ-3 ADSP-BF704BCPZ-3 ADSP-BF704KCPZ-4 ADSP-BF704BCPZ-4 ADSP-BF705KBCZ-3 ADSP-BF705BBCZ-3 ADSP-BF705KBCZ-4 ADSP-BF705BBCZ-4 ADSP-BF706KCPZ-3 ADSP-BF706BCPZ-3 ADSP-BF706KCPZ-4 ADSP-BF706BCPZ-4 ADSP-BF707KBCZ-3 ADSP-BF707BBCZ-3 ADSP-BF707KBCZ-4 ADSP-BF707BBCZ-4 1 2 Processor Instruction  Rate (Max) 100 MHz 200 MHz 200 MHz 100 MHz 200 MHz 200 MHz 300 MHz 300 MHz 400 MHz 400 MHz 300 MHz 300 MHz 400 MHz 400 MHz 300 MHz 300 MHz 400 MHz 400 MHz 300 MHz 300 MHz 400 MHz 400 MHz 300 MHz 300 MHz 400 MHz 400 MHz 300 MHz 300 MHz 400 MHz 400 MHz L2 SRAM 128K bytes 128K bytes 128K bytes 128K bytes 128K bytes 128K bytes 256K bytes 256K bytes 256K bytes 256K bytes 256K bytes 256K bytes 256K bytes 256K bytes 512K bytes 512K bytes 512K bytes 512K bytes 512K bytes 512K bytes 512K bytes 512K bytes 1024K bytes 1024K bytes 1024K bytes 1024K bytes 1024K bytes 1024K bytes 1024K bytes 1024K bytes Temperature Grade2 0°C to +70°C 0°C to +70°C –40°C to +85°C 0°C to +70°C 0°C to +70°C –40°C to +85°C 0°C to +70°C –40°C to +85°C 0°C to +70°C –40°C to +85°C 0°C to +70°C –40°C to +85°C 0°C to +70°C –40°C to +85°C 0°C to +70°C –40°C to +85°C 0°C to +70°C –40°C to +85°C 0°C to +70°C –40°C to +85°C 0°C to +70°C –40°C to +85°C 0°C to +70°C –40°C to +85°C 0°C to +70°C –40°C to +85°C 0°C to +70°C –40°C to +85°C 0°C to +70°C –40°C to +85°C Package Description 88-Lead LFCSP_VQ 88-Lead LFCSP_VQ 88-Lead LFCSP_VQ 184-Ball CSP_BGA 184-Ball CSP_BGA 184-Ball CSP_BGA 88-Lead LFCSP_VQ 88-Lead LFCSP_VQ 88-Lead LFCSP_VQ 88-Lead LFCSP_VQ 184-Ball CSP_BGA 184-Ball CSP_BGA 184-Ball CSP_BGA 184-Ball CSP_BGA 88-Lead LFCSP_VQ 88-Lead LFCSP_VQ 88-Lead LFCSP_VQ 88-Lead LFCSP_VQ 184-Ball CSP_BGA 184-Ball CSP_BGA 184-Ball CSP_BGA 184-Ball CSP_BGA 88-Lead LFCSP_VQ 88-Lead LFCSP_VQ 88-Lead LFCSP_VQ 88-Lead LFCSP_VQ 184-Ball CSP_BGA 184-Ball CSP_BGA 184-Ball CSP_BGA 184-Ball CSP_BGA Package Option CP-88-8 CP-88-8 CP-88-8 BC-184-1 BC-184-1 BC-184-1 CP-88-8 CP-88-8 CP-88-8 CP-88-8 BC-184-1 BC-184-1 BC-184-1 BC-184-1 CP-88-8 CP-88-8 CP-88-8 CP-88-8 BC-184-1 BC-184-1 BC-184-1 BC-184-1 CP-88-8 CP-88-8 CP-88-8 CP-88-8 BC-184-1 BC-184-1 BC-184-1 BC-184-1 Z = RoHS Compliant Part. Referenced temperature is ambient temperature. The ambient temperature is not a specification. See Operating Conditions for the junction temperature (TJ) specification which is the only temperature specification. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12396-0-2/19(D) Rev. D | Page 114 of 114 | February 2019